06th week of 2022 patent applcation highlights part 59 |
Patent application number | Title | Published |
20220045117 | BAND-PASS FILTER FOR STACKED SENSOR - In some embodiments, the present disclosure relates to an integrated chip structure. The integrated chip structure includes an image sensor disposed within a first substrate. A first band-pass filter and a second band-pass filter are disposed on the first substrate. A dielectric structure is disposed on the first substrate. The dielectric structure is laterally between the first band-pass filter and the second band-pass filter and laterally abuts the first band-pass filter and the second band-pass filter. | 2022-02-10 |
20220045118 | COMPOUND SEMICONDUCTOR X-RAY DETECTOR TILES AND METHOD OF DICING THEREOF - A radiation detector tile includes a single crystal compound semiconductor tile having a zinc blende crystal structure, a (111) plane first major (i.e. prominent) surface and four side surfaces which are rotated by an angle of 13° to 17° to a {110} family of planes. The tile may be formed by dicing a (111) oriented wafer at directions which are rotated by an angle of 13° to 17° from <110> in-plane slipping directions to reduce or eliminate the side surface chipping and sub surface dislocation defects. | 2022-02-10 |
20220045119 | MANUFACTURE OF SEMICONDUCTOR DISPLAY DEVICE - A method of manufacturing light emitting diode (LED) devices is provided. In one example, the method comprises: forming a plurality of LED dies on a starter substrate, each of the plurality of LED dies including a device-side bump; moving, using a pick up tool (PUT), the starter substrate and the plurality of LED dies towards a backplane, the backplane including a plurality of backplane-side bumps; establishing the conductive bonds between the device-side bumps of the plurality of LED dies and the backplane-side bumps of the backplane at the plurality of contact locations; and operating the PUT to release the starter substrate to enable transferring of the plurality of LED dies to the backplane. | 2022-02-10 |
20220045120 | LIGHT-EMITTING DIODE (LED) LIGHT BOARD, SPLICED LED LIGHT BOARD AND DISPLAY DEVICE - The present application provides a light-emitting diode (LED) light board, a spliced LED light board and a display device. The LED light board includes a substrate, a plurality of LED chips, and a gate driving module; the LED chip array is arranged on the substrate; the gate driving module is disposed on the substrate and configured to provide a gate driving signal to the LED chips, the gate driving module includes a plurality of gate driving units; the LED chips are arranged on opposite sides of the gate driving module, and each of the gate driving units is electrically connected to its corresponding ones of the LED chips on opposite sides of the gate driving unit. | 2022-02-10 |
20220045121 | MONOLITHIC MULTI-CHIP-COLLECTIVE LIGHT-EMITTING DIODE - A monolithic multi-chip-collective light emitting diode includes: an n-type structure, a p-type structure, and an active-region sandwiched between the n-type structure and the p-type structure; a plurality of monolithically integrated mini chips, wherein each of the mini chips comprises a mini n-contact formed on the n-type structure which is exposed by an opening in the p-type structure and the active-region, a mini p-ohmic contact formed on the p-type structure, and a mini light emitting area defined by the mini p-ohmic contact; an n-bridge metal electrically connecting the mini n-contact of each of the mini chips to an n-bonding pad, wherein the n-bridge metal is formed on the p-type structure and on sidewall of the opening in the p-type structure and the active-region. | 2022-02-10 |
20220045122 | SCAN NEEDLE AND SCAN DISPLAY SYSTEM INCLUDING SAME - A scan needle includes a substrate, a first color light emitting pixel array comprising a plurality of first color light emitting pixels formed on the substrate, a second color light emitting pixel array comprising a plurality of second color light emitting pixels formed on the substrate, and a third color light emitting pixel array comprising a plurality of third color light emitting pixels formed on the substrate. The first color light emitting pixel array is parallel to the second color light emitting pixel array, and the second color light emitting pixel array is parallel to the third color light emitting pixel array. | 2022-02-10 |
20220045123 | MICRO-LED DISPLAY PANEL AND METHOD FOR MAKING SAME - A micro-LED display panel includes a substrate, an insulating layer on the substrate, and a plurality of micro-LEDs on the substrate and embedded in the insulating layer. The micro-LEDs define a display area. Each micro-LED includes a bottom surface coupled to a lower electrode and a top surface exposed from the insulating layer and coupled to the upper electrode. Conductive blocks are set outside the display area, the conductive blocks are electrically coupled to a driving circuit on the substrate. Top wires are set on a surface of the insulating layer away from the substrate and each top wire is electrically coupled to at least one upper electrode and at least one conductive block. | 2022-02-10 |
20220045124 | TILED DISPLAY DEVICE - A display device includes display devices each including a display area and a non-display area adjacent to the display area, the display area of each of the display devices including a pixel, and a substrate on which each of the display devices is disposed. Each of the display devices includes a thin film transistor layer disposed on the substrate and including a thin film transistor, and a connection line electrically connected to the thin film transistor and disposed in the non-display area on the substrate. Connection lines of display devices adjacent to each other among the plurality of display devices are disposed staggered with respect to each other. | 2022-02-10 |
20220045125 | SEMICONDUCTOR DEVICE AND ELECTRONIC DEVICE - A semiconductor device that can perform product-sum operation with low power consumption is provided. The semiconductor device includes first and second circuits; the first circuit includes a first holding node and the second circuit includes a second holding node. The first circuit is electrically connected to first and second input wirings and first and second wirings, the second circuit is electrically connected to the first and second input wirings and the first and second wirings, and the first and second circuits each have a function of holding first and second potentials corresponding to first data at the first and second holding nodes. When a potential corresponding to second data is input to each of the first and second input wirings, the first circuit outputs a current to one of the first wiring and the second wiring and the second circuit outputs a current to the other of the first wiring and the second wiring. The currents output from the first and second circuits to the first wiring or the second wiring are determined in accordance with the first and second potentials held at the first and second holding nodes. | 2022-02-10 |
20220045126 | LAYOUT PATTERN OF MAGNETORESISTIVE RANDOM ACCESS MEMORY - A layout pattern of a magnetoresistive random access memory (MRAM) includes a substrate having a first cell region, a second cell region, a third cell region, and a fourth cell region and a diffusion region on the substrate extending through the first cell region, the second cell region, the third cell region, and the fourth cell region. Preferably, the diffusion region includes a H-shape according to a top view. | 2022-02-10 |
20220045127 | SELECTOR DEVICES - Disclosed herein are selector devices and related devices and techniques. In some embodiments, a selector device may include a first electrode, a second electrode, and a selector material between the first electrode and the second electrode. The selector material may include a dielectric material and a conductive dopant. | 2022-02-10 |
20220045128 | MEMORY MATERIAL AND MEMORY DEVICE APPLYING THE SAME - A memory material and a memory device applying the same are provided. The memory material is a chalcogenide doped with carbon atom. The chalcogenide contains arsenic (As) atom, selenium (Se) atom, germanium (Ge) atom and silicon (Si) atom. | 2022-02-10 |
20220045129 | SEMICONDUCTOR STORAGE DEVICE - A semiconductor storage device includes lower and upper bit lines, word lines between the bit lines, and memory cells between the bit lines and the word lines. The memory cells are divided into logical slices and a memory cell from each logical slice is selected when carrying out a read or write operation. A first logical slice includes memory cells, each of which is between one of two bit lines and one of three word lines that are adjacent to each other. The two bit lines include one lower bit line and one upper bit line. A second logical slice includes memory cells, each of which is between one of three bit lines and one of three word lines that are not adjacent to each other. The three bit lines include one lower bit line and two upper bit lines. | 2022-02-10 |
20220045130 | Three Terminal Tandem Solar Generation Unit - The present invention refers to a three terminal tandem solar generation unit ( | 2022-02-10 |
20220045131 | COLOR FILTER LAYER AND DISPLAY DEVICE - A color filter layer and a display device are provided. A material of the color filter layer includes a dye, a polymer resin, a monomer, a photoinitiator, and a solvent. A material of the dye is one of a core-shell material or a titanium dioxide material. The shell material includes an organic polymer, and the core material is an inorganic fluorescent material. The shell material covers the core material, and the inorganic fluorescent material includes a europium-doped compound. | 2022-02-10 |
20220045132 | COLOR CONVERSION PANEL AND DISPLAY DEVICE INCLUDING THE SAME - A color conversion panel includes a plurality of pixel areas including a first pixel area and a second pixel area, and a non-pixel area which is adjacent to the first pixel area and the second pixel area, a light blocking layer in the non-pixel area, a color filter layer including a first color filter in the first pixel area and a second color filter in the second pixel area, a color conversion layer which color converts incident light, and scatters and reflects external light, the color conversion layer including a first color conversion pattern corresponding to the first color filter and a light transmission pattern corresponding to the second color filter, and a light absorbing layer which faces the color conversion layer and absorbs light which is scattered and reflected from the color conversion layer. | 2022-02-10 |
20220045133 | DISPLAY PANEL AND DISPLAY DEVICE - A display panel including pixels each including a self-luminous element and a color filter, including a green light emitting element among the self-luminous elements. The green light emitting element has an optical resonator structure in which a light transmissive metal thin film electrode, a green light emitting layer, and a light reflective electrode are disposed in this order with the light transmissive metal thin film electrode closest to one of the color filters corresponding to the green light emitting element, in order to enhance light intensity of a first wavelength, and the one of the color filters has a light transmittance of 50% or less for light having a second wavelength that is longer than the first wavelength and has a higher visibility characteristic as a green color component than the first wavelength. | 2022-02-10 |
20220045134 | DISPLAY PANEL - A display panel includes an upper substrate to which external light is incident, a sealing member which is in a non-display area and couples the upper substrate to a lower display substrate. The upper display substrate includes: a base substrate; a light shielding layer and filter layer each corresponding to the non-display area and absorbing a portion of external light which is transmitted through the base substrate at the non-display area, the filter layer and the light shielding layer having different colors from each other. In a first non-display area of the base substrate which corresponds to the sealing member, only one among the filter layer and the light shielding layer is disposed. In a second non-display area of the base substrate which is adjacent to the first non-display area, both the filter layer and the light shielding layer are disposed. | 2022-02-10 |
20220045135 | DISPLAY PANEL AND DISPLAY DEVICE - A display panel and a display device are provided. The display device in an embodiment of the present disclosure includes a pixel array and a flexible substrate. The flexible substrate includes a first area and a second area disposed on a bottom of the pixel array, and a bending area disposed between the first area and the second area; wherein, the flexible substrate in the bending area is completely or partially hollowed out along a bending direction. | 2022-02-10 |
20220045136 | DISPLAY PANEL - A display panel includes a display area in which a plurality of pixels is disposed, a non-display area disposed outside the display area, a plurality of protrusions protruding from the non-display area and disposed along an edge of the non-display area, and a first driver disposed in the non-display area and including a plurality of first stages respectively corresponding to the plurality of protrusions. | 2022-02-10 |
20220045137 | DISPLAY APPARATUS - A display apparatus includes: a substrate; at least one inorganic layer disposed on the substrate and including a first area, a second area, and an elongated recess disposed between the first area and the second area, the first area and the second area being adjacent to each other in a first direction; an organic material disposed in the recess; a plurality of first pixel electrodes disposed on the first area of the inorganic layer; and a plurality of second pixel electrodes disposed on the second area of the inorganic layer. The number of the plurality of first pixel electrodes and the number of the plurality of second pixel electrodes are different from each other. | 2022-02-10 |
20220045138 | DISPLAY PANEL AND MANUFACTURING METHOD THEREOF - A display panel and a manufacturing method thereof, the display panel includes a first sub-pixel strip, a second sub-pixel strip, and a third sub-pixel strip arranged in a row direction or a column direction. The sub-pixels on each sub-pixel strip of the present disclosure have the same color and are arranged in series. The first sub-pixels on the first sub-pixel strip and the second sub-pixels on the second sub-pixel strip are staggered to improve flatness of printing the luminous material and luminous uniformity of OLED devices. | 2022-02-10 |
20220045139 | DISPLAY DEVICE - A display device includes a plurality of subpixels. The plurality of subpixels include a first subpixel including a first light-emitting layer, and a first subpixel circuit, a second subpixel including a second light-emitting layer, and a second subpixel circuit, a third subpixel including a third light-emitting layer, and a third subpixel circuit, and a fourth subpixel including a fourth light-emitting layer, and a fourth subpixel circuit. An area of an opening exposing a first electrode in the first subpixel is larger than an area of the opening exposing the first electrode in each of the second subpixel, the third subpixel, and the fourth subpixel. A plurality of light emission control lines include a first light emission control line connected to the first subpixel circuit and the third subpixel circuit, and a second emission control line connected to the second subpixel circuit and the fourth subpixel circuit. | 2022-02-10 |
20220045140 | DISPLAY PANEL, METHOD FOR MANUFACTURING THE SAME, DISPLAY DEVICE AND METHOD FOR MANUFACTURING THE SAME - A display panel, a method for manufacturing the same, a display device and a method for manufacturing the same are provided. The display panel includes a display region and a peripheral region arranged on a substrate, and further includes multiple active driving circuits and multiple redundant driving circuits. At least one active driving circuit is electrically connected to at least one of multiple pixel units, and each redundant driving circuit includes at least one electrode layer arranged on the substrate. The peripheral region includes a flat region and a curved region, at least part of the redundant driving circuits are located in a flat redundant driving circuit region included in the flat region. The flat redundant driving circuit region includes at least two alignment mark regions. In the alignment mark regions, at least one electrode layer is hollowed out, and/or at least one electrode layer is filled up. | 2022-02-10 |
20220045141 | DISPLAY SUBSTRATE, MANUFACTURING METHOD THEREOF, AND DISPLAY DEVICE - The present disclosure provides a display substrate, a manufacturing method thereof, and a display device. The display substrate includes a base substrate and a plurality of subpixels arranged on the base substrate in an array form. The plurality of subpixels includes a plurality of display subpixels at a display region of the display substrate and a plurality of virtual subpixels, and at least a part of the virtual subpixels are arranged adjacent to the display subpixels. The virtual subpixel includes a first potential signal line pattern, a virtual subpixel driving circuit including a virtual driving transistor and a first conductive connection member coupled to a gate electrode of the virtual driving transistor, and a second conductive connection member coupled to the first conductive connection member and the first potential signal line pattern. | 2022-02-10 |
20220045142 | ORGANIC LIGHT EMITTING DISPLAY DEVICE - An organic light emitting display device includes a substrate, a light emitting structure, a first conductive pattern, and a functional module. The substrate has an opening region, a peripheral region surrounding the opening region, and a display region surrounding the peripheral region, and includes a first groove, which has an enlarged lower portion, formed in the peripheral region and an opening formed in the opening region. The light emitting structure is in the display region on the substrate. The first conductive pattern overlaps the first groove in the peripheral region on the substrate. The functional module is in the opening of the substrate. | 2022-02-10 |
20220045143 | DISPLAY APPARATUS HAVING ZERO BEZEL BY BENDING BEZEL AREA - A display apparatus includes a first substrate having a display area and a non-display area; a pixel array layer provided on the display area of the first substrate; and a second substrate provided on the pixel array layer and having first and second grooves at side edges of the second substrate, wherein the first and second grooves are respectively located at first and second bending areas to facilitate a curvature radius of the end portions of the display and achieve a zero bezel display. | 2022-02-10 |
20220045144 | DISPLAY PANEL, DISPLAY APPARATUS INCLUDING THE SAME, AND METHOD FOR MANUFACTURING THE DISPLAY PANEL - A display panel includes an emitting part including a light emitting element and a transmitting part adjacent to the emitting part and including a low adhesion part including a carbon compound. The low adhesion pattern includes fluorine (F). | 2022-02-10 |
20220045145 | LIGHT-EMITTING DEVICE AND METHOD OF MANUFACTURING THE SAME - A light-emitting device and a method of manufacturing the same. The light-emitting device includes a body portion, and a light-emitting portion arranged in the body portion and configured to emit light to the outside. The light-emitting portion includes a plurality of pixels. At least two of the pixels are configured to emit pieces of light having different wavelengths from each other. | 2022-02-10 |
20220045146 | ORGANIC LIGHT-EMITTING DIODE DISPLAY SUBSTRATE AND MANUFACTURING METHOD THEREOF, AND DISPLAY PANEL - An organic light-emitting diode (OLED) display substrate, a manufacturing method thereof and a display panel are provided. The OLED display substrate has pixel regions and includes a base substrate and a pixel defining layer disposed on the base substrate; in regions of the pixel defining layer corresponding to the pixel regions, accommodation parts penetrating the pixel defining layer are disposed, and the pixel defining layer is further provided with guide parts disposed corresponding to the accommodation parts, the guide parts are located on a periphery of the corresponding accommodation parts and formed by recessed areas which are formed on a side of the pixel defining layer away from the base substrate, the recessed areas do not penetrate the pixel defining layer, and an orthographic projection of the guide part on the base substrate is directly coupled to an orthographic projection of the corresponding accommodation part on the base substrate. | 2022-02-10 |
20220045147 | DISPLAY DEVICE AND METHOD FOR MANUFACTURING THEREOF - A display device includes a substrate, a first transistor including a channel on the substrate, a first electrode and a second electrode, and a gate electrode overlapping the channel of the first transistor, a first interlayer insulation layer on the first and second electrodes of the first transistor, a second transistor including a channel disposed on the first interlayer insulation layer, a first electrode and a second electrode of the second transistor, and a gate electrode that overlaps the channel of the second transistor, a first connection electrode disposed on the first interlayer insulation layer, and connected with the first electrode of the first transistor, a gate insulation layer disposed between the first interlayer insulation layer and the first connection electrode, and a second connection electrode that connects the first connection electrode and the first electrode of the second transistor. | 2022-02-10 |
20220045148 | DISPLAY APPARATUS - A display apparatus including a circuit with improved characteristics and including a thin-film transistor includes a first interlayer insulating layer arranged on a substrate, a first semiconductor layer arranged on the first interlayer insulating layer and including an oxide semiconductor material, a first gate electrode arranged on the first semiconductor layer, a second interlayer insulating layer arranged on the first gate electrode, and a first electrode layer arranged on the second interlayer insulating layer and electrically connected to the first semiconductor layer through a first contact hole penetrating the second interlayer insulating layer, wherein the first semiconductor layer includes an opening corresponding to the first contact hole, and the first electrode layer contacts an inner surface of the opening. | 2022-02-10 |
20220045149 | DISPLAY APPARATUS AND METHOD OF MANUFACTURING THE SAME - A display apparatus includes a base substrate including a display region in which an image is displayed and a peripheral region that is a non-display region adjacent to the display region, a plurality of pixels disposed on the base substrate in the display region, each of the pixels including a thin film transistor that includes an oxide semiconductor pattern, a data driver disposed in the peripheral region and configured to provide a data voltage to the pixels, and a plurality of test patterns disposed on the base substrate in the peripheral region, each of the test patterns including a test thin film transistor that includes a test oxide semiconductor pattern. | 2022-02-10 |
20220045150 | AMOLED DISPLAY PANEL AND CORRESPONDING DISPLAY DEVICE - The present disclosure provides an active-matrix organic light-emitting diode (AMOLED) display panel and a display device. The AMOLED display panel includes a plurality of first pixel units and a plurality of second pixel units. The first pixel unit includes a first sub-pixel and a second sub-pixel. The present disclosure is achieved by the first sub-pixel and the second sub-pixel in the first pixel unit to share one of the data lines, and by another first sub-pixel and a third sub-pixel in the second pixel unit to share one of the data lines, such that a quantity of data lines and a quantity of fan-out wires are reduced, so as to reduce a size of a lower bezel. | 2022-02-10 |
20220045151 | DISPLAY PANEL AND DISPLAY APPARATUS INCLUDING THE SAME - A display panel includes: a substrate including a main display area, a component area, and a peripheral area; a main sub-pixel at the main display area on the substrate; a main pixel circuit connected to the main sub-pixel, and including a main storage capacitor; an auxiliary sub-pixel at the component area on the substrate; an auxiliary pixel circuit at the peripheral area on the substrate, and including an auxiliary storage capacitor; and a connecting line connecting the auxiliary sub-pixel to the auxiliary pixel circuit. A capacity of the auxiliary storage capacitor is greater than a capacity of the main storage capacitor. | 2022-02-10 |
20220045152 | DISPLAY DEVICE - A display device includes: a substrate; a buffer layer on the substrate; a first active pattern and a second active pattern on the buffer layer and spaced apart from each other; a first gate insulation layer on the first active pattern and the second active pattern; a first gate electrode and a second gate electrode on the first gate insulation layer, the first gate electrode and the second gate electrode respectively overlapping the first active pattern and the second active pattern; a second gate insulation layer on the first gate electrode and the second gate electrode; and a capacitor electrode on the second gate insulation layer, the capacitor electrode overlapping the first gate electrode, wherein a permittivity of the first gate insulation layer is greater than a permittivity of the buffer layer. | 2022-02-10 |
20220045153 | DISPLAY PANEL, PREPARING METHOD THEREOF, AND DISPLAY DEVICE - A display panel, a method for preparing a display panel, and a display device are disclosed. The display panel includes a substrate layer; a light shielding metal layer and a first electrode plate of a storage capacitor on the substrate layer; a buffer layer covering the light shielding metal layer and the first electrode plate on the substrate layer; an active layer and a second electrode plate of the storage capacitor on the buffer layer; a gate insulating layer on the buffer layer and the active layer, and a source, a gate and a drain on the gate insulating layer. | 2022-02-10 |
20220045154 | DISPLAY PANEL AND DISPLAY DEVICE - The present application provides a display panel and a display device. The display panel includes a substrate, a driving circuit layer disposed on the substrate, and a light-emitting layer disposed on the driving circuit layer. The driving circuit layer includes a first metal layer, the first metal layer includes a first metal trace, the light-emitting layer includes multiple light-emitting portions, and a vertical distance between an orthographic projection of a center of each light-emitting portion projected on the first metal layer and a symmetry axis of the first metal trace is less than or equal to 5 μm. | 2022-02-10 |
20220045155 | DISPLAY PANEL AND DISPLAY DEVICE - A display panel and a display device are provided. A display area of the display panel includes an optical component area and a regular display area, and the optical component area and the regular display area both include light-emitting devices, so that the area of the display area becomes larger to meet the trend of full screen display. In the optical component area, a transparent conductive layer includes paired first and second etching slots, a connection wire arranged between the paired first and second etching slots, and an auxiliary layer arranged outside the paired first and second etching slots. | 2022-02-10 |
20220045156 | DISPLAY PANEL AND DISPLAY DEVICE INCLUDING THE SAME - A display panel includes a first sub-display panel, a second sub-display panel adjacent to the first sub-display panel in a first direction, and a connection member electrically connecting the first sub-display panel to the second sub-display panel. The first sub-display panel includes a first pixel, a second pixel between and adjacent to the first pixel and the second sub-display panel, a first low power voltage line for transferring a power voltage to the first pixel, and a first gate line electrically connected to the first pixel and the second pixel, the second pixel receives the power voltage from the first low power voltage line, the second sub-display panel includes a third pixel adjacent to the first sub-display panel, and the third pixel is electrically connected to the first gate line. | 2022-02-10 |
20220045157 | DISPLAY PANEL, METHOD FOR MANUFACTURING THE SAME, AND DISPLAY DEVICE - A display panel, a method for manufacturing the same and a display device are provided. In a second pixel region of the display panel, there is a first gap between first and second electrical connection elements in a first electrical connection layer, there is a second gap between third and fourth electrical connection elements in a second electrical connection layer, a third electrical connection layer is coupled to a fifth signal line pattern included in each sub-pixel of a corresponding sub-pixel group. The fifth signal line pattern is used to transmit a fifth signal with a fixed electrical potential, and an orthographic projection of the third electrical connection layer onto a substrate of the display panel covers at least part of an orthographic projection of the first gap onto the substrate and at least part of an orthographic projection of the second gap onto the substrate. | 2022-02-10 |
20220045158 | DISPLAY DEVICE - Provided is a display device which comprises a substrate, a plurality of pixels disposed on the substrate, a first initialization voltage line disposed on the substrate along a first direction, and a second initialization voltage line disposed on a different layer from the first initialization voltage line, wherein the second initialization voltage line may include a horizontal portion disposed along the first direction and a vertical portion disposed along a second direction crossing the first direction, and the vertical portion may be disposed between a plurality of pixels adjacent to each other in the first direction. | 2022-02-10 |
20220045159 | DISPLAY APPARATUS - A display apparatus having a display area enlarged to display an image in an area where a component is arranged includes a substrate including a first area having a transmission portion, and a second area surrounding the first area, a first data line extending in a first direction on the second area, and including a first line and a second line spaced from each other with the first area therebetween, a connection line on the second area, adjacent to, and bypassing, the first area, and including an end connected to the first line, and another end connected to the second line, a pixel circuit on the second area, including a thin-film transistor, and a node connection line electrically connected to the thin-film transistor, and a first pixel electrode above the pixel circuit, wherein the connection line is spaced from the node connection line. | 2022-02-10 |
20220045160 | DISPLAY PANEL AND DISPLAY APPARATUS INCLUDING THE SAME - In a display panel having a main display area, a component area including pixel groups spaced apart from each other, and a transmission area between the pixel groups, the display panel includes: a substrate; a plurality of main display elements on the substrate to correspond to the main display area and main pixel circuits respectively connected to the main display elements; auxiliary display elements on the substrate to respectively correspond to the pixel groups and auxiliary pixel circuits respectively connected to the auxiliary display elements; a first data line and a second data line spaced apart from each other with the component area therebetween; and a detour line connecting the first data line to the second data line, wherein the detour line is on a layer that is closer to the substrate than a layer on which the first data line and the second data line are arranged. | 2022-02-10 |
20220045161 | TRANSPARENT OLED DISPLAY PANEL, DISPLAY APPARATUS AND MANUFACTURING METHOD - A transparent OLED display panel, a manufacturing method therefor, and a display apparatus, relate to the field of display technologies. The transparent OLED display panel has a plurality of transparent regions (a) and a plurality of display regions (b), wherein the transparent regions and the display regions are alternately arranged (a) in a first direction. The transparent OLED display panel includes a plurality of pixels ( | 2022-02-10 |
20220045162 | INTERPOSER STRUCTURE AND METHOD FOR MANUFACTURING THEREOF - An interposer structure is provided. The interposer structure includes a plurality of interposer units in an array arrangement from a top view perspective. Each of the interposer units includes a first region and a plurality of second regions. The first region has a capacitor structure. Each of the plurality of second regions is free of the capacitor structure. The first region surrounds the plurality of second regions. A method for manufacturing an interposer structure is also provided. | 2022-02-10 |
20220045163 | Ultra-High Voltage Resistor with Voltage Sense - A semiconductor device includes an active region, a LOCOS region formed within the active region and that extends vertically above a top surface of the active region, a gate region formed above the top surface of the active region, and a polysilicon resistor having a bottom surface that is offset vertically and physically isolated from a top surface of the LOCOS region. The active region includes a source region laterally disposed from the gate region, a drain region laterally disposed from the gate region, and a drift region laterally disposed between the gate region and the drain region. The polysilicon resistor is formed above the drift region. The active region further includes a first charge balance region formed in the active region below the drift region. | 2022-02-10 |
20220045164 | INTEGRATED CIRCUIT DEVICES INCLUDING A VERTICAL FIELD-EFFECT TRANSISTOR AND METHODS OF FORMING THE SAME - Integrated circuit devices and methods of forming the same are provided. Integrated circuit devices may include a first active region including a first vertical field effect transistor (VFET), a second active region including a second VFET, and a diffusion break between the first active region and the second active region on a substrate. The diffusion break may include first and second isolation layers in the substrate and a diffusion break channel region protruding from a portion of the substrate. The portion of the substrate may be between the first isolation layer and the second isolation layer. In some embodiments, the first and second isolation layers may be adjacent to respective opposing sidewalls of the diffusion break channel region. | 2022-02-10 |
20220045165 | CHANNEL CONDUCTION IN SEMICONDUCTOR DEVICES - An example apparatus includes a first source/drain region and a second source/drain region formed in a substrate to form an active area of the apparatus. The first source/drain region and the second source/drain region are separated by a channel. The apparatus includes a gate opposing the channel. A sense line is coupled to the first source/drain region and a storage node is coupled to the second source/drain region. An isolation trench is adjacent to the active area. The trench includes a dielectric material with a conductive bias opposing the conductive bias of the channel in the active area. | 2022-02-10 |
20220045166 | SEMICONDUCTOR DEVICE AND METHOD FOR FABRICATING THE SAME - A semiconductor device and a fabricating method thereof are provided. The semiconductor device includes a substrate, a first nanowire spaced apart from a first region of the substrate, a first gate electrode surrounding a periphery of the first nanowire, a second nanowire spaced apart from a second region of the substrate and extending in a first direction and having a first width in a second direction intersecting the first direction, a supporting pattern contacting the second nanowire and positioned under the second nanowire, and a second gate electrode extending in the second direction and surrounding the second nanowire and the supporting pattern. | 2022-02-10 |
20220045167 | VFET STANDARD CELL ARCHITECTURE WITH IMPROVED CONTACT AND SUPER VIA - A cell architecture for vertical field-effect transistors (VFETs) is provided. The cell architecture includes: top source/drain (S/D) contact structure having a square shape in a plan view; and horizontal metal patterns formed on the top S/D contact structures and extended in an X-direction to be connected to a vertical pattern through with an output signal of a logic circuit formed by the VFETs. The cell architecture further includes a gate contact structure formed on a gate connection pattern connecting gates of the VFETs, wherein a super via is formed on the gate contact structure to receive an input signal of the logic circuit. | 2022-02-10 |
20220045168 | INSULATED TRENCH GATES WITH DOPANTS IMPLANTED THROUGH GATE OXIDE - In an insulated trench gate device, polysilicon in the trench is etched below the top surface of the trench, leaving a thin gate oxide layer exposed near the top of the trench. An angled implant is conducted that implants dopants through the exposed gate oxide and into the side of the trench. If the implanted dopants are n-type, this technique may be used to extend an n+ source region to be below the top of the polysilicon in the trench. If the implanted dopants are p-type, the dopants may be used to form a p-MOS device that turns on when the polysilicon is biased with a negative voltage. P-MOS and n-MOS devices can be formed in a single cell using this technique, where turning on the n-MOS device turns on a vertical power switch, and turning on the p-MOS device turns off the power switch. | 2022-02-10 |
20220045169 | SOURCE/DRAIN EPI STRUCTURE FOR DEVICE BOOST - A method includes providing a substrate, a semiconductor fin extending from the substrate, and a gate structure over the substrate and engaging the semiconductor fin; etching the semiconductor fin to form a source/drain trench; and epitaxially growing a source/drain feature in the source/drain trench, which includes epitaxially growing a first semiconductor layer having silicon germanium (SiGe); epitaxially growing a second semiconductor layer having SiGe above the first semiconductor layer; epitaxially growing a third semiconductor layer having SiGe over the second semiconductor layer; and epitaxially growing a fourth semiconductor layer having SiGe and disposed at a corner portion of the source/drain feature where the source/drain feature has a largest lateral dimension. Each of the first, second, third, and fourth semiconductor layers includes a p-type dopant, and the fourth semiconductor layer has a higher dopant concentration of the p-type dopant than each of the first, second, and third semiconductor layers. | 2022-02-10 |
20220045170 | SEMICONDUCTOR DEVICE AND METHOD FOR FABRICATING THE SAME - A method for fabricating semiconductor device includes the steps of: forming a gate structure on a substrate; forming a spacer around the gate structure; and forming a buffer layer adjacent to the gate structure. Preferably, the buffer layer includes a crescent moon shape and the buffer layer includes an inner curve, an outer curve, and a planar surface connecting the inner curve and an outer curve along a top surface of the substrate, in which the planar surface directly contacts the outer curve on an outer sidewall of the spacer. | 2022-02-10 |
20220045171 | SEMICONDUCTOR DEVICE - Among multiple drain regions, a contact surface area between second contacts and a drain region most proximal to a central portion of an element region in a second direction is less than a contact surface area between second contacts and a drain region disposed on an outermost side of the element region in the second direction. The multiple drain regions are arranged in the second direction. | 2022-02-10 |
20220045172 | SILICON CARBIDE SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD OF SILICON CARBIDE SEMICONDUCTOR DEVICE - A silicon carbide semiconductor device includes a substrate, a drift layer disposed above the substrate, a base region disposed above the drift layer, a source region disposed above the base region, a gate trench formed deeper than the base region from a surface of the source region, a gate insulating film covering an inner wall surface of the gate trench, a gate electrode disposed on the gate insulating film, an interlayer insulating film covering the gate electrode and the gate insulating film and having a contact hole, a source electrode brought in ohmic contact with the source region through the contact hole, and a drain electrode disposed to a rear surface of the substrate. The source region has a lower impurity concentration on a side close to the base region than on a surface side brought in ohmic contact with the source region. | 2022-02-10 |
20220045173 | SEMICONDUCTOR DEVICE WITH STRAIN RELAXED LAYER - A semiconductor device includes an epitaxial substrate. The epitaxial substrate includes a substrate. A strain relaxed layer covers and contacts the substrate. A III-V compound stacked layer covers and contacts the strain relaxed layer. The III-V compound stacked layer is a multilayer epitaxial structure formed by aluminum nitride, aluminum gallium nitride or a combination of aluminum nitride and aluminum gallium nitride. | 2022-02-10 |
20220045174 | HORIZONTAL CURRENT BIPOLAR TRANSISTOR WITH SILICON-GERMANIUM BASE - A semiconductor device including a Horizontal Current Bipolar Transistor (HCBT) and methods of manufacture. The device has a semiconductor substrate of a first conductivity type defining a wafer plane parallel to the semiconductor substrate and has a base region and a collector region forming a first metallurgical junction. The device also has an emitter region forming a second metallurgical junction with the base region. A flat portion of the first metallurgical junction and a flat portion of the second metallurgical junction are substantially parallel to each other and close an acute angle with the wafer plane. At least a portion of the base region comprises silicon-germanium alloy or silicon-germanium-carbon alloy. | 2022-02-10 |
20220045175 | SEMICONDUCTOR DEVICE, INVERTER CIRCUIT, DRIVE, VEHICLE, AND ELEVATOR - A semiconductor device according to embodiments includes a gate electrode; a gate insulating layer; and a silicon carbide layer having a first plane and a second plane facing the first plane, the silicon carbide layer including a first silicon carbide region of p-type and a second silicon carbide region positioned between the first silicon carbide region and the gate insulating layer, and the second silicon carbide region including at least one oxygen atom bonded to four silicon atoms. | 2022-02-10 |
20220045176 | 2d-Channel Transistor Structure with Source-Drain Engineering - Semiconductor devices and methods of forming the same are provided. A method includes providing a workpiece having a semiconductor structure; depositing a two-dimensional (2D) material layer over the semiconductor structure; forming a source feature and a drain feature electrically connected to the semiconductor structure and the 2D material layer, wherein the source feature and drain feature include a semiconductor material; and forming a gate structure over the two-dimensional material layer and interposed between the source feature and the drain feature. The gate structure, the source feature, the drain feature, the semiconductor structure and the 2D material layer are configured to form a field-effect transistor. The semiconductor structure and the 2D material layer function, respectively, as a first channel and a second channel between the source feature and the drain feature. | 2022-02-10 |
20220045177 | EPITAXIAL SUBSTRATE - There is provided an epitaxial substrate, including: a GaN substrate whose main surface is a c-plane; and a GaN layer epitaxially grown on the main surface, wherein the main surface includes a region where an off-angle is 0.4° or more, and an E3 trap concentration in the GaN layer grown on the region is 3.0×10 | 2022-02-10 |
20220045178 | GATE ELECTRODE DEPOSITION AND STRUCTURE FORMED THEREBY - A method includes depositing a first work function tuning layer over a gate dielectric layer using an atomic layer deposition process. The atomic layer deposition process comprises depositing one or more first nitride monolayers; and depositing one or more carbide monolayers over the one or more first nitride monolayers. The method further includes depositing an adhesion layer of the first work function tuning layer; and depositing a conductive material over the adhesion layer. | 2022-02-10 |
20220045179 | SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD THEREOF - The present disclosure provides a semiconductor device and a manufacturing method thereof. The manufacturing method comprises: providing a substrate comprising a storage region, forming stacked gates of storage transistors on the substrate; forming side walls on two sides of each stacked gate wherein the top surfaces of side walls are arranged to be lower than the top surfaces of the stacked gates; performing ion implantation in the storage region defined by the side walls; and performing an ashing process and a wet cleaning process using the side walls as protective layers of the stacked gates to remove a photoresist remaining after the ion implantation. The present disclosure further provides a semiconductor device formed according to the manufacturing method. According to the semiconductor device and the manufacturing method thereof, the problem of stacked gate collapse from the ion implantation process can be solved, thereby improving the yield. | 2022-02-10 |
20220045180 | THIN-FILM TRANSISTOR FOR ELECTRO-STATIC DISCHARGE (ESD) PROTECTION AND ESD PROTECTION STRUCTURE - A thin-film transistor for electro-static discharge (ESD) protection and an ESD protection structure are provided. The thin-film transistor for ESD protection includes a substrate; an active layer disposed on the substrate; a gate insulating layer disposed on the active layer and on the substrate; a gate electrode disposed on the gate insulating layer and opposite to the active layer; an interlayer insulating layer disposed on the gate electrode and on the gate insulating layer; and a source electrode and a drain electrode disposed on the interlayer insulating layer and spaced apart. The source electrode has first ESD peaks, and the drain electrode has second ESD peaks facing first ESD peaks. The thin-film transistor for ESD protection has a thin-film transistor ESD path and a peak ESD path by disposing opposite ESD peaks on the source and drain electrodes, improving ESD efficiency, preventing circuits from being burnt, and guaranteeing product yield. | 2022-02-10 |
20220045181 | SEMICONDUCTOR DEVICE AND METHOD OF FORMING SAME - A semiconductor device and a method of forming the device are disclosed. In the semiconductor device, a shielded gate trench field effect transistor (FET) is formed in a cell region, and a super barrier rectifier (SBR) is formed in a non-cell region. In the SBR, a second dielectric layer has an upper dielectric layer and a lower dielectric layer, which are joined to each other smoothly by virtue of a beak-like portion. This avoids the presence of any sharp corner between the upper and lower dielectric layers and effectively mitigates the problem of an excessively small thickness of the upper dielectric layer at a bottom portion thereof, which tends to cause current leakage. | 2022-02-10 |
20220045182 | SEMICONDUCTOR MEMORY DEVICE AND METHOD FOR MANUFACTURING THE SAME - A semiconductor memory device includes a substrate having a first active pattern including first and second source/drain regions, a gate electrode intersecting the first active pattern and disposed between the first and second source/drain regions, a bit line intersecting the first active pattern and electrically connected to the first source/drain region, a spacer disposed on a sidewall of the bit line, a contact electrically connected to the second source/drain region and spaced apart from the bit line with the spacer interposed therebetween, an interface layer disposed between the second source/drain region and the contact, and forming an ohmic contact between the second source/drain region and the contact, and a data storage element disposed on the contact. A bottom of the contact is lower than a top surface of the substrate. The contact is formed of a metal, a conductive metal nitride, and/or a combination thereof. | 2022-02-10 |
20220045183 | SHIELD GATE TRENCH POWER DEVICE AND METHOD FOR MAKING THE SAME - A shield gate trench power device, wherein a shield dielectric layer is formed by stacking a thermal oxide layer and a CVD dielectric layer on the inner side surface of a gate trench; a gap region formed by means of filling with the shield dielectric layer is filled with source polysilicon; a top trench is formed on two sides of the source polysilicon by etching a portion of the shield dielectric layer close to the side surface of the gate trench, and the entire top trench is located in the thermal oxide layer; the top trench is filled with a polysilicon gate. A method for manufacturing a shield gate trench power device. The uniformity of the thickness of the shield dielectric layer on the sidewall and bottom of the gate trench can be improved. | 2022-02-10 |
20220045184 | SHIELDED GATE TRENCH MOSFET WITH ESD DIODE MANUFACTURED USING TWO POLY-SILICON LAYERS PROCESS - A SGT MOSFET having ESD diode and a method of manufacturing the same are disclosed. The SGT trench MOSFET according to the present invention, has n+ doped gate shielded electrodes in an N channel device and requires only two poly-silicon layers, making the device can be shrunk with reducing shielded gate width for Rds reduction without increasing switching loss and having dynamic switching instability. | 2022-02-10 |
20220045185 | SEMICONDUCTOR DEVICE - The present disclosure provides a semiconductor device. The semiconductor device comprises a substrate, a plurality of isolation regions in the substrate and an active region surrounded by the isolation regions. A p-type doped region is interposed between two n-type doped regions in the substrate. A buried gate structure is formed in the substrate and disposed between the p-type doped region and the n-type doped region. The buried gate structure comprises a gate conductive material, a gate insulating layer disposed over the gate conductive material and a gate liner surrounding the gate conductive material and the gate insulating layer. A plurality of contact plugs are formed on the p-type doped region and the plurality of n-type doped regions. | 2022-02-10 |
20220045186 | SEMICONDUCTOR STRUCTURE AND METHOD FOR MANUFACTURING SAME - A semiconductor structure includes: a substrate with conductive contact regions; a bit line structure and an isolation wall located on a sidewall of the bit line structure, the isolation wall includes at least one isolation layer including a first isolation part close to the bit line structure and a second isolation part deviating from the same, the second isolation part has doped ions, such that it has a greater hardness than the first isolation part, or has a smaller dielectric constant than the first isolation part; and a capacitor contact hole, which exposes the conductive contact region, and has a top width greater than a bottom width in a direction parallel to an orientation of the bit line structure. | 2022-02-10 |
20220045187 | SEMICONDUCTOR DEVICE AND METHOD FOR FABRICATING THE SAME - The present application discloses a method for fabricating a semiconductor device with a flat surface. The method for fabricating a semiconductor device including providing a substrate, forming a gate structure on the substrate, and forming a plurality of word lines having top surfaces at a same vertical level as a top surface of the gate structure. | 2022-02-10 |
20220045188 | CONTACT STRUCTURES IN SEMICONDUCTOR DEVICES - A semiconductor device with different configurations of contact structures and a method of fabricating the same are disclosed. The semiconductor device includes first and second gate structures disposed on first and second fin structures, first and second source/drain (S/D) regions disposed on the first and second fin structures, first and second contact structures disposed on the first and second S/D regions, and a dipole layer disposed at an interface between the first nWFM silicide layer and the first S/D region. The first contact structure includes a first nWFM silicide layer disposed on the first S/D region and a first contact plug disposed on the first nWFM silicide layer. The second contact structure includes a pWFM silicide layer disposed on the second S/D region, a second nWFM silicide layer disposed on the pWFM silicide layer, and a second contact plug disposed on the pWFM silicide layer. | 2022-02-10 |
20220045189 | INSULATED TRENCH GATES WITH MULTIPLE LAYERS FOR IMPROVED PERFORMANCE OF SEMICONDUCTOR DEVICES - Trenches having a gate oxide layer are formed in the surface of a silicon wafer for vertical gates. Conductive doped polysilicon is then deposited in the trenches to form a relatively thin layer of doped polysilicon along the sidewalls. Thus, there is a central cavity surrounded by polysilicon. Next, the cavity is filled in with a much higher conductivity material, such as aluminum, copper, a metal silicide, or other conductor to greatly reduce the overall resistivity of the trenched gates. The thin polysilicon forms an excellent barrier to protect the gate oxide from diffusion from the inner conductor atoms. The inner conductor and the polysilicon conduct the gate voltage in parallel to lower the resistance of the gates, which increases the switching speed of the device. In another embodiment, a metal silicide is used as the first layer, and a metal fills the cavity. | 2022-02-10 |
20220045190 | METHOD OF MANUFACTURING SEMICONDUCTOR DEVICES AND SEMICONDUCTOR DEVICES - In a method of manufacturing a semiconductor device, a gate dielectric layer is formed over a channel region made of a semiconductor material, a first barrier layer is formed on the gate dielectric layer, a second barrier layer is formed on the first barrier layer, a first work function adjustment layer is formed on the second barrier layer, the first work function adjustment layer and the second barrier layer are removed. After the first work function adjustment layer and the second barrier layer are removed, a second work function adjustment layer is formed over the gate dielectric layer, and a metal gate electrode layer is formed over the second work function adjustment layer. | 2022-02-10 |
20220045191 | SEMICONDUCTOR DEVICE - A semiconductor device includes a stacked structure having channel formation region layers CH | 2022-02-10 |
20220045192 | METAL OXIDE INTERLAYER STRUCTURE FOR nFET AND pFET - The present disclosure provides a method of forming a semiconductor device including an nFET structure and a pFET structure where each of the nFET and pFET structures include a semiconductor substrate and a gate trench. The method includes depositing an interfacial layer in each gate trench; depositing a first metal oxide layer over the interfacial layer; removing the first metal oxide layer from the pFET structure; depositing a ferroelectric layer in each gate trench; depositing a second metal oxide layer over the ferroelectric layer; removing the second metal oxide layer from the nFET structure; and depositing a gate electrode in each gate trench. | 2022-02-10 |
20220045193 | NANOSHEET TRANSISTOR WITH ASYMMETRIC GATE STACK - Embodiments of the present invention are directed to methods and resulting structures for nanosheet devices having asymmetric gate stacks. In a non-limiting embodiment of the invention, a nanosheet stack is formed over a substrate. The nanosheet stack includes alternating semiconductor layers and sacrificial layers. A sacrificial liner is formed over the nanosheet stack and a dielectric gate structure is formed over the nanosheet stack and the sacrificial liner. A first inner spacer is formed on a sidewall of the sacrificial layers. A gate is formed over channel regions of the nanosheet stack. The gate includes a conductive bridge that extends over the substrate in a direction orthogonal to the nanosheet stack. A second inner spacer is formed on a sidewall of the gate. The first inner spacer is formed prior to the gate stack, while the second inner spacer is formed after, and consequently, the gate stack is asymmetrical. | 2022-02-10 |
20220045194 | SEMICONDUCTOR DEVICE STRUCTURE WITH INNER SPACER LAYER - A semiconductor device structure is provided. The semiconductor device includes a first nanowire structure over a second nanowire structure, a gate stack wrapping around the first nanowire structure and the second nanowire structure, a source/drain feature adjoining the first nanowire structure and the second nanowire structure, a gate spacer layer over the first nanowire structure and between the gate stack and the source/drain feature, and an inner spacer layer between the first nanowire structure and the second nanowire structure and between the gate stack and the source/drain feature. The gate spacer layer has a first carbon concentration, the inner spacer has a second carbon concentration, and the second carbon concentration is lower than the first carbon concentration. | 2022-02-10 |
20220045195 | SEMICONDUCTOR CONTACT FORMATION - Systems, methods and apparatus are provided for a semiconductor structure. An example method includes a method for forming a contact surface on a vertically oriented access devices. The method includes forming a first source/drain region and a second source/drain region vertically separated by a channel region, forming a sacrificial etch stop layer on a first side of the second source/drain region, wherein the channel region is in contact with a second side of the second source/drain region, forming a dielectric layer on a first side of the sacrificial etch stop layer, where the second source/drain region is connected to a second side of the sacrificial etch stop layer, removing the dielectric layer using a first etch process to expose the sacrificial etch stop layer, and removing the sacrificial etch stop layer using a second etch process to form a contact surface on the second source/drain region. | 2022-02-10 |
20220045196 | UNIFORM INTERFACIAL LAYER ON VERTICAL FIN SIDEWALLS OF VERTICAL TRANSPORT FIELD-EFFECT TRANSISTORS - A method of forming a semiconductor structure includes patterning a hard mask layer over a top surface of a substrate. The method also includes forming a first portion of one or more vertical fins below the patterned hard mask layer. The method further includes forming a top spacer on sidewalls of the hard mask layer and the first portion of the one or more vertical fins. The method further includes forming a second portion of the one or more vertical fins in the substrate below the top spacer and trimming sidewalls of the second portion of the one or more vertical fins. The method further includes forming an interfacial layer on the trimmed sidewalls of the second portion of the one or more vertical fins. The one or more vertical fins provide one or more vertical transport channels for one or more vertical transport field-effect transistors. | 2022-02-10 |
20220045197 | METHOD OF FORMING A SEMICONDUCTOR STRUCTURE - A method for forming a semiconductor structure includes: providing a structure including a substrate and a target layer disposed on the substrate, and the target layer includes a central area and a periphery area; forming a plurality of linear fin features within the central area in which the linear fin features are substantially parallel to each other and include edge imbalance portions; and removing the edge imbalance portions of the linear fin features to obtain linear uniform fin features. | 2022-02-10 |
20220045198 | SOURCE/DRAIN STRUCTURE FOR SEMICONDUCTOR DEVICE - The present disclosure describes a semiconductor structure and a method for forming the same. The method can include forming a fin structure over a substrate. The fin structure can include a channel layer and a buffer layer between the channel layer and the substrate. The method can further include forming a recess structure in the channel layer. The recess structure can include a bottom surface over the buffer layer. The method can further include forming a first epitaxial layer over the bottom surface of the recess structure. The first epitaxial layer can include a first atomic concentration of germanium. The method can further include forming a second epitaxial layer over the first epitaxial layer. The second epitaxial layer can include a second atomic concentration of germanium greater than the first atomic concentration of germanium. | 2022-02-10 |
20220045199 | Controlling Fin-Thinning Through Feedback - A method includes forming isolation regions extending into a semiconductor substrate. A semiconductor strip is between the isolation regions. The method further includes recessing the isolation regions so that a top portion of the semiconductor strip protrudes higher than top surfaces of the isolation regions to form a semiconductor fin, measuring a fin width of the semiconductor fin, generating an etch recipe based on the fin width, and performing a thinning process on the semiconductor fin using the etching recipe. | 2022-02-10 |
20220045200 | Semiconductor Device Including a Plurality of Trenches - A semiconductor device is proposed. The semiconductor device includes a plurality of trenches extending into in a semiconductor body from a first main surface. A first group of the plurality of trenches includes a gate electrode. A second group of the plurality of trenches includes a source electrode. A third group of the plurality of trenches includes an auxiliary electrode. The source electrode is electrically coupled to a source contact area via a source wiring line and the auxiliary electrode. The source wiring line and the auxiliary electrode are electrically connected in series between the source contact area and the source electrode. | 2022-02-10 |
20220045201 | SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD - A semiconductor device including a semiconductor substrate; a trench formed in a front surface of the semiconductor substrate; a gate conducting portion formed within the gate trench; and a first region formed adjacent to the trench in the front surface of the semiconductor substrate and having a higher impurity concentration than the semiconductor substrate. A shoulder portion is provided on a side wall of the gate trench between the top end of the gate conducting portion and the front surface of the semiconductor substrate and has an average slope, relative to a depth direction of the semiconductor substrate, that is greater than a slope of the side wall of the gate trench at a position opposite the top end of the gate conducting portion, and a portion of the first region that contacts the gate trench is formed as a deepest portion thereof | 2022-02-10 |
20220045202 | SEMICONDUCTOR DEVICE - According to one embodiment, a semiconductor device includes first to third electrodes, first and second semiconductor layers, and an insulating member. The third electrode in a first direction is between the first and second electrodes in the first direction. The first direction is from the first toward second electrode. The first semiconductor layer includes Al | 2022-02-10 |
20220045203 | SEMICONDUCTOR DEVICE - A semiconductor device includes an enhancement mode high electron mobility transistor (HEMT) with an active region and an isolation region. The HEMT includes a substrate, a group III-V body layer, a group III-V barrier layer, a group III-V gate structure and a group III-V patterned structure. The group III-V body layer and the group III-V barrier layer are disposed on the substrate. The group III-V gate structure is disposed on the group III-V barrier layer within the active region. The group III-V patterned structure is disposed on the group III-V barrier layer within the isolation region. The composition of the group III-V patterned structure is the same as the composition of the group III-V gate structure. | 2022-02-10 |
20220045204 | SILICON CARBIDE SEMICONDUCTOR DEVICE AND POWER CONVERTER - In an SiC-MOSFET with a built-in Schottky diode, a bipolar current may be passed in a second well region formed at a terminal part to reduce the breakdown voltage of the terminal part. In the SiC-MOSFET with the built-in Schottky diode, a source electrode forming non-ohmic connection such as Schottky connection with the second well region is provided on the second well region formed below a gate pad in the terminal part. By the absence of ohmic connection between the second well region and the source electrode, reduction in breakdown voltage is suppressed at the terminal part. | 2022-02-10 |
20220045205 | TRENCH GATE POWER SWITCH WITH DOPED REGIONS TO INDUCE BREAKDOWN AT SELECTED AREAS - A power device is divided into an active area, an active area perimeter, and a termination region. An array of insulated gates formed in trenches form cells in a p-well body, where n+ source regions are formed in the top surface of the silicon wafer and surround the tops of the trenches. A top cathode electrode contacts the source regions, and an anode electrode is on the bottom of the die. A sufficiently high reverse voltage causes a breakdown current to flow between the anode and cathode electrodes. To ensure that a reverse breakdown voltage current occurs away from the gate oxide and/or the termination region, the active area and the active area perimeter of the p-well are additionally doped with p-type dopants to form deep p+ regions in selected areas that extend below the trenches. The deep p+ regions channel the breakdown current away from active cells and the termination region. | 2022-02-10 |
20220045206 | SEMICONDUCTOR DEVICES WITH LOW RESISTANCE GATE AND SHIELD ELECTRODES AND METHODS - A semiconductor device includes a region of semiconductor material and a trench gate structure. The trench gate structure includes an active trench, a shield dielectric layer in a lower portion of the active trench, and a shield electrode of a first polycrystalline semiconductor material adjacent to the shield dielectric layer. A gate dielectric layer is adjacent to an upper portion of the active trench and a gate electrode of a second polycrystalline semiconductor material is adjacent to the gate dielectric layer. A shield conductive layer of a first conductive material is adjacent to the shield electrode and a gate conductive layer of the first conductive material is adjacent to the gate electrode. A dielectric fill structure is in the active trench electrically isolating the gate electrode and the gate conductive layer from the shield electrode and the shield conductive layer. In some examples, the semiconductor device includes a trench shield contact structure that includes the shield conductive layer. | 2022-02-10 |
20220045207 | SEMICONDUCTOR DEVICE AND METHOD FOR MANUFACTURING SEMICONDUCTOR DEVICE - The present application relates to a semiconductor device, comprising a substrate, with a body region being formed on the substrate, and a well region being formed in the body region; and further comprising trenches penetrating through the well region and the body region and extending to the substrate, wherein a first polysilicon body and a second polysilicon body, which are isolated from each other, are respectively formed at the bottom and the top of each trench to form a split gate structure, the trenches are filled with an inter-layer dielectric layer, a conductive plug penetrating through the inter-layer dielectric layer and extending into the first polysilicon body is formed in each trench, the conductive plug is isolated from the second polysilicon body by means of the inter-layer dielectric layer, the conductive plug is connected to a source electrode, and the second polysilicon body is connected to a gate electrode. | 2022-02-10 |
20220045208 | SEMICONDUCTOR DEVICE - A semiconductor device includes a semiconductor layer, an insulation gate-type first transistor which is formed in the semiconductor layer, an insulation gate-type second transistor which is formed in the semiconductor layer, and a control wiring which is formed on the semiconductor layer such as to be electrically connected to the first transistor and the second transistor, and transmits control signals that control the first transistor and the second transistor to be in ON states in a normal operation and that control the first transistor to be in an OFF state and the second transistor to be in an ON state in an active clamp operation. | 2022-02-10 |
20220045209 | TRANSISTOR DEVICE HAVING A SOURCE REGION SEGMENTS AND BODY REGION SEGMENTS - In one general aspect, an apparatus can include a first trench disposed in a semiconductor region and including a gate electrode and a second trench disposed in the semiconductor region. The apparatus can include a mesa region disposed between the first trench and the second trench. The apparatus can include a source region segment of a first conductivity type disposed in a first side of the mesa region where the source region segment is included in a plurality of source region segments and where the plurality of source region segments are aligned along the longitudinal axis. The apparatus can include a body region segment of a second conductivity type disposed in a second side of the mesa region opposite the first side of the mesa region and having a portion disposed above the source region segment where the body region segment is included in a plurality of body region segments. | 2022-02-10 |
20220045210 | METHOD FOR FABRICATING SHIELD GATE MOSFET - A method for fabricating a shield gate MOSFET includes forming an epitaxial layer having a first conductivity type, forming a plurality of trenches in the epitaxial layer, forming a first and a second doped regions in the epitaxial layer at a bottom of each of the trenches, wherein the first doped region has a second conductivity type, and the second doped region has the first conductivity type. An insulating layer and a conductive layer as a shield gate are orderly formed in each of the trenches, and a portion of the conductive layer and the insulating layer are removed to expose a portion of the epitaxial layer in the trenches. An inter-gate oxide layer and a gate oxide layer are formed in the trenches, and a control gate is formed on the inter-gate oxide layer in the plurality of trenches. | 2022-02-10 |
20220045211 | SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD FOR THE SAME - A semiconductor device including a semiconductor element is provided. The semiconductor element includes a saturation current suppression layer formed above a drift layer and including electric field block layers arranged in a stripe manner and JFET portions arranged in a stripe manner. The electric field block layers and the JFET portions are alternately arranged. The semiconductor element includes trench gate structures. A longer direction of the trench gate structure intersects with a longer direction of the electric field block layer and a longer direction of JFET portion. The JFET portion includes a first layer having a first conductivity type impurity concentration larger than the drift layer and a second layer formed above the first layer and having a first conductivity type impurity concentration smaller than the first layer. | 2022-02-10 |
20220045212 | SEMICONDUCTOR DEVICE WITH PROGRAMMABLE ELEMENT AND METHOD FOR FABRICATING THE SAME - The present application discloses a semiconductor device and a method for fabricating the semiconductor device. The semiconductor device includes a substrate, a channel region positioned in the substrate, first impurity regions positioned in the substrate and respectively positioned on two ends of the channel region, a gate dielectric layer positioned on the channel region, a gate bottom conductive layer positioned on the gate dielectric layer, first contacts respectively positioned on the first impurity regions, programmable insulating layers respectively positioned on the first contacts, a top conductive layer positioned on the programmable insulating layers and electrically coupled to the gate bottom conductive layer. | 2022-02-10 |
20220045213 | Silicon Carbide Power Device with MOS Structure and Stressor - A silicon carbide power device, e.g., a vertical power MOSFET or an IGBT, includes a silicon carbide wafer. A first stressor and a second stressor are arranged in the silicon carbide wafer at a first main side. A first channel region, a first portion of a drift layer and a second channel region are laterally arranged between the first stressor and the second stressor in a second lateral direction parallel to the first main side and perpendicular to the first lateral direction. A stress can be introduced by the first stressor and the second stressor in the first channel region and in the second channel region. | 2022-02-10 |
20220045214 | Passivated and Faceted for Fin Field Effect Transistor - A fin field effect transistor (FinFET), and a method of forming, is provided. The FinFET has a fin having one or more semiconductor layers epitaxially grown on a substrate. A first passivation layer is formed over the fins, and isolation regions are formed between the fins. An upper portion of the fins are reshaped and a second passivation layer is formed over the reshaped portion. Thereafter, a gate structure may be formed over the fins and source/drain regions may be formed. | 2022-02-10 |
20220045215 | SEMICONDUCTOR DEVICE - A semiconductor device includes a substrate; first and second fins protruding from the substrate; a first transistor including the first fin; a second transistor above the first transistor; and a first power supply line electrically connected to the first fin through the second fin. The first transistor includes first and second impurity areas in the first fin, and a first gate insulating film on the first fin between the first and second impurity areas. The second transistor includes a first semiconductor area above the first fin, a third impurity area in the first semiconductor area above the first impurity area, a fourth impurity area in the first semiconductor area above the second impurity area, and a second gate insulating film on the first semiconductor area between the third and fourth impurity areas. The first and second transistors have a common gate on the first and second gate insulating films. | 2022-02-10 |
20220045216 | SEMICONDUCTOR DEVICE - A semiconductor device including a first oxide semiconductor layer, a first gate electrode opposing the first oxide semiconductor layer, a first gate insulating layer between the first oxide semiconductor layer and the first gate electrode, a first insulating layer covering the first oxide semiconductor layer and having a first opening, a first conductive layer above the first insulating layer and in the first opening, the first conductive layer being electrically connected to the first oxide semiconductor layer, and an oxide layer between an upper surface of the first insulating layer and the first conductive layer, wherein the first insulating layer is exposed from the oxide layer in a region not overlapping the first conductive layer in a plan view. | 2022-02-10 |