06th week of 2022 patent applcation highlights part 57 |
Patent application number | Title | Published |
20220044917 | SUBSTRATE TREATING APPARATUS AND SUBSTRATE SUPPORT UNIT - The inventive concept relates to a substrate support unit provided in an apparatus for treating a substrate using plasma. In an embodiment, the substrate support unit includes a dielectric plate on which the substrate is placed, a lower electrode that is disposed under the dielectric plate and that has a first diameter, a power supply rod that applies RF power to the lower electrode and has a second diameter, and a ground member disposed under the lower electrode and spaced apart from the lower electrode by a first gap by an insulating member, the ground member including a plate portion having a through-hole formed therein through which the power supply rod passes, in which the through-hole has a third diameter. | 2022-02-10 |
20220044918 | MULTI-PATTERNED SPUTTER TRAPS AND METHODS OF MAKING - A method of forming a particle trap on a sputtering chamber component comprises forming a first pattern on at least a portion of a surface of the sputtering chamber component to form a first patterned top surface, and forming a second pattern on at least a portion of the first patterned top surface. | 2022-02-10 |
20220044919 | GAS ANALYZER APPARATUS - There is provided a gas analyzer apparatus including: a sample chamber which is equipped with a dielectric wall structure and into which only sample gas to be measured is introduced; a plasma generation mechanism that generates plasma inside the sample chamber, which has been depressurized, using an electric field and/or a magnetic field applied through the dielectric wall structure; and an analyzer unit that analyzes the sample gas via the generated plasma. By doing so, it is possible to provide a gas analyzer apparatus capable of accurately analyzing sample gases, even those including corrosive gas, over a long period of time. | 2022-02-10 |
20220044920 | SPUTTERING APPARATUS AND FILM FORMING METHOD - A sputtering apparatus includes a first target and a second target that emit sputter particles, a substrate support configured to support a substrate, and a slit plate disposed between the first and the second targets and the substrate and having a slit unit through which the sputter particles pass. The slit unit includes a first slit to the first and the second target side and a second slit to the substrate side. The second slit has a first protrusion and a second protrusion protruding toward the center of the second slit. When the slit unit is viewed from the first target, the first protrusion is hidden. When the slit unit is viewed from the second target, the second protrusion is hidden. | 2022-02-10 |
20220044921 | METHODS AND SYSTEMS FOR DETECTING AEROSOL PARTICLES - Disclosed are systems are methods for identifying the composition of single aerosol particles, particularly that of bioaerosol particles. A continuous timing laser tightly coupled with a pulse ionization laser is used to index aerosol particles, measure particle properties, and trigger the ionization laser to fire when each particle enters the beam of the trigger laser. Ionized fragments and optionally photons produced when each particle is struck by the ionization laser are analyzed using one or more detectors including a TOF-MS detector and an optical detector. Individual single particle spectra are aligned and denoised prior to averaging. | 2022-02-10 |
20220044922 | METHODS FOR FORMING DIELECTRIC MATERIALS WITH SELECTED POLARIZATION FOR SEMICONDUCTOR DEVICES - Dielectric films for semiconductor devices and methods of forming. A processing method includes forming a first film of a first dielectric material on a substrate by performing a first plurality of cycles of atomic layer deposition and, thereafter, heat-treating the first film, where a thickness of the first film is below a threshold thickness needed for spontaneous polarization in the first dielectric material. The processing method further includes forming a second film of a second dielectric material on the substrate by performing a second plurality of cycles of atomic layer deposition and, thereafter, heat-treating the second film, where a thickness of the second film is greater than the thickness of the first film, and the second film is ferroelectric or antiferroelectric. The first and second dielectric materials can include at least one metal oxide, for example zirconium oxide, hafnium oxide, or a laminate or mixture thereof. | 2022-02-10 |
20220044923 | FORMATION OF SiN THIN FILMS - Methods of forming silicon nitride thin films on a substrate in a reaction space under high pressure are provided. The methods can include a plurality of plasma enhanced atomic layer deposition (PEALD) cycles, where at least one PEALD deposition cycle comprises contacting the substrate with a nitrogen plasma at a process pressure of 20 Torr to 500 Torr within the reaction space. In some embodiments the silicon precursor is a silyly halide, such as H | 2022-02-10 |
20220044924 | SEMICONDUCTOR STRUCTURE PROCESSING METHOD AND MANUFACTURING METHOD - This application relates to a semiconductor structure processing method, including: providing a semiconductor layer including a pattern, where a trench is located amongst the pattern; cleaning the pattern using a rinse liquid, where the rinse liquid fills the trench after the cleaning; forming a flexible layer, where the flexible layer displaces the rinse liquid and fills the trench, and covers a surface of the semiconductor layer; and hardening the flexible layer and subsequently removing the flexible layer. | 2022-02-10 |
20220044925 | SUBSTRATE TREATMENT APPARATUS AND MANUFACTURING METHOD OF SEMICONDUCTOR DEVICE - In a manufacturing method of a semiconductor device according to one embodiment, a first gas containing a first metal element is introduced into a chamber having a substrate housed therein. Next, the first gas is discharged from the chamber using a purge gas. Subsequently, a second gas reducing the first gas is introduced into the chamber. Next, the second gas is discharged from the chamber using the purge gas. Further, a third gas different from the first gas, the second gas, and the purge gas is introduced into the chamber at least either at a time of discharging the first gas or at a time of discharging the second gas. | 2022-02-10 |
20220044926 | DEPOSITION OF LOW-STRESS CARBON-CONTAINING LAYERS - Examples of the present technology include semiconductor processing methods that provide a substrate in a substrate processing region of a substrate processing chamber, where the substrate is maintained at a temperature less than or about 50° C. An inert precursor and a hydrocarbon-containing precursor may be flowed into the substrate processing region of the substrate processing chamber, where a flow rate ratio of the inert precursor to the hydrocarbon-containing precursor may be greater than or about 10:1. A plasma may be generated from the inert precursor and the hydrocarbon-containing precursor, and a carbon-containing material may be deposited from the plasma on the substrate. The carbon-containing material may include diamond-like-carbon, and may have greater than or about 60% of the carbon atoms with sp | 2022-02-10 |
20220044927 | DEPOSITION OF LOW-STRESS BORON-CONTAINING LAYERS - Examples of the present technology include semiconductor processing methods to form boron-containing materials on substrates. Exemplary processing methods may include delivering a deposition precursor that includes a boron-containing precursor to a processing region of a semiconductor processing chamber. A plasma may be formed from the deposition precursor within the processing region of the semiconductor processing chamber. The methods may further include depositing a boron-containing material on a substrate disposed within the processing region of the semiconductor processing chamber, where the substrate is characterized by a temperature of less than or about 50° C. The as-deposited boron-containing material may be characterized by a surface roughness of less than or about 2 nm, and a stress level of less-than or about −500 MPa. In some embodiments, a layer of the boron-containing material may function as a hardmask. | 2022-02-10 |
20220044928 | SILICON COMPOUNDS AND METHODS FOR DEPOSITING FILMS USING SAME - A chemical vapor deposition method for producing a dielectric film, the method comprising: providing a substrate into a reaction chamber; introducing gaseous reagents into the reaction chamber wherein the gaseous reagents comprise a silicon precursor comprising an silicon compound having Formula I as defined herein and applying energy to the gaseous reagents in the reaction chamber to induce reaction of the gaseous reagents to deposit a film on the substrate. The film as deposited is suitable for its intended use without an optional additional cure step applied to the as-deposited film. | 2022-02-10 |
20220044929 | FUNCTIONALIZED CYCLOSILAZANES AS PRECURSORS FOR HIGH GROWTH RATE SILICON-CONTAINING FILMS - Described herein are functionalized cyclosilazane precursor compounds and compositions and methods comprising same to deposit a silicon-containing film such as, without limitation, silicon oxide, silicon nitride, silicon oxynitride, silicon carbonitride, silicon oxycarbonitride, or carbon-doped silicon oxide via a thermal atomic layer deposition (ALD) or plasma enhanced atomic layer deposition (PEALD) process, or a combination thereof. | 2022-02-10 |
20220044930 | PULSED-PLASMA DEPOSITION OF THIN FILM LAYERS - Examples of the present technology include semiconductor processing methods that may include generating a plasma from a deposition precursor in a processing region of a semiconductor processing chamber. The plasma may be generated at a delivered power within a first period of time when plasma power is delivered from a power source operating at a first duty cycle. The methods may further include transitioning the power source from the first duty cycle to a second duty cycle after the first period of time. A layer may be deposited on a substrate in the processing region of the semiconductor processing chamber from the generated plasma. The layer, as deposited, may be characterized by a thickness of 50 Å or less. Exemplary deposition precursors may include one or more silicon-containing precursors, and an exemplary layer deposited on the substrate may include an amorphous silicon layer. | 2022-02-10 |
20220044931 | PLASMA ENHANCED DEPOSITION PROCESSES FOR CONTROLLED FORMATION OF OXYGEN CONTAINING THIN FILMS - Methods for controlling the formation of oxygen containing thin films, such as silicon oxycarbide (SiOC) and silicon oxycarbonitride (SiOCN) thin films, on a substrate in a reaction space are provided. The methods can include at least one plasma enhanced atomic layer deposition (PEALD) cycle including alternately and sequentially contacting the substrate with a silicon precursor that comprises oxygen and a second reactant that does not include oxygen. In some embodiments the plasma power can be selected from a range to achieve a desired step coverage or wet etch rate ratio (WERR) for films deposited on three dimensional features. | 2022-02-10 |
20220044932 | METHOD FOR PREPARING SEMICONDUCTOR DEVICE STRUCTURE WITH FINE PATTERNS AT DIFFERENT LEVELS - The present disclosure provides a method for preparing a semiconductor device structure with fine patterns at different levels. The method includes forming a hard mask material over a substrate; etching the hardmask material to form hard mask pillars; forming spacers over sidewall surfaces of the hard mask pillars; etching the hard mask pillars and the target material by using the spacers as a mask to integrally forming a plurality of target structures, a high-level recesses in one of the plurality of target structures and a low-level recess between two target structures; and integrally forming a high-level conductive pattern in the high-level conductive pattern and a low-level conductive pattern in the low-level recess. | 2022-02-10 |
20220044933 | SEMICONDUCTOR DEVICE WITH REDUCED CRITICAL DIMENSIONS - A semiconductor structure includes a base layer with a top surface and a plurality of processed areas. A primary pattern is disposed on the top surface of the base layer, wherein the primary pattern has a pattern top surface, a processed area on the pattern top surface, and a sidewall, and the primary pattern has a first critical dimension, and the processed areas are on the part of the top surface of the base layer exposed by the primary pattern. A secondary pattern is disposed on the sidewall of the primary pattern, wherein the secondary pattern has a second critical dimension, and the second critical dimension is smaller than the first critical dimension. | 2022-02-10 |
20220044934 | METHOD FOR MANUFACTURING SILICON CARBIDE EPITAXIAL SUBSTRATE - In a step of calculating formation conditions for the second silicon carbide layer, a formation time of the second silicon carbide layer is calculated as a value obtained by multiplying a value obtained by dividing the second thickness by the first thickness, by the first formation time, and a flow rate of a second ammonia gas in a step of forming the second silicon carbide layer by epitaxial growth is calculated as a value obtained by multiplying a value obtained by dividing the second concentration by the first concentration, by the first flow rate. | 2022-02-10 |
20220044935 | SUBSTRATE PROCESSING APPARATUS AND SUBSTRATE PROCESSING METHOD - A substrate processing apparatus configured to process a substrate includes a holder configured to hold, in a combined substrate in which a first substrate and a second substrate are bonded to each other, the second substrate; and a modifying device configured to form, to an inside of the first substrate held by the holder, a peripheral modification layer by radiating laser light for periphery along a boundary between a peripheral portion of the first substrate as a removing target and a central portion thereof, and, also, configured to form an internal modification layer by radiating laser light for internal surface along a plane direction of the first substrate. The modifying device switches the laser light for periphery and the laser light for internal surface by adjusting at least a shape or a number of the laser light for periphery and the laser light for internal surface. | 2022-02-10 |
20220044936 | METHOD AND APPARATUS FOR LASER DRILLING BLIND VIAS - In an embodiment, a method of forming a blind via in a substrate comprising a mask layer, a conductive layer, and a dielectric layer is provided. The method includes detecting the mask layer by a sensor, the mask layer providing a substrate surface; determining a property of the blind via, the property comprising one or more of a top diameter, a bottom diameter, a volume, or a taper angle; focusing a Gaussian laser beam, under laser process parameters, at the substrate surface to remove at least a portion of the mask layer; adjusting the laser process parameters based on the property; and focusing the laser beam, under the adjusted laser process parameters, to remove at least a portion of the dielectric layer within the volume to form the blind via. The mask layer can be pre-etched. Apparatus for forming a blind via in a substrate are also provided. | 2022-02-10 |
20220044937 | TRANSISTOR GATE STRUCTURE AND METHOD OF FORMING - A device includes a first nanostructure; a second nanostructure over the first nanostructure; a high-k gate dielectric around the first nanostructure and the second nanostructure, the high-k gate dielectric having a first portion on a top surface of the first nano structure and a second portion on a bottom surface of the second nanostructure; and a gate electrode over the high-k gate dielectric. The gate electrode comprises: a first work function metal around the first nanostructure and the second nanostructure, the first work function metal filling a region between the first portion of the high-k gate dielectric and the second portion of the high-k gate dielectric; and a tungsten layer over the first work function metal, the tungsten layer being free of fluorine. | 2022-02-10 |
20220044938 | SILICON DRY ETCHING METHOD - A silicon dry etching method of the invention, includes: preparing a silicon substrate; forming a mask pattern having an opening on the silicon substrate; forming a deposition layer on the silicon substrate in accordance with the mask pattern while introducing a first gas; carrying out a dry etching process with respect to the silicon substrate in accordance with the mask pattern while introducing a second gas, and thereby forming a recess pattern on a surface of the silicon substrate; and carrying out an ashing process with respect to the silicon substrate while introducing a third gas. | 2022-02-10 |
20220044939 | METHOD FOR INCREASING PHOTORESIST ETCH SELECTIVITY TO ENABLE HIGH ENERGY HOT IMPLANT IN SIC DEVICES - A method for performing an ion implantation process including providing a hardmask layer disposed atop a substrate, providing a photoresist layer disposed atop the hardmask layer and defining a pattern exposing a portion of the hardmask layer, performing a room temperature ion implantation process wherein an ion beam formed of an ionized first dopant species is directed onto the exposed portion of the hardmask layer to make the exposed portion more susceptible to ion etching or wet etching, performing an etching process wherein the exposed portion of the hardmask layer is etched away to expose an underlying portion of the substrate, and performing a high energy, hot ion implantation process wherein an ion beam formed of a ionized second dopant species is directed onto the exposed portion of the substrate. | 2022-02-10 |
20220044940 | SEMICONDUCTOR STRUCTURE AND MANUFACTURING METHOD THEREOF - A semiconductor structure and a manufacturing method thereof are provided. The manufacturing method includes: forming a stacked structure on the substrate, the stacked structure at least including a first material layer, a second material layer and a third material layer from bottom to top; patterning the stacked structure to obtain a first pattern structure; forming a spacer structure on a side wall of the first pattern structure, a top of the spacer structure being not lower than a top of the first material layer; and removing the third material layer, wherein during removing the third material layer, an etching selectivity of the third material layer to the second material layer is greater than 1. | 2022-02-10 |
20220044941 | Methods Of Etching Metals In Semiconductor Devices - A semiconductor structure includes a conductive feature disposed over a semiconductor substrate, a via disposed in a first interlayer dielectric (ILD) layer over the conductive feature, and a metal-containing etch-stop layer (ESL) disposed on the via, where the metal-containing ESL includes a first metal and is resistant to etching by a fluorine-containing etchant. The semiconductor structure further includes a conductive line disposed over the metal-containing ESL, where the conductive line includes a second metal different from the first metal and is etchable by the fluorine-containing etchant, and where the via is configured to interconnect the conductive line to the conductive feature. Furthermore, the semiconductor structure includes a second ILD layer disposed over the first ILD layer. | 2022-02-10 |
20220044942 | PACKAGING METHOD AND PACKAGING DEVICE FOR SELECTIVELY ENCAPSULATING PACKAGING STRUCTURE - The present invention provides a packaging method and a packaging device for selectively encapsulating a packaging structure. The method includes: providing a substrate; mounting components on the substrate, the components including a component that needs to be encapsulated and a component that does not need to be encapsulated; forming a protective structure in an area of the component that does not need to be encapsulated so as to form a protective area for isolating the component that does not need to be encapsulated and an encapsulating area located outside the protective area; filling the encapsulating area with an injection molding material; and removing the protective structure. According to the present invention, any part of the packaging structure may be selectively encapsulated by self-adjustment as required. The operation is simple, and the process flow is simplified. | 2022-02-10 |
20220044943 | APPARATUS FOR IMPRINT LITHOGRAPHY COMPRISING A LOGIC ELEMENT CONFIGURED TO GENERATE A FLUID DROPLET PATTERN AND A METHOD OF USING SUCH APPARATUS - An apparatus for imprint lithography can include a logic element configured to generate a fluid droplet pattern of fluid droplets of a formable material to be dispensed onto a substrate. The fluid droplet pattern includes an imprint field, wherein the imprint field has a side and a drop exclusion zone along the side, and the drop exclusion zone is narrower at a first point farther from the center of a side and wider at a second point closer to the center of the side. In another aspect, a method can be carried out using the apparatus. The apparatus and method can be useful in filling an imprint field with a formable material relatively quickly without extrusion defects or other complications. | 2022-02-10 |
20220044944 | SUBSTRATE PROCESSING APPARATUS AND SUBSTRATE PROCESSING METHOD - A substrate processing apparatus is configured to dry a substrate by replacing a liquid film formed on a top surface of the substrate, which is horizontally held, with a supercritical fluid. The substrate processing apparatus includes a pressure vessel, a cover body and a supporting body. The pressure vessel has therein a drying chamber for the substrate. The cover body is configured to close an opening of the drying chamber. The supporting body is configured to support the substrate horizontally within the drying chamber. The supporting body is fixed to the drying chamber. | 2022-02-10 |
20220044945 | SUBSTRATE PROCESSING APPARATUS AND SUBSTRATE PROCESSING METHOD - A substrate processing apparatus includes a transfer block in which a transfer device configured to transfer a substrate is placed, and a processing block provided adjacent to the transfer block. The processing block includes a liquid film forming unit configured to form a liquid film on a top surface of the substrate which is held horizontally, and a drying unit configured to replace the liquid film with a supercritical fluid to dry the substrate. The drying unit includes a pressure vessel having therein a drying chamber for the substrate, a cover body configured to close an opening of the drying chamber, and a supporting body configured to support the substrate horizontally in the drying chamber. The supporting body is fixed to the drying chamber. The transfer device advances into the drying chamber through the opening of the drying chamber while holding horizontally the substrate having the liquid film thereon. | 2022-02-10 |
20220044946 | NON-CONTACT CLEAN MODULE - A cleaning module for cleaning a wafer comprises a wafer gripping device configured to support a wafer in a vertical orientation and comprises a catch cup and a gripper assembly. The catch cup comprises a wall that has an annular inner surface that defines a processing region and has an angled portion that is symmetric about a central axis of the wafer gripping device. The gripper assembly comprises a first plate assembly, a second plate assembly, a plurality of gripping pin, and a plurality of loading pin. The gripping pins are configured to grip a wafer during a cleaning process and the loading pins are configured to grip the wafer during a loading and unloading process. The cleaning module further comprises a sweep arm coupled to a nozzle mechanism configured to deliver liquids to the front and back side of the wafer. | 2022-02-10 |
20220044947 | TRANSPORTATION MONITORING METHOD AND SYSTEM THEREOF - A transportation monitoring method is provided, including the following steps. A monitoring image of a robot blade outside a carrier is captured from a fixed field of view by an image capturing device. The robot blade is configured to move an item into or out of the carrier. Next, a sampling area is obtained from the monitoring image by a processing device. Also, a tilting state of the robot blade is determined according to the sampling area by the processing device. When the processing device determines that the robot blade is tilted, the processing device sends a warning signal. A transportation monitoring system is also provided. | 2022-02-10 |
20220044948 | MONITORING WAFER AND MONITORING SYSTEM - The present disclosure provides a monitoring wafer and a monitoring system. The monitoring wafer includes: an initial wafer, a searchlight module, a data acquisition module and a wireless transmission module, the searchlight module is configured to emit searchlight to the wafer chuck, the data acquisition module is configured to acquire searchlight information of the searchlight on the wafer chuck, and the wireless transmission module is configured to receive and transmit the searchlight information. | 2022-02-10 |
20220044949 | INTERACTIVE AND ITERATIVE TRAINING OF A CLASSIFICATION ALGORITHM FOR CLASSIFYING ANOMALIES IN IMAGING DATASETS - A method includes detecting a plurality of anomalies in an imaging dataset of a wafer. The wafer includes a plurality of semiconductor structures. The method also includes executing multiple iterations. At least some of the iterations include determining a current classification of the plurality of anomalies using a machine-learned classification algorithm and tiles of the imaging dataset associated with the plurality of anomalies. The current classification includes a current set of classes into which the anomalies of the plurality of anomalies are binned. The method further includes, based on at least one decision criterion, selecting at least one anomaly of the plurality of anomalies for a presentation to a user. In addition, the method includes, based on an annotation of the at least one anomaly provided by the user with respect to the current classification, re-training the classification algorithm. | 2022-02-10 |
20220044950 | STORAGE SYSTEM, QUERY SYSTEM AND STORAGE METHOD FOR RETICLES, AND COMPUTER DEVICE - A storage system for reticles includes carrier devices, including reticle placing regions for placing the reticles; a storage device, storing a preset coordinate system and position information of the carrier devices in the preset coordinate system; detection devices, arranged in one-to-one correspondence with the carrier devices, where each detection device performs reticle detection on a respective carrier device, send first detection signal responsive to a reticle being placed in the reticle placing region, and send second detection signal responsive to a reticle being placed outside the reticle placing region, the detection devices are connected with the storage device, and the storage device is further configured to store reticle position information of the reticle in the preset coordinate system when receiving the first or second detection signal; and alarm devices, connected with the detection devices in one-to-one correspondence, where each alarm device implements alarm display when receiving the second detection signal. | 2022-02-10 |
20220044951 | CONTAINER AND SUBSTRATE TREATING APPARATUS - Disclosed is a container. The container includes a housing having an interior space, and a support part that supports an expendable component in the interior space, and the support part includes an alignment pin that aligns the expendable component. | 2022-02-10 |
20220044952 | VACUUM PROCESS APPARATUS AND SUBSTRATE TRANSFER METHOD - In a vacuum processing apparatus, a load lock module includes a housing and substrate holding sections, the housing having first substrate transfer ports formed on one of right and left sides thereof and a second substrate transfer port formed on a rear side thereof, and each substrate holding section being configured to hold a substrate on a right or left side in the housing. Further, a normal pressure transfer chamber extends over or under the housing from one of the right and left sides of the housing to the other one thereof so that each first substrate transfer port is opened. The normal pressure transfer chamber includes a stacked transfer region that is a region overlapping the housing. Further, a normal pressure transfer mechanism transfers the substrate between each substrate holding section and a transfer container carried into each of loading/unloading ports via the stacked transfer region. | 2022-02-10 |
20220044953 | SUBSTRATE TREATMENT APPARATUS AND TRANSFER SCHEDULE CREATION METHOD - A substrate treatment apparatus includes: treatment parts each of which performs a predetermined treatment; and a transfer mechanism which transfers a transfer object. Transfer objects are transferred in a predetermined transfer-in order into the substrate treatment apparatus. The substrate treatment apparatus includes a controller which acquires a process job. The controller determines before starting transfer of one transfer object to the treatment part, when the process job is different between the one transfer object and a preceding transfer object transferred into the substrate treatment apparatus prior to the one transfer object and a same kind of treatment is included in the respective process jobs thereof, a possibility of performing preceding execution of executing the same kind of treatment on the one transfer object previous to completion of the same kind of treatment on the preceding transfer object. | 2022-02-10 |
20220044954 | Alignment Platform and Electronic Component Transmission Apparatus - The present invention reveals an alignment platform for aligning electronic component precisely to the operation position during testing or hot pressing processes. The alignment platform makes a rotor to rotate by a driving apparatus. The rotor has an eccentric axle to where a connecting member is disposed. The connecting member is moved by the eccentric axle, driving an active plate to move. The eccentric axle, the driving apparatus, the connecting member, and the active plate are configured to move under control in a micro or nano meter scale. Thus, precisely alignment of electronic component can be achieved. Floating mechanism of electronic component transmission apparatus or electronic component handler may be dismissed for lowering cost and prolonging lifetime. | 2022-02-10 |
20220044955 | Metal Spring Anchor for Advanced Packaging - An Fan-out packaging system, comprising dedicated frame with associated movable metallic spring feature(s) for incoming known-good-die (KGD), is invented. The movable spring anchor(s) along with the boundaries of the frame locks the KGD in its designated position during EMC implementation and subsequent processes. In this system/approach, the position accuracy of KGDs during the wafer reconstitution process will be mostly dominated by the dicing accuracy. The proposed system is a very low cost approach as it does not need the expensive software/tool set and does not have a low throughput site-to-site lithography correction during exposure after metrology is carried out for every flash field. This system is particularly useful for chiplet consisting of component chips from different technologies and from substrate made of different material. The frames can be further used as part of function component for the packaged system either as electromagnetic shield, or heat dissipation/heat sink, or even RF antenna as well as other passive devices or active components. | 2022-02-10 |
20220044956 | SUBSTRATE SUPPORTING APPARATUS, SUBSTRATE PROCESSING APPARATUS INCLUDING THE SAME, AND SUBSTRATE PROCESSING METHOD - A substrate processing method capable of stably loading a substrate regardless of a variation in pressure of a reaction space includes supplying an inert gas; and forming a thin film by sequentially and repeatedly supplying a source gas, supplying a reaction gas, and activating the reaction gas, wherein a center portion of a substrate and a center portion of a susceptor are spaced apart from each other to form a separate space, the reaction space above the substrate and the separate space communicate with each other via one or more channels, an inert gas is introduced to the separate space through the one or more channels during the supplying of the inert gas, and the inert gas prevents pressure imbalance between the separate space and the reaction space during a thin film deposition process. | 2022-02-10 |
20220044957 | PIN LIFTING DEVICE - Disclosed is a pin lifting device which includes a housing extending along an adjustment axis, a housing end at a first end region of the housing and has a housing opening, a drive part arranged at a second end region of the housing, an adjusting device having a part which can move in the housing in the direction of the adjustment axis, a guide section for the adjusting device formed on the inside of the housing between a first stop at the frontal housing end and a second stop remote therefrom, a tight connecting device formed inside the housing between the frontal housing end and the adjusting device, and a connecting channel extending from the first stop to the second stop at the guide section. A contiguous second inner region leads to minimal changes in the volume of the second inner region even during movements of the movable part. | 2022-02-10 |
20220044958 | INTEGRATED TOOL LIFT - Semiconductor processing tools are provided that include an upper support framework, a plurality of semiconductor processing chambers arranged along a first axis, a linear guide system fixedly supported by the upper support framework and extending along a second axis substantially parallel to the first axis, and a carriage. Each chamber has a base portion fixedly mounted relative to the upper support framework and a removable top cover with one or more hoisting features. The carriage includes a hoist arm configured to pivot about a vertical axis that is substantially perpendicular to the second axis, the carriage is configured to movably engage with the linear guide system and translate along the second axis relative to the linear guide system. The carriage and hoist arm are movable such that a hoist feature engagement interface of the hoist arm can be moved engage with hoisting features of any of the removable top covers. | 2022-02-10 |
20220044959 | SUBSTRATE SUPPORTING MEMBER, SUBSTRATE TREATING APPARATUS INCLUDING THE SAME AND SUBSTRATE TREATING METHOD THEREOF - A substrate supporting member capable of controlling the flow of charges on a substrate by controlling ground resistance values of a guide pin and a support pin using a variable resistor, and a substrate treating apparatus including the same are provided. The substrate supporting member includes the body; a support pin installed on the body and for supporting the substrate; a guide pin installed on the body and for supporting the substrate; and a charge control device for controlling a charge around the substrate by controlling an electrical connection between the support pin and a first resistor and an electrical connection between the guide pin and a second resistor. | 2022-02-10 |
20220044960 | INTEGRATED CIRCUIT STRUCTURE WITH SEMICONDUCTOR-BASED ISOLATION STRUCTURE AND METHODS TO FORM SAME - Embodiments of the disclosure provide an integrated circuit (IC) structure, including a semiconductor-based isolation structure on a substrate. A shallow trench isolation (STI) structure may be positioned on the semiconductor-based isolation structure. An active semiconductor region is on the substrate and adjacent each of the semiconductor-based isolation structure and the STI structure. The active semiconductor region includes a doped semiconductor material. At least one device on the active semiconductor region may be horizontally distal to the STI structure. | 2022-02-10 |
20220044961 | SEMICONDUCTOR STRUCTURE AND MANUFACTURING METHOD THEREOF - Provided are a semiconductor structure and a manufacturing method thereof. The manufacturing method for the semiconductor structure comprises: providing a substrate, wherein the substrate comprises active regions and isolation regions each located between the adjacent active regions, and each of the active regions comprises corner regions adjacent to the isolation regions; performing a doping process to implant doping ions into the corner regions, wherein the doping ions are configured to slow down an oxidation rate of the corner regions; and performing a removing process to remove the oxidized portion of the substrate after the doping process, wherein during the removing process, a side wall of each of the corner regions is exposed from a structure in the isolation region. | 2022-02-10 |
20220044962 | SEMICONDUCTOR DEVICE, MANUFACTURING METHOD THEREOF, SOLID-STATE IMAGING DEVICE, AND ELECTRONIC APPARATUS - A method of manufacturing a semiconductor device includes bonding a first semiconductor wafer including a first substrate and a first insulating layer formed to contact one surface of the first substrate, and a second semiconductor wafer including a second substrate and a second insulating layer, forming a third insulating layer, performing etching so that the second insulating layer remains on a second wiring layer, forming a first connection hole, forming an insulating film on the first connection hole, performing etching of the second insulating layer and the insulating film, forming a second connection hole, and forming a first via formed in inner portions of the connection holes and connected to the second wiring layer, wherein a diameter of the first connection hole formed on the other surface of the first substrate is greater than a diameter of the first connection hole formed on the third insulating layer. | 2022-02-10 |
20220044963 | METHOD FOR PREPARING SEMICONDUCTOR STRUCTURE HAVING VOID BETWEEN BONDED WAFERS - A method includes providing a first wafer including a first substrate, a first dielectric layer disposed over the first substrate and a first component formed within the first dielectric layer; providing a second wafer including a second substrate, a second dielectric layer disposed over the second substrate, and a second component formed within the second dielectric layer; removing a first portion of the first dielectric layer to form a first recess; removing a second portion of the second dielectric layer to form a second recess; disposing the second wafer over the first wafer to bond the first dielectric layer to the second dielectric layer; removing a third portion of the second substrate and the second dielectric layer to form a third recess coupled to the second recess; and disposing a conductive material to fill the first recess, the second recess and the third recess to form a conductive structure. | 2022-02-10 |
20220044964 | SEMICONDUCTOR STRUCTURE AND METHOD FOR MANUFACTURING SAME - Provided are a semiconductor structure and a method for manufacturing the same. The method for manufacturing a semiconductor structure includes that a substrate is provided, and a first structure is formed on the substrate; a first supporting layer is formed, the first supporting layer covering the first structure; a second supporting layer is formed, the second supporting layer covering the first supporting layer; and the first supporting layer and the second supporting layer on an upper surface of the first structure, and the first supporting layer between the first structure and the second supporting layer are removed, a top surface of the second supporting layer being higher than the top surface of the first structure. | 2022-02-10 |
20220044965 | Conductive Via Of Integrated Circuitry, Memory Array Comprising Strings Of Memory Cells, Method Of Forming A Conductive Via Of Integrated Circuitry, And Method Of Forming A Memory Array Comprising Strings Of Memory Cells - A method used in forming a conductive via of integrated circuitry comprises forming a lining laterally over sidewalk of an elevationally-elongated opening. The lining comprises elemental-form silicon. The elemental-form silicon of an uppermost portion of the lining is ion implanted in the elevationally-elongated opening. The ion-implanted elemental-form silicon of the uppermost portion of the lining is etched selectively relative to the elemental-form silicon of a lower portion of the lining below the uppermost portion that was not subjected to said ion implanting. The elemental-form silicon of the lower portion of the lining is reacted with a metal halide to form elemental-form metal in a lower portion of the elevationally-elongated opening that is the metal from the metal halide. Conductive material in the elevationally-elongated opening is formed atop and directly against the elemental-form metal. Other embodiments, including structure independent of method, are disclosed. | 2022-02-10 |
20220044966 | METHODS FOR SUB-LITHOGRAPHY RESOLUTION PATTERNING - Disclosed are approaches for forming a semiconductor device. In some embodiments, a method may include providing a plurality of patterning structures over a device layer, each of the plurality of patterning structures including a first sidewall, a second sidewall, and an upper surface, and forming a mask by depositing a masking material at a non-zero angle of inclination relative to a perpendicular to a plane defined by a top surface of the device layer. The mask may be formed over the plurality of patterning structures without being formed along the second sidewall. The method may further include selectively forming a metal layer along the second sidewall of each of the plurality of patterning structures. | 2022-02-10 |
20220044967 | ENCAPSULATED TOP VIA INTERCONNECTS - Integrated chips and methods of forming the same include forming a lower conductive line over an underlying layer. An upper conductive via is formed over the lower conducting lines. An encapsulating layer is formed on the lower conductive line and the upper conductive via using a treatment process that converts an outermost layer of the lower conductive line and the upper conductive via into the encapsulating layer. | 2022-02-10 |
20220044968 | MAINFRAME-LESS WAFER TRANSFER PLATFORM FOR WAFER PROCESSING MODULES - In an embodiment, a semiconductor processing tool for implementing hybrid laser and plasma dicing of a substrate is provided. The semiconductor processing tool comprises a transfer module, where the transfer module comprises a track robot for handling the substrate, and a loadlock attached to the transfer module. In an embodiment, the loadlock comprises a linear transfer system for handling the substrate. In an embodiment, the processing tool further comprises a processing chamber attached to the loadlock, wherein the linear transfer system of the loadlock is configured to insert and remove the substrate from the processing chamber. | 2022-02-10 |
20220044969 | LASER PROCESSING METHOD, SEMICONDUCTOR DEVICE MANUFACTURING METHOD, AND EXAMINATION DEVICE - An inspecting device includes a stage configured to support a wafer in which a plurality of rows of modified regions are formed in a semiconductor substrate, a light source configured to output light, an objective lens configured to pass light propagated through the semiconductor substrate, a light detection part configured to detect light passing through the objective lens, and an inspection part configured to inspect whether or not there is a tip of a fracture in an inspection region between a first modified region closest to a front surface of the semiconductor substrate and a second modified region closest to the first modified region. The objective lens aligns a focus from the back surface side in an inspection region. The light detection part detects light propagating in the semiconductor substrate from the front surface side to the back surface side. | 2022-02-10 |
20220044970 | METHOD OF PROCESSING A SUBSTRATE - This invention relates to a method of processing a substrate, having on one side a device area with a plurality of devices. The method includes attaching a first protective film to the one side of the substrate, so that at least a central area of a front surface of the first protective film is in direct contact with the one side of the substrate, and attaching a second protective film to the opposite side of the substrate. After attaching the second protective film, a laser beam is applied to the substrate from the opposite side of the substrate. The substrate and second protective film are transparent to the laser beam. The laser beam is applied to the substrate in a plurality of positions so as to form a plurality of modified regions in the substrate. | 2022-02-10 |
20220044971 | INTEGRATED CIRCUITS WITH RECESSED GATE ELECTRODES - Integrated circuits including MOSFETs with selectively recessed gate electrodes. Transistors having recessed gate electrodes with reduced capacitive coupling area to adjacent source and drain contact metallization are provided alongside transistors with gate electrodes that are non-recessed and have greater z-height. In embodiments, analog circuits employ transistors with gate electrodes of a given z-height while logic gates employ transistors with recessed gate electrodes of lesser z-height. In embodiments, subsets of substantially planar gate electrodes are selectively etched back to differentiate a height of the gate electrode based on a given transistor's application within a circuit. | 2022-02-10 |
20220044972 | Method For Forming Gate Oxide - A method for forming a gate oxide film of a transistor device includes: step 1: forming a hard mask layer on the surface of a semiconductor substrate, etching the hard mask layer and the semiconductor substrate to form shallow trenches; step 2: performing an tilt-angle ion implantation to the upper area of the side surfaces of each shallow trench to form an upper doped region; step 3: filling a field oxide layer into the shallow trenches and removing the hard mask layer; and step 4: performing thermal oxidation to form a gate oxide film on the surface of an active region. The method can improve the morphology of the gate oxide film, thus increase the breakdown voltage threshold and reliability of the device. | 2022-02-10 |
20220044973 | VERTICAL STACKED NANOSHEET CMOS TRANSISTORS WITH DIFFERENT WORK FUNCTION METALS - A method for forming a semiconductor device includes forming a structure having at least a first nanosheet stack for a first device, a second nanosheet stack for a second device and disposed over the first nanosheet stack, a disposable gate structure, and a gate spacer. The disposable gate structure and sacrificial layers of the first and second nanosheet stacks are removed thereby forming a plurality of cavities. A conformal gate dielectric layer is formed in the plurality cavities and surrounding at least portions of the first and second nanosheet stacks. A first conformal work function layer is formed in contact with the gate dielectric layer. Portions of the first conformal work function layer are removed without using a mask from at least the second nanosheet stack. A second conformal work function layer is formed on exposed portions of the gate dielectric layer. | 2022-02-10 |
20220044974 | GAS PHASE PRODUCTION OF RADICALS FOR DIELECTRICS - A method for depositing a dielectric material includes heating a substrate disposed in a dielectric deposition chamber; dispensing a dielectric precursor from a first showerhead towards a major outer surface of the substrate; dispensing a mixture containing oxygen and ammonia from a second showerhead towards the major outer surface of the substrate; and reacting the dielectric precursor with the mixture to deposit a layer of oxynitride dielectric material on the substrate. | 2022-02-10 |
20220044975 | LAYER DETECTION FOR HIGH ASPECT RATIO ETCH CONTROL - Controlling an etch process applied to a multi-layered structure, by calculating a spectral derivative of reflectance of an illuminated region of interest of a multi-layered structure during an etch process applied to the multi-layered structure, identifying in the spectral derivative a discontinuity that indicates that an edge of a void formed by the etch process at the region of interest has crossed a layer boundary of the multi-layered structure, determining that the crossed layer boundary corresponds to a preselected layer boundary of the multi-layered structure, and applying a predefined control action to the etch process responsive to determining that the crossed layer boundary corresponds to the preselected layer boundary of the multi-layered structure. | 2022-02-10 |
20220044976 | DISPLAY DEVICE - A display device includes a light emitting area and a sub-area disposed at a side of the light emitting area, a measurement area disposed in the sub-area, measurement patterns and a first electrode extension portion being disposed in the measurement area, a first electrode and a second electrode that are disposed in the light emitting area and spaced apart from each other, and face each other, a first insulating layer disposed on the first electrode and the second electrode, at least a part of the first insulating layer being disposed on the first electrode extension portion, and at least one light emitting element having ends disposed on the first electrode and the second electrode in the light emitting area. The measurement area includes a first measurement area in which a first measurement hole exposing a part of an upper surface of the first electrode extension portion is disposed. | 2022-02-10 |
20220044977 | SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD FOR SEMICONDUCTOR DEVICE - A semiconductor device includes a case enclosing a region where a semiconductor element as a component of an electric circuit exists. A resin part is fixed to an inside of the case in contact with the region. The resin part is provided with a conductive film, which is a part of the electric circuit. The conductive film is provided in the resin part so that the conductive film comes into contact with the region. | 2022-02-10 |
20220044978 | SEMICONDUCTOR DEVICE AND METHOD FOR MANUFACTURING THE SAME | 2022-02-10 |
20220044979 | HERMETIC PACKAGE FOR HIGH CTE MISMATCH - The present disclosure relates to a hermetic package capable of handling a high coefficient of thermal expansion (CTE) mismatch configuration. The disclosed hermetic package includes a metal base and multiple segments that are discrete from each other. Herein, a gap exists between every two adjacent ceramic wall segments and is sealed with a connecting material. The ceramic wall segments with the connecting material form a ring wall, where the gap between every two adjacent ceramic wall segments is located at a corner of the ring wall. The metal base is either surrounded by the ring wall or underneath the ring wall. | 2022-02-10 |
20220044980 | SEMICONDUCTOR DEVICE - A semiconductor device includes a semiconductor chip provided inside with a p-n junction, an opaque sealing resin covering a surface of the semiconductor chip, and a functional region arranged between the semiconductor chip and the sealing resin and configured to prevent light, which is generated when a forward current flows through the p-n junction and has a particular wavelength causing deterioration of the sealing resin, from reaching the sealing resin. | 2022-02-10 |
20220044981 | HERMETIC PACKAGE FOR HIGH CTE MISMATCH - The present disclosure relates to a hermetic package capable of handling a high coefficient of thermal expansion (CTE) mismatch configuration. The disclosed hermetic package includes a metal base and multiple segments that are discrete from each other. Herein, a gap exists between every two adjacent ceramic wall segments and is sealed with a connecting material. The ceramic wall segments with the connecting material form a ring wall, where the gap between every two adjacent ceramic wall segments is located at a corner of the ring wall. The metal base is either surrounded by the ring wall or underneath the ring wall. | 2022-02-10 |
20220044982 | AMPLIFIER WITH INTEGRATED TEMPERATURE SENSOR - A device includes a semiconductor die including a transistor. The transistor includes a plurality of parallel transistor elements. Each transistor element includes a drain region, a source region, and a gate region. The semiconductor die includes a first temperature sensor between a first transistor element in the plurality of transistor elements and a second transistor element in the plurality of transistor elements. The first temperature sensor is configured to generate a first output signal having a magnitude that is proportional to a temperature of the first temperature sensor. | 2022-02-10 |
20220044983 | THERMAL CONDUCTIVE SILICONE COMPOSITION AND SEMICONDUCTOR DEVICE - Provided are a thermal conductive silicone composition having a favorable heat dissipation property; and a semiconductor device using such composition. The thermal conductive silicone composition contains:
| 2022-02-10 |
20220044984 | Circuit Carrier Arrangement And Method For Producing Such A Circuit Carrier Arrangement - A circuit carrier arrangement includes: a cooling plate ( | 2022-02-10 |
20220044985 | PUMP-MOTOR ASSEMBLY FOR AN ENERGY STORAGE SYSTEM - In one aspect, a pump-motor assembly is provided outside of and adjacent to a storage container that stores a back-up energy storage unit. The pump-motor assembly includes a pump-motor that maintains a minimum pressure of a liquid coolant in a liquid coolant system that cools the back-up energy storage unit, and a housing that is completely enclosed, the housing containing the pump-motor, and having a removable access panel on one side thereof the enclosed structure, and an opening on another side thereof to the storage container. | 2022-02-10 |
20220044986 | TRANSISTOR WITH I/O PORTS IN AN ACTIVE AREA OF THE TRANSISTOR - A semiconductor device includes an active region formed in a substrate. The active region includes input fingers, output fingers, and common fingers disposed within the substrate and oriented substantially parallel to one another. An input port is electrically connected to the input fingers and an output port is electrically connected to the output fingers. A common region is electrically connected to the common fingers. At least one of the input and output ports is positioned within the active region between the input, output, and common fingers. The common region is interposed between a pair of the common fingers such that the common fingers of the pair are spaced apart by a gap, and at least one of the input and output ports is position in the gap. | 2022-02-10 |
20220044987 | SEMICONDUCTOR DEVICE WITH SEALED SEMICONDUCTOR CHIP - A semiconductor device includes a semiconductor chip with bonding pads, the bonding pads being arranged along one side of an element forming surface of the semiconductor chip, a lead frame including first and second internal leads arranged such that tips thereof correspond to some of the bonding pads of the semiconductor chip, and first and second bonding wires by which the first internal leads and the some of the bonding pads are bonded to each other. The semiconductor device further includes a hanging pin section provided on the element non-forming surface of the semiconductor chip, and a sealing member with which the semiconductor chip is sealed including the hanging pin section and a bonding section between the first and second internal leads and the first and second bonding wires. | 2022-02-10 |
20220044988 | SOLDERING STRUCTURE AND POWER MODULE COMPRISING THE SAME - A soldering structure configured for preventing solder overflow during soldering and a power module, may include a component to be soldered; and a metal layer having a bonding area, to which the component to be soldered is bonded by solder, and a groove portion formed around the bonding area. | 2022-02-10 |
20220044989 | SEMICONDUCTOR PACKAGE HAVING DIE PAD WITH COOLING FINS - Embodiments of the present disclosure are directed to leadframe semiconductor packages having die pads with cooling fins. In at least one embodiment, the leadframe semiconductor package includes leads and a semiconductor die (or chip) coupled to a die pad with cooling fins. The cooling fins are defined by recesses formed in the die pad. The recesses extend into the die pad at a bottom surface of the semiconductor package, such that the bottom surfaces of the cooling fins of the die pad are flush or coplanar with a surface of the package body, such as an encapsulation material. Furthermore, bottom surfaces of the cooling fins of the die pad are flush or coplanar with exposed bottom surfaces of the leads. | 2022-02-10 |
20220044990 | WIRING SUBSTRATE, SEMICONDUCTOR PACKAGE AND METHOD OF MANUFACTURING WIRING SUBSTRATE - A second wiring layer is connected to a first wiring layer via an insulating layer. The second wiring layer comprises pad structures. Each pad structure includes a first metal layer formed on the insulating layer, a second metal layer formed on the first metal layer, and a third metal layer formed on the second metal layer. The pad structures comprises a first pad structure and a second pad structure. A via-wiring diameter of the first pad structure is different from a via-wiring diameter of the second pad structure. A distance from an upper surface of the insulating layer to an upper surface of the second metal layer of the first pad structure is the same as a distance from the upper surface of the insulating layer to an upper surface of the second metal layer of the second pad structure. | 2022-02-10 |
20220044991 | WIRING SUBSTRATE, SEMICONDUCTOR PACKAGE HAVING THE WIRING SUBSTRATE, AND MANUFACTURING METHOD THEREOF - Provided is a wiring substrate and its manufacturing method in which a thick wiring layer capable of being applied with a large current and a thin wiring layer capable of being subjected to microfabrication coexist in the same layer. The wiring substrate includes: an insulating film located over a first wiring and having a via; and a second wiring over the insulating film. The second wiring has a stacked structure including a first layer and a second layer covering the first layer. The second layer is in direct contact with the first wiring in the via. A thickness of the second layer in a region overlapping with the first layer is different from a thickness of the second layer in the via | 2022-02-10 |
20220044992 | SEMICONDUCTOR PACKAGE - A semiconductor package includes a redistribution substrate having first and second surfaces opposed to each other, and including an insulation member, a plurality of redistribution layers on different levels in the insulation member, and a redistribution via having a shape narrowing from the second surface toward the first surface in a first direction; a plurality of UBM layers, each including a UBM pad on the first surface of the redistribution substrate, and a UBM via having a shape narrowing in a second direction, opposite to the first direction; and at least one semiconductor chip on the second surface of the redistribution substrate, and having a plurality of contact pads electrically connected to the redistribution layer adjacent to the second surface among the plurality of redistribution layers. | 2022-02-10 |
20220044993 | SEMICONDUCTOR DEVICE - A semiconductor device including an interlayer insulating layer on a substrate; a conductive line on the interlayer insulating layer; and a contact plug penetrating the interlayer insulating layer, the contact plug being connected to the conductive line, wherein the contact plug includes an upper pattern penetrating an upper region of the interlayer insulating layer, the upper pattern protruding upwardly from a top surface of the interlayer insulating layer, the upper pattern includes a first portion penetrating the upper region of the interlayer insulating layer; and a second portion protruding upwardly from the top surface of the interlayer insulating layer, and a width of a lower region of the second portion in a direction parallel to a top surface of the substrate is greater than a width of an upper region of the second portion in the direction parallel to the top surface of the substrate. | 2022-02-10 |
20220044994 | REDUCED PITCH MEMORY SUBSYSTEM FOR MEMORY DEVICE - A memory device includes an array of memory cells and a plurality of bit-lines with each bit-line connected to a respective set of memory cells of the array of memory cells. The memory device includes a memory subsystem having first and second memory circuits. Each first memory circuit can be disposed laterally adjacent to a second memory circuit. Each first memory circuit includes a first bit-line connection and each second memory circuit including a second bit-line connection, the first and second bit-line connections can connect to respective bit-lines. Each first bit-line connection is disposed on a first bit-line connection line of the memory subsystem and each second bit-line connection is disposed on a second bit-line connection line of the memory subsystem, and the second bit-line connection line can be offset from the first bit-line connection line by a predetermined distance that is greater than zero. | 2022-02-10 |
20220044995 | Memory Arrays And Methods Used In Forming A Memory Array - A method used in forming a memory array comprising strings of memory cells comprises forming a stack comprising vertically-alternating first tiers and second tiers having channel-material strings therein. Conductive vias are formed through insulating material that is directly above the channel-material strings. Individual of the conductive vias are directly electrically coupled to individual of the channel-material strings. After forming the conductive vias, horizontally-elongated trenches are formed into the stack to form laterally-spaced memory-block regions. Intervening material is formed in the trenches laterally-between and longitudinally-along the immediately-laterally-adjacent memory-block regions. Additional methods and structures independent of method are disclosed. | 2022-02-10 |
20220044996 | SEMICONDUCTOR DEVICE WITH CONNECTING STRUCTURE AND METHOD FOR FABRICATING THE SAME - The present application discloses a method for fabricating a semiconductor device. The method includes providing a first semiconductor structure; and forming a first connecting structure comprising a first connecting insulating layer on the first semiconductor structure, a plurality of first connecting contacts in the first connecting insulating layer, and a plurality of first supporting contacts in the first connecting insulating layer. | 2022-02-10 |
20220044997 | METHOD OF FABRICATING SEMICONDUCTOR DEVICE - A method for fabricating a semiconductor device is provided and includes the following steps: providing a substrate; forming a lower electrode on the substrate; forming at least one sub-dielectric layer on the lower electrode; patterning the dielectric layer to form an intermediate dielectric layer, where the intermediate dielectric layer exposes a portion of the at least one sub-dielectric layer; forming a hole by etching the portion of the at least one sub-dielectric layer not covered by the intermediate dielectric layer; filling at least one plug into the hole; and forming an upper electrode on the intermediate dielectric layer. | 2022-02-10 |
20220044998 | LOW COST THREE-DIMENSIONAL STACKING SEMICONDUCTOR ASSEMBLIES - Semiconductor device package assemblies and associated methods are disclosed herein. The semiconductor device package assembly includes (1) a base component having a front side and a back side, the base component having a first metallization structure at the front side; (2) a semiconductor device package having a first side, a second side with a recess, and a second metallization structure at the first side and a contacting region exposed in the recess at the second side; (3) an interconnect structure at least partially positioned in the recess at the second side of the semiconductor device package; and (4) a thermoset material or structure between the front side of the base component and the second side of the semiconductor device package. The interconnect structure is in the thermoset material and includes discrete conductive particles electrically coupled to one another. | 2022-02-10 |
20220044999 | Conductive Interconnects - Some embodiments include conductive interconnects which include the first and second conductive materials, and which extend upwardly from a conductive structure. Some embodiments include integrated assemblies having conductive interconnects. | 2022-02-10 |
20220045000 | SEMICONDUCTOR DEVICE AND FABRICATION METHOD FOR THE SAME - A reliable semiconductor device and a method for preparing the reliable semiconductor device are provided. The semiconductor device includes at least one die comprising an integrated circuit region; a first recess region surrounding the integrated circuit region; and a second recess region surrounding the first recess region. A first columnar blocking structure is disposed in the first recess region and a second columnar blocking structure is disposed in the second recess region | 2022-02-10 |
20220045001 | METAL-OXIDE-SEMICONDUCTOR FIELD-EFFECT-TRANSISTORS (MOSFET) AS ANTIFUSE ELEMENTS - Embodiments herein may describe techniques for an integrated circuit including a MOSFET having a source area, a channel area, a gate electrode, and a drain area. The channel area may include a first channel region with a dopant of a first concentration next to the source area, and a second channel region with the dopant of a second concentration higher than the first concentration next to the drain area. A source electrode may be in contact with the source area, a gate oxide layer above the channel area, and the gate electrode above the gate oxide layer. A first resistance exists between the source electrode and the gate electrode. A second resistance exists between the source electrode, the gate electrode, and a path through the gate oxide layer to couple the source electrode and the gate electrode after a programming operation is performed. Other embodiments may be described and/or claimed. | 2022-02-10 |
20220045002 | METHOD FOR PREPARING VERTICAL ELECTRICAL FUSE DEVICE - The present disclosure relates to a method for preparing an electrical fuse (e-fuse) device. The method includes forming a mask layer over a semiconductor substrate, and etching the semiconductor substrate by using the mask layer as a mask to form a fuse link over a semiconductor base. The method also includes epitaxially growing a first bottom anode/cathode region and a second bottom anode/cathode region over the semiconductor base and adjacent to a bottom portion of the fuse link. The fuse link is between the first bottom anode/cathode region and the second anode/cathode region. The method further includes epitaxially growing a top anode/cathode region to replace the mask layer. | 2022-02-10 |
20220045003 | INTEGRATED CIRCUIT DEVICES INCLUDING METAL WIRES AND METHODS OF FORMING THE SAME - Integrated circuit devices and methods of forming the same are provided. The integrated circuit devices may include a first insulating layer and a plurality of metal wires on the first insulating layer. The plurality of metal wires may include a first metal wire including a first upper surface and a first lower surface that faces the first insulating layer and a second metal wire including a second upper surface and a second lower surface that faces the first insulating layer and is coplanar with the first lower surface. The first metal wire may have a first width monotonically decreasing from the first lower surface to the first upper surface, and the second metal wire may have a second width monotonically increasing from the second lower surface to the second upper surface. | 2022-02-10 |
20220045004 | SEMICONDUCTOR DEVICES INCLUDING POWER CONNECTION LINES - A semiconductor chip includes a first core region including a first core and a first power line configured to provide a first voltage to the first core, a second core region including a second core and a second power line configured to provide the first voltage to the second core, a cache region between the first core region and the second core region, the cache region including a cache and a third power line providing a second voltage to the cache, and arranged between the first core region and the second core region; and a first power connection line connecting the first power line to the second power line and arranged in the cache region. | 2022-02-10 |
20220045005 | THREE-DIMENSIONAL MEMORY DEVICE INCLUDING BUMP-CONTAINING BIT LINES AND METHODS FOR MANUFACTURING THE SAME - A semiconductor die can include an alternating stack of insulating layers and electrically conductive layers located on a substrate, memory stack structures extending through the alternating stack, drain regions located at a first end of a respective one of the vertical semiconductor channels of a memory stack structure, and bit lines extending over the drain regions and electrically connected to a respective subset of the drain regions. At least of a subset of the bit lines includes bump-containing bit lines. Each of the bump-containing bit lines includes a line portion and a bump portion that protrudes upward from a top surface of the line portion by a bump height. Bit line contact via structures overlie the bit lines and contact a bump portion of a respective one of the bump-containing bit lines. | 2022-02-10 |
20220045006 | SEMICONDUCTOR DEVICE WITH POROUS INSULATING LAYERS AND METHOD FOR FABRICATING THE SAME - The present application discloses a semiconductor device and a method for fabricating the semiconductor device. The semiconductor device includes. | 2022-02-10 |
20220045007 | METHODS FOR FABRICATING MICROELECTRONIC DEVICES WITH CONTACTS TO CONDUCTIVE STAIRCASE STEPS, AND RELATED DEVICES AND SYSTEMS - Methods for forming microelectronic devices include forming a staircase structure in a stack structure having a vertically alternating sequence of insulative and conductive materials arranged in tiers. Steps are at lateral ends of the tiers. Contact openings of different aspect ratios are formed in fill material adjacent the staircase structure, with some openings terminating in the fill material and others exposing portions of the conductive material of upper tiers of the stack structure. Additional conductive material is selectively formed on the exposed portions of the conductive material. The contact openings initially terminating in the fill material are extended to expose portions of the conductive material of lower elevations. Contacts are formed, with some extending to the additional conductive material and others extending to conductive material of the tiers of the lower elevations. Microelectronic devices and systems incorporating such staircase structures and contacts are also disclosed. | 2022-02-10 |
20220045008 | SEMICONDUCTOR PACKAGE AND METHOD OF FABRICATING THE SAME - A semiconductor package and associated methods, the package including a substrate; first and second semiconductor chips on the substrate; and external terminals below the substrate, wherein the substrate includes a core portion; first and second buildup portions on top and bottom surfaces of the core portion, the first and second buildup portions including a dielectric pattern and a line pattern; and an interposer chip in an embedding region in the core portion and electrically connected to the first and second buildup portions, the interposer chip includes a base layer; a redistribution layer on the base layer; and a via that penetrates the base layer, the via being connected to the redistribution layer and exposed at a surface of the base layer, the redistribution layer is connected to a line pattern of the first buildup portion, and the via is connected to a line pattern of the second buildup portion. | 2022-02-10 |
20220045009 | SEMICONDUCTOR DEVICE HAVING WAFER-TO-WAFER BONDING STRUCTURE AND MANUFACTURING METHOD THEREOF - A semiconductor device includes a lower wafer including a first substrate, a first dielectric layer that is defined on the first substrate, and a first wiring line that is defined in the first dielectric layer; an upper wafer including a second substrate, an isolation layer that is defined in an upper surface of the second substrate, a second dielectric layer, bonded to an upper surface of the first dielectric layer, that covers a lower surface of the second substrate and that includes at least one portion defined in the lower surface of the second substrate below and in contact with the isolation layer, and a third dielectric layer that is defined on the upper surface of the second substrate, and a second wiring line that is defined on the third dielectric layer; and a through via passing through, under the second wiring line, the third dielectric layer, the isolation layer, the second dielectric layer under the isolation layer and the first dielectric layer, and coupling the second wiring line and the first wiring line. | 2022-02-10 |
20220045010 | SEMICONDUCTOR PACKAGE - A semiconductor package includes a first sub-semiconductor device, an interposer, and a second sub-semiconductor device stacked on each other, and a heat sink covering the second sub-semiconductor device. The first sub-semiconductor device includes a first substrate and a first semiconductor chip. The interposer includes a dielectric layer, a thermal conductive layer in contact with a bottom surface of the dielectric layer, a first thermal conductive pad in contact with a top surface of the dielectric layer, and thermal conductive vias penetrating the dielectric layer to connect the thermal conductive layer to the first thermal conductive pad. A bottom surface of the thermal conductive layer is adjacent to and connected to a top surface of the first semiconductor chip. The second sub-semiconductor device is disposed on the dielectric layer without overlapping the first thermal conductive pad. The heat sink further covers the first thermal conductive pad to be connected thereto. | 2022-02-10 |
20220045011 | SEMICONDUCTOR DEVICES WITH BACKSIDE POWER DISTRIBUTION NETWORK AND FRONTSIDE THROUGH SILICON VIA - The present disclosure describes a semiconductor structure having a power distribution network including first and second conductive lines. A substrate includes a first surface that is in contact with the power distribution network. A plurality of backside vias are in the substrate and electrically coupled to the first conductive line. A via rail is on a second surface of the substrate that opposes the first surface. A first interlayer dielectric is on the via rail and on the substrate. A second interlayer dielectric is on the first interlayer dielectric. A third interlayer dielectric is on the second interlayer dielectric. First and top interconnect layers are in the second and third interlayer dielectrics, respectively. Deep vias are in the interlayer dielectric and electrically coupled to the via rail. The deep vias are also connected to the first and top interconnect layers. A power supply in/out layer is on the third interlayer dielectric and in contact with the top interconnect layer. | 2022-02-10 |
20220045012 | METHOD FOR PREPARING SEMICONDUCTOR PACKAGE STRUCTURE - The present disclosure provides a method for preparing a semiconductor package structure. The method includes the following steps. A first die is provided. A second die including a plurality of first conductors is bonded to the first die. A plurality of second conductors are disposed on the first die. A molding is disposed to encapsulate the first die, the second die and the plurality of second conductors. An RDL is disposed on the second die and the molding. A plurality of connecting structures are disposed on the RDL. | 2022-02-10 |
20220045013 | MODULE AND METHOD OF MANUFACTURING THE SAME - A module is provided that includes a substrate having a first main surface, a first component mounted on the first main surface, a first sealing resin disposed so as to cover the first main surface and the first component, and a shield film covering at least an upper surface of the first sealing resin. The shield film includes a conductive layer, a first protective layer covering the conductive layer, and a second protective layer. The first protective layer is locally formed with a marking section. The second protective layer includes a first region covering the first protective layer and a second region covering the marking section. | 2022-02-10 |
20220045014 | EMBEDDED PACKAGING STRUCTURE HAVING SHIELDING CAVITY AND MANUFACTURING METHOD THEREOF - An embedded package structure having a shielding cavity according to an embodiment of the present disclosure includes a device embedded in an insulating layer, and a shielding cavity enclosing the device, wherein the shielding cavity is defined by a shielding wall embedded in the insulating layer and surrounding the device on four sides, and first and second wiring layers which cover first and second end faces of the shielding wall and are electrically connected with the shielding wall; wherein a signal line leading-out opening is to formed between the first end face of the shielding wall and the first wiring layer, and a signal line connected with a terminal of the device is led, from the signal line leading-out opening, out of the shielding cavity. | 2022-02-10 |
20220045015 | NAND FLASH BLOCK ARCHITECTURE ENHANCEMENT TO PREVENT BLOCK LIFTING - Disclosed is a three-dimensional memory device. In one embodiment, a device is disclosed comprising a source plate; plugs fabricated fabricated on or partially formed in the source plate; a stack formed on the substrate and plugs comprising alternating insulating layers and conductive layers and channel-material strings of memory cells extending through the insulating layers and conductive layers; a first set of pillars extending through the stack formed by a process including etching the alternating insulating layers and conductive layers and depositing a pillar material therein, wherein each pillar in the first set of pillars terminates atop a respective plug in the plurality of plugs; and a second set of pillars extending through the stack formed by a process including etching the alternating insulating layers and conductive layers and depositing a pillar material therein, wherein each pillar in the second set of pillars terminates in the source plate. | 2022-02-10 |
20220045016 | PACKAGE STRUCTURE WITH REINFORCED ELEMENT AND FORMATION METHOD THEREOF - A package structure and a formation method of a package structure are provided. The method includes forming multiple conductive vias in a carrier substrate and forming a redistribution structure over the carrier substrate. The redistribution structure has multiple polymer-containing layers and multiple conductive features. The method also includes disposing multiple chip structures over the redistribution structure. The method further includes bonding the carrier substrate to a package structure. | 2022-02-10 |