06th week of 2011 patent applcation highlights part 27 |
Patent application number | Title | Published |
20110032719 | CONTROL DEVICE FOR CONTROLLING THE POSITION OF A BUMPER FASCIA - A headlamp assembly for an automotive vehicle having a bumper fascia which restrains the movement of the bumper fascia is provided. The bumper fascia includes an exterior surface and an opposite interior surface which faces the engine compartment of the automotive vehicle. The headlamp assembly includes a headlamp housing for receiving a lamp unit. A lens is attached to the headlamp housing to cover a portion of the front end so as to protect the lamp unit. A protrusion extending from a bottom side of the headlamp housing engages with a notch formed on the interior surface of the bumper to control the position of the bumper fascia relative to the headlamp housing. | 2011-02-10 |
20110032720 | High and low beam headlamp with a pivoting multifaceted reflector - A vehicle headlamp having a pivotal multifaceted reflector, a light source, and an actuator typically including a solenoid, the actuator disposed and coupled to the multifaceted reflector and to other portions of the headlamp so as to pivot, under the action of the actuator, into a first position to generate a first beam of light serving as a high beam, and into a second position to generate a second beam of light serving as a low beam, and so providing a high beam and a low beam using the same light source, fixed within the headlamp, and a single reflector. In some embodiments, the high beam meets FMVSS 108 requirements for a vehicle headlamp high beam, and the low beam meets FMVSS 108 requirements for a vehicle headlamp low beam. | 2011-02-10 |
20110032721 | VEHICULAR LAMP - A vehicular lamp includes a body that opens forward; an outer cover attached to the body so as to cover the opening; a first light source disposed within a lamp chamber formed from the body and the outer cover; an optical member that reflects first light source light from the first light source forward; a second light source disposed within the lamp chamber; and a light guide in which an end portion thereof receives second light source light from the second light source and an extended side surface thereof radiates forward at least a portion of the second light source light. The light guide is provided at a position that does not block a light component that forms a main light distribution of the first light source light. | 2011-02-10 |
20110032722 | LAMP UNIT FOR VEHICULAR HEADLAMP - A lamp unit for a vehicular headlamp includes: a projection lens arranged to have an optical axis extending in a vehicle longitudinal direction; a light-emitting element that is a light source arranged on a rear side with respect to a rear focal point of the projection lens; and a reflector that is formed so that a longitudinal section of the reflector has the shape of an ellipse having a first focal point at a center of light emission of the light-emitting element and a second focal point at the rear focal point of the projection lens, wherein the reflector is arranged to cover the light-emitting element and reflects irradiated light toward the projection lens, the irradiated light being light irradiated from the light-emitting element. A major axis of the ellipse, passing through the first focal point and the second focal point, is inclined with respect to the optical axis. | 2011-02-10 |
20110032723 | LIGHTING DEVICE FOR A VEHICLE - A lighting device ( | 2011-02-10 |
20110032724 | LIGHT EMITTING DEVICE AND METHOD FOR MANUFACTURING SAME, LIGHTING FIXTURE, AND LIGHTING SYSTEM - A light emitting device includes: a light emitting element; a substrate including a groove-like light guide extending along a first direction, emission light emitted from the light emitting element and introduced into the light guide being reflected by an inner wall surface of the light guide, spreading along the first direction, and being turned into upward light directed upward above the substrate; and a lens provided above the light guide and configured to collect the upward light and control light distribution characteristic in a plane generally perpendicular to the first direction. | 2011-02-10 |
20110032725 | Optical Module and Optical Unit - A semiconductor laser used as a light source of an optical module is susceptible to the return light from the lens surface. The problem has been conventionally solved by offsetting the optical axis of a lens and the optical axis of a semiconductor laser, but a high-precision and costly process for adjusting the positioning is required. An optical module and an optical unit, wherein the oscillation state of a semiconductor laser can be limited in the range of normal characteristics at a low cost, are provided by proposing a lens which eliminates the need for adjusting the positioning because there is little return light. As a first lens on which the light exiting a semiconductor laser impinges at first, a lens having an optical surface whose convex surface faces toward the semiconductor laser side is employed so that the light is diverged thus reducing the intensity of light returning to the semiconductor laser. | 2011-02-10 |
20110032726 | LIGHT DISTRIBUTION ASSEMBLY - A light distribution assembly includes a housing having a longitudinal length and having one or more light sources mounted to the housing. The light distribution assembly also includes a coupler section having a body extending from the housing along a longitudinal axis between a light entry end and a light exit end. The light entry end has a major axis extending in a first direction and the light exit end has a major axis extending in a second direction, wherein the coupler section is shaped such that the body is rotated about the longitudinal axis of the coupler section so that first direction is approximately perpendicular relative to the second direction. One or more light pipes are attached to the light exit end of the coupler section. | 2011-02-10 |
20110032727 | BACKLIGHT REFLECTORS HAVING A PRISMATIC STRUCTURE - A back reflector for a lightguide in a turning film backlight includes a prism film layer in direct contact with a reflective layer. The lightguide includes a light guiding region having a refractive index that is substantially spatially uniform. The reflective layer may be specular or diffuse and may include a multilayer polymeric film. | 2011-02-10 |
20110032728 | Light Source Device, and Display Apparatus Provided with Such Light Source Device - A light source device includes a first light source group, a second light source group, a light guide body, and a light diffusion body. The light guide body includes a high light distribution region and a low light distribution region generated by the respective light sources of the second light source group. The high light distribution region includes a plurality of first portions. The low light distribution region includes a second portion between the first portions and a third portion. The presence ratio of the light diffusion body | 2011-02-10 |
20110032729 | ORTHOGONALLY SEPARABLE LIGHT BAR - Embodiments described herein provide optical systems in which phosphors are used to down-convert light. In general, optical systems can include a light guide configured to propagate light from an entrance face to a distal end along a propagation axis using total internal reflection. A phosphor layer can be disposed orthogonal to the entrance surface of the light guide. | 2011-02-10 |
20110032730 | SAMPLING CIRCUIT AND CONTROL METHOD - An embodiment provides a sampling circuit, which has a sampling capacitor and a voltage compensation circuit. The voltage compensation circuit has a reference capacitor and a compensation circuit. The sampling capacitor samples a voltage signal and memorizes the signal as a sampling signal. The reference capacitor memorizes a reference signal with a predetermined value. The compensation circuit changes the reference signal with a recovery amount to recover the reference signal to the predetermined value, and simultaneously changes the sampling signal with an adjustment amount. | 2011-02-10 |
20110032731 | MULTIPLE INDEPENDENTLY REGULATED PARAMETERS USING A SINGLE MAGNETIC CIRCUIT ELEMENT - Methods, systems, and devices are described for using isolated and non-isolated circuit structures and control methods for achieving multiple independently regulated input and output parameters using a single, simple, primary magnetic circuit element. For example, structures and methods are revealed for achieving single-stage power factor correction with high power factor and multiple independently regulated outputs using a single, simple, primary magnetic circuit element. Other structures and methods are revealed for achieving multiple independently regulated outputs without power factor correction using a single primary magnetic circuit element for both isolated and non-isolated power conversion applications. | 2011-02-10 |
20110032732 | Secondary side post regulator of flyback power converter with multile outputs - A flyback power converter with multiple outputs has a transformer, a low-voltage output circuit, a high-voltage output circuit, and a secondary side post regulator circuit is provided. The transformer has a first secondary winding and a second secondary winding. The low-voltage output circuit has a low-voltage output capacitor and a rectifier unit, and is coupled to the first secondary winding to generate a low voltage output. The high-voltage output circuit has a high-voltage output switch and a high-voltage output capacitor, and is coupled to the second secondary winding to generate a high voltage output. The secondary side post regulator circuit adjusts on-time of the high-voltage output switch according to a feedback signal to have the energy stored in the high-voltage capacitor transmitted to the low-voltage capacitor to lower down the voltage level of the high output voltage. | 2011-02-10 |
20110032733 | DC-DC CONVERTER AND POWER SUPPLYING SYSTEM INCLUDING SAME - A DC-DC converter has a first-voltage-side port, a second-voltage-side port, and a third-voltage-side port, and performs, at different timings, an operation of boosting a first voltage to a third voltage and an operation of bucking a second voltage to the third voltage. A power supplying system includes a fuel cell, a secondary battery, an accessory system, the DC-DC converter, and another DC-DC converter connected between the fuel cell and a motor, and boosting the first voltage of the fuel cell to a fourth voltage to supply power to the motor through an inverter. The former DC-DC converter has the first-voltage-side port connected to the fuel cell, has the second-voltage-side port connected to the secondary battery, and has the third-voltage-side port connected to the accessory system. | 2011-02-10 |
20110032734 | CASCADED SWITCHING POWER CONVERTER FOR COUPLING A PHOTOVOLTAIC ENERGY SOURCE TO POWER MAINS - A cascaded switching power converter for coupling a photovoltaic (PV) energy source to power mains provides a high-efficiency and a potentially simple control mechanism for AC solar energy conversion systems. The PV energy source charges a capacitive storage element through a DC-DC converter, and an inverter couples energy from the capacitive storage element to the mains supply. The DC-DC converter is controlled so that ripple present on the capacitive storage element due to current drawn by the inverter is not reflected at the input of the DC-DC converter, which is accomplished by varying the conversion ratio of the DC-DC converter with the ripple voltage present across the capacitor. The average voltage of the capacitor can also be increased with increases in the available power output from the PV energy source, so that a corresponding increase in power is transferred to the mains supply. | 2011-02-10 |
20110032735 | UNIVERSAL THREE PHASE CONTROLLERS FOR POWER CONVERTERS - The systems and methods described herein provide for a universal controller capable of controlling multiple types of three phase, two and three level power converters. The universal controller is capable of controlling the power converter in any quadrant of the PQ domain. The universal controller can include a region selection unit, an input selection unit, a reference signal source unit and a control core. The control core can be implemented using one-cycle control, average current mode control, current mode control or sliding mode control and the like. The controller can be configured to control different types of power converters by adjusting the reference signal source. Also provided are multiple modulation methods for controlling the power converter. | 2011-02-10 |
20110032736 | MIRROR-IMAGE VOLTAGE SUPPLY - A voltage supply incorporates two voltage supplies connected in a mirror-image series arrangement to generate a DC voltage between the respective common terminals of the voltage supplies. | 2011-02-10 |
20110032737 | Power Factor Correction Circuit for Three-Phase Power Supply - A power-factor correction circuit for a three-phase power supply is provided. The correction circuit comprises a filtering unit at the input receiving the three phases of the current, at least one inductor per phase placed downstream of the filtering unit, a rectifying bridge powering a current-chopping stage, wherein the filtering unit comprises a differential-mode filtering cell comprising at least one inductive circuit formed of a single magnetic material in a double E, each leg of the E being surrounded by a winding. The invention applies notably to the field of power electronics, in particular to the production of three-phase power supply units. | 2011-02-10 |
20110032738 | SYSTEM AND METHOD FOR POWER FACTOR CORRECTION - A first rectifier diode is electrically connected between a first input terminal where an alternating current (AC) power is received and a first output terminal where a direct current (DC) power is output. A second rectifier diode is electrically connected between the first input terminal and a second output terminal. The first and second rectifier diodes rectify first and second portions of the AC power into the DC power, respectively. When switching of a plurality of power factor correction (PFC) switches is enabled, the plurality of PFC switches increases a voltage of the DC power to greater than a peak voltage of the AC power. An inductor is electrically connected between a second input terminal and two of the plurality of PFC switches. When the switching is disabled, first and second bypass diodes provide a current path past the plurality of PFC switches and the inductor. | 2011-02-10 |
20110032739 | METHOD AND DEVICE TO COMPENSATE FOR AN ASYMMETRICAL DC BIAS CURRENT IN A POWER TRANSFORMER CONNECTED TO A HIGH VOLTAGE CONVERTER - A method and a device to compensate for an asymmetrical DC bias current in a multi-phase transformer. The transformer is connected between an AC power system and an AC/DC or DC/AC high voltage converter. For each phase of the AC side of the transformer a current quantity is determined. The current quantity reflects the time dependent behaviour of the magnetizing current in the phase. Time intervals in the current quantity are determined during which the current quantity reaches a positive or a negative maximum, respectively. A DC magnetizing quantity is determined from a difference between the amplitude of the positive maximum and the amplitude of the negative maximum. An asymmetrical quantity is determined from a difference between the amplitudes of the positive and/or negative maxima of at least two of the phases and a control signal is generated from the asymmetrical quantity and provided to a control device of the converter in order to adjust the generation of the AC or DC voltage in the particular phase of the converter which corresponds to the phase of the AC side of the transformer. | 2011-02-10 |
20110032740 | MEMORY SYSTEM HAVING IMPROVED SIGNAL INTEGRITY - A memory system having improved signal integrity includes a printed circuit board for use in a memory device, N memory semiconductor packages mounted on the printed circuit board, a first switch mounted on the printed circuit board, a controller mounted on the printed circuit board, N first signal lines connecting the semiconductor packages to the first switch such that the semiconductor packages and the first switch are in an N-to-1 correspondence, a second signal line connecting the first switch to the controller, and N selection lines connecting the semiconductor packages to the first switch such that the semiconductor packages and the first switch are in an N-to-1 correspondence. The N selection lines connect the semiconductor packages to the controller and transmit an enable signal. N is a natural number. | 2011-02-10 |
20110032741 | SEMICONDUCTOR MEMORY DEVICE - The SRAM cell is formed by an inverter circuit (P | 2011-02-10 |
20110032742 | One-time programmable memory cell with shiftable threshold voltage transistor - According to one exemplary embodiment, a one-time programmable memory cell includes an access transistor coupled to a shiftable threshold voltage transistor between a bitline and a ground, where the access transistor has a gate coupled to a wordline. The shiftable threshold voltage transistor has a drain and a gate shorted together. A programming operation causes a permanent shift in a threshold voltage of the shiftable threshold voltage transistor to occur in response to a programming voltage on the bitline and the wordline. In one embodiment, the access transistor is an NFET while the shiftable threshold voltage transistor is a PFET. In another embodiment, the access transistor is an NFET and the shiftable threshold voltage transistor is also an NFET. The programming voltage can cause an absolute value of the threshold voltage to permanently increase by at least 50.0 millivolts. | 2011-02-10 |
20110032743 | Colloidal-Processed Silicon Particle Device - Colloidal-processed Si particle devices, device fabrication, and device uses have been presented. The generic device includes a substrate, a first electrode overlying the substrate, a second electrode overlying the substrate, laterally adjacent the first electrode, and separated from the first electrode by a spacing. A colloidal-processed Si particle layer overlies the first electrode, the second electrode, and the spacing between the electrodes. The Si particle layer includes a first plurality of nano-sized Si particles and a second plurality of micro-sized Si particles. | 2011-02-10 |
20110032744 | RECORDING METHOD FOR MAGNETIC MEMORY DEVICE - [Object] To provide a recording method for a magnetic memory device including a recording layer that holds information as a magnetization direction of a magnetic body and a magnetization reference layer that is provided with respect to the recording layer with an insulation layer interposed therebetween, the magnetic memory device being recorded with information by a current flowing between the recording layer and the magnetization reference layer via the insulation layer, the recording method being capable of maintaining, even when a write pulse considerably higher than an inversion threshold value is applied, the same level of error rate as in a case where a write pulse a little higher than the inversion threshold value is applied. | 2011-02-10 |
20110032745 | NON-VOLATILE SEMICONDUCTOR MEMORY DEVICE - A non-volatile semiconductor memory device according to an aspect of embodiments of the present invention includes a memory cell array including: multiple first wirings; multiple second wirings crossing the multiple first wirings; and multiple electrically rewritable memory cells respectively arranged at intersections of the first wirings and the second wirings, and each formed of a variable resistor which stores a resistance value as data in a non-volatile manner. The non-volatile semiconductor memory device according to an aspect of the embodiments of the present invention further includes a controller for selecting a given one of the memory cells, generating an erase pulse which is used for erasing data, and supplying the erase pulse to the selected memory cell. The erase pulse has a pulse width which is increased or decreased exponentially in accordance with an access path length to the selected memory cell. | 2011-02-10 |
20110032746 | NONVOLATILE SEMICONDUCTOR MEMORY DEVICE - A nonvolatile semiconductor memory device according to an embodiment includes a memory cell array including: a plurality of first lines; a plurality of second lines intersecting the first lines; and a plurality of memory cells each including a variable resistance element disposed at the intersection of the first and second lines and configured to store an electrically rewritable resistance value as data in a nonvolatile manner, and a control unit configured to detect an amount of a current flowing through the first line when a memory cell is accessed, and adjust the voltage of the first or second line based on the amount of the current. | 2011-02-10 |
20110032747 | VARIABLE RESISTANCE MEMORY DEVICES AND METHODS OF PROGRAMMING VARIABLE RESISTANCE MEMORY DEVICES - A variable resistance memory device includes a variable resistance memory cell, and a by-pass circuit configured to electrically by-pass a programming pulse supplied to the variable resistance memory cell after a resistive state of the variable resistance memory cell has changed in response to the programming pulse. | 2011-02-10 |
20110032748 | POLARITY DEPENDENT SWITCH FOR RESISTIVE SENSE MEMORY - A memory unit includes a resistive sense memory cell configured to switch between a high resistance state and a low resistance state upon passing a current through the resistive sense memory cell and a semiconductor transistor in electrical connection with the resistive sense memory cell. The semiconductor transistor includes a gate element formed on a substrate. The semiconductor transistor includes a source contact and a bit contact. The gate element electrically connects the source contact and the bit contact. The resistive sense memory cell electrically is connected to the bit contact. The source contact is more heavily implanted with dopant material then the bit contact. | 2011-02-10 |
20110032749 | NAND Based Resistive Sense Memory Cell Architecture - Various embodiments are directed to an apparatus comprising a semiconductor memory array with non-volatile memory unit cells arranged into a NAND block. Each of the unit cells comprises a resistive sense element connected in parallel with a switching element. The resistive sense elements are connected in series to form a first serial path, and the switching elements are connected in series to form a second serial path parallel to the first serial path. Each resistive sense element is serially connected to an adjacent resistive sense element in the block by a tortuous conductive path having a portion that extends substantially vertically between said elements to provide operational isolation therefor. | 2011-02-10 |
20110032750 | SEMICONDUCTOR MEMORY DEVICE COMPRISING A PLURALITY OF STATIC MEMORY CELLS - A driver power supply circuit stepping down a power supply voltage is arranged at a power supply node of a word line driver. The driver power supply circuit includes a non-silicide resistance element of N+ doped polycrystalline silicon, and a pull-down circuit lowering a voltage level of the driver power supply node. The pull-down circuit includes a pull-down transistor having the same threshold voltage characteristics as a memory cell transistor pulling down a voltage level of the driver power supply node, and a gate control circuit adjusting at least a gate voltage of the pull-down transistor. The gate control circuit corrects the gate potential of the pull-down transistor in a manner linked to variations in threshold voltage of the memory cell transistor. | 2011-02-10 |
20110032751 | SEMICONDUCTOR DEVICE - The present invention is directed to provide a semiconductor device having a dual-port memory circuit in which influence of placement of replica cells exerted on enlargement of chip area is reduced. A memory cell array of a dual-port memory circuit has: a first replica cell array used to respond to an instruction of reading operation from one of dual ports; and a second replica cell array used to respond to an instruction of reading operation from the other dual port. Each of the replica cell arrays has: replica bit lines obtained by mutually short-circuiting parallel lines having a length obtained by cutting, in half, an inversion bit line and a non-inversion bit line of complementary bit lines to which data input/output terminals of a memory cell are coupled; and replica cells coupled to the replica bit lines and having transistor placement equivalent to that of the memory cells. | 2011-02-10 |
20110032752 | Multi-Level Memory Device Using Resistance Material - A multi-level memory device includes an insulating layer having an opening therein, and a multi-level cell (MLC) formed in the opening that has a resistance level varies based on the data stored therein. The MLC is configured to have a resistance level that varies as write pulses having the same pulse height and different pulse widths are applied to the MLC. | 2011-02-10 |
20110032753 | MEMORY CELLS INCLUDING RESISTANCE VARIABLE MATERIAL PATTERNS OF DIFFERENT COMPOSITIONS - A non-volatile memory device includes a plurality of word lines, a plurality of bit lines, and an array of variable resistance memory cells each electrically connected between a respective word line and a respective bit line. Each of the memory cells includes first and second resistance variable patterns electrically connected in series between first and second electrodes. A material composition of the first resistance variable pattern is different than a material composition of the second resistance variable pattern. Multi-bit data states of each memory cell are defined by a contiguous increase in size of a programmable high-resistance volume within the first and second resistance variable patterns. | 2011-02-10 |
20110032754 | PHASE CHANGE MEMORY ADAPTIVE PROGRAMMING - Some embodiments include methods and apparatus having a module configured to program a memory cell using a signal to cause the memory cell to have a programmed resistance value, to adjust a programming parameter value of the signal if the programmed resistance value is outside a target resistance value range, and to repeat at least one of the programming and the adjusting if the programmed resistance value is outside the target resistance value range, the signal including a different programming parameter value each time the programming is repeated. | 2011-02-10 |
20110032755 | VOLTAGE BOOSTING IN MRAM CURRENT DRIVERS - Disclosed is a current driving mechanism for a magnetic memory device, comprising: a) a current driver circuit; and b) a current decoding block coupled to the current driver circuit, wherein the current decoding block comprises a transistor M | 2011-02-10 |
20110032756 | Compact Semiconductor Memory Device Having Reduced Number of Contacts, Methods of Operating and Methods of Making - An integrated circuit including a link or string of semiconductor memory cells, wherein each memory cell includes a floating body region for storing data. The link or siring includes at least one contact configured to electrically connect the memory cells to at least one control line, and the number of contacts in the string or link is the same as or less than the number of memory cells in the string or link. | 2011-02-10 |
20110032757 | Programming Memory With Reduced Pass Voltage Disturb And Floating Gate-To-Control Gate Leakage - Program disturb is reduced in a non-volatile storage system by programming storage elements on a selected word line WLn in separate groups, according to the state of their WLn−1 neighbor storage element, and applying an optimal pass voltage to WLn−1 for each group. Initially, the states of the storage elements on WLn−1 are read. A program iteration includes multiple program pulses. A first program pulse is applied to WLn while a first pass voltage is applied to WLn−1, a first group of WLn storage elements is selected for programming, and a second group of WLn storage elements is inhibited. Next, a second program pulse is applied to WLn while a second pass voltage is applied to WLn−1, the second first group of WLn storage elements is selected for programming, and the first group of WLn storage elements is inhibited. A group can include one or more data states. | 2011-02-10 |
20110032758 | NONVOLATILE MEMORY DEVICE OUTPUTTING ANALOG SIGNAL AND MEMORY SYSTEM HAVING THE SAME - A memory system and a nonvolatile memory device therein are disclosed. The memory system comprises a memory device outputting a plurality of analog signals during a read operation, a converter to convert the plurality of analog signals into binary data, and a memory controller to operate an error correction operation on the binary data. The error correction operation uses a soft decision algorithm. | 2011-02-10 |
20110032759 | MEMORY SYSTEM AND RELATED METHOD OF PROGRAMMING - A method of programming a nonvolatile memory device comprises counting a number of state pairs in a unit of input data, modulating the unit of input data to reduce the number of state pairs contained therein, and programming the modulated unit of input data in the nonvolatile memory device. Each state pair comprises data with a first state and designated for programming in a memory cell connected to a first word line, and data with a second state and designated for programming in a memory cell connected to a second word line adjacent to the first word line. The memory cell connected to the first word line is adjacent to the memory cell connected to the second word line. | 2011-02-10 |
20110032760 | METHOD OF READING DATA IN SEMICONDUCTOR MEMORY DEVICE WITH CHARGE ACCUMULATION LAYER - According to one embodiment, a method of reading data in a semiconductor memory device including a plurality of memory cells associated with rows and columns and a plurality of latch circuits associated with the columns includes reading flag data from the memory cells associated with one of the columns into associated one of the latch circuits, selecting one of the latch circuits sequentially, while shifting one of the latch circuits to be selected, and reading the flag data from one of the latch circuits selected in an N | 2011-02-10 |
20110032761 | METHODS OF ERASE VERIFICATION FOR A FLASH MEMORY DEVICE - Methods and apparatus are disclosed, such as those involving a flash memory device that includes a memory block. The memory block includes a plurality of data lines extending substantially parallel to one another, and a plurality of memory cells. One such method includes erasing the memory cells; and performing erase verification on the memory cells. The erase verification includes determining one memory cell by one memory cell whether the individual memory cells coupled to one of the data lines have been erased. The method can also include performing a re-erase operation that selectively re-erases unerased memory cells based at least partly on the result of the erase verification. | 2011-02-10 |
20110032762 | MULTI-DOT FLASH MEMORY - According to one embodiment, a multi-dot flash memory includes an active area, a floating gate arranged on the active area via a gate insulating film and having a first side and a second side facing each other in a first direction, a word line arranged on the floating gate via an inter-electrode insulating film, a first bit line arranged on the first side of the floating gate via a first tunnel insulating film and extending in a second direction intersecting the first direction, and a second bit line arranged on the second side of the floating gate via a second tunnel insulating film and extending in the second direction. The active area has a width in the first direction narrower than that between a center of the first bit line and a center of the second bit line. | 2011-02-10 |
20110032763 | SEMICONDUCTOR DEVICES INCLUDING FIRST AND SECOND BIT LINES - In some embodiments, a semiconductor device includes first bit lines connected to respective first contacts. Spacers are disposed on sidewalls of the first bit lines. A second bit line is self-alignedly disposed between adjacent spacers, and a second contact is self-aligned with and connected to the second bit line. | 2011-02-10 |
20110032764 | SEMICONDUCTOR DEVICE AND CONTROL METHOD OF THE SAME - The present invention provides a semiconductor memory and a control method therefor, the semiconductor device including a first current-voltage conversion circuit ( | 2011-02-10 |
20110032765 | Memory Formed By Using Defects - A non-volatile memory is provided. The non-volatile memory comprises at least a silicon-on-insulator transistor including a substrate; an insulating layer disposed on the substrate; an active region disposed on the insulating layer; and an energy barrier device disposed in the active region and outputting a relatively small current when the non-volatile memory is read. | 2011-02-10 |
20110032766 | N-CHANNEL SONOS NON-VOLATILE MEMORY FOR EMBEDDED IN LOGIC - A system and method of an electrically programmable and erasable non-volatile memory cell fabricated using a single-poly, logic process with the addition of ONO deposition and etching is disclosed. In one embodiment, a non-volatile memory system includes at least one non-volatile memory cell consists of a SONOS transistor fabricated on a P substrate, with a deep N-well located in the P substrate, with a P-well located in the deep N-well. The memory cell further includes an access NMOS transistor, coupled to the SONOS transistor and located in the same P-well that includes an oxide only gate-dielectric. The cell can be fabricated in a modified logic process with other transistors and with their physical characteristics preserved. | 2011-02-10 |
20110032767 | SEMICONDUCTOR MEMORY, SYSTEM, AND METHOD OF CONTROLLING SEMICONDUCTOR MEMORY - A semiconductor memory includes: a non-volatile memory cell including a floating gate and a memory transistor; a state machine that generates a normal program signal for performing a normal program operation and a verify signal for performing a verify operation and generates a soft program signal for performing a soft program operation when detecting a fail in the verify operation after the normal program operation, whether a threshold voltage of the memory transistor reaches a value being checked in the verify operation; a voltage generating circuit that generates a normal program voltage and a verify voltage based on the normal program signal and the verify signal and generates a soft program voltage based on the soft program signal; and a determination circuit that detects a pass when the threshold voltage reaches the value and detects the fail when the threshold voltage does not reach the value. | 2011-02-10 |
20110032768 | ERASE DEGRADATION REDUCTION IN NON-VOLATILE MEMORY - Methods for erasing a memory device and memory systems are provided, such as those including a non-volatile memory device is erased by using an intermediate erase step prior to a normal erase step. The intermediate erase step is comprised of an erase pulse voltage, applied to the semiconductor well of the selected memory block of memory cells, while edge rows of memory cells are biased at a low positive voltage (e.g., 0.2-2V). An erase verify operation is then performed. If the selected memory block is not erased, a normal memory erase step is then performed in which the same erase pulse voltage is used but all of the rows are biased at ground potential as in a normal erase step. If the memory block is still fails the erase verify operation, the erase pulse voltage is increased and the process repeated. | 2011-02-10 |
20110032769 | SYSTEM FOR VERIFYING NON-VOLATILE STORAGE USING DIFFERENT VOLTAGES - When performing a data sensing operation, including a verify operation during programming of non-volatile storage elements (or, in some cases, during a read operation after programming), a first voltage is used for unselected word lines that have been subjected to a programming operation and a second voltage is used for unselected word lines that have not been subjected to a programming operation. In some embodiments, the second voltage is lower than the first voltage. | 2011-02-10 |
20110032770 | High Temperature Methods for Enhancing Retention Characteristics of Memory Devices - Methods are described for improving the retention of a memory device by execution of a retention improvement procedure. The retention improvement procedure comprises a baking process of the memory device in a high temperature environment, a verifying process of the memory device that checks the logic state of memory cells, and a reprogramming process to program the memory device once again by programming memory cells in a 0-state to a high-Vt state. The baking step of placing the memory device in a high temperature environment causes a charge loss by expelling shallow trapped charges, resulting in the improvement of retention reliability. | 2011-02-10 |
20110032771 | Memory and Reading Method Thereof - A reading method applied for a memory, which includes a cell row including a first memory cell coupled to a first bit line and a second memory cell coupled to a second bit line is provided. The reading method comprises the following steps. Firstly, the first bit line coupled to a first terminal of the first memory cell is selected for reading the first memory cell in a time period. Next, the second terminal of the first memory cell is discharged via the second bit line coupled to the second memory cell in the time period. | 2011-02-10 |
20110032772 | SEMICONDUCTOR DEVICE WITH VERTICAL GATE AND METHOD FOR FABRICATING THE SAME - A vertical channel type non-volatile memory device having a plurality of memory cells stacked along a channel includes the channel configured to be protruded from a substrate, a tunnel insulation layer configured to surround the channel, a plurality of floating gate electrodes and a plurality of control gate electrodes configured to be alternately stacked along the channel, and a charge blocking layer interposed between the plurality of the floating gate electrodes and the plurality of the control gate electrodes alternately stacked. | 2011-02-10 |
20110032773 | POWER SUPPLIES IN FLASH MEMORY DEVICES AND SYSTEMS - Power supplies in flash memory devices are disclosed. A first section of a flash memory device includes non-volatile memory for storing data. A second section of the flash memory device includes at least first and second pumping circuits. The first pumping circuit receives a first voltage and produces, at an output of the first pumping circuit, a second voltage at a second voltage level that is higher than the first voltage level. The second pumping circuit has an input coupled to the first pumping circuit output for cooperatively employing the first pumping circuit to pump up from a voltage greater than the first voltage to produce a third voltage at a third voltage level that is higher than the second voltage level. | 2011-02-10 |
20110032774 | Semiconductor Memory With Improved Memory Block Switching - A non-volatile memory core comprises one or more memory bays. Each memory bay comprises one or more memory blocks that include a grouping of non-volatile storage elements. In one embodiment, memory blocks in a particular memory bay share a group of read/write circuits. During a memory operation, memory blocks are transitioned into active and inactive states. The process of transitioning blocks from an inactive state to an active state includes enabling charge sharing between a memory block entering the active state and another memory block that was previously in the active state. This charge sharing improves performance and/or reduces energy consumption for the memory system. | 2011-02-10 |
20110032775 | MEMORY DEVICES AND METHOD FOR DRIVING A SIGNAL LINE TO A KNOWN SIGNAL LEVEL - A system and method for erasing a block of data in a plurality of memory cells includes clamping one of a digit line and an I/O line in a sensing circuit of a memory device to a fixed logic level. The memory cells of the block of memory cells are selected and refreshed to the fixed logic level. A sense amplifier includes a clamping circuit adapted to connect one of a digit line and an I/O line to a fixed logic level in response to an erase signal during a refresh of the selected block of memory cells. | 2011-02-10 |
20110032776 | MEMORY CIRCUIT AND VOLTAGE DETECTION CIRCUIT INCLUDING THE SAME - Provided are a memory circuit having a small circuit scale and a voltage detection circuit including the memory circuit. An NMOS transistor ( | 2011-02-10 |
20110032777 | Semiconductor memory circuit - The present invention provides a semiconductor memory circuit capable of reducing current consumption at non-operation in a system equipped with a plurality of chips that share the use of a power supply, address signals and a data bus. The semiconductor memory circuit has an internal circuit which is capable of selectively performing the supply and stop of an operating voltage via switch means and includes a memory array. An input circuit, which receives a predetermined control signal therein, controls the supply and stop of the operating voltage by the switch means to reduce a DC current and a leak current when no memory operation is done, whereby low power consumption can be realized. | 2011-02-10 |
20110032778 | SEMICONDUCTOR MEMORY DEVICE - A sense amplifier circuit senses and amplifies a signal read from memory cells arranged at intersections of word-lines and bit-lines. A write circuit reads first data held in a first memory cell of the memory cells, and writes second data corresponding to the first data in a second memory cell different from the first memory cell. A data latch circuit holds data read from the first memory cell. A logic operation circuit performs a logic operation using data read from the second memory cell and data held in the data latch circuit as input values and outputs third data as an operation value. A write-back circuit writes the third data back to the first memory cell. | 2011-02-10 |
20110032779 | SEMICONDUCTOR MEMORY DEVICE - A semiconductor memory device includes a memory cell provided at an intersection of a word line and a bit line, a precharge circuit connected to the bit line, a column select circuit controlled in accordance with a write control signal, and a clamp circuit provided as a write circuit. The clamp circuit includes a transistor configured to control the potential of a selected bit line to a first potential (e.g., 0 V), and a variable capacitor configured to control the potential of the selected bit line to a second potential (e.g., a negative potential) which is lower than the first potential. The capacitance of the variable capacitor decreases when a power supply voltage is increased, whereby the amount of a decrease from the first potential to the second potential is reduced. | 2011-02-10 |
20110032780 | Semiconductor device - The semiconductor device includes a first pair of data lines, a second pair of data lines, a third pair of data lines, a first amplifier (SA) connected to the first pair of data lines, a first switch that controls connection between the first pair of data lines and the second pair of data lines, a second switch that controls connection between the second pair of data lines and the third pair of data lines, a second amplifier that amplifies data on the second pair of data lines, for output to the third pair of data lines, a third amplifier connected to the third pair of data lines, and a control circuit that controls the second switch forming a pair of switches. When two data lines constituting the third pair of data lines both assume a first state, the control circuit controls the second switch to be turned off, thereby controlling the second pair of data lines and the third pair of data lines to be disconnected. Output data of the first amplifier is then output to the second pair of data lines via the first switch. When the two data lines constituting the third pair of data lines assume a second state different from the first state according to data output from the third amplifier, the second switch is controlled to be turned on, thereby controlling the second pair of data lines and the third pair of data lines to be connected. Then, the first amplifier receives the data output from the first amplifier. | 2011-02-10 |
20110032781 | MEMORY DEVICE AND MEMORY CONTROL METHOD - The embodiments of the present invention disclose a memory device having a fast and shared redundancy decision scheme and a memory control method. The memory device includes an address receiver, a command receiver, a command controller, a row address generator, a column address generator and a shared redundancy decision circuit. | 2011-02-10 |
20110032782 | Test method and device for memory device - Provided is a test method for a memory device including a plurality of storage regions and an SPO recovery unit. The test method stores data in the plurality of storage regions. The test method shuts off supply of power to the memory device and resupplies the power to the memory device. The test method determines an operational state of the SPO recovery unit after the resupplying step based on the stored data. | 2011-02-10 |
20110032783 | SEMICONDUCTOR STORAGE APPARATUS, AND METHOD AND SYSTEM FOR BOOSTING WORD LINES - A semiconductor storage apparatus includes: a word line coupled to a cell transistor; a first capacitor having a first end coupled to the word line; a boost driver coupled to a second end of the first capacitor; a voltage-drop circuit configured to generate a given voltage drop between a first voltage and a second voltage; and a boost-drive circuit configured to boost a voltage at the second end from the second voltage to the first voltage. | 2011-02-10 |
20110032784 | SEMICONDUCTOR MEMORY WITH MULTIPLE WORDLINE SELECTION - A semiconductor memory circuit, comprising: a memory array, the memory array including a plurality of wordlines each connected to a respective row of cells and a plurality of bitlines each connected to a respective column of cells. The semiconductor memory circuit also comprises at least one row decoder for selecting a group of wordlines within the plurality of wordlines; and a plurality of driver circuits for driving the plurality of bitlines respectively and setting the cells connected to the group of wordlines to a predetermined logic state. Also, a method for presetting at least part of a memory array, the memory array comprising a plurality of wordlines each connected to a respective row of cells. The method comprises selecting a group of wordlines within the plurality of wordlines; and simultaneously setting memory cells connected to the group of wordlines to a predetermined logic state. | 2011-02-10 |
20110032785 | WORDLINE DRIVER, MEMORY DEVICE INCLUDING THE SAME AND METHOD OF DRIVING A WORDLINE - A wordline driver includes a pre-driver, a sub-wordline driver and a transmission circuit. The pre-driver generates a wordline enable signal and a wordline disable signal based on one or more selection signals, a decoded address signal, and one or more timing control signals. The transmission circuit transmits the wordline enable signal and the wordline disable signal. The sub-wordline driver controls a voltage level of the sub-wordline based on the wordline enable signal and the wordline disable signal that are transmitted by the transmission circuit. Therefore, driving capacity may be improved. | 2011-02-10 |
20110032786 | SUB-WORD LINE DRIVER CIRCUIT AND SEMICONDUCTOR MEMORY DEVICE HAVING THE SAME - A sub-word line driver includes a substrate, a plurality of gate lines and at least one gate tab. The substrate includes a plurality of isolation areas and a plurality of active areas, where the two active areas are separated by each isolation area, and the isolation areas and the active areas are extended in a first direction and are arranged in a second direction perpendicular to the first direction. The plurality of gate lines are formed on the substrate, where the gate lines are extended in a second direction and are arranged in the first direction. The at least one gate tab is formed on the substrate, where the at least one gate tab is extended in the first direction to cover the isolation area. Incorrect operation of the sub-word line driver may be prevented, and a power consumption of the sub-word line driver may be reduced. | 2011-02-10 |
20110032787 | INPUT BUFFER CIRCUIT, SEMICONDUCTOR MEMORY DEVICE AND MEMORY SYSTEM - An input buffer circuit includes a logic unit, a clock enable buffer, and a clock buffer. The logic unit is configured to receive a clock signal and a clock enable signal, and to output a decision signal indicative of whether the clock signal is normally input, where the decision signal is activated when the clock signal is normally input. The clock enable buffer is configured to buffer the clock enable signal and to activate an internal clock enable signal, in response to an activation of the decision signal. The clock buffer is configured to buffer the clock signal and to output an internal clock signal, in response to an activation of the internal clock enable signal. | 2011-02-10 |
20110032788 | LIQUID MIXING CHAMBER - An apparatus and method for mixing and dispensing liquids without contamination of starting liquids during the dispensing operation, the apparatus comprising a first container, resiliently deformable, containing a first liquid, a second container containing a second liquid, and a mixing chamber. | 2011-02-10 |
20110032789 | EMULSION MANUFACTURING EQUIPMENT - [Object]To provide emulsion manufacturing equipment that can continuously produce and consume an emulsion, reduce a tank volume, and reduce production cost without need for an agitator.
| 2011-02-10 |
20110032790 | VENTURI-EFFECT MODULAR MIXER - A Venturi-effect mixer for mixing a working fluid with at least one decontamination/detoxification product. The mixer ( | 2011-02-10 |
20110032791 | STIRRING SYSTEM AND METHOD FOR HOMOGENIZING GLASS MELTS - The invention relates to a stirring system for molten glass and to a stirring vessel ( | 2011-02-10 |
20110032792 | PROCESSING CONTAINER STRUCTURE FOR FOOD PROCESSOR - A processing container structure for food processor is provided. The structure has a processing container main body whose inside walls are uniformly provided with multiple ribs arranged vertically. The ribs have certain lengths and thicknesses and protrude inwards. The protruding areas of the ribs are gradually increased from top to bottom. | 2011-02-10 |
20110032793 | ACOUSTIC SYSTEM QUALITY ASSURANCE AND TESTING - Embodiments of the invention provide systems and methods for testing acoustic systems. According to one embodiment, a method for testing an acoustic system can comprise receiving a signal from the acoustic system at a testing device coupled with the acoustic system via one of a plurality of channels between the acoustic system and the testing device. The signal can include a pattern of pulses including Doppler pulses. At least one Doppler pulse from the pattern pulses of the signal can be detected with the testing device. A response to the signal from the acoustic system can be provided by generating an echo pulse with the testing device based on the detected at least one Doppler pulse wherein the echo pulse is frequency shifted from the detected at least one Doppler pulse and mimics a response to the detected at least one Doppler pulse for a selected acoustic probe. | 2011-02-10 |
20110032794 | Undersea seismic monitoring network - The present invention provides an undersea seismic monitoring network, the monitoring network comprises at least one underwater vehicle and at least two monitoring stations located on the seabed, where each of the monitoring stations comprises at least one sensor for gathering seismic data and a radio modem for transmitting and receiving data to and from the underwater vehicle via a first wireless connection and where a second wireless connection is established between the monitoring stations, wherein the first wireless connection is formed by electromagnetic radiation through the water and the second wireless connection is formed by the propagation of an electromagnetic signal at least partially through the seabed. | 2011-02-10 |
20110032795 | Method for Reducing Marine Source Volume While Maintaining Image Quality - A technique facilitates the acquisition of seismic data at a substantially reduced source volume. The methodology generally comprises conducting a seismic survey with seismic sources that have a reduced source volume to collect seismic data. The low frequency data which is lost due to the reduced source volume is replaced with data acquired from a complementary method, such as a receiver-side acquisition method. The two sets of data are combined to provide a comprehensive seismic survey image without requiring conventional seismic source volume. | 2011-02-10 |
20110032796 | System and method for producing an acoustic pulse using live steam - An improved system and method for seismic exploration using live steam involves creating a cavity of live steam in a body of water, the cavity of live steam imploding due to the water cooling the live steam thereby producing an acoustic pulse, receiving reflections of the acoustic pulse at one or more receivers, and processing the reflections of the acoustic pulse. The cavity of live steam can be created by controlling release valves to introduce live steam into the body of water or by introducing hydrogen and at least one of oxygen or air into the water to create a bubble and then igniting the bubble. | 2011-02-10 |
20110032797 | Magnetic mass-lift impulsive seismic energy source including attracting and repulsing electromagnets - A seismic energy source includes a base plate and a block fixedly coupled in a frame. The base plate is configured for contact with a part of the Earth's subsurface to be seismically energized. The frame has a first electromagnet associated therewith. A second electromagnet is disposed in a travelling reaction mass, which is movably disposed in the frame between the first electromagnet assembly and the top block. The reaction mass includes at least a third electromagnet associated therewith. The source has circuits for selectively energizing the first, second and at least a third electromagnets, and which are configured to energize the first and second electromagnets to repel each other such that the traveling reaction mass is lifted from the first electromagnet, and configured to energize the at least a third electromagnet after a selected delay time to cause attraction between the traveling reaction mass and the top block | 2011-02-10 |
20110032798 | APPARATUS FOR CORRECTING THE TIMING FUNCTION IN A NODAL SEISMIC DATA ACQUISITION UNIT - A wireless seismic data acquisition unit with a wireless receiver providing access to a common remote time reference shared by a plurality of wireless seismic data acquisition units in a seismic system. The receiver is capable of replicating local version of remote time epoch to which a seismic sensor analog-to-digital converter is synchronized. The receiver is capable of replicating local version of remote common time reference for the purpose of time stamping local node events. The receiver is capable of being placed in a low power, non-operational state over periods of time during which the seismic data acquisition unit continues to record seismic data, thus conserving unit battery power. The system implements a method to correct the local time clock based on intermittent access to the common remote time reference. The method corrects the local time clock via a voltage controlled oscillator to account for environmentally induced timing errors. The invention further provides for a more stable method of correcting drift in the local time clock. | 2011-02-10 |
20110032799 | ACOUSTIC SYSTEM QUALITY ASSURANCE AND TESTING - Embodiments of the invention provide systems and methods for testing acoustic systems. According to one embodiment, a method for testing an acoustic system can comprise receiving a signal from the acoustic system at a testing device coupled with the acoustic system via one of a plurality of channels between the acoustic system and the testing device. The signal can include a pattern of pulses. At least one pulse from the pattern of pulses of the signal can be detected with the testing device. A response to the signal from the acoustic system can be provided by generating an echo pulse with the testing device based on the detected at least one pulse. The echo pulse can mimic a response to the detected at least one pulse for a selected acoustic probe. | 2011-02-10 |
20110032800 | PHASED ARRAY ULTRASONIC CONTACT TRANSDUCER, WITH A FLEXIBLE WEDGE AND A PROFILOMETER - Phased array ultrasonic contact transducer, with a flexible wedge and a profilometer. This transducer applies to the non-destructive monitoring of an object and comprises: a set of elements that are rigidly integral with each other, at least part of the elements serving as ultrasound transmitters, a wedge whereof at least the front face is flexible to be applied against the surface of the object and the rear face of which is made integral with the set of elements, and a profilometer to measure surface variations and supply signals representative thereof to allow the transmitters to create a focused ultrasonic beam whereof the characteristics are controlled in relation to the object. | 2011-02-10 |
20110032801 | UNDERWATER DETECTION DEVICE - This disclosure provides a detection device, which includes a transceiving module for periodically transmitting a detection pulse signal toward a space and receiving a reflection wave from a target object as a reception signal, a signal loading module for generating a distance section row by dividing a given detection distance range into a plurality of distance sections, obtaining reception data by sequentially sampling the reception signal for every distance section, and storing the reception signal in a memory, and an interference processing module for sequentially performing interference removal processing for the reception data of each of the distance sections stored in the memory. The interference processing module includes an interference wave determination module for determining for every distance section whether the reception data of the distance section row including a target distance section is resulting from an interference wave, a signal generating module, if the reception data is determined to be resulting from the interference wave for generating data to be displayed based on one or more reception data other than the reception data in proximity to the reception data at least either in a distance direction or a transmission cycle direction, and if the reception data is determined to be resulting from the reflection wave, for using the reception data as the data to be displayed, and a display module for displaying the data to be displayed. | 2011-02-10 |
20110032802 | WATCH WITH TIME ZONE DISPLAY - The analogue display watch includes two separate time displays ( | 2011-02-10 |
20110032803 | MINUTE-REPEATER TIMEPIECE - The escapement racks for the hour ( | 2011-02-10 |
20110032804 | WRIST MOUNTED WATCHCASE HAVING SEPARABLE MAIN BODY AND SURROUNDING PROTECTIVE FRAME AND WRISTWATCH INCORPORATING SAME - A watch includes a watch movement, a dial supported on the watch movement, hands moveable by the watch movement with a watch case receiving the watch movement. The watch case includes a cylindrical main body configured to receive the watch movement therein, a bezel supported on the main body and a crystal supported by the main body. The watch case further includes a frame receiving the main body, wherein the frame comprises a back frame plate configured to be adjacent the user, a top frame plate spaced from the back frame plate and including a central opening therein for receipt of the main body, a pair of lugs on opposed ends of the frame, wherein each lug extends between the spaced top frame plate and the back frame plate, a bar extending between each pair of lugs, wherein each bar is configured to receive a strap of a wrist watch. | 2011-02-10 |
20110032805 | INFORMATION RECORDING MEDIUM, REPRODUCING DEVICE AND REPRODUCING METHOD - An information recording medium according to the present invention includes at least three information recording layers. If the readout power of a laser beam in reading information from an information recording layer L(n) is identified by Pw(n), and if the readout power of the laser beam in reading information from an information recording layer L(n+a) is identified by Pw(n+a), then a base thickness between the information recording layers is determined so that the intensity of the light when the information recording layer L(n+a) is irradiated with a laser beam having the readout power Pw(n) becomes equal to or lower than that of the light when the information recording layer L(n+a) is irradiated with a laser beam having the readout power Pw(n+a). | 2011-02-10 |
20110032806 | OPTICAL DISC AND OPTICAL DISC APPARATUS - An optical disc recording method for recording disc information to be used in recording/reproducing control on an optical disc, comprises the following steps of: providing a first disc information unit and a second disc information unit, each having a predetermined data size, in a predetermined management information area of the optical disc; the disc information includes write strategy information; separating the write strategy information into first write strategy information and second write strategy information; recording the first disc information into the first disc information unit; and recording the second disc information into the second disc information unit. | 2011-02-10 |
20110032807 | OPTICAL PICKUP DEVICE AND OPTICAL DISK DEVICE INCLUDING THE SAME - An optical pickup device is provided. In an optical pickup device, a light receiving element has light receiving regions for focusing as part of the plurality of light receiving regions. A diffraction element has diffraction regions for focusing as part of the plurality of diffraction regions. A part of division lines which define the diffraction region for focusing is formed in a shape which is convex from the outer side toward the inner side with respect to the center of the incidence range on the diffraction element where a returning light beam enters. The part of the division lines formed in the shape which is convex from the outer side toward the inner side divides an incidence range on the diffraction element where a returning light beam enters, regardless of whether or not there is a focus error. | 2011-02-10 |
20110032808 | INTEGRATED CIRCUIT, INFORMATION RECORDING/REPRODUCING APPARATUS, AND SIGNAL PROCESSING METHOD - An information recording/reproducing apparatus including an optical pickup unit for generating an RF signal performs signal processing to acquire, at a restart of recording after a halt of recording, a data ID to be used as a reference for specifying a recording restart position in the recording medium based on the RF signal. The signal processing includes reproduced signal generation processing to generate a reproduced signal based on the RF signal, and data ID acquisition determination processing to determine, at the restart of recording after the halt of recording, whether or not the data ID has been properly acquired, based on the reproduced signal. If it is determined in the data ID acquisition determination step that the data ID has not been properly acquired, a reproduction parameter to be used for generating the reproduced signal in the reproduced signal generation step is adjusted. | 2011-02-10 |
20110032809 | INFORMATION RECORDING MEDIUM EVALUATION METHOD, INFORMATION RECORDING MEDIUM, METHOD FOR MANUFACTURING INFORMATION RECORDING MEDIUM, SIGNAL PROCESSING METHOD AND ACCESS CONTROL APPARATUS - A method for rating an information recording medium according to the present invention includes the steps of: receiving a digital read signal, which has been generated based on an analog read signal representing information that has been read from the information recording medium, and shaping the waveform of the digital read signal; subjecting the shaped digital read signal to maximum likelihood decoding, thereby generating a binarized signal showing a result of the maximum likelihood decoding; and calculating the quality of the digital read signal based on the shaped digital read signal and the binarized signal. If the quality of the read signal is calculated by a PRML method in which a number of zero-cross portions are included in a merging path of a minimum difference metric, the quality is calculated by using only a state transition pattern in which only one zero-cross portion is included in a merging path of a non-minimum difference metric. | 2011-02-10 |
20110032810 | MASTER DEVICE - The invention relates to a master device which can be used in a method for producing a recording medium, a substantially spirally or concentrically running main track structure and at least one substantially spirally or concentrically running secondary track structure being formed on the master device, the secondary track structure being arranged on at least one side of the main track structure, the secondary track structure having discontinuities varying an optically detectable surface texture of the recording medium in such a way that at least first auxiliary information is represented on the recording medium. | 2011-02-10 |
20110032811 | DIFFRACTIVE OPTICAL ELEMENT, OBJECTIVE OPTICAL SYSTEM INCLUDING THE SAME, AND OPTICAL PICKUP INCLUDING THE SAME - A diffractive optical element includes a first optical part and a second optical part bonded to each other with a bonded surface therebetween configured as a diffraction surface. In this diffractive optical element, the diffraction order of diffracted light with the largest quantity of light out of diffracted light for one of a plurality of kinds of laser beams obtained on the diffraction surface is different from the diffraction order for at least another laser beam. | 2011-02-10 |
20110032812 | OPTICAL HEAD DEVICE AND OPTICAL DISK PLAYBACK SYSTEM - Problem: To provide a recording and reproducing device that is capable of improving in its reproduction quality by efficiently detecting a reproduction signal having small low frequency noises even when reproducing data on a super-resolution optical disk including recording marks smaller than a diffraction limit. | 2011-02-10 |
20110032813 | METHOD AND DEVICE FOR CONTROLLING UPLINK POWER - A method for controlling uplink power is provided, which is used for implementing the uplink power control of the virtual multiple input multiple output system, so as to save the system resource. The method includes: determining at least two user equipments being paired in a virtual multiple input multiple output system; and in accordance with the orthogonality of the at least two user equipments, adjusting at least the power of one of the user equipments. In addition, a device for implementing the method is provided. | 2011-02-10 |
20110032814 | Session Resilience Prioritization Queuing Mechanism to Minimize and Eliminate Packet Loss - A method for managing a plurality of subscriber sessions tied to mobile devices in a router, each subscriber session of the plurality of subscriber sessions assigned to a line card in the router, the line card implementing a data plane entity and a control card implementing a control plane entity, the method comprising: redistributing each subscriber session in the plurality of subscriber sessions assigned to a failed line card in the router to minimize packets lost and maximize subscriber session retention, redistributing including classifying each subscriber session in the plurality of subscriber sessions into a plurality of priority queues, in response to detection of the failed line card, transferring each subscriber session in the plurality of subscriber sessions assigned to the failed line card to one of a plurality of operating line cards in priority queue order. | 2011-02-10 |
20110032815 | MOBILE COMMUNICATION SYSTEM, MOBILE STATION, BASE STATION, AND HANDOVER CONTROLLING METHOD - A mobile station measures reception quality levels of individual peripheral cells of a source cell and transmits information of the measured reception quality levels of the individual peripheral cells to a source base station that manages the source cell. The source base station selects a group of cells that are to be handed over, based on the information of reception quality levels of the individual peripheral cells that is received from the mobile station, and transmits information of handover ready completion cells that are ready for handover in the selected group of cells to the mobile station. The mobile station selects a target cell that is to be handed over, based on the information of handover ready completion cells that is received from the source base station, and on the information of reception quality levels of the individual peripheral cells at that time. | 2011-02-10 |
20110032816 | Connection Failure Notification Method And Apparatus - An access point according to the present invention generates and broadcasts a notification message to the mobile devices serviced by an access point upon detection of a connection failure between the serving access point and a network node. The notification message controls the impact of the connection failure on neighboring cells by including redirect information that identifies one or more alternate access points for the affected mobile devices. The affected mobile devices subsequently attempt to access the access points identified by the redirect information. The notification message may also include timing information that informs the affected mobile devices when they may attempt to access an alternate access point identified by the redirect information. | 2011-02-10 |
20110032817 | Method, Apparatus and Communication System for Protecting Signaling Transmission - The present invention discloses a method, an apparatus, and a communication system for protecting signaling transmission, relates to the communication field, and enables end-to-end signaling protection. In an embodiment of the present invention, a primary signaling path and at least one secondary signaling path are created between terminals; the transmission protocol of the primary signaling path is different from the transmission protocol of the secondary signaling path, and the secondary signaling path works instead when the primary signaling path is in an abnormal state. The embodiments of the present invention are primarily applied to communication systems, and in particular, to the communication systems that support multiple transmission modes, for example, WCDMA system that supports IP bearers. | 2011-02-10 |
20110032818 | PATH CONTROL DEVICE, PATH CONTROL METHOD, AND PATH CONTROL PROGRAM - A path control device included in a terminal device ( | 2011-02-10 |