| 06th week of 2012 patent applcation highlights part 27 |
| Patent application number | Title | Published |
|---|
| 20120033456 | ACTIVE CLAMP DC-DC CONVERTER - An active clamp DC-DC converter includes a transformer having a primary coil and a secondary coil, a main switching device connected in series to the primary coil of the transformer so that the main switching device and the primary coil are connected in parallel to a DC power source, a reset capacitor, a reset switching device connected in series to the reset capacitor so that the reset switching device and the reset capacitor are connected in parallel to the primary coil of the transformer, a rectifying circuit connected to the secondary coil of the transformer, a smoothing circuit connected to the rectifying circuit, and a control circuit adjusting a dead time that elapses from the time when the reset switching device is turned off until the time when the main switching device is turned on, based on a voltage across the main switching device. | 2012-02-09 |
| 20120033457 | HOLD-UP TIME EXTENDING CIRCUIT AND CONVERTER INCLUDING THE SAME - The present invention relates to a hold-up time expansion circuit and a converter including the same. | 2012-02-09 |
| 20120033458 | System and Method for Power Conversion - A system and method for operating power supplies. A method comprises altering a current sense (CS) signal, turning off a switch of the converter in response to a determining that the CS signal is greater than or equal to a first threshold, and leaving on the switch of the converter in response to a determining that the CS signal is less than the first threshold. | 2012-02-09 |
| 20120033459 | CIRCUIT REGULATOR AND SYNCHRONOUS TIMING PULSE GENERATION CIRCUIT THEREOF - A circuit regulator is used to generate a pulse-width-modulation signal, so as to control a power to be selectively input or not input to a primary side of a switching power supply. The circuit regulator includes a synchronous timing pulse generation circuit, outputs a starting pulse after performing signal process of time delay, timing pulse regulation, and synchronization control on a pulse-width-modulation signal and a discharging time signal of a secondary side, and accordingly effectively controls a pulse starting time of the pulse-width-modulation signal. Therefore, the synchronous timing pulse generation circuit can be applied to the circuit regulator, so as to further effectively prevent an inductor current of the switching power supply from entering a Continuous Conduction Mode (CCM). | 2012-02-09 |
| 20120033460 | High-Side Synchronous Rectifier Circuits and Control Circuits for Power Converters - A control circuit for a switching power converter is provided. The control circuit is installed between a secondary side and an output of the power converter and coupled to control a switching device. The control circuit includes a linear predict circuit, a reset circuit, a charge/discharge circuit, and a PWM circuit. The linear predict circuit is coupled to receive a linear predict signal from the secondary side for generating a charging signal. The reset circuit is couple to receive a resetting signal for generating a discharging signal. The charge/discharge circuit is coupled to receive the charging signal and the discharging signal for generating a ramp signal. The PWM circuit is coupled to receive the linear predict signal for enabling a switching signal and receive the ramp signal for resetting the switching signal. | 2012-02-09 |
| 20120033461 | CONTROLLING A HIGH-VOLTAGE DIRECT-CURRENT (HVDC) LINK - The present disclosure is directed to a High Voltage Direct Current (HVDC) link with Voltage Source Converters VSC and interconnecting two power systems. A model-predictive control with a receding horizon policy is employed for controlling the outer loop of a two-loop or two-layer control scheme or setup for the HVDC link. The two-loop control scheme takes advantage of the difference in speed of the dynamics of the various system variables of the HVDC link and the interconnected power systems. Model-based prediction representative of the interconnected power systems' behavior enables comparison of the future effect of different control inputs applied within the control scheme, while taking into account any physical, safety and operating constraints. It is valid for a complete operating range, e.g., it avoids performance degradation when moving away from the nominal operating point of the control scheme for a HVDC link. | 2012-02-09 |
| 20120033462 | POWER FLOW CONTROL IN A MESHED HVDC POWER TRANSMISSION NETWORK - A meshed HVDC power transmission network comprises at least three HVDC converter stations interconnected in a first closed path by at least three transmission lines. A first DC power flow control device is series connected to a first of the at least three transmission lines. That first DC power flow control device takes its power from the first transmission line and balances the DC current distribution in the first closed path. | 2012-02-09 |
| 20120033463 | POWER CONDITIONING UNIT - The present invention relates to a power conditioning unit for delivering power from a dc power source to an ac output, particularly ac voltages greater than 50 volts, either for connecting directly to a grid utility supply, or for powering mains devices independent from the mains utility supply. We describe a power conditioning unit for delivering power from a dc power source to an ac mains output, the power conditioning unit comprising an input for receiving power from said dc power source, an output for delivering ac power, an energy storage capacitor, a dc-to-dc converter having an input connection coupled to said input and an output connection coupled to the energy storage capacitor, and a dc-to-ac converter having an input connection coupled to said energy storage capacitor and an output connection coupled to said output, wherein said energy storage capacitor has a capacitance of less than twenty microfarads. | 2012-02-09 |
| 20120033464 | Universal Power Converter - Methods and systems for transforming electric power between two or more portals. Any or all portals can be DC, single phase AC, or multi-phase AC. Conversion is accomplished by a plurality of bi-directional conducting and blocking semiconductor switches which alternately connect an inductor and parallel capacitor between said portals, such that energy is transferred into the inductor from one or more input portals and/or phases, then the energy is transferred out of the inductor to one or more output portals and/or phases, with said parallel capacitor facilitating “soft” turn-off, and with any excess inductor energy being returned back to the input. Soft turn-on and reverse recovery is also facilitated. Said bi-directional switches allow for two power transfers per inductor/capacitor cycle, thereby maximizing inductor/capacitor utilization as well as providing for optimum converter operation with high input/output voltage ratios. Control means coordinate the switches to accomplish the desired power transfers. | 2012-02-09 |
| 20120033465 | THERMAL SHUTDOWN UNIT, SWITCH CONTROLLER INCLUDING THE SAME, AND CONTROL METHOD OF THERMAL SHUTDOWN PROTECTION OPERATION - The present invention relates to a thermal shutdown unit, a switch controller including the same, and a method controlling a thermal shutdown protection operation. | 2012-02-09 |
| 20120033466 | PARTIAL POWER MICRO-CONVERTER ARCHITECTURE - A system and method for reducing the amount of power processed in a power converter during power generation is provided. In one aspect, the system includes a partial power converter connected between a set of power sources and a load. The partial power converter includes a primary power converter coupled to a first power source and a set of auxiliary power converters coupled to the remaining power sources. Moreover, the secondary power converters only process current that is necessary to achieve a maximum power point (MPP) for each power source. In one example, the secondary power converters are smaller in size and/or power rating, as compared to the primary power converter, and thus reduce the size and cost of the system. Additionally, the secondary power converters operate on an “as-needed” basis rather than in “always-on” fashion, and thus are more reliable and efficient. | 2012-02-09 |
| 20120033467 | SWITCHING MODE POWER SUPPLY AND METHOD OF CONTROLLING THE SAME - A switching mode power supply (SMPS) includes at least one transformer, a switching unit to switch a voltage applied to the at least one transformer, a snubber circuit connected to the switching unit, a first switch to control an on or off operation of the snubber circuit, and a second switch to control an on or off operation of the first switch. | 2012-02-09 |
| 20120033468 | POWER CONVERSION SYSTEMS - In a general aspect, a power conversion system includes a power converter, a transformer, and a voltage adjustment device. The power converter is configured to receive a variable DC power generated by a power generation device and to convert the received DC power to AC power at a first voltage. The transformer is configured to receive the AC power from the power converter and to deliver AC power at a second voltage to a utility power network. The voltage adjustment device is configured to adjust the first voltage to a target value determined on the basis of a voltage of the DC power. | 2012-02-09 |
| 20120033469 | Electric Power Conversion System Having An Adaptable Transformer Turns Ratio For Improved Efficiency - An electric power conversion system has an adaptable transformer turns ratio for improved efficiency. The transformer has multiple taps on its primary. Switching circuitry is configured to connect an energy source to the taps in at least two modes such that the transformer operates with a first primary-to-secondary turns ratio in the first mode and with a second primary-to-secondary turns ratio in the second mode. The first turns ratio is greater than the second turns ratio. Control circuitry is configured to operate the switching circuitry in the first mode when a voltage level of the energy source is above a first threshold and to operate the switching circuitry in the second mode when the voltage level is below a second threshold. | 2012-02-09 |
| 20120033470 | METHOD OF CONTROLLING POWER CONVERSION DEVICE - A correction-term adder 1 compares a maximum value max(V*) with an absolute value of a minimum value min(V*). The correction-term adder 1 selects a signal 1−max(V*) when the maximum value max(V*) is larger than the absolute value of the minimum value min(V*), on the other hand, selects a signal −1−min(V*) when the absolute value of the minimum value min(V*) is larger than the maximum value max(V*). Thereby, a signal of correction amount α is calculated. Moreover, the correction-term adder 1 produces a triangular-wave-shaped signal k(max(V*)+min(V*)) by multiplying a gain k by an addition signal max(V*)+min(V*) of the maximum value max(V*) and the minimum value min(V*). This triangular-wave-shaped signal k(max(V*)+min(V*)) is synchronized with the correction amount α. The correction-term adder 1 produces a correction amount β by selecting smaller one in absolute value between the triangular-wave-shaped signal k(max(V*)+min(V*)) and the correction amount α, and adds the correction amount β to the voltage command values V* | 2012-02-09 |
| 20120033471 | TWO-WIRE DIMMER SWITCH FOR LOW-POWER LOADS - A two-wire load control device (such as, a dimmer switch) for controlling the amount of power delivered from an AC power source to an electrical load (such as, a high-efficiency lighting load) includes a thyristor coupled between the source and the load, a gate coupling circuit coupled between a first main load terminal and the gate of the thyristor, and a control circuit coupled to a control input of the gate coupling circuit. The control circuit generates a drive voltage for causing the gate coupling circuit to conduct a gate current to thus render the thyristor conductive at a firing time during a half cycle of the AC power source, and to allow the gate coupling circuit to conduct the gate current at any time from the firing time through approximately the remainder of the half cycle, where the gate coupling circuit conducts approximately no net average current to render and maintain the thyristor conductive. | 2012-02-09 |
| 20120033472 | Multi-Phase Drive System - A drive system for driving a multi-phase motor (such as a three-phase AC motor) or other load. Where a transformer is used, the transformer may have a disconnected wye configuration on the secondary side. The system may also utilize the average or other combination of DC bus voltages of inverters for each load phase, to provide feedback control. | 2012-02-09 |
| 20120033473 | SYSTEMS AND METHODS FOR ELECTRICAL POWER GRID MONITORING USING LOOSELY SYNCHRONIZED PHASORS - The present disclosure describes systems and methods for monitoring an electrical power grid using loosely synchronized phasors. The grid can include a phasor measurement unit (PMU) that keeps a highly-accurate time, such as a time provided by GPS signals. A solar power inverter can include a clock that is synchronized to a less-accurate time, such as a time provided by a public time server or a radio time signal. The inverter can also include a PMU that generates phasors timestamped according to the less-accurate time. The inverter can receive phasors from the grid PMU. Although the grid and inverter phasors can be loosely synchronized in time, the inverter can analyze the grid and inverter phasors to determine a state of the grid. For example, the inverter can calculate a Pearson's correlation coefficient based on the grid and inverter phasors, and use the result to determine a state of the grid. | 2012-02-09 |
| 20120033474 | HIGHLY EFFICIENT HALF-BRIDGE DC-AC CONVERTER - The invention relates to a DC to AC converter circuit. In particular, the invention relates to a half-bridge inverter for converting a DC to an AC voltage. The half-bridge inverter for converting a DC input voltage to provide an AC output voltage at an output terminal, comprising a first switching circuit connected to at least one input terminal and to the output terminal and configured to provide a high or a low voltage level at the output terminal; a second switching circuit connected to the output terminal and configured to provide a connection to an intermediate voltage level, the intermediate voltage level being between the high and the low voltage level; and wherein the second switching circuit is further connected to the at least one input terminal allowing the second switching circuit to provide the high or the low voltage level at the output terminal. | 2012-02-09 |
| 20120033475 | POWER CONVERSION APPARATUS - Technology leading to a size reduction in a power conversion apparatus comprising a cooling function and technology relating to enhancing productivity and enhancing reliability necessary for commercial production are provided. Series circuits comprising an upper arm and lower arm of an inverter circuit are built in a single semiconductor module | 2012-02-09 |
| 20120033476 | INVERTER CIRCUIT, POWER CONVERTER CIRCUIT, AND ELECTRIC VEHICLE - An object is to reduce, with the control circuit of the full-bridge inverter circuit, distortions in an output signal of the inverter circuit resulting from an error in control of the switching of the high-side transistors and low-side transistors included in the first half-bridge circuit and the second half-bridge circuit. The pulse width of a signal that controls ON/OFF of the high-side transistors and low-side transistors included in the first half-bridge circuit and the second half-bridge circuit is reduced, i.e., the duty cycle of the signal is reduced. This results in a reduction in short-circuit periods during which both the high-side transistor and the low-side transistor are on, thereby reducing distortions in a signal. | 2012-02-09 |
| 20120033477 | MEMORY MODULES HAVING DAISY CHAIN WIRING CONFIGURATIONS AND FILTERS - Examples described include memory units coupled to a controller using a daisy chain wiring configuration. A filter located between a first memory unit and the controller attenuates a particular frequency, which may improve ringback in a signal received at the memory units. In some examples, a quarter-wavelength stub is used to implement the filter. In some examples, signal components at 800 MHz may be attenuated by a stub, which may improve ringback. | 2012-02-09 |
| 20120033478 | NON-VOLATILE MEMORY DEVICE AND SENSING METHOD FOR FORMING THE SAME - A non-volatile memory device and a method for forming the same are disclosed, which relate to a ferroelectric memory device having non-volatile characteristics. The non-volatile memory device includes a control gate configured to receive a read voltage, an insulation film formed over the control gate, a metal layer formed over the insulation film, configured to include a channel region, and a drain region and source region at both ends of the channel region, a ferroelectric layer formed over the channel region of the metal layer, and a program and read gate formed over the ferroelectric layer. A write operation of data corresponding to a resistance state of the channel region is performed by changing polarity of the ferroelectric layer in response to a voltage applied to the program and read gate, the drain and source regions, and the control gate. A read operation of data is performed by sensing a current value changing with a polarity state of the ferroelectric layer on the condition that the read voltage is input to the control gate and a sensing bias voltage is input to one of the drain region and the source region. | 2012-02-09 |
| 20120033479 | MODIFICATION OF LOGIC BY MORPHOLOGICAL MANIPULATION OF A SEMICONDUCTOR RESISTIVE ELEMENT - An electronic device includes a substrate with a resistive element located thereover. The resistive element includes a semiconductor region. A read module is configured to determine a resistance of the resistive element. A programming module is configured to cause a current to flow through the semiconductor region. The current is sufficient to induce a change of morphology of at least a portion of the semiconductor region. | 2012-02-09 |
| 20120033480 | SEMICONDUCTOR MEMORY DEVICE - A semiconductor memory device according to the embodiment comprises a memory cell array including first line, second line crossing the first line, and memory cell containing variable resistance element provided on the intersection of the first and second lines; a data write unit operative to cause the variable resistance element to make a transition from a first resistance to a second resistance different from the first resistance; and a resistance state detection unit including an abnormality detection circuit operative to detect a transition of the resistance of the variable resistance element to a third resistance when the data write unit causes the variable resistance element to make the transition from the first resistance to the second resistance (where the third resistancethe first resistance>the second resistance). | 2012-02-09 |
| 20120033481 | Memory Element With A Reactive Metal Layer - A memory cell including conductive oxide electrodes is disclosed. The memory cell includes a memory element operative to store data as a plurality of resistive states. The memory element includes a layer of a conductive metal oxide (CMO) (e.g., a perovskite) in contact with an electrode that may comprise one or more layers of material. At least one of those layers of material can be a conductive oxide (e.g., a perovskite such as LaSrCoO | 2012-02-09 |
| 20120033482 | Bit Set Modes for a Resistive Sense Memory Cell Array - Various embodiments of the present invention are generally directed to a method and apparatus for providing different bit set modes for a resistive sense memory (RSM) array, such as a spin-torque transfer random access memory (STRAM) or resistive random access memory (RRAM) array. In accordance with some embodiments, a group of RSM cells in a non-volatile semiconductor memory array is identified for application of a bit set operation. A bit set value is selected from a plurality of bit set values each separately writable to the RSM cells to place said cells in a selected resistive state. The selected bit set value is thereafter written to at least a portion of the RSM cells in the identified group. | 2012-02-09 |
| 20120033483 | SEMICONDUCTOR DEVICE AND DRIVING METHOD OF SEMICONDUCTOR DEVICE - A memory cell includes a capacitor, a first transistor, and a second transistor whose off-state current is smaller than that of the first transistor. The first transistor has higher switching speed than the second transistor. The first transistor, the second transistor, and the capacitor are electrically connected in series. Accumulation of charge in the capacitor and release of charge from the capacitor are performed through the first transistor and the second transistor. In this manner, the power consumption of the semiconductor device can be reduced and data can be written and read at higher speed. | 2012-02-09 |
| 20120033484 | SEMICONDUCTOR DEVICE AND DRIVING METHOD THEREOF - The semiconductor device is formed using a material which allows a sufficient reduction in off-state current of a transistor; for example, an oxide semiconductor material, which is a wide gap semiconductor, is used. When a semiconductor material which allows a sufficient reduction in off-state current of a transistor is used, the semiconductor device can hold data for a long period. In addition, the timing of potential change in a signal line is delayed relative to the timing of potential change in a write word line. This makes it possible to prevent a data writing error. | 2012-02-09 |
| 20120033485 | SEMICONDUCTOR DEVICE - In a semiconductor device which includes a bit line, m (m is a natural number of 3 or more) word lines, a source line, m signal lines, first to m-th memory cells, and a driver circuit, the memory cell includes a first transistor and a second transistor for storing electrical charge accumulated in a capacitor, and the second transistor includes a channel formed in an oxide semiconductor layer. In the semiconductor device, the driver circuit generates a signal to be output to a (j−1)th (j is a natural number of 3 or more) signal line with the use of a signal to be output to a j-th signal line. | 2012-02-09 |
| 20120033486 | SEMICONDUCTOR DEVICE AND METHOD FOR DRIVING SEMICONDUCTOR DEVICE - It is an object to provide a semiconductor device with a novel structure in which stored data can be held even when power is not supplied, and does not have a limitation on the number of writing operations. A semiconductor device includes a plurality of memory cells each including a transistor including a first semiconductor material, a transistor including a second semiconductor material that is different from the first semiconductor material, and a capacitor, and a potential switching circuit having a function of supplying a power supply potential to a source line in a writing period. Thus, power consumption of the semiconductor device can be sufficiently suppressed. | 2012-02-09 |
| 20120033487 | SEMICONDUCTOR DEVICE AND DRIVING METHOD THEREOF - A semiconductor device including a nonvolatile memory cell in which a writing transistor which includes an oxide semiconductor, a reading transistor which includes a semiconductor material different from that of the writing transistor, and a capacitor are included is provided. Data is written to the memory cell by turning on the writing transistor and applying a potential to a node where a source electrode (or a drain electrode) of the writing transistor, one electrode of the capacitor, and a gate electrode of the reading transistor are electrically connected, and then turning off the writing transistor, so that the predetermined amount of charge is held in the node. Further, when a p-channel transistor is used as the reading transistor, a reading potential is a positive potential. | 2012-02-09 |
| 20120033488 | SEMICONDUCTOR DEVICE AND DRIVING METHOD THEREOF - A semiconductor device including a memory cell formed using a wide bandgap semiconductor, for example, an oxide semiconductor is provided. The semiconductor device includes a potential change circuit having a function of outputting a potential lower than a reference potential for reading data from the memory cell. With the use of the wide bandgap semiconductor, an off-state current of a transistor included in the memory cell can be sufficiently reduced, and the semiconductor device which can hold data for a long period can be provided. | 2012-02-09 |
| 20120033489 | MEMORY DEVICE, PRECHARGE CONTROLLING METHOD THEREOF, AND DEVICES HAVING THE SAME - A pre-charge controlling method and device are provided. The pre-charge controlling method includes pre-charging a first global bit line with a first pre-charge voltage by using at least a first pre-charge circuit located between a plurality of sub arrays included in a memory cell array and pre-charging the first global bit line with a second pre-charge voltage by using a second pre-charge circuit located outside the memory cell array. | 2012-02-09 |
| 20120033490 | Generating a Non-Reversible State at a Bitcell Having a First Magnetic Tunnel Junction and a Second Magnetic Tunnel Junction - A method of generating a non-reversible state at a bitcell having a first magnetic tunnel junction (MTJ) and a second MTJ includes applying a program voltage to the first MTJ of the bitcell without applying the program voltage to the second MTJ of the bitcell. A memory device includes a bitcell having a first MTJ and a second MTJ and programming circuitry configured to generate a non-reversible state at the bitcell by applying a program signal to a selected one of the first MTJ and the second MTJ of the bitcell. | 2012-02-09 |
| 20120033491 | PROGRAMMING OF MEMORY CELLS IN A NONVOLATILE MEMORY USING AN ACTIVE TRANSITION CONTROL - An electrically programmable non-volatile memory array and associated circuitry, including programming circuitry that adaptively senses completed programming of a selected memory cell. A programming bit line driver is connected to the bit line, and a first transistor has its source/drain path connected in series with the memory cell, and its gate connected to the output of the current comparator. As the MOS transistor in the selected cell becomes programmed, its drain current drawn from the bit line driver decays, and a remainder current into the current comparator increases. Upon the remainder current exceeding the reference current, the comparator turns off the first transistor; a second transistor connected between the source and drain of the cell transistor is turned on. In another approach, a summed current controls the gates of the first and second transistors. Programming terminates, and over-programming is avoided. | 2012-02-09 |
| 20120033492 | DATA WRITING METHOD AND DATA STORAGE DEVICE - The invention provides a data writing method. In one embodiment, a data storage device comprises a flash memory. First, the flash memory is directed to read a plurality of programming voltage values for data programming. The programming voltage values are then adjusted to obtain a plurality of adjusted programming voltage values according to difference bits between a plurality of stored data patterns corresponding to the programming voltage values. The adjusted programming voltage values are then sent to the flash memory. The flash memory is then directed to perform data programming according to the adjusted programming voltage values, wherein the data programmed according to the adjusted programming voltage values has a lower error bit rate than that of the data programmed according to the programming voltage values. | 2012-02-09 |
| 20120033493 | ERASE COMPLETION RECOGNITION - Embodiments include but are not limited to apparatuses and systems including a main memory array, at least one erase status memory cell associated with the main memory array and configured to store a value indicative of an erase completion status of the main memory array, and a control module operatively coupled to the at least one erase status memory cell, the control module configured to perform operations on the main memory array based at least in part on the value stored in the at least one erase status memory cell. Other embodiments may be described and claimed. | 2012-02-09 |
| 20120033494 | DETECTING THE COMPLETION OF PROGRAMMING FOR NON-VOLATILE STORAGE - A set of non-volatile storage elements are subjected to a programming process in order to store data. During the programming process, one or more verification operations are performed to determine whether the non-volatile storage elements have reached their target condition to store the appropriate data. Programming can be stopped when all non-volatile storage elements have reached their target level or when the number of non-volatile storage elements that have not reached their target level is less than a number or memory cells that can be corrected using an error correction process during a read operation (or other operation). The number of non-volatile storage elements that have not reached their target level can be estimated by counting the number of non-volatile storage elements that have not reached a condition that is different (e.g., lower) than the target level. | 2012-02-09 |
| 20120033495 | SEMICONDUCTOR DEVICE - A semiconductor device is provided which comprises a nonvolatile memory capable of storing complementary data and performing a more accurate blank check than ever before. | 2012-02-09 |
| 20120033496 | SEMICONDUCTOR STORAGE DEVICE WITH VOLATILE AND NONVOLATILE MEMORIES - A semiconductor storage device includes a first memory area configured in a volatile semiconductor memory, second and third memory areas configured in a nonvolatile semiconductor memory, and a controller which executes following processing. The controller executes a first processing for storing a plurality of data by the first unit in the first memory area, a second processing for storing data outputted from the first memory area by a first management unit in the second memory area, and a third processing for storing data outputted from the first memory area by a second management unit in the third memory area. | 2012-02-09 |
| 20120033497 | NON-VOLATILE MEMORY DEVICE HAVING CONFIGURABLE PAGE SIZE - A flash memory device having at least one bank, where the each bank has an independently configurable page size. Each bank includes at least two memory planes having corresponding page buffers, where any number and combination of the memory planes are selectively accessed at the same time in response to configuration data and address data. The configuration data can be loaded into the memory device upon power up for a static page configuration of the bank, or the configuration data can be received with each command to allow for dynamic page configuration of the bank. By selectively adjusting a page size the memory bank, the block size is correspondingly adjusted. | 2012-02-09 |
| 20120033498 | SEMICONDUCTOR MEMORY DEVICE AND METHOD OF READING THE SAME - A semiconductor memory device comprises planes each configured to comprise flag cells storing data about program methods of memory cells of the plane, page buffer units configured to sense the data of the flag cells, a flag cell data detection circuit configured to make a determination of program methods of the planes on the basis of a result, obtained by comparing the sensed data of the flag cells of the planes, and the sensed data of the flag cells, and a microcontroller configured to control the page buffer units, wherein the page buffer units read least significant bit (LSB) data of the planes or both the least significant bit (LSB) data and most significant bit (MSB) data on the basis of the determination of the flag cell data detection circuit. | 2012-02-09 |
| 20120033499 | FLASH MEMORY DEVICE AND READING METHOD THEREOF - A flash memory device and reading method of the flash memory device. The reading method includes determining a read voltage set of memory cells corresponding to a first word line from at least one of flag cell data of the first word line and flag cell data of a second word line adjacent to the first word line, and reading the memory cells corresponding to the first word line according to the determined read voltage set. | 2012-02-09 |
| 20120033500 | NATURAL THRESHOLD VOLTAGE DISTRIBUTION COMPACTION IN NON-VOLATILE MEMORY - In a non-volatile memory system, a programming speed-based slow down measure such as a raised bit line is applied to the faster-programming storage elements. A multi-phase programming operation which uses a back-and-forth word line order is performed in which programming speed data is stored in latches in one programming phase and read from the latches for use in a subsequent programming phase of a given word line. The faster and slower-programming storage elements can be distinguished by detecting when a number of storage elements reach a specified verify level, counting an additional number of program pulses which is set based on a natural threshold voltage distribution of the storage elements, and subsequently performing a read operation that separates the faster and slower programming storage elements. A drain-side select gate voltage can be adjusted in different programming phases to accommodate different bit line bias levels. | 2012-02-09 |
| 20120033501 | NONVOLATILE MEMORY DEVICE WITH 3D MEMORY CELL ARRAY - Disclosed is a nonvolatile memory device which includes a 3D memory cell array having words lines that extend from a lowest memory cell array layer closest to a substrate to a highest memory cell array layer farthest from the substrate, a voltage generator circuit generating first and second voltage signals, and a row selecting circuit that simultaneously applies the first voltage signal to a selected word line and the second voltage signal to an unselected word line. The selected word line and the unselected word line have different resistances, yet the first voltage signal is applied to the selected word line and the second voltage signal is applied to the unselected word line with a same rising slope over a defined period of time. | 2012-02-09 |
| 20120033502 | METHOD OF READING DATA IN NON-VOLATILE MEMORY DEVICE, AND DEVICE THEREOF - A method of reading data in a non-volatile memory device. The method includes reading a plurality of memory cells of a first page in a memory cell array using a first read level, reading a plurality of memory cells of a second page adjacent to the memory cells of the first page using a second read level, determining whether a state of each memory cell of the first page has been changed based on the first read level to verify a threshold voltage of each memory cell of the second page based on the second read level, and revising the state of each memory cell of the second page according to a result of the determination. | 2012-02-09 |
| 20120033503 | CHARGE TRAP FLASH MEMORY DEVICE AND AN ERASING METHOD THEREOF - An erase method of a charge trap flash memory device, the method including receiving a temperature detection result, and performing an erase operation based on the temperature detection result, wherein the erase operation includes an erase execution interval, an erase verify interval and a delay time between the erase execution interval and the erase verify interval, wherein the erase operation changes a level of a word line voltage applied to word lines during the erase execution interval, a length of the delay time, or a level of the word line voltage applied to the word lines during the delay time. | 2012-02-09 |
| 20120033504 | ERASE VOLTAGE REDUCTION IN A NON-VOLATILE MEMORY DEVICE - In erasing a memory block of memory cells, a semiconductor tub that contains a memory block to be erased can be biased with a high, positive voltage. The control gates of the memory cells that make up the memory block can be biased with a negative voltage. An erase verification can then be performed to determine if the memory block has been successfully erased. If the memory block has not been erased, the erase operation of biasing the tub with the positive voltage and the control gates with the negative voltage can be repeated until the erase verification is successful. | 2012-02-09 |
| 20120033505 | SEMICONDUCTOR DEVICE AND METHOD FOR DRIVING SEMICONDUCTOR DEVICE - A semiconductor device with a novel structure is provided, in which the operation voltage is reduced or the storage capacity is increased by reducing variation in the threshold voltages of memory cells after writing. The semiconductor device includes a plurality of memory cells each including a transistor including an oxide semiconductor and a transistor including a material other than an oxide semiconductor, a driver circuit that drives the plurality of memory cells, and a potential generating circuit that generates a plurality of potentials supplied to the driver circuit. The driver circuit includes a data buffer, a writing circuit that writes one potential of the plurality of potentials into each of the plurality of memory cells as data, a reading circuit that reads the data written into the memory cells, and a verifying circuit that verifies whether the read data agrees with data held in the data buffer or not. | 2012-02-09 |
| 20120033506 | SEMICONDUCTOR DEVICE - A semiconductor device includes an internal circuit and an internal voltage generation circuit which generates an internal voltage stabilized with respect to a variation of the power supply voltage supplied from the outside and supplies the internal voltage to the internal circuit. The internal voltage generation circuit performs control so that when the power supply voltage rises to exceed a predetermined value, an operation of stabilizing the internal voltage is stopped to cause the internal voltage to increase with the rise of the power supply voltage. | 2012-02-09 |
| 20120033507 | ON DIE THERMAL SENSOR OF SEMICONDUCTOR MEMORY DEVICE - An on die thermal sensor (ODTS) of a semiconductor memory device includes a high voltage generating unit for generating a high voltage having a voltage level higher than that of a power supply voltage of the semiconductor memory device; and a thermal information output unit for sensing and outputting a temperature as a thermal information code, wherein the thermal information output unit uses the high voltage as its driving voltage. | 2012-02-09 |
| 20120033508 | LEVEL SHIFTER FOR USE WITH MEMORY ARRAYS - In a first aspect, a level shifter circuit for use in a memory array is provided that includes (1) a first voltage domain powered by a first voltage; (2) a second voltage domain powered by a second voltage; (3) level shifter circuitry that converts an input signal from the first voltage domain to the second voltage domain; and (4) isolation circuitry that selectively isolates the first voltage domain from the second voltage domain so as to selectively prevent current flow between the first voltage domain and the second voltage domain. Numerous other aspects are provided. | 2012-02-09 |
| 20120033509 | Memory data reading and writing technique - A novel circuit for reading data in solid state memory cells is presented. It can be used for any type of memory cell array but more specifically it is particularly suited for volatile memories like SRAM and DRAM. It is based on sensing the current in the ground line of the memory cell when the data is being read. This eliminates the need for detecting large voltage swings on the bit line resulting in large delays or complex sense amplification circuits. It offers the advantages of being very small in silicon area, very fast and very efficient. The read and write static noise margins are increased with respect to conventional techniques. The current can be amplified and converted to a voltage signal by a transimpedance amplifier ac coupled to a sense resistor on the ground line. The signal can be successively latched. The same technique can be used to detect when the writing of a cell has been successfully carried out. | 2012-02-09 |
| 20120033510 | SEMICONDUCTOR DEVICE - An object is to provide a semiconductor device with a novel structure, which can hold stored data even when power is not supplied and which has an unlimited number of write cycles. The semiconductor device is formed using a memory cell including a wide band gap semiconductor such as an oxide semiconductor. The semiconductor device includes a potential change circuit having a function of outputting a potential lower than a reference potential for reading data from the memory cell. When the wide band gap semiconductor which allows a sufficient reduction in of state current of a transistor included in the memory cell is used, a semiconductor device which can hold data for a long period can be provided. | 2012-02-09 |
| 20120033511 | CONTROL CIRCUIT OF READ OPERATION FOR SEMICONDUCTOR MEMORY APPARATUS - A control circuit for a read operation of a SERDES (SERializer and DESeriallizer) type semiconductor memory apparatus is disclosed that includes a first line driver configured to output a portion of a output signals from sense amplifier according to a first delay signal; a second line driver configured to output a rest of the output signals from the sense amplifier according to a second delay signal; and a first delay unit configured to output a second delay signal synchronized with a clock to the second line driver. | 2012-02-09 |
| 20120033512 | SEMICONDUCTOR MEMORY DEVICE - According to one embodiment, a semiconductor memory device includes first cells, first lines, second lines, a first cell array, and a signal driver. The first cell has in either a first state or a second state. Retention time in the second state is longer than in the first state. The first cell array has the first cells formed in a matrix the individuals. The first cells are electrically connected by the first, second lines. The signal driver drives the first cells. The signal driver causes the first cells to transition to either the first state or the second state by controlling any one of a voltage, a current, and a charge amount applied to the first cells, or a combination of these, and waveforms of the voltage, current, and charge amount and/or the length of transfer time of at least one of the voltage, current, and charge amount. | 2012-02-09 |
| 20120033513 | DISTRIBUTED WRITE DATA DRIVERS FOR BURST ACCESS MEMORIES - An address strobe latches a first address. A burst cycle increments the address internally with additional address strobes. A new memory address is only required at the beginning of each burst access. Read commands are issued once per burst access eliminating toggling Read control line at cycle frequency. Control line transition terminates access and initializes another burst access. | 2012-02-09 |
| 20120033514 | STROBE-OFFSET CONTROL CIRCUIT - A method of operation in a memory controller is disclosed. The method includes receiving a strobe signal having a first phase relationship with respect to first data propagating on a first data line, and a second phase relationship with respect to second data propagating on a second data line. A first sample signal is generated based on the first phase relationship and a second sample signal is generated based on the second phase relationship. The first data signal is received using a first receiver clocked by the first sample signal. The second data signal is received using a second receiver clocked by the second sample signal. | 2012-02-09 |
| 20120033515 | SEMICONDUCTOR MEMORY DEVICE - A semiconductor memory device includes a plurality of memory cell mats each comprising a plurality of normal memory cell arrays; and a redundancy memory cell array configured to replace a defective memory cell with a plurality of redundancy memory cells corresponding to a redundancy word line when the redundancy word line corresponding to one or more redundancy memory cell arrays is activated in response to an address corresponding to the defective memory cell among the plurality of normal memory cell arrays. | 2012-02-09 |
| 20120033516 | WORD LINE DRIVING CIRCUIT, SEMICONDUCTOR MEMORY DEVICE INCLUDING THE SAME, AND METHOD FOR TESTING THE SEMICONDUCTOR MEMORY DEVICE - A semiconductor memory device in accordance with the present invention is able to facilitate detecting whether a word line fails or not by floating the word line. The semiconductor memory device includes a word line driver, and a floating controller. The word line driver is configured to control a word line to be enabled/disabled. The floating controller is configured to control the word line driver to float the word line in response to a word line floating signal. | 2012-02-09 |
| 20120033517 | ADAPTIVE WRITE BIT LINE AND WORD LINE ADJUSTING MECHANISM FOR MEMORY - A memory includes a capacitor coupled to a write bit line or a word line. An initializer is configured to initialize a voltage level at a first node between the capacitor and the write bit line or a word line. An initial level adjuster is configured to adjust a voltage level of a second node at one terminal of the capacitor. A pulse generator configured to supply a pulse to the initial level adjuster to control the initial level adjuster. A boost signal is configured to be supplied to a third node on the other terminal of the capacitor opposite the first node to boost a voltage level of the write bit line lower than ground or to boost a voltage level of the word line higher than a power supply voltage. | 2012-02-09 |
| 20120033518 | CURRENT SINK SYSTEM FOR SOURCE-SIDE SENSING - Source-side sensing techniques described herein determine the data value stored in a memory cell based on the difference in current between the read current from the source terminal of the memory cell and a sink current drawn from the read current. The sink current is drawn in response to the magnitude of a reference current provided by a reference current source such as a reference cell. | 2012-02-09 |
| 20120033519 | TEMPERATURE ALERT AND LOW RATE REFRESH FOR A NON-VOLATILE MEMORY - A method and apparatus are described for measuring a temperature within a non-volatile memory, storing, in a register within the non-volatile memory, a temperature alert comprising one or more bits indicating the non-volatile memory has exceeded a threshold temperature for a period of time, determining, by a host, that the temperature alert is active, and in response to the determination that the temperature alert is active, refreshing at least a portion of the non-volatile memory. | 2012-02-09 |
| 20120033520 | MEMORY WITH LOW VOLTAGE MODE OPERATION - A memory comprising memory cells wherein the memory is configured to operate in a normal voltage mode and a low voltage mode. The method includes during the normal voltage mode, operating the memory cells at a first voltage across each of the memory cells. The method further includes upon transitioning from the normal voltage mode to the low voltage mode, operating the memory cells at a second voltage across each of the memory cells, wherein the second voltage is lower than the first voltage. The method further includes performing an access on a subset of the memory cells while maintaining the second voltage across the memory cells. | 2012-02-09 |
| 20120033521 | Semiconductor apparatus and its control method - Semiconductor apparatus includes first power supply line and second power supply line, first sub power supply line, first switch circuit, first logic circuit and first control circuit. First switch circuit is disposed between first power supply line and first sub power supply line, and controlled based on first signal. First logic circuit is disposed between first sub power supply line and second power supply line and comprises first input node and second input node receiving second signal and third signal respectively, and output node. First logic circuit outputs an active voltage associated with a logical level of second signal to output node in active state, and outputs a standby voltage associated with a voltage of second power supply line to output node regardless of the logical level of second signal in non-active state. First control circuit generates third signal based on first signal and fourth signal independent of first signal, and letting first logic circuit transit from non-active state to active state by providing third signal to second input node of first logic circuit. | 2012-02-09 |
| 20120033522 | VARIATION-TOLERANT WORD-LINE UNDER-DRIVE SCHEME FOR RANDOM ACCESS MEMORY - A Random Access Memory (RAM) is provided. The RAM includes a plurality of word-line drivers, at least a first tracking transistor and a second tracking transistor. Each word-line driver has an input node receiving a decoding signal, a power node receiving an operation voltage and a driving node driving a word-line. In an embodiment, the first tracking transistor has two channel terminal nodes respectively coupled to the driving node of one of the word-line driver and a channel terminal node of the second tracking transistor; wherein the first tracking transistor has electronic characteristics tracking those of a driving transistor of word-line driver, and the second tracking transistor has electronic characteristics tracking those of pass-gate transistor(s) in each cell of the RAM. | 2012-02-09 |
| 20120033523 | INPUT CIRCUIT OF SEMICONDUCTOR MEMORY APPARATUS AND CONTROLLING METHOD THEREOF - Disclosed is an input circuit of a semiconductor memory apparatus. The input circuit includes a first buffer and a second buffer. The first buffer has an input terminal connected with a first input pin for receiving a control signal used in a multi-control mode for controlling an entire memory area by dividing the entire memory area, and an output terminal having a first level according to a control mode signal. The second buffer has an input terminal connected with a second input pin for receiving one of plural signals used in a single control mode for controlling the entire memory area without dividing the entire memory area, and an output terminal having a second level according to the control mode signal. | 2012-02-09 |
| 20120033524 | COAXIAL COMPACT STATIC MIXER AND USE THEREOF - Scalable compact static mixer comprising a rotationally symmetrical cascaded mixing structure. | 2012-02-09 |
| 20120033525 | METHOD AND APPARATUS FOR MARINE WIDE AZIMUTH TOWED STREAM SEISMIC ACQUISITION - This is a method of acquiring marine wide azimuth towed streamer seismic data. Preferably, a recording boat which tows a plurality of seismic streamers and at least one source may be accompanied by a plurality of source boats that each tow at least one source. The source boats may preferably activate their respective sources such that the subsurface reflections generated by each source interfere. The time separation between successive shots may preferably be a random variable related to the lowest frequency of interest in the data. Additionally, the source boats may preferably be alternatively fired from the head and tail of the recording streamers. | 2012-02-09 |
| 20120033526 | Wavefield deghosting of seismic data recorded using multiple seismic sources at different water depths - Seismic data are acquired by actuating a first source at a first time and one or more additional seismic sources each with their own characteristic times with respect to a time of signal recording, the sources substantially collocated and at different depths. A first wavefield is determined that would occur if the first source were actuated at a selected time with respect to an initiation time of the recordings and being time adjusted for the water depth. One or more additional wavefields are determined that would occur if the one or more additional sources were each actuated at said selected time with respect to said initiation time, and being time adjusted for water depths of the one or more additional sources. The first wavefield and the one or more additional wavefields are combined to determine a deghosted source wavefield corresponding to actuation of a single seismic energy source. | 2012-02-09 |
| 20120033527 | FAST 3-D SURFACE MULTIPLE PREDICTION - A method and apparatus for predicting a plurality of surface multiples for a plurality of traces in a record of seismic data. In one embodiment, the method includes providing a plurality of target traces at a nominal offset and a nominal azimuth; selecting a plurality of pairs of input traces, wherein the midpoints of the input traces in each pair are separated by half the nominal offset and the azimuth of a line connecting the midpoints of the input traces in each pair is equal to the nominal azimuth; convolving the selected pairs of input traces to generate a plurality of convolutions; and applying a three dimensional operator to the convolutions. | 2012-02-09 |
| 20120033528 | Pipelined Pulse-Echo Scheme for an Acoustic Image Tool for Use Downhole - The present disclosure is related to apparatuses and methods for estimating borehole parameters using a plurality of reflections caused by a plurality of acoustic pulses. The reflections may overlap each other and/or the acoustic pulses. The methods may include estimating an envelope of the received acoustic signal at the at least one element of the array of transducers; and estimating at least one arrival time of at least one of the plurality of overlapping events from the envelope of the received acoustic signals, the arrival times being characteristic of the geometry of the borehole. The method may also include imaging the borehole wall. The apparatus may include an array of transducers on a rotatable transducer assembly with at least one element on the array configured to generate a plurality of acoustic pulses and receive reflections and a processor configured to perform the method. | 2012-02-09 |
| 20120033529 | OPTIMAL SOURCE SIGNATURE DETERMINATION - The invention relates to processing seismic data that includes signals from at least two sources and typically three or four sources where source separation is necessary for geophysical analysis. Specifically, the present invention is an analytical technique that quickly creates a more accurate source signature delivered by analysis of the source generated data contamination present in the separated data. The technique is to invert a segment of the data using a seed source signature and compute an error that reflects the generated data contamination observed in the separated source data. The source signature is iteratively revised as the segment is continually inverted with the goal of finding the optimal source signature that provides the lowest computed error. The source signature that provides the lowest error is, or is very close to, the true source signature and is then used in the separation process for the entire composite data set. This will provide much more information for geophysical interpretation. | 2012-02-09 |
| 20120033530 | SOUND IMAGE LOCALIZATION APPARATUS - According to one embodiment, a sound image localization apparatus includes following units. The first signal generating unit is configured to generate a first acoustic signal. The first speaker is configured to generate a first sound according to the first acoustic signal. The input unit is configured to input a localization magnification n. The first control filter unit is configured to adjust the first acoustic signal with a first control filter G | 2012-02-09 |
| 20120033531 | Electronic Device and Method Providing Improved World Clock Feature - An improved electronic device and method provide an improved clock feature that includes an improved world clock function. | 2012-02-09 |
| 20120033532 | TIME INTERVAL INDICATING DEVICE - A device for indicating the passage of two or more time intervals is provided. In one embodiment, the device includes a base portion with a user interface and a light portion. The light portion includes three lights of different colors that are disposed in a vertical arrangement above the base portion. The user interface includes a display and a keypad for programming the device with one or more time durations, and for associating one or more of the lights with each time interval. A controller is in communication with the user interface and operatively coupled with the lights to illuminate and turn off each light during its associated interval. The device may include an audio section linked to the controller for further indicating the intervals or transitions therebetween by outputting one or more sounds. | 2012-02-09 |
| 20120033533 | ELECTRONIC DEVICE WITH ALARM MODE AND ALARM METHOD THEREOF - An electronic device includes an input unit to generate input signals according to a users input. A storage unit to store audio files, an alarm speaker unit to sound the alarm audio files and execute the alarm commands. In addition, a processing unit to sound the alarm after a system time reaches a preset time period. Moreover, analyses operation type according to the input signals to control the speaker unit to resound the alarm or not sound the alarm after a time period according to the operation type. An alarm method is also provided. | 2012-02-09 |
| 20120033534 | MICROWAVE ASSISTED MAGNETIC HEAD - A microwave assisted magnetic head is formed to include a main pole magnetic layer including a main pole; a shielded magnetic layer including a shielded pole; a recording coil that is formed to generate a writing magnetic field from a tip of the main pole; and a microwave radiation waveguide made of a conductive nonmagnetic material that is disposed in a recording gap, the recording gap being a gap between the main pole and the shielded pole. The main pole magnetic layer and the shielded magnetic layer have an intermediate connection part that connects the layers at a depth-side, and an electrical insulation magnetic film is disposed in the intermediate connection part, and the main pole and the shielded pole are electrically connected with the microwave radiation waveguide that is disposed in the recording gap, which is the gap between the main pole and the shielded pole so that a simple configuration, with a relatively easy and efficient manufacturing process, is realized that overlaps AC magnetic fields in an in-plane direction of a microwave band, which is the same as, or close to, a ferromagnetic resonant frequency of a medium recording layer. | 2012-02-09 |
| 20120033535 | OPTICAL DISC AND OPTICAL DISC DRIVE - The present invention provides a multilayer optical disc and an optical disc drive which can identify recording layers without performing tracking servo control or changing the structure of the disc. In a multilayer optical disc | 2012-02-09 |
| 20120033536 | OPTICAL RECORDING METHOD AND OPTICAL RECORDING DEVICE - In an optical recording method, recording parameters (WU) to be used for recording are obtained using recommended recording parameter values (WR) read from an optical recording medium and previously obtained vector information (PC) and approximation coefficients (Ca, Cb) (S | 2012-02-09 |
| 20120033537 | COPY STATION - In an embodiment, a method for making copies of a master disc is described. The method includes receiving a master disc. The method also includes capturing an image of a label on a first side of the master disc. The method also includes generating a data image of data stored on the master disc. The method also includes making one or more copies of the master disc using one or more blank discs. Making the one or more copies includes recording the data image onto a data side of each of the one or more blank discs and printing the image of the label on an opposing side of each of the one or more blank discs. | 2012-02-09 |
| 20120033538 | STORAGE APPARATUS - A storage apparatus comprising: a casing forming a housing chamber; a disk drive housed in, at a spacing from, the housing chamber, such that unit outer walls of the disk drive are separated by a clearance from inner walls of the casing; and a buffer member interposed in the clearance between the disk drive and the casing, for absorbing an impact stress. The buffer member is formed of a material having flexibility, and is provided with: a support part fitted to a wall surface of one of either the disk drive or the casing; a hemispherically shaped dome part, formed on the support part; and an abutment part, formed along a top portion of the dome part, abutting on a wall surface of the other of either the disk drive or the casing. The dome part and the support part form, together with the wall surface of the one of either the disk drive or the casing, a sealing chamber sealing in air, whereby the dome part is lent elasticity. | 2012-02-09 |
| 20120033539 | METHOD FOR HIGH DENSITY DATA STORAGE AND IMAGING - An approach is presented for designing a polymeric layer for nanometer scale thermo-mechanical storage devices. Cross-linked polyimide oligomers are used as the recording layers in atomic force data storage device, giving significantly improved performance when compared to previously reported cross-linked and linear polymers. The cross-linking of the polyimide oligomers may be tuned to match thermal and force parameters required in read-write-erase cycles. Additionally, the cross-linked polyimide oligomers are suitable for use in nano-scale imaging. | 2012-02-09 |
| 20120033540 | METHOD FOR GENERATING REFERENCE SIGNAL SEQUENCE IN MULTI-ANTENNA WIRELESS COMMUNICATION SYSTEM AND APPARATUS FOR SAME - The present application discloses a method in which a base station transmits a reference signal sequence in a wireless communication system. In detail, the method comprises the steps of: generating a pseudo-random sequence using a first m-sequence and a second m-sequence; generating the reference signal sequence using the pseudo-random sequence; and transmitting the reference signal to a mobile station via antenna ports different from one another. The second m-sequence has an initial value containing parameters for discriminating reference signal sequences among users. | 2012-02-09 |
| 20120033541 | SYSTEM AND METHOD FOR TRANSPORT CONTROL PROTOCOL IN A MULTI-CHASSIS DOMAIN - Aggregation switches connected to an edge node by a multi-chassis link aggregation group, wherein the aggregation switches are connected by a virtual fiber link that provides a connection for exchange of information between the Aggregation Switches regarding MAC addressing to synchronize MAC address tables. A transport control protocol defines a VLAN and multicast group of ports on the Aggregation Switch to receive management or control packets. | 2012-02-09 |
| 20120033542 | TECHNIQUES FOR DETERMINING LOCAL REPAIR CONNECTIONS - Techniques for configuring a local repair connection for a protected connection including determining a path for the local repair connection. The path traversed by a local repair connection starts at a node in the path associated with the protected connection and ends at a merge point node in the path associated with the protected connection that is downstream from the start node. In one embodiment, the merge point node may even be more than two hops downstream from the start node in the path associated with the protected connection. The local repair path may include zero or more nodes that are not included in the path associated with the protected connection. Techniques are also described for optimizing the path associated with a local repair connection. | 2012-02-09 |
| 20120033543 | Method and System for Implementing Network Element-Level Redundancy - According to a further embodiment, a method may include communicatively coupling a first network element to a second network element via a first path of a point-to-point network. The method may also include communicatively coupling the first network element to a third network element via a second path of the point-to-point network. The method may additionally include communicatively coupling the second network element and the third network element to a multipoint-to-multipoint network. The method may further include configuring the first path and the second path as paths of a linear protected switching connection such that traffic associated with a service and communicated between the first network element and the multipoint-to-multipoint network via one of the first path and the second path may be switched over to the other of the first path and the second path in response to an event. | 2012-02-09 |
| 20120033544 | METHOD AND APPARATUS FOR CORRELATING AND SUPPRESSING PERFORMANCE ALERTS IN INTERNET PROTOCOL NETWORKS - A method and apparatus for correlating and suppressing performance alerts in a packet network are disclosed. In one embodiment, a method for handling alerts in a packet network includes receiving a plurality of alerts relating to one or more faults in the packet network, wherein the plurality of alerts is generated from information contained in a plurality of call detail records, correlating the plurality of alerts into one or more sets of performance alerts, each of the one or more sets of performance alerts being associated with a common one of the one or more faults, and suppressing at least one further alert relating to at least one of the one or more sets. | 2012-02-09 |
| 20120033545 | Methods and Devices For Providing Robust Nomadic Wireless Mesh Networks Using Directional Antennas - The number of directional antennas and associated radios needed to ensure a nomadic wireless mesh network (NWMN) remains operational in the event of node or link failures, while minimizing delay and other unwanted effects, may be determined using novel methods and devices. Such a determination may reduce the number of antennas and radios a service or network provider normally uses, thus reducing its costs. | 2012-02-09 |
| 20120033546 | Method and System for Implementing Network Element-Level Redundancy - According to another embodiment, a method may include communicatively coupling a first network element to a second network element via a first link of a multi-chassis link aggregation group. The method may also include communicatively coupling the first network element to a third network element via a second link of the multi-chassis link aggregation group. The method may additionally include communicatively coupling the second network element to a fourth network element via a first path of a point-to-point network. The method may further include communicatively coupling the third network element to the fourth network element via a second path of the point-to-point network. The method may also include configuring the first path and the second path as paths of a linear protected switching connection such that traffic associated with a service and communicated between the first network element and the fourth network element via the first link and the first path may be switched over to the second link and the second path in response to an event. | 2012-02-09 |
| 20120033547 | Method and System for Implementing Network Element-Level Redundancy - According to an additional embodiment, a method may include communicatively coupling a first network element to a second network element via a first path of a first point-to-point network. The method may also include communicatively coupling the first network element to a third network element via a second path of the first-point-to-point network. The method may additionally include communicatively coupling the second network element to a fourth network element via a first path of a second point-to-point network. The method may further include communicatively coupling the third network element to the fourth network element via a second path of the second point-to-point network. The method may also include configuring the first path and the second path of the first point-to-point network as paths of a first linear protected switching connection and the first path and the second path of the second point-to-point network as paths of a second linear protected switching connection such that traffic associated with a service and communicated between the first network element and the fourth network element via the first path of the first point-to-point network and the first path of the second point-to-point network may be switched over to the second path of the first point-to-point network and the second path of the second point-to-point network in response to an event. | 2012-02-09 |
| 20120033548 | CLIENT QoS BASED CONNECTION SESSION JOGGING - A communication device, comprising communication interface circuitry, processing circuitry coupled to the communication interface circuitry, and a user interface coupled to the processing circuitry, interacts with a remote device in a communication infrastructure that supports multiple possible communication pathways such as first and second communication pathways between the communication device and the remote device. A data exchange relating to at least a voice delivery service is initiated by the processing circuitry over the first communication pathway. A jog input indication is generated during the data exchange via the user interface in response to a user input, and delivered to the processing circuitry. The jog input indication is indicative of dissatisfaction of the user with ongoing performance of the first communication pathway in the data exchange. In response to the jog input indication received, the processing circuitry switches the data exchange from the first communication pathway to the second communication pathway. | 2012-02-09 |
| 20120033549 | Method and System for Implementing Network Element-Level Redundancy - According to one embodiment, a method may include communicatively coupling a first network element to a second network element via a first path of a point-to-point network. The method may also include communicatively coupling the first network element to a third network element via a second path of the point-to-point network. The method may further include configuring the first path and the second path as paths of a linear protected switching connection such that traffic associated with a service and communicated via one of the first path and the second path may be switched over to the other of the first path and the second path in response to an event. | 2012-02-09 |
| 20120033550 | PACKET RELAY DEVICE AND CONGESTION CONTROL METHOD - A packet relay device is equipped with a buffer memory including a plurality of queues for temporarily storing packets, and a storage unit for storing the first queue lengths indicating the respective queue length of each of the queues and a second queue length indicating a value according to a total of the plurality of first queue lengths. When the packet relay device receives packets, it discerns the queue to which the received packet belongs from among the plurality of queues, and temporarily stores the packet in relation to the discerned queue within the buffer memory. Then, the first queue length and the second queue length are updated, and a determination is made of whether or not to send a congestion notification to the packet sending source according to the first queue length corresponding to the discerned queue, and to the second queue length. | 2012-02-09 |
| 20120033551 | Handling Signaling Congestion And Related Communication Device - A method of handling signaling congestion for a machine type communication (MTC) device and/or a MTC server in a wireless communication system is disclosed. The method comprises receiving system information from a network; and stopping a triggering operation in a communication window according to the system information, wherein the system information indicates occurrence of a signaling congestion situation in the network. | 2012-02-09 |
| 20120033552 | Utilizing Betweenness to Determine Forwarding State in a Routed Network - A set of critical nodes or links is identified on the network through which most of the shortest paths on the network occur. Each node compares their distance to end points on the network with a distance between the end points and each of the distinct critical nodes. Where the distance between the end points and the critical nodes is shorter than the distance between the end points and the node, the node is not on the shortest path and does not install forwarding state. Where the distance between the end points and the critical node is larger than or equal to the distance between the end points and the node, the node may be on the shortest path between the pair of end nodes and installs forwarding state. Installation of forwarding state may cause packet duplication, but determining forwarding state is dramatically simplified. | 2012-02-09 |
| 20120033553 | NETWORK FLOW TERMINATION - A network has a plurality of edge nodes ( | 2012-02-09 |
| 20120033554 | METHOD AND APPARATUS FOR RADIO LINK CONTROL DURING NETWORK CONGESTION IN A MOBILE WIRELESS DEVICE - A method and apparatus for radio link control during network congestion in a mobile wireless communication device connected to a radio network subsystem in a wireless cellular network. The mobile wireless communication device detects a pending uplink control message. The mobile wireless communication device determines that an uplink channel on which the pending uplink control message is to be sent has insufficient bandwidth for uplink transmission. After waiting a congestion delay time interval, the mobile wireless communication device sends the pending uplink control message on an uplink signaling channel instead of on the uplink channel. In some embodiments, the uplink channel is associated with a radio access bearer and the uplink signaling channel is associated with a signaling radio bearer. | 2012-02-09 |
| 20120033555 | ROUTING METHOD, APPARATUS AND SYSTEM - A routing method and apparatus are provided. The routing method includes the following steps: sending a probe frame that carries an address of a destination node to a neighboring node(s); receiving a response message returned; selecting one neighboring node from the neighboring node(s) that returns the response message as a next-hop node to which data is sent. A neighboring node with a cost parameter which is lower than a cost parameter in a routing table of the destination node is selected as the next-hop node. In the routing method, when a routing node forwards data, the route is found in real time by broadcasting a probe frame, and data may be sent as long as any one of the neighboring nodes that may arrive at the destination node is in an active state, and thus a data transmission delay is shortened. | 2012-02-09 |
