06th week of 2012 patent applcation highlights part 15 |
Patent application number | Title | Published |
20120032254 | ESD PROTECTION DEVICE AND METHOD FOR FABRICATING THE SAME - An electrostatic discharge (ESD) protection device includes a substrate; a source region of a first conductivity type in the substrate; a drain region of the first conductivity type in the substrate; a gate electrode overlying the substrate between the source region and the drain region; and a core pocket doping region of the second conductivity type within the drain region. The core pocket doping region does not overlap with an edge of the drain region. | 2012-02-09 |
20120032255 | INTEGRATED CIRCUIT HAVING COMPENSATION COMPONENT - An integrated circuit and component is disclosed. In one embodiment, the component is a compensation component, configuring the compensation regions in the drift zone in V-shaped fashion in order to achieve a convergence of the space charge zones from the upper to the lower end of the compensation regions is disclosed. | 2012-02-09 |
20120032256 | SEMICONDUCTOR DEVICE AND METHOD OF FORMING THE SAME - A semiconductor device includes a first island and a first electrode. The first island includes a first semiconductor region, a first insulation region, and a first insulating film. The first semiconductor region has first and second side surfaces adjacent to the first insulation region and the first insulating film, respectively. The first electrode is adjacent to the first insulation region and the first insulating film. The first insulating film is between the first electrode and the first semiconductor region. | 2012-02-09 |
20120032257 | Dual Work Function Recessed Access Device and Methods of Forming - A recessed access device having a gate electrode formed of two or more gate materials having different work functions may reduce the gate-induced drain leakage current losses from the recessed access device. The gate electrode may include a first gate material having a high work function disposed in a bottom portion of the recessed access device and a second gate material having a lower work function disposed over the first gate material and in an upper portion of the recessed access device. | 2012-02-09 |
20120032258 | Semiconductor Device Structures and Related Processes - Improved highly reliable power RFP structures and fabrication and operation processes. The structure includes plurality of localized dopant concentrated zones beneath the trenches of RFPs, either floating or extending and merging with the body layer of the MOSFET or connecting with the source layer through a region of vertical doped region. This local dopant zone decreases the minority carrier injection efficiency of the body diode of the device and alters the electric field distribution during the body diode reverse recovery. | 2012-02-09 |
20120032259 | BOTTOM SOURCE POWER MOSFET WITH SUBSTRATELESS AND MANUFACTURING METHOD THEREOF - A bottom source power metal-oxide-semiconductor field-effect transistor (MOSFET) device includes a gate electrode and a source electrode formed on an initial insulation layer on a first surface of a semiconductor chip and a drain electrode formed on a second surface of the semiconductor chip. The source electrode includes a source metal, a source electrode bump formed on the source metal and a source electrode metal layer on top of the source electrode bump. A first insulation layer covers the gate electrode. A through via aligned to the gate electrode is formed from the second surface of the chip to expose a portion of the gate electrode from the second surface. | 2012-02-09 |
20120032260 | ELECTRONIC DEVICE WITH CONNECTING STRUCTURE - A semiconductor device including a connecting structure includes an edge region, a first trench and a second trench running toward the edge region, a first electrode within the first trench, and a second electrode within the second trench, the first and second electrodes being arranged in a same electrode plane with regard to a main surface of a substrate of the electronic device within the trenches, and the first electrode extending, at an edge region side end of the first trench, farther toward the edge region than the second electrode extends, at an edge region side end of the second trench, toward the edge region. | 2012-02-09 |
20120032261 | TRENCH MOSFET HAVING FLOATING DUMMY CELLS FOR AVALANCHE IMPROVEMENT - A trench MOSFET comprising source regions having a doping profile of a Gaussian-distribution along the top surface of epitaxial layer and floating dummy cells formed between edge trench and active area is disclosed. A SBR of n region existing at cell corners renders the parasitic bipolar transistor difficult to turn on, and the floating dummy cells having no parasitic bipolar transistor act as buffer cells to absorb avalanche energy when gate bias is increasing for turning on channel, therefore, the UIS failure issue is avoided and the avalanche capability of the trench MOSFET is enhanced. | 2012-02-09 |
20120032262 | ENHANCED HVPMOS - A p-channel LDMOS device with a controlled n-type buried layer (NBL) is disclosed. A Shallow Trench Isolation (STI) oxidation is defined, partially or totally covering the drift region length. The NBL layer, which can be defined with the p-well mask, connects to the n-well diffusion, thus providing an evacuation path for electrons generated by impact ionization. High immunity to the Kirk effect is also achieved, resulting in a significantly improved safe-operating-area (SOA). The addition of the NBL deep inside the drift region supports a space-charge depletion region which increases the RESURF effectiveness, thus improving BV. An optimum NBL implanted dose can be set to ensure fully compensated charge balance among n and p doping in the drift region (charge balance conditions). The p-well implanted dose can be further increased to maintain a charge balance, which leads to an Rdson reduction. | 2012-02-09 |
20120032263 | SEMICONDUCTOR DEVICE AND METHOD OF PRODUCING SAME - A semiconductor device has a planarizing layer that is made of an inorganic film, and has a recessed portion formed in a region thereof in which a conductive film is disposed. A first contact hole penetrating through at least an interlayer insulating film is formed on a first wiring layer, while a second contact hole penetrating through at least the interlayer insulating film is formed on the conductive film so as to run through the inside of the recessed portion. | 2012-02-09 |
20120032264 | High density semiconductor latch - A novel semiconductor latch is presented. The semiconductor structure is simple and has a reduced number of semiconductor junctions. It offers the advantage of being very small in area, very fast and very efficient. The current conductivity in the structures of the latch circuit is controlled by the gates voltage by means of depleting and enhancing the areas under the gate oxide. The signal isolation is obtained mainly by the carrier depletion of the channel region. By having a reduced number of semiconductor junctions, the intrinsic current leakage can be very small. This latch is the elementary component for volatile memory and logic elements based on this principle. | 2012-02-09 |
20120032265 | GRADED HIGH GERMANIUM COMPOUND FILMS FOR STRAINED SEMICONDUCTOR DEVICES - Embodiments of an apparatus and methods for providing a graded high germanium compound region are generally described herein. Other embodiments may be described and claimed. | 2012-02-09 |
20120032266 | SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING THE SAME - A semiconductor device is disclosed. The semiconductor device includes a semiconductor substrate; a memory cell region defined in the semiconductor substrate; and a line-and-space pattern formed in the memory cell region in which the lines constitute an active region and the spaces constitute an element isolation region. The first and the second lines of the active region counted from two opposing ends of the memory cell region are each separated into two or more line segments. The segment ends of the line segments of the first and the second lines are linked to form a loop by a linking pattern. | 2012-02-09 |
20120032267 | DEVICE AND METHOD FOR UNIFORM STI RECESS - A semiconductor device and method for forming the semiconductor device include forming structures in a semiconductor substrate. The structures have two or more different spacings between them. A dielectric material is deposited in the spacings. Ion species are implanted to a depth in the dielectric material to change an etch rate of the dielectric material down to the depth. The dielectric material having the ion species is etched selective to the dielectric material below the depth such that a substantially uniform depth in the dielectric material is created across the at least two spacings. | 2012-02-09 |
20120032268 | Layout and Process of Forming Contact Plugs - A device includes a semiconductor substrate including an active region, a gate electrode directly over the active region, and a gate contact plug over and electrically coupled to the gate electrode. The gate contact plug includes at least a portion directly over, and vertically overlapping, the active region. | 2012-02-09 |
20120032269 | SEMICONDUCTOR INTEGRATED CIRCUIT DEVICE AND METHOD FOR FABRICATING THE SAME - Provided are a semiconductor integrated device and a method for fabricating the same. The semiconductor integrated circuit includes a semiconductor substrate including a first dopant, a first conductive layer pattern formed on the semiconductor substrate, an interlayer dielectric layer formed on the first conductive layer pattern, a second conductive layer pattern formed on the interlayer dielectric layer, and a first vacuum ultraviolet (VUV) blocking layer which blocks a VUV ray radiated to the semiconductor substrate. | 2012-02-09 |
20120032270 | DEPLETION MODE FIELD EFFECT TRANSISTOR FOR ESD PROTECTION - A field effect transistor is provided having a reduced drain capacitance per unit gate width. A gate electrode | 2012-02-09 |
20120032271 | High density semiconductor inverter - A novel semiconductor inverter is presented. The semiconductor structure is simple and has a reduced number of semiconductor junctions. It offers the advantage of being very small in area, very fast and very efficient. The current conductivity from either of the two main terminals to the output terminal is controlled by the gate voltage by means of depleting and enhancing the areas underneath the gate oxide. The signal isolation is obtained mainly by the carrier depletion of the channel region. Having a reduced number of semiconductor junctions, the intrinsic current leakage can be very small. This inverter is the elementary component for latches, memory and logic elements based on this technology. | 2012-02-09 |
20120032272 | SEMICONDUCTOR DEVICE, SEMICONDUCTOR INTEGRATED CIRCUIT, SRAM, AND METHOD FOR PRODUCING Dt-MOS TRANSISTOR - A semiconductor device includes a silicon substrate; an element isolation region; an element region including a first well; a contact region; a gate electrode extending from the element region to a sub-region of the element isolation region between the element region and the contact region; a source diffusion region; a drain diffusion region; a first insulating region contacting a lower end of the source diffusion region; a second insulating region contacting a lower end of the drain diffusion region; and a via plug configured to electrically connect the gate electrode with the contact region. The first well is disposed below the gate electrode and is electrically connected with the contact region via the silicon substrate under the sub-region. The lower end of the element isolation region except the sub-region is located lower than the lower end of the first well. | 2012-02-09 |
20120032273 | SEMICONDUCTOR DEVICE - A semiconductor device includes: a micro CMOS region including a micro CMOS and a micro interconnect that is connected to the micro CMOS; and a high breakdown voltage device region including a high breakdown voltage device that has a breakdown voltage higher than that of the micro CMOS, and drain and source interconnects that are connected to the high breakdown voltage device and have a width greater than that of the micro interconnect in a plan view. In the high breakdown voltage device region, an electrically-isolated dummy interconnect is not provided adjacent to at least the drain interconnect and the source interconnect. | 2012-02-09 |
20120032274 | Vertically Stacked FETs With Series Bipolar Junction Transistor - Vertically stacked Field Effect Transistors (FETs) are created on a vertical structure formed on a semiconductor substrate where a first FET and a second FET are controllable independently. A bipolar junction transistor is connected between and in series with the first FET and the second FET, the bipolar junction transistor may be controllable independently of the first and second FET. | 2012-02-09 |
20120032275 | METAL SEMICONDUCTOR ALLOY STRUCTURE FOR LOW CONTACT RESISTANCE - Contact via holes are etched in a dielectric material layer overlying a semiconductor layer to expose the topmost surface of the semiconductor layer. The contact via holes are extended into the semiconductor material layer by continuing to etch the semiconductor layer so that a trench having semiconductor sidewalls is formed in the semiconductor material layer. A metal layer is deposited over the dielectric material layer and the sidewalls and bottom surface of the trench. Upon an anneal at an elevated temperature, a metal semiconductor alloy region is formed, which includes a top metal semiconductor alloy portion that includes a cavity therein and a bottom metal semiconductor alloy portion that underlies the cavity and including a horizontal portion. A metal contact via is formed within the cavity so that the top metal semiconductor alloy portion laterally surrounds a bottom portion of a bottom portion of the metal contact via. | 2012-02-09 |
20120032276 | N-WELL/P-WELL STRAP STRUCTURES - Embodiments of N-well or P-well strap structures are disclosed with lower space requirements achieved by forming the strap on both sides of one or more floating polysilicon gate fingers. | 2012-02-09 |
20120032277 | SEMICONDUCTOR DEVICE - A semiconductor device includes a MOS transistor. The MOS transistor includes a pair of first, second, and third impurity diffusion regions. The second impurity diffusion regions have a first conductive type and are provided in a semiconductor substrate in opposite sides of the first impurity diffusion region. The impurities concentration of the first conductive type in the second impurity diffusion regions is higher than the impurities concentration of the first conductive type in the first impurity diffusion regions. The third impurity diffusion regions have a second conductive type and are provided in the semiconductor substrate such that it contacts not the second impurity diffusion regions, but the first impurity diffusion regions. | 2012-02-09 |
20120032278 | SHALLOW PN JUNCTION FORMED BY IN SITU DOPING DURING SELECTIVE GROWTH OF AN EMBEDDED SEMICONDUCTOR ALLOY BY A CYCLIC GROWTH/ETCH DEPOSITION PROCESS - A silicon/carbon alloy may be formed in drain and source regions, wherein another portion may be provided as an in situ doped material with a reduced offset with respect to the gate electrode material. For this purpose, in one illustrative embodiment, a cyclic epitaxial growth process including a plurality of growth/etch cycles may be used at low temperatures in an ultra-high vacuum ambient, thereby obtaining a substantially bottom to top fill behavior. | 2012-02-09 |
20120032279 | III-V METAL-OXIDE-SEMICONDUCTOR DEVICE - A barrier layer, hafnium oxide layer, between a III-V semiconductor layer and an lanthanum oxide layer is used to prevent interaction between the III-V semiconductor layer and the lanthanum oxide layer. Meanwhile, the high dielectric constant of the lanthanum oxide can be used to increase the capacitance of the semiconductor device. | 2012-02-09 |
20120032280 | MOS TRANSISTORS INCLUDING SiON GATE DIELECTRIC WITH ENHANCED NITROGEN CONCENTRATION AT ITS SIDEWALLS - A method of forming an integrated circuit (IC) having at least one MOS device includes forming a SiON gate dielectric layer on a silicon surface. A gate electrode layer is deposited on the SiON gate layer and then patterning forms a gate stack. Exposed gate dielectric sidewalls are revealed by the patterning. A supplemental silicon oxide layer is formed on the exposed SiON sidewalls followed by nitriding. After nitriding, a post nitridation annealing (PNA) forms an annealed N-enhanced SiON gate dielectric layer including N-enhanced SiON sidewalls, wherein along lines of constant thickness a N concentration at the N-enhanced SiON sidewalls is ≧ the N concentration in a bulk of the annealed N-enhanced SiON gate layer −2 atomic %. A source and drain region on opposing sides of the gate stack are formed to define a channel region under the gate stack. | 2012-02-09 |
20120032281 | SEMICONDUCTOR DEVICE PRODUCTION METHOD AND SEMICONDUCTOR DEVICE - A semiconductor device production method includes: forming an insulating film on a semiconductor substrate, forming a concave portion in the insulating film, forming a gate insulating film at bottom of the concave portion, the bottom being on the semiconductor substrate; covering an inner wall surface of the concave portion and a top face of the insulating film with a first gate electrode film that is made of an electrically conductive material containing a first metal; covering the first gate electrode film with a covering film of a material having a second melting point higher than a first melting point of the electrically conductive material, leaving part of the side face of the concave portion uncovered; and performing heat treatment following the covering film formation to allow the first gate electrode film to reflow. | 2012-02-09 |
20120032282 | MICROELECTROMECHANICAL SYSTEM (MEMS) CARRIER AND METHOD OF FABRICATING THE SAME - An MEMS carrier is provided that includes a core board having a first surface and an opposite second surface, a circuit layer formed on the first surface and having a plurality of conductive pads, and a through hole formed through the first and the second surfaces; a carrier layer formed on the second surface of the core board and covering an end of the through hole; a patterned metal layer formed on a portion of the carrier layer that covers the end of the through hole; a solder mask layer formed on the first surface of the core board and the circuit layer, wherein the solder mask layer has a plurality of openings for exposing the conductive pads; and a shielding metal layer disposed on a sidewall of the through hole, the patterned metal layer, and the portion of the carrier layer that covers the end of the through hole. Without the use of a circuit board, the MEMS carrier has reduced height and size. | 2012-02-09 |
20120032283 | SENSOR MODULE - A sensor module includes a substrate system which has multiple substrates situated one on top of the other and connected in each case via a wafer bond connection. The substrate system includes at least one first sensor substrate and at least one second sensor substrate, the first sensor substrate having a first sensor structure and the second sensor substrate having a second sensor structure. The first and second sensor structures are designed for detecting different characteristics. At least the first sensor structure includes a micromechanical functional structure. Moreover, a method for manufacturing such a sensor module is disclosed. | 2012-02-09 |
20120032284 | FILM FOR RESIN SPACER, LIGHT-RECEIVING DEVICE AND METHOD FOR MANUFACTURING SAME, AND MEMS DEVICE AND METHOD FOR MANUFACTURING SAME - According to one aspect of the present invention, a film for a resin spacer ( | 2012-02-09 |
20120032285 | Electronic Device Including MEMS Devices And Holed Substrates, In Particular Of The LGA Or BGA Type - An electronic device includes a substrate provided with a passing opening and a MEMS device including an active surface wherein a portion of the MEMS device is integrated sensitive to chemical/physical variations of a fluid. The active surface of the MEMS device faces the substrate and is spaced therefrom, the sensitive portion being aligned to the opening. A protective package incorporates at least partially the MEMS device and the substrate, leaving at least the sensitive portion of the MEMS device, and the opening of the substrate exposed. A barrier element is positioned in an area which surrounds the sensitive portion to realize a protection structure for the MEMS device, so that the sensitive portion is free. | 2012-02-09 |
20120032286 | THREE DIMENSIONAL FOLDED MEMS TECHNOLOGY FOR MULTI-AXIS SENSOR SYSTEMS - An apparatus is fabricated with a plurality of semiconductor-device substrates and/or MEMS substrates with micromachined sensors, circuits, transducers, and/or MEMS devices fabricated on the plurality of substrates. A plurality of flexible hinges couple the plurality of substrates into a substantially flat two dimensional foldable assembly. Electrical interconnects coupled to the sensors, circuits, transducers, and/or MEMS devices extend other ones of the plurality of substrates. The foldable assembly of substrates is assembled or folded into a three dimensional polyhedral structure with the plurality of substrates configured in three dimensions to form defined relative orientations in space with respect to each other. The invention includes a wafer scale method of fabricating the apparatus. | 2012-02-09 |
20120032287 | MRAM Device and Integration Techniques Compatible with Logic Integration - A semiconductor device includes a magnetic tunnel junction (MTJ) storage element configured to be disposed in a common interlayer metal dielectric (IMD) layer with a logic element. Cap layers separate the common IMD layer from a top and bottom IMD layer. Top and bottom electrodes are coupled to the MTJ storage element. Metal connections to the electrodes are formed in the top and bottom IMD layers respectively through vias in the separating cap layers. Alternatively, the separating cap layers are recessed and the bottom electrodes are embedded, such that direct contact to metal connections in the bottom IMD layer is established. Metal connections to the top electrode in the common IMD layer are enabled by isolating the metal connections from the MTJ storage elements with metal islands and isolating caps. | 2012-02-09 |
20120032288 | MAGNETORESISTIVE ELEMENT AND METHOD OF MANUFACTURING THE SAME - According to one embodiment, a magnetoresistive element comprises a multilayered structure and insulating film. The multilayered structure is formed on a substrate, and includes a fixed layer which has the invariable magnetization direction, a free layer which contains cobalt or iron and has the variable magnetization direction, and a nonmagnetic layer sandwiched between the fixed layer and free layer. The insulating film is formed on the side surface of the free layer, and contains boron and nitrogen. | 2012-02-09 |
20120032289 | MAGNETIC MEMORY DEVICE AND METHOD OF MANUFACTURING THE SAME - A magnetic memory device including a memory layer having a vertical magnetization on the layer surface, of which the direction of magnetization is changed according to information; and a reference layer provided against the memory layer, and being a basis of information while having a vertical magnetization on the layer surface, wherein the memory device memorizes the information by reversing the magnetization of the memory layer by a spin torque generated when a current flows between layers made from the memory layer, the nonmagnetization layer and the reference layer, and a coercive force of the memory layer at a memorization temperature is 0.7 times or less than a coercive force at room temperature, and a heat conductivity of a center portion of an electrode formed on one side of the memory layer in the direction of the layer surface is lower than a heat conductivity of surroundings thereof. | 2012-02-09 |
20120032290 | SOLID-STATE IMAGING DEVICE AND METHOD FOR MANUFACTURING THE SAME - A solid-state imaging device including: a semiconductor layer; a charge accumulation region configured to be formed inside the semiconductor layer and serve as part of a photodiode; and a reflective surface configured to be disposed inside or under the charge accumulation region and be so formed as to reflect light that has passed through the charge accumulation region and direct the light toward a center part of the charge accumulation region. | 2012-02-09 |
20120032291 | Stand-Alone Device - A stand-alone device comprising a silicon wafer having its front surface including a first layer of a first conductivity type and a second layer of a second conductivity type forming a photovoltaic cell; first vias crossing the wafer from the rear surface of the first layer and second vias crossing the wafer from the rear surface of the second layer; metallization levels on the rear surface of the wafer, the external level of these metallization levels defining contact pads; an antenna formed in one of the metallization levels; and one or several chips assembled on said pads; the metallization levels being shaped to provide selected interconnects between the different elements of the device. | 2012-02-09 |
20120032292 | PHOTODETECTOR HAVING A VERY THIN SEMICONDUCTING REGION - The instant disclosure describes a photodetector that includes at least one portion of a semiconducting layer formed directly on at least a portion of a reflective layer and to be illuminated with a light beam, at least one pad being formed on the portion of the semiconducting layer opposite the reflective layer portion, wherein the pad and the reflective layer portion are made of a metal or of a negative permittivity material, the optical cavity formed between said at least one reflective layer portion and said at least one pad has a thickness strictly lower than a quarter of the ratio of the light beam wavelength to the optical index of the semiconducting layer, and typically representing about one tenth of said ratio. | 2012-02-09 |
20120032293 | EDGE DEVICES LAYOUT FOR IMPROVED PERFORMANCE - A word line driver includes an active area having a length that extends in a first direction over a semiconductor substrate. A plurality of fingers formed over an upper surface of the active area. Each of the plurality of fingers has a length that extends in a second direction and forms a MOS transistor with a portion of the active area. A first dummy structure is disposed between an outer one of the plurality of fingers and an edge of the semiconductor substrate. The first dummy structure includes a portion that is at least partially disposed over a portion of the active area. | 2012-02-09 |
20120032294 | METHOD FOR FABRICATION OF A SEMICONDUCTOR DEVICE AND STRUCTURE - A semiconductor device comprising: a first single crystal silicon layer comprising first transistors, first alignment mark, and at least one metal layer overlying said first single crystal silicon layer, wherein said at least one metal layer comprises copper or aluminum more than other materials; a second layer overlying said at least one metal layer, said second layer comprising second transistors, second alignment mark, and a through via through said second layer, wherein said through via is a part of a connection path between said first transistors and said second transistors, wherein alignment of said through via is based on said first alignment mark and said second alignment mark and effected by a distance between said first alignment mark and said second alignment mark. | 2012-02-09 |
20120032295 | SEMICONDUCTOR DEVICE AND METHOD FOR PRODUCING SUCH A DEVICE - A semiconductor device and method for producing such a device is disclosed. One embodiment provides a semiconductor functional wafer having a first and second main surface. Component production processes are performed for producing a component functional region at the first main surface, wherein the component production processes produce an end state that is stable up to at least a first temperature. A carrier substrate is fitted to the first main surface. Access openings are produced to the first main surface. At least one further component production process is performed for producing patterned component functional regions at the first main surface of the functional wafer in the access openings. The end state produced in this process is stable up to a second temperature, which is less than the first temperature. | 2012-02-09 |
20120032296 | SEMICONDUCTOR DEVICE, SEMICONDUCTOR CIRCUIT SUBSTRATE, AND METHOD OF MANUFACTURING SEMICONDUCTOR CIRCUIT SUBSTRATE - A semiconductor circuit substrate includes a transistor-forming substrate and a circuit-forming substrate. The transistor-forming substrate is a GaN substrate and has a Bipolar Junction Transistor (BJT) located in its top surface. The bottom surface of the transistor-forming substrate is flat and has contact regions. The circuit-forming substrate is a material other than a compound semiconductor and has no semiconductor active elements. The circuit-forming substrate has a flat top surface, contact regions buried in and exposed at the top surface, and passive circuits. The transistor-forming substrate and the circuit-forming substrate are directly bonded together without any intervening film, such as an insulating film. | 2012-02-09 |
20120032297 | Electronic Device and Method for Fabricating the Same, Spiral Inductor Device and Method for Fabricating the Same - The invention provides an electronic device and method for fabricating the same, and a spiral inductor device and method for fabricating the same. The electronic device includes a substrate and a conductive trace pattern formed on the substrate, wherein the conductive trace pattern has an opening to expose the substrate. | 2012-02-09 |
20120032298 | SEMICONDUCTOR DEVICE, ELECTRONIC APPARATUS, AND METHOD OF MANUFACTURING SEMICONDUCTOR DEVICE - A semiconductor chip is mounted on a first surface of an interconnect substrate, and has a multilayer interconnect layer. A first inductor is formed over the multilayer interconnect layer, and a wiring axis direction thereof is directed in a horizontal direction to the interconnect substrate. A second inductor is formed on the multilayer interconnect layer, and a wiring axis direction thereof is directed in the horizontal direction to the interconnect substrate. The second inductor is opposite to the first inductor. A sealing resin seals at least the first surface of the interconnect substrate and the semiconductor chip. A groove is formed over the whole area of a portion that is positioned between the at least first inductor and the second inductor of a boundary surface of the multilayer interconnect layer and the sealing resin. | 2012-02-09 |
20120032299 | SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING THE SAME - A method of manufacturing a semiconductor device includes forming an insulating film over a semiconductor substrate, forming a capacitor including a lower electrode, a capacitor dielectric film including a ferroelectric material, and an upper electrode over the insulating film, forming a first protective insulating film over a side surface and upper surface of the capacitor by a sputtering method, and forming a second protective insulating film over the first protective insulating film by an atomic layer deposition method. | 2012-02-09 |
20120032300 | METHOD OF MANUFACTURING A FERROELECTRIC CAPACITOR AND A FERROELECTRIC CAPACITOR - A lower electrode film is formed above a substrate. A ferroelectric film is formed above the lower electrode film. An amorphous intermediate film of a perovskite-type conductive oxide is formed above the ferroelectric film. A first upper electrode film comprising oxide of at least one metal selected from a group of Pt, Pd, Rh, Ir, Ru, and Os is formed on the intermediate film. The intermediate film is crystallized by carrying out a first heat treatment in an atmosphere containing an oxidizing gas after the formation of the first upper electrode film. After the first heat treatment, a second upper electrode film comprising oxide of at least one metal selected from a group of Pt, Pd, Rh, Ir, Ru, and Os is formed on the first upper electrode film, at a temperature lower than the growth temperature for the first upper electrode film. | 2012-02-09 |
20120032301 | SEMICONDUCTOR DEVICE - A semiconductor device includes a lead frame including an island, a power supply lead, and a GND lead; a sheet-like solid electrolytic capacitor that is mounted on the island; a semiconductor chip that is mounted on the solid electrolytic capacitor, a plane area of the semiconductor chip being smaller than that of the solid electrolytic capacitor; a bonding wire that connects the semiconductor chip and the solid electrolytic capacitor, and a bonding wire that connects the solid electrolytic capacitor and the power supply lead or the GND lead, in which at least the connection part between the anode plate and the anode part of the solid electrolytic capacitor and the connection part between the anode plate and the bonding wire do not overlap when being vertically projected. | 2012-02-09 |
20120032302 | VERTICAL CAPACITORS FORMED ON SEMICONDUCTING SUBSTRATES - Semiconductor devices ( | 2012-02-09 |
20120032303 | Bipolar Junction Transistor Based on CMOS Technology - The present invention relates to semiconductor technologies, and more particularly to a bipolar junction transistor (BJT) in a CMOS base technology and methods of forming the same. The BJT includes a semiconductor substrate having an emitter region, a base having a first contact, and a collector having a second contact and a well plug; a first silicide film on the first contact; a second silicide film on the second contact; a first silicide blocking layer on or over the semiconductor substrate between the first and second silicide films, and a second silicide blocking layer on the semiconductor substrate between the first silicide film and the emitter region. | 2012-02-09 |
20120032304 | SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD THEREOF - It is an object of the present invention to manufacture a micromachine having a plurality of structural bodies with different functions and to shorten the time required for sacrifice layer etching in a process of manufacturing the micromachine. Another object of the present invention is to prevent a structural layer from being attached to a substrate after the sacrifice layer etching. In other words, an object of the present invention is to provide an inexpensive and high-value-added micromachine by improving throughput and yield. The sacrifice layer etching is conducted in multiple steps. In the multiple steps of the sacrifice layer etching, a part of the sacrifice layer that does not overlap with the structural layer is removed by the earlier sacrifice layer etching and a part of the sacrifice layer that is under the structural layer is removed by the later sacrifice layer etching. | 2012-02-09 |
20120032305 | SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD THEREOF - A semiconductor device and a manufacturing method thereof is disclosed in which the semiconductor device includes a p-type anode layer formed by a transition metal acceptor transition, and the manufacturing process is significantly simplified without the breakdown voltage characteristics deteriorating. An inversion advancement region inverted to a p-type by a transition metal acceptor transition, and in which the acceptor transition is advanced by point defect layers, is formed on the upper surface of an n-type drift layer. The inversion advancement region configures a p-type anode layer of a semiconductor device of the invention. The transition metal is, for example, platinum or gold. An n-type semiconductor substrate with a concentration higher than that of the n-type drift layer is adjacent to the lower surface of the n-type drift layer. | 2012-02-09 |
20120032306 | Method for Patterning a Semiconductor Surface, and Semiconductor Chip - A method for patterning a semiconductor surface is specified. A photoresist is applied to an outer area of a second semiconductor wafer. A surface of the photoresist that is remote from the second semiconductor wafer is patterned by impressing a patterned surface of the first wafer into the photoresist. A patterning method is applied to the surface of the photoresist, wherein a structure applied on the photoresist is transferred at least in places to the outer area of the second semiconductor wafer. | 2012-02-09 |
20120032307 | SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING THE SAME - In a CSP type semiconductor device, the invention prevents a second wiring from forming a narrowed portion on a lower surface of a step portion at the time of forming the second wiring that is connected to the back surface of a first wiring formed near a side surface portion of a semiconductor die on the front surface and extends onto the back surface of the semiconductor die over the step portion of a window that is formed from the back surface side of the semiconductor die so as to expose the back surface of the first wiring. A glass substrate is bonded on a semiconductor substrate on which a first wiring is formed on the front surface near a dicing line with an adhesive resin being interposed therebetween. The semiconductor substrate is then etched from the back surface to form a window having step portions with inclined sidewalls around the dicing line as a center. A second wiring is then formed so as to be connected to the first wiring exposed in the window and extend onto the back surface of the semiconductor substrate over the step portions of the window except part of the step portions on the dicing line and near the dicing line, which extend perpendicular to the dicing line. | 2012-02-09 |
20120032308 | GATE TRIM PROCESS USING EITHER WET ETCH OR DRY ETCH APPROACH TO TARGET CD FOR SELECTED TRANSISTORS - Disclosed are methods and devices for targeting CD of selected transistors in a semiconductor device. Varying CD is done by forming hard mask lines in a hard mask layer that have varying amounts of spacer material associated therewith. Hard mask lines corresponding to selected transistors are either left covered or uncovered by a resist applied over the hard mask layer. Then, spacer material is selectively removed from the hard mask lines to vary the width of hard mask lines and associated side wall spacers. A gate layer is then etched through the spaces in the hard mask lines to form gate lines having varying widths and targeted CD. | 2012-02-09 |
20120032309 | INK COMPOSITION FOR FORMING LIGHT SHIELDING FILM OF ORGANIC SEMICONDUCTOR DEVICE, METHOD FOR FORMING LIGHT SHIELDING FILM, AND ORGANIC TRANSISTOR DEVICE HAVING LIGHT SHIELDING FILM - There is provided an ink composition for forming a light shielding film in an organic semiconductor device which is capable of stably forming a fine pattern when forming a finely patterned light shielding film by the letterpress reverse printing method or microcontact printing method, which can be baked at a temperature equal to or less than the substrate heatproof temperature, and which is also capable of providing light shielding property and mechanical strength, the ink composition for forming a light shielding film in an organic semiconductor device which is an ink composition for forming a light shielding film in an organic semiconductor device comprising a black pigment; a resin component; a surface energy modifier; a quick-drying organic solvent; a slow-drying organic solvent; and a mold releasing agent, wherein the resin component comprises a solid resin that is in a solid state at 200° C. or less and a liquid resin that is in a liquid state at 10 to 50° C. at a ratio (solid resin/liquid resin) of 0.2 to 0.6. | 2012-02-09 |
20120032310 | Production Process For A Semi-Conductor Device And Semi-Conductor Device - A process for producing a semiconductor device comprises the following process steps: provision of a semiconductor substrate ( | 2012-02-09 |
20120032311 | MULTI COMPONENT DIELECTRIC LAYER - An in-situ process is described incorporating plasma enhanced chemical vapor deposition comprising flowing at least one of a Si, Si+C, B, Si+B, Si+B+C, and B+C containing precursor, and a N containing precursors at first times and removing the N precursor at second times and starting the flow of an oxidant gas and a porogen gas into the chamber. A dielectric layer is described comprising a network having inorganic random three dimensional covalent bonding throughout the network which contains at least one SiCN, SiCNH, SiN, SiNH, BN, BNH, CBN, CBNH, BSiN, BSiNH, SiCBN and SiCBNH as a first component and a low k dielectric as a second component adjacent thereto. | 2012-02-09 |
20120032312 | SEMICONDUCTOR SUBSTRATE, SEMICONDUCTOR DEVICE, AND METHOD OF PRODUCING SEMICONDUCTOR SUBSTRATE - A semiconductor substrate which allows desired electrical characteristics to be more easily acquired, a semiconductor device of the same, and a method of producing the semiconductor substrate. The method of producing this semiconductor substrate is provided with: a first epitaxial layer forming step (S | 2012-02-09 |
20120032313 | SEMICONDUCTOR DEVICE HAVING LATERAL DIODE - A semiconductor device having a lateral diode includes a semiconductor layer, a first semiconductor region in the semiconductor layer, a contact region having an impurity concentration greater than that of the first semiconductor region, a second semiconductor region located in the semiconductor layer and separated from the contact region, a first electrode electrically connected through the contact region to the first semiconductor region, and a second electrode electrically connected to the second semiconductor region. The second semiconductor region includes a low impurity concentration portion, a high impurity concentration portion, and an extension portion. The second electrode forms an ohmic contact with the high impurity concentration portion. The extension portion has an impurity concentration greater than that of the low impurity concentration portion and extends in a thickness direction of the semiconductor layer. | 2012-02-09 |
20120032314 | PACKAGE-ON-PACKAGE WITH FAN-OUT WLCSP - A package-on-package includes a package carrier; a semiconductor die assembled face-down to a chip side of the package carrier; a rewiring laminate structure between the semiconductor die and the package carrier; a plurality of bumps arranged on the rewiring laminate structure for electrically connecting the semiconductor die with the package carrier; and an IC package mounted on the package carrier. The IC package and the semiconductor die are at least partially overlapped. | 2012-02-09 |
20120032315 | INTEGRATED CIRCUIT PACKAGING SYSTEM WITH DIE PADDLE AND METHOD OF MANUFACTURE THEREOF - A method of manufacture of an integrated circuit packaging system includes: providing a package paddle having a single integral structure with a paddle central portion surrounded by a paddle peripheral portion; forming a terminal adjacent the package paddle; mounting an integrated circuit over the paddle central portion; and forming an encapsulation over the integrated circuit and the terminal, the encapsulation free of delamination with the encapsulation directly on the paddle peripheral portion. | 2012-02-09 |
20120032316 | SEMICONDUCTOR DEVICE, METHOD OF MANUFACTURING SEMICONDUCTOR DEVICE, MOLD, AND SEALING DEVICE - A rear surface opposite to one plane of a die pad is formed to be exposed from one plane of a sealing resin. In addition, a concave portion disposed to be parallel with at least a first side of an outermost edge of a central structure and a second side adjacent to the first side, respectively, is formed in the one plane of the sealing resin. Here, a depth of the concave portion is equal to or greater than a height of the outermost edge of the central structure. | 2012-02-09 |
20120032317 | Self-Aligning Structures and Method for Integrated Chips - A lead frame having a die thereon connects a conductive area on the die to a lead frame contact using a conductive clip that includes a structural portion that is received with a recess-like “tub” formed in the lead frame contact. The end of the clip received in the tub is held in place during subsequent handling by a solder paste deposit until the clip and leadframe undergo solder reflow to effect a reliable electrical connection. The effective surface area between one side of the clip and the other side of the clip within the tub is different so that the surface tension of the liquefied solder formed during the solder reflow step will “draw” the clip into a preferred alignment against a “stop” surface. | 2012-02-09 |
20120032318 | LAYERED CHIP PACKAGE AND METHOD OF MANUFACTURING SAME - A layered chip package includes a main body, and wiring that includes a plurality of wires disposed on a side surface of the main body. The main body includes: a main part including a plurality of layer portions; a plurality of first terminals disposed on the top surface of the main part and connected to the wiring; and a plurality of second terminals disposed on the bottom surface of the main part and connected to the wiring. Each layer portion includes a semiconductor chip. The plurality of second terminals are positioned to overlap the plurality of first terminals as viewed in a direction perpendicular to the top surface of the main body. A plurality of pairs of first and second terminals that are electrically connected via the wires include a plurality of pairs of a first terminal and a second terminal that are positioned not to overlap each other. | 2012-02-09 |
20120032319 | HIGH-VOLTAGE PACKAGED DEVICE - Packaged devices and methods for making and using the same are described. The packaged devices contain one or more circuit components, such as a die, that is attached to a leadframe having a first lead, a second lead, and a third lead (although, higher lead counts may be employed in some implementations). A portion of the circuit component and the leadframe are encapsulated in a molded housing so that the first lead is exposed from a first end of the housing while the second and third leads are exposed from a second end of the housing. In some configurations, the packaged device does not contain a fourth lead that is both electrically connected to the first lead and that is exposed from the second end of the molded housing. In other configurations, an area extending from the second lead to the third lead in the molded housing comprises an insulating material having a substantially uniform conductivity. Thus, the packaged devices have relatively large creepage and clearance distances between the first lead and the second and third leads. As a result, the packaged devices are able to operate at relatively high operating voltages without experiencing voltage breakdown. Other embodiments are described. | 2012-02-09 |
20120032320 | FLEXIBLE MICRO-SYSTEM AND FABRICATION METHOD THEREOF - A fabrication method for integrating chip(s) onto a flexible substrate in forming a flexible micro-system. The method includes a low-temperature flip-chip and a wafer-level fabrication process. Using the low-temperature flip-chip technique, the chip is bonded metallically onto the flexible substrate. To separate the flexible substrate from the substrate, etching is used to remove the sacrificial layer underneath the flexible substrate. The instant disclosure applies standardized micro-fabrication process for integrating chip(s) onto the flexible substrate. Without using special materials or fabrication procedures, the instant disclosure offers a cost-effective fabrication method for flexible micro-systems. | 2012-02-09 |
20120032321 | Electrical Contact Alignment Posts - An electronic apparatus and method of fabrication of the apparatus, the apparatus including a first electronic device having an interconnection surface with a first plurality of interconnection pads extending from the surface by a first distance and a second plurality of alignment posts extending from the surface by a second distance greater than the first distance, and a second electrical device having an interconnection surface with a first plurality of electrical interconnection pads, each pad arranged to contact a corresponding first electronic device interconnection surface pad upon assembly of the first electronic device interconnection surface upon the second electronic device interconnection surface, the second electronic device interconnection surface including a third plurality of alignment posts, each located to be adjacent to at least one of the first electronic device alignment posts upon assembly. | 2012-02-09 |
20120032322 | FLIP CHIP PACKAGE UTILIZING TRACE BUMP TRACE INTERCONNECTION - A flip chip package includes a substrate having a die attach surface; and a die mounted on the die attach surface with an active surface of the die facing the substrate, wherein the die is interconnected to the substrate via a plurality of copper pillar bumps on the active surface, wherein at least one of the plurality of copper pillar bumps has a bump width that is substantially equal to or smaller than a line width of a trace on the die attach surface of the substrate. | 2012-02-09 |
20120032323 | SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING THE SAME - A preferred aim of the invention is to provide technique for improving reliability of semiconductor devices when using a low-dielectric-constant film having a lower dielectric constant than a silicon oxide film to a part of an interlayer insulating film. More specifically, to achieve the preferred aim, an interlayer insulating film IL | 2012-02-09 |
20120032324 | SEMICONDUCTOR DEVICE - A semiconductor device, including: a semiconductor layer; a first conductive layer formed above the semiconductor layer and having a first width; a second conductive layer connected to the first conductive layer and having a second width which is smaller than the first width; an interlayer dielectric formed above the first conductive layer and the second conductive layer; and an electrode pad formed above the interlayer dielectric. A connection section at which the first conductive layer and the second conductive layer are connected is disposed in a specific region positioned inward from a line extending vertically downward from an edge of the electrode pad; and a reinforcing section is provided at the connection section. | 2012-02-09 |
20120032325 | SEMICONDUCTOR DEVICE - There is provided a semiconductor device with which stress can be prevented from locally concentrating on an external connecting terminal on a post and thus damages of the external connecting terminal can be prevented. The semiconductor device includes a semiconductor chip, a sealing resin layer stacked on a surface of the semiconductor chip, and the post which penetrates the sealing resin layer in a stacking direction of the semiconductor chip and the sealing resin layer, protrudes from the sealing resin layer, and has a periphery of the protruding portion opposedly in contact with a surface of the sealing resin layer in the stacking direction. | 2012-02-09 |
20120032326 | AIR THROUGH-SILICON VIA STRUCTURE - A silicon substrate has a conductive via extending from a first surface of the silicon substrate through the silicon substrate to a second surface of the silicon substrate. A dielectric via extends from the second surface of the silicon substrate toward the first surface of the silicon substrate. | 2012-02-09 |
20120032327 | SYSTEMS AND METHODS FOR REINFORCING CHIP PACKAGES - In accordance with some embodiments of the present disclosure, a chip package is provided. The chip package may include a chip, a substrate, and an interconnect layer disposed between the chip and the substrate. In some embodiments, the interconnect layer may include an array of bonding interconnects configured to provide electrical communication between the chip and a printed circuit board and reinforcement interconnects arranged around an outermost row of the array of bonding interconnects. | 2012-02-09 |
20120032328 | Package structure with underfilling material and packaging method thereof - A method for packaging semiconductor device is provided, which comprises: providing a carrier substrate having a top surface and a back surface, a circuit arrangement on the top surface of the carrier substrate, and a through hole is disposed near the center of the carrier substrate and is formed passed through the carrier substrate; providing a chip having an active surface and a back surface, a plurality of pads is disposed on the periphery of the active surface and a plurality of connecting elements is disposed thereon; the active surface of chip is flipped and bonded on the circuit arrangement on the top surface of the carrier substrate, and the plurality of connecting elements is not covering the through hole; filling the underfilling material to encapsulate between the plurality of connecting elements and the top surface of the carrier substrate and to fill with the through hole; and performing a suction process to remove the air within the underfilling material between the plurality of connecting elements on the chip and the top surface of the carrier substrate, such that the underfilling material can completely encapsulate between the plurality of connecting elements on the chip and the top surface of the carrier surface. | 2012-02-09 |
20120032329 | SEMICONDUCTOR INTEGRATED CIRCUIT DEVICE - In semiconductor integrated circuit devices for vehicle use, an aluminum pad on a semiconductor chip and an external device are coupled to each other by wire bonding using a gold wire for the convenience of mounting. Such a semiconductor integrated circuit device, however, causes a connection failure due to the interaction between aluminum and gold in use for a long time at a relatively high temperature (about 150 degrees C.). A semiconductor integrated circuit device can include a semiconductor chip as a part of the device, an electrolytic gold plated surface film (gold-based metal plated film) provided over an aluminum-based bonding pad on a semiconductor chip via a barrier metal film, and a gold bonding wire (gold-based bonding wire) for interconnection between the plated surface film and an external lead provided over a wiring board (wiring substrate). | 2012-02-09 |
20120032330 | MITIGATION OF PLATING STUB RESONANCE BY CONTROLLING SURFACE ROUGHNESS - Plating stub resonance in a circuit board may be mitigated by increasing surface roughness of the plating stub conductor. Roughening the plating stub increases its resistance due to the skin effect at higher frequencies, which decreases the quality factor of the transmission line and consequently increases the damping factor, to reduce any resonance that would occur in the plating stub as formed prior to roughening. The surface roughness can be increased in a variety of ways, including chemical processes, by selectively applying a laser beam, or by applying an etch-resistance material in selected locations. | 2012-02-09 |
20120032331 | CIRCUIT SUBSTRATE AND MANUFACTURING METHOD THEREOF AND PACKAGE STRUCTURE AND MANUFACTURING METHOD THEREOF - A circuit substrate includes the following elements. A conductive layer and a dielectric layer are disposed on an inner circuit structure in sequence, and a plurality of conductive blind vias are embedded in the dielectric layer and connected to a portion of the conductive layer. A plating seed layer is disposed between each of the first blind vias and the first conductive layer. Another conductive layer is disposed on the dielectric layer, wherein a portion of the another conductive layer is electrically connected to the conductive layer through the conductive blind vias. A third plating seed layer is disposed between the third conductive layer and each of the first blind vias and on the first dielectric layer. | 2012-02-09 |
20120032332 | Semiconductor Devices Having A Diffusion Barrier Layer and Methods of Manufacturing the Same - Methods of manufacturing a semiconductor device include forming a gate insulation layer including a high-k dielectric material on a substrate that is divided into a first region and a second region; forming a diffusion barrier layer including a first metal on a second portion of the gate insulation layer in the second region; forming a diffusion layer on the gate insulation layer and the diffusion barrier layer; and diffusing an element of the diffusion layer into a first portion of the gate insulation layer in the first region. | 2012-02-09 |
20120032333 | SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING THE SAME - A first insulating film is formed on a semiconductor substrate, an interconnect groove is formed in the first insulating film, the inside of the interconnect groove is filled with a metal film, thereby forming a first interconnect. Then, a protective film is formed on the first insulating film and the first interconnect, and the surface of the protective film is exposed to reactive gas, thereby forming a reaction layer on an interface between the first interconnect and the protective film. | 2012-02-09 |
20120032334 | SOFT ERROR RATE (SER) REDUCTION IN ADVANCED SILICON PROCESSES - Provided is a method of fabricating a semiconductor device. The method includes providing a substrate. The method includes forming a portion of an interconnect structure over the substrate. The portion of the interconnect structure has an opening. The method includes obtaining a boron-containing gas that is free of a boron-10 isotope. The method includes filling the opening with a conductive material to form a contact. The filling of the opening is carried out using the boron-containing gas. Also provided is a semiconductor device. The semiconductor device includes a substrate. The semiconductor device includes an interconnect structure formed over the substrate. The semiconductor device includes a conductive contact formed in the interconnect structure. The conductive contact has a material composition that includes Tungsten and Boron, wherein the Boron is a | 2012-02-09 |
20120032335 | ELECTRONIC COMPONENT AND METHOD FOR MANUFACTURING THE SAME - An electronic component including a wiring board having a power-source pattern and a signal pattern, a semiconductor element mounted on the wiring board and having a power-source electrode pad and a signal electrode pad, a first connection portion being made of a conductive material and connecting the signal pattern of the wiring board and the signal electrode pad of the semiconductor element, and a second connection portion being made of a conductive material and connecting the power-source pattern of the wiring board and the power-source electrode pad of the semiconductor element. The conductive material of the first connection portion and the conductive material of the second connection portion are selected such that the conductive material of the second connection portion has an electrical resistance which is lower than an electrical resistance of the conductive material of the first connection portion. | 2012-02-09 |
20120032336 | SELF-ALIGNED PERMANENT ON-CHIP INTERCONNECT STRUCTURE FORMED BY PITCH SPLITTING - A method of fabricating an interconnect structure is provided. The method includes forming a hybrid photo-patternable dielectric material atop a substrate. The hybrid photo-patternable dielectric material has dual-tone properties with a parabola like dissolution response to radiation. The hybrid photo-patternable dielectric material is then image-wise exposed to radiation such that a self-aligned pitch split pattern forms. A portion of the self-aligned split pattern is removed to provide a patterned hybrid photo-patternable dielectric material having at least one opening therein. The patterned hybrid photo-patternable dielectric material is then converted into a cured and patterned dielectric material having the at least one opening therein. The at least one opening within the cured and patterned dielectric material is then filed with at least an electrically conductive material. Also provided are a hybrid photo-patternable dielectric composition and an interconnect structure. | 2012-02-09 |
20120032337 | Flip Chip Substrate Package Assembly and Process for Making Same - Apparatus and methods for providing a package substrate and assembly for a flip chip integrated circuit. A substrate is provided having a solder mask layer, openings in the solder mask layer for conductive bump pads, and openings in the solder mask layer between the conductive bump pads exposing a dielectric layer underneath the solder mask layer. A flip chip integrated circuit is attached to the substrate using a thermal reflow to reflow conductive solder bumps on the integrated circuit to the conductive bump pads. An underfill material is dispensed beneath the integrated circuit and physically contacting the dielectric layer of the substrate. In additional embodiments, one or more integrated circuits are flip chip mounted to the substrate. The resulting assembly has improved thermal characteristics over the assemblies of the prior art. | 2012-02-09 |
20120032338 | SEMICONDUCTOR DEVICE AND METHOD FOR FABRICATING THE SAME - Disclosed is a semiconductor device which includes a base substrate; a lower electrode formed on a main surface of the base substrate; and an insulating film formed over the lower electrode and the main surface of the base substrate. The insulating film has a contact hole defined by a wall extending upwardly from the top surface of the lower electrode. The insulating film has a film density distribution in which a film density decreases with increasing distance from the main surface of the base substrate in the thickness direction. A width of the contact hole increases as the film density decreases. | 2012-02-09 |
20120032339 | INTEGRATED CIRCUIT STRUCTURE WITH THROUGH VIA FOR HEAT EVACUATING - An integrated circuit structure includes a semiconductor substrate, an active device disposed on a first region of the semiconductor substrate, a layer stack disposed on a second region of the semiconductor substrate, a through via penetrating through the layer stack and the semiconductor substrate, and a third dielectric layer disposed between the through via and the semiconductor substrate. In one embodiment of the present invention, the layer stack includes a first dielectric layer disposed on the semiconductor substrate and a heat-conducting member disposed on the first dielectric layer. | 2012-02-09 |
20120032340 | Semiconductor Die and Method of Forming FO-WLCSP Vertical Interconnect Using TSV and TMV - A semiconductor device has a TSV wafer and semiconductor die mounted over the TSV wafer. A channel is formed through the TSV wafer. An encapsulant is deposited over the semiconductor die and TSV wafer. Conductive TMV are formed through the encapsulant over the conductive TSV and contact pads of the semiconductor die. The conductive TMV can be formed through the channel. A conductive layer is formed over the encapsulant and electrically connected to the conductive TMV. The conductive TMV are formed during the same manufacturing process. An insulating layer is formed over the encapsulant and conductive layer. A plurality of semiconductor die of the same size or different sizes can be stacked over the TSV wafer. The plurality of semiconductor die can be stacked over opposite sides of the TSV wafer. An internal stacking module can be stacked over the semiconductor die and electrically connected through the conductive TMV. | 2012-02-09 |
20120032341 | SEMICONDUCTOR PACKAGE AND MANUFACTURING METHOD THEREOF - A semiconductor package and a manufacturing method thereof are provided. The semiconductor package includes a substrate, a semiconductor element, a package body and a conductive part. The substrate has an electrical contact. The semiconductor element is disposed on the substrate. The package body covers the semiconductor element and defines a through hole from which the electrical contact is exposed. Wherein, the package body includes a resin body and a plurality of fiber layers. The fiber layers are disposed in the resin body and define a plurality of fiber apertures which is arranged as an array. The conductive part is electrically connected to the substrate through the through hole. | 2012-02-09 |
20120032342 | SEMICONDUCTOR PACKAGE FOR SELECTING SEMICONDUCTOR CHIP FROM A CHIP STACK - A semiconductor package includes: first, second, third and fourth semiconductor chips stacked while having the arrangement of chip selection vias; and a connection unit provided between a second semiconductor chip and a third semiconductor chip, and configured to mutually connect some of the chip selection vias of the second and third semiconductor chips and disconnect the others of the chip selection vias of the second and third semiconductor chips, wherein the first and second semiconductor chips and the third and fourth semiconductor chips are stacked in a flip chip type. | 2012-02-09 |
20120032343 | PACKAGE SUBSTRATE FOR BUMP ON TRACE INTERCONNECTION - A package substrate including a conductive pattern disposed on a die attach surface of the package substrate; at least one bumping trace inlaid into the conductive pattern; and at least one gap disposed along with the bumping trace in the conductive pattern to separate the bumping trace from a bulk portion of the conductive pattern. The bumping trace may have a lathy shape from a plan view and a width substantially between 10 μm and 40 μm and a length substantially between 70 μm and 130 μm, for example. | 2012-02-09 |
20120032344 | SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING SEMICONDUCTOR DEVICE - A plurality of interconnects is, for example, a plurality of Cu interconnects, extending parallel to each other. Sidewall insulating films are formed at the sidewalls of each of a plurality of interconnects. An air gap is formed between each of a plurality of interconnects, and is located between a plurality of sidewall insulating films. The insulating film is formed on a plurality of interconnects, a plurality of sidewall insulating films, and the air gap. A via passes through the insulating film, and is connected to any of the interconnects. The sidewall insulating film is formed of a material having an etching rate lower than that of the insulating film in the conditions in which the insulating film is etched. | 2012-02-09 |
20120032345 | MULTILAYER CIRCUIT - A multilayer circuit ( | 2012-02-09 |
20120032346 | ENVIRONMENT-RESISTANT MODULE, MICROPACKAGE AND METHODS OF MANUFACTURING SAME - An environment-resistant module which provides both thermal and vibration isolation for a packaged micromachined or MEMS device is disclosed. A microplatform and a support structure for the microplatform provide the thermal and vibration isolation. The package is both hermetic and vacuum compatible and provides vertical feedthroughs for signal transfer. A micromachined or MEMS device transfer method is also disclosed that can handle a wide variety of individual micromachined or MEMS dies or wafers, in either a hybrid or integrated fashion. The module simultaneously provides both thermal and vibration isolation for the MEMS device using the microplatform and the support structure which may be fabricated from a thin glass wafer that is patterned to create crab-leg shaped suspension tethers or beams. | 2012-02-09 |
20120032347 | CHIP SCALE PACKAGE AND FABRICATION METHOD THEREOF - A fabrication method of a chip scale package includes providing electronic components, each having an active surface with electrode pads and an opposite inactive surface, and a hard board with a soft layer disposed thereon; adhering the electronic components to the soft layer via the inactive surfaces thereof; pressing the electronic components such that the soft layer encapsulates the electronic components while exposing the active surfaces thereof; forming a dielectric layer on the active surfaces of the electronic components and the soft layer; and forming a first wiring layer on the dielectric layer and electrically connected to the electrode pads, thereby solving the conventional problems caused by directly attaching a chip on an adhesive film, such as film-softening, encapsulant overflow, warpage, chip deviation and contamination that lead to poor electrical connection between the electrode pads and the wiring layer formed in a subsequent RDL process and even waste product. | 2012-02-09 |
20120032348 | THREE-DIMENSIONAL INTEGRATED CIRCUITS WITH PROTECTION LAYERS - A semiconductor structure includes a first die comprising a first substrate and a first bonding pad over the first substrate, a second die having a first surface and a second surface opposite the first surface, wherein the second die is stacked on the first die and a protection layer having a vertical portion on a sidewall of the second die, and a horizontal portion extending over the first die. | 2012-02-09 |
20120032349 | METHOD OF FABRICATING STACKED ASSEMBLY INCLUDING PLURALITY OF STACKED MICROELECTRONIC ELEMENTS - A method is provided for fabricating a stacked microelectronic assembly by steps including stacking and joining first and second like microelectronic substrates, each including a plurality of like microelectronic elements attached together at dicing lanes. Each microelectronic element has boundaries defined by edges including a first edge and a second edge. The first and second microelectronic substrates can be joined in different orientations, such that first edges of microelectronic elements of the first microelectronic substrate are aligned with second edges of microelectronic elements of the second microelectronic substrate. After exposing traces at the first and second edges of the microelectronic elements of the stacked microelectronic substrates, first and second leads can be formed which are connected to the exposed traces of the first and second microelectronic substrates, respectively. The second leads can be electrically isolated from the first leads. | 2012-02-09 |
20120032350 | Systems and Methods for Heat Dissipation Using Thermal Conduits - The addition of thermal conduits by bonding bond wires to bond pads either in a wire loop configuration or a pillar configuration can improve thermal dissipation of a fabricated die. The thermal conduits can be added as part of the normal packaging process of a semiconductor die and are electrically decoupled from the circuitry fabricated on the fabricated die. In an alternative, a dummy die is affixed to the fabricated die and the thermal conduits are affixed to the dummy die. Additionally, thermal conduits can be used in conjunction with a heat spreader. | 2012-02-09 |
20120032351 | SEMICONDUCTOR PACKAGE - A semiconductor package is provided. The semiconductor package includes a substrate, a semiconductor device, a plurality of element contacts, a molding compound and a plurality of substrate contacts. The substrate has opposite to the first surface the first surface and the second surface. The semiconductor device is disposed on the first surface. The element contacts electrically connect the substrate and the semiconductor device. The molding compound encapsulates the semiconductor device and a portion of the molding compound is located between the semiconductor device and the first surface, wherein the molding compound includes a plurality of fillers, the fillers amount to 85-89% of the molding compound and the sizes of the fillers range between 18 and 23 micrometers. The substrate contacts are formed on the second surface. | 2012-02-09 |
20120032352 | SIDE WETTABLE PLATING FOR SEMICONDUCTOR CHIP PACKAGE - A method for providing a semiconductor chip package with side wettable plating includes singulating a semiconductor chip package from an array of packages formed in a block format, immersing the semiconductor chip package in a bath of plating solution, contacting a lead land of the semiconductor chip package with conductive contact material within the bath of plating solution, connecting the conductive contact material to a cathode electrical potential, connecting an anode within the bath of plating solution to an anode electrical potential, and plating the lead land of the semiconductor chip package. | 2012-02-09 |
20120032353 | SEMICONDUCTOR DEVICE - A semiconductor device includes a wiring board having connection pads thereon and a semiconductor chip mounted on the wiring board. The wiring board and the semiconductor chip are covered with a sealing portion. Conductive members are extended upward from the connection pads and are exposed from the sealing portion. Rewiring lines are connected to the exposed conductive members. Land portions are arranged on the sealing portion and are electrically connected to the conductive members through the rewiring lines. | 2012-02-09 |