| 06th week of 2013 patent applcation highlights part 13 |
| Patent application number | Title | Published |
|---|
| 20130032892 | BIPOLAR TRANSISTOR IN BIPOLAR-CMOS TECHNOLOGY - A process of forming an integrated circuit containing a bipolar transistor and an MOS transistor, by forming a base layer of the bipolar transistor using a non-selective epitaxial process so that the base layer has a single crystalline region on a collector active area and a polycrystalline region on adjacent field oxide, and concurrently implanting the MOS gate layer and the polycrystalline region of the base layer, so that the base-collector junction extends into the substrate less than one-third of the depth of the field oxide, and vertically cumulative doping density of the polycrystalline region of the base layer is between 80 percent and 125 percent of a vertically cumulative doping density of the MOS gate. An integrated circuit containing a bipolar transistor and an MOS transistor formed by the described process. | 2013-02-07 |
| 20130032893 | SEMICONDUCTOR DEVICE COMPRISING METAL GATE ELECTRODE STRUCTURES AND NON-FETS WITH DIFFERENT HEIGHT BY EARLY ADAPTATION OF GATE STACK TOPOGRAPHY - Gate height scaling in sophisticated semiconductor devices may be implemented without requiring a redesign of non-transistor devices. To this end, the semiconductor electrode material may be adapted in its thickness above active regions and isolation regions that receive the non-transistor devices. Thereafter, the actual patterning of the adapted gate layer stack may be performed so as to obtain gate electrode structures of a desired height for improving, in particular, AC performance without requiring a redesign of the non-transistor devices. | 2013-02-07 |
| 20130032894 | METHODS FOR NORMALIZING STRAIN IN SEMICONDCUTOR DEVICES AND STRAIN NORMALIZED SEMICONDUCTOR DEVICES - A method of normalizing strain in semiconductor devices and normalized strain semiconductor devices. The method includes: forming first and second field effect transistors of an integrated circuit; forming a stress layer over the first and second field effect transistors, the stress layer inducing strain in channel regions of the first and second field effect transistors; and selectively thinning the stress layer over at least a portion of the second field effect transistor. | 2013-02-07 |
| 20130032895 | HIGH-VOLTAGE TRANSISTOR DEVICE AND ASSOCIATED METHOD FOR MANUFACTURING - A high-voltage transistor device comprises a spiral resistive field plate over a first well region between a drain region and a source region of the high-voltage transistor device, wherein the spiral resistive field plate is separated from the first well region by a first isolation layer, and is coupled between the drain region and the source region. The high-voltage transistor device further comprises a plurality of first field plates over the spiral resistive field plate with each first field plate covering one or more segments of the spiral resistive field plate, wherein the plurality of first field plates are isolated from the spiral resistive field plate by a first dielectric layer, and wherein the plurality of first field plates are isolated from each other, and a starting first field plate is connected to the source region. | 2013-02-07 |
| 20130032896 | SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD THEREOF - A semiconductor device includes a p-type semiconductor layer, n-type column regions formed of columnar thermal donors exhibiting an n-type property, a p-type column region interposed between the n-type column regions, the n-type column regions configured to form a super-junction structure in cooperation with the p-type column region, a channel region formed in the semiconductor layer, a source region formed in the channel region, a gate insulator film formed on the semiconductor layer, and a gate electrode formed on the gate insulator film and opposite to the channel region across the gate insulator film. | 2013-02-07 |
| 20130032897 | MOSFET GATE ELECTRODE EMPLOYING ARSENIC-DOPED SILICON-GERMANIUM ALLOY LAYER - A stack of a gate dielectric layer, a metallic material layer, an amorphous silicon-germanium alloy layer, and an amorphous silicon layer is deposited on a semiconductor substrate. In one embodiment, the amorphous silicon-germanium alloy layer is deposited as an in-situ amorphous arsenic-doped silicon-germanium alloy layer. In another embodiment, the amorphous silicon-germanium alloy layer is deposited as intrinsic semiconductor material layer, and arsenic is subsequently implanted into the amorphous silicon-germanium alloy layer. The stack is patterned and annealed to form a gate electrode. | 2013-02-07 |
| 20130032898 | METAL-GATE/HIGH-k/GE MOSFET WITH LASER ANNEALING AND FABRICATION METHOD THEREOF - The present invention discloses a metal-gate/high-κ/Ge MOSFET with laser annealing and a fabrication method thereof. The fabrication method comprises the following steps: forming a substrate; implanting a source area and a drain area on the substrate; activating the source area and the drain area by first laser light; depositing gate dielectric material on the substrate; annealing high-κ dielectric material by second laser light; and forming a metal gate on the high-κ dielectric material. | 2013-02-07 |
| 20130032899 | SEMICONDUCTOR DEVICE - An N-type MIS transistor includes an active region surrounded by an element isolation region in a semiconductor substrate, a gate insulating film formed on the active region and the element isolation region and having a high-k insulating film, and a gate electrode formed on the gate insulating film. An N-type impurity region is formed at least in a portion located below the gate insulating film out of a portion of the active region which contacts the element isolation region. | 2013-02-07 |
| 20130032900 | BUFFER LAYER AND METHOD OF FORMING BUFFER LAYER - Buffer layer and method of forming the buffer layer, the method including forming a high-k dielectric layer, forming a titanium nitride layer over the high-k dielectric layer, forming a silicon layer on the titanium nitride layer, annealing the silicon layer into the titanium nitride layer to form an annealed silicon layer and forming an n-metal over the high-k dielectric layer. | 2013-02-07 |
| 20130032901 | FULL SILICIDATION PREVENTION VIA DUAL NICKEL DEPOSITION APPROACH - Semiconductor devices are formed without full silicidation of the gates and with independent adjustment of silicides in the gates and source/drain regions. Embodiments include forming a gate on a substrate, forming a nitride cap on the gate, forming a source/drain region on each side of the gate, forming a first silicide in each source/drain region, removing the nitride cap subsequent to the formation of the first silicide, and forming a second silicide in the source/drain regions and in the gate, subsequent to removing the nitride cap. Embodiments include forming the first silicide by forming a first metal layer on the source/drain regions and performing a first RTA, and forming the second silicide by forming a second metal layer on the source/drain regions and on the gate and performing a second RTA. | 2013-02-07 |
| 20130032902 | INTEGRATED CIRCUIT WITH SENSOR AND METHOD OF MANUFACTURING SUCH AN INTEGRATED CIRCUIT - Disclosed is an integrated circuit comprising a substrate ( | 2013-02-07 |
| 20130032903 | INTEGRATED CIRCUIT WITH SENSOR AND METHOD OF MANUFACTURING SUCH AN INTEGRATED CIRCUIT - Disclosed is an integrated circuit comprising a substrate ( | 2013-02-07 |
| 20130032904 | Coated Capacitive Sensor - In one embodiment, a method of forming a MEMS device includes providing a substrate, forming a sacrificial layer above the substrate layer, forming a silicon based working portion on the sacrificial layer, releasing the silicon based working portion from the sacrificial layer such that the working portion includes at least one exposed outer surface, forming a first layer of silicide forming metal on the at least one exposed outer surface of the silicon based working portion, and forming a first silicide layer with the first layer of silicide forming metal. | 2013-02-07 |
| 20130032905 | SEMICONDUCTOR PACKAGE CONFIGURED TO ELECTRICALLY COUPLE TO A PRINTED CIRCUIT BOARD AND METHOD OF PROVIDING SAME - In some examples, a semiconductor package can be configured to electrically couple to a printed circuit board. The semiconductor package can include: (a) a lid having one or more first electrically conductive leads; (b) a base coupled to the lid and having one or more second electrically conductive leads electrically coupled to the one or more first electrically conductive leads; (c) one or more first semiconductor devices mechanically coupled to the lid and electrically coupled to the one or more first electrically conductive leads; and (d) one or more first micro-electrical-mechanical system devices mechanically coupled to the lid and electrically coupled to the one or more first electrically conductive leads. At least one of the lid or the base can have at least one port hole. The one or more first electrically conductive leads can be configured to couple to the printed circuit board. Other embodiments are disclosed. | 2013-02-07 |
| 20130032906 | FERROELECTRIC DEVICE - A ferroelectric device comprises: a silicon substrate (a first substrate); a lower electrode (a first electrode) formed on one surface side of first substrate; a ferroelectric film formed on a surface of lower electrode opposite to first substrate side; and an upper electrode (a second electrode) formed on a surface of ferroelectric film opposite to lower electrode side. The ferroelectric film is formed of a ferroelectric material with a lattice constant difference from silicon. The ferroelectric device further comprises a shock absorbing layer formed of a material with better lattice matching with ferroelectric film than silicon and provided directly below the lower electrode. The first substrate is provided with a cavity that exposes a surface of shock absorbing layer opposite to lower electrode side. | 2013-02-07 |
| 20130032907 | MRAM with sidewall protection and method of fabrication - BEOL memory cells are described that include one or more sidewall protection layers on the memory device (including, for example, an MTJ element) deposited prior to interconnect via etching to prevent the formation of electrical shorts between layers. One embodiment uses a single layer sidewall protection sleeve that is deposited after the memory device has been patterned. The layer material is vertically etched down to expose the upper surface of the top electrode while leaving a residual layer of protective material surrounding the rest of the memory device. The material for the protection layer is selected to resist the etchant used to remove the first dielectric material from the via in the subsequent interconnect process. A second embodiment uses dual-layer sidewall protection in which the first layer covers the memory element is preferably an oxygen-free dielectric and the second layer protects the first layer during via etching. | 2013-02-07 |
| 20130032908 | Hybrid Film for Protecting MTJ Stacks of MRAM - A method includes patterning a plurality of magnetic tunnel junction (MTJ) layers to form a MTJ stack, and forming a first dielectric cap layer over a top surface and on a sidewall of the MTJ stack. The step of patterning and the step of forming the first dielectric cap layer are in-situ formed in a same vacuum environment. A second dielectric cap layer is formed over and contacting the first dielectric cap layer. | 2013-02-07 |
| 20130032909 | HALL EFFECT ELEMENT HAVING A WIDE CROSS SHAPE WITH DIMENSIONS SELECTED TO RESULT IN IMPROVED PERFORMANCE CHARACTERISTICS - A Hall effect element includes a Hall plate having geometric features selected to result in a highest ratio of a sensitivity divided by a plate resistance. The resulting shape is a so-called “wide-cross” shape. | 2013-02-07 |
| 20130032910 | MAGNETIC MEMORY DEVICE AND METHOD OF MANUFACTURING THE SAME - A magnetic memory device includes a first fixing layer, a first tunnel barrier coupled to the first fixing layer, a free layer coupled to the first tunnel barrier and having a stacked structure including a first ferromagnetic layer, an oxide tunnel spacer, and a second ferromagnetic layer, a second tunnel barrier coupled to the free layer, and a second fixing layer coupled to the second tunnel barrier. | 2013-02-07 |
| 20130032911 | MAGNETIC MEMORY DEVICE AND FABRICATION METHOD THEREOF - A vertical magnetic memory device includes a pinned layer including a plurality of first ferromagnetic layers that are alternately stacked with at least one first spacer, wherein the pinned layer is configured to have a vertical magnetization, a free layer including a plurality of second ferromagnetic layers that are alternately stacked with at least one second spacer, and a tunnel barrier coupled between the pinned layer and the free layer. | 2013-02-07 |
| 20130032912 | High-k Dielectric Liners in Shallow Trench Isolations - A circuit structure includes a semiconductor substrate having a top surface. A dielectric material extends from the top surface into the semiconductor substrate. A high-k dielectric layer is formed of a high-k dielectric material, wherein the high-k dielectric layer comprises a first portion on a sidewall of the dielectric material, and a second portion underlying the dielectric material. | 2013-02-07 |
| 20130032913 | GRAPHENE STRUCTURE, PRODUCTION METHOD THEREOF, PHOTOELECTRIC CONVERSION ELEMENT, SOLAR CELL, AND IMAGE PICKUP APPARATUS - A graphene structure includes a conductive layer and a protective layer. The conductive layer is formed of graphene doped with a dopant, and the protective layer is laminated on the conductive layer and formed of a material having a higher oxidation-reduction potential than water. | 2013-02-07 |
| 20130032914 | SOLID-STATE IMAGING APPARATUS AND ELECTRONIC APPARATUS - A solid-state imaging apparatus including: a sensor substrate that has a plurality of pixels configured to receive incident light, the plurality of pixels being arranged on an upper surface of a semiconductor substrate; a transparent substrate that has a lower surface facing an upper surface of the sensor substrate and is configured to transmit the incident light therethrough; and a diffraction grating that is provided at any position between an upper surface of the transparent substrate and the upper surface of the sensor substrate and is configured to transmit the incident light therethrough, in which the diffraction grating is formed so as to diffract reflected diffraction light caused by that the incident light is incident on a pixel area in which the plurality of pixels are arranged on the upper surface of the semiconductor substrate and is diffracted. | 2013-02-07 |
| 20130032915 | SOLID STATE IMAGING DEVICE AND METHOD FOR MANUFACTURING THE SAME - According to one embodiment, a solid state imaging device includes a substrate, and a plurality of interference filters. The substrate includes a plurality of photoelectric conversion units. The plurality of interference filters is provided individually for the plurality of photoelectric conversion units. The plurality of interference filters includes a plurality of layers with different refractive indices stacked. The plurality of interference filters is configured to selectively transmit light in a prescribed wavelength range. A space is provided between adjacent ones of the interference filters. | 2013-02-07 |
| 20130032916 | Pad Structures in BSI Image Sensor Chips - An integrated circuit structure includes a semiconductor substrate, and a dielectric pad extending from a bottom surface of the semiconductor substrate up into the semiconductor substrate. A low-k dielectric layer is disposed underlying the semiconductor substrate. A first non-low-k dielectric layer is underlying the low-k dielectric layer. A metal pad is underlying the first non-low-k dielectric layer. A second non-low-k dielectric layer is underlying the metal pad. An opening extends from a top surface of the semiconductor substrate down to penetrate through the semiconductor substrate, the dielectric pad, and the low-k dielectric layer, wherein the opening lands on a top surface of the metal pad. A passivation layer includes a portion on a sidewall of the opening, wherein a portion of the passivation layer at a bottom of the opening is removed. | 2013-02-07 |
| 20130032917 | SOLID-STATE IMAGE SENSING APPARATUS - This invention provides a solid-state image sensing apparatus in which a sensor portion that performs photo-electric conversion and plural layers of wiring lines including a signal line for the sensor portion are formed on a semiconductor substrate; which includes an effective pixel portion configured such that light enters the sensor portion, and an optical black portion shielded so that the light does not enter the sensor portion; and which has a light-receiving surface on the back surface side of the semiconductor substrate. The optical black portion includes the sensor portion, a first light-shielding film formed closer to the back surface side of the semiconductor substrate than the sensor portion, and a second light-shielding film formed closer to the front surface side of the semiconductor substrate than the sensor portion. | 2013-02-07 |
| 20130032918 | IMAGE SENSOR AND METHOD FOR MANUFACTURING THE SAME - An image sensor may include a semiconductor substrate, a plurality of light receiving devices formed within the semiconductor substrate, and a plurality of device isolation films for isolating the light receiving devices from each other. When an arrangement direction of a pixel array may be formed by arranging the light receiving devices is a horizontal direction, the pixel array may be formed by alternately arranging a first type light receiving device and a second type light receiving device having different horizontal lengths. | 2013-02-07 |
| 20130032919 | SOLID-STATE IMAGE PICKUP ELEMENT AND ELECTRONIC DEVICE - There is provided a solid-state image pickup element including a pixel array part in which a plurality of pixels are arranged on a silicon substrate in arrays, and a drive part driving the pixel. The pixel includes a photoelectric conversion part formed near a second face of the silicon substrate opposite to a first face on which a wiring layer is laminated, for generating a charge corresponding to incident light, an overflow part formed in contact with the second face and fixed to a predetermined voltage, and a potential barrier part formed to be connected with the photoelectric conversion part and the .overflow part, for serving as a barrier against a charge overflowed from the photoelectric conversion part on the overflow part. | 2013-02-07 |
| 20130032920 | Pad Structures Formed in Double Openings in Dielectric Layers - An image sensor device includes a semiconductor substrate having a front side and a backside. A first dielectric layer is on the front side of the semiconductor substrate. A metal pad is in the first dielectric layer. A second dielectric layer is over the first dielectric layer and on the front side of the semiconductor substrate. An opening penetrates through the semiconductor substrate from the backside of the semiconductor substrate, wherein the opening includes a first portion extending to expose a portion of the metal pad and a second portion extending to expose a portion of the second dielectric layer. A metal layer is formed in the first portion and the second portion of the opening. | 2013-02-07 |
| 20130032921 | BACKSIDE ILLUMINATED IMAGE SENSOR WITH STRESSED FILM - An image sensor includes a photosensitive region disposed within a semiconductor layer and a stress adjusting layer. The photosensitive region is sensitive to light incident through a first side of the image sensor to collect an image charge. The stress adjusting layer is disposed over the first side of the semiconductor layer to establish a stress characteristic that encourages photo-generated charge carriers to migrate towards the photosensitive region. | 2013-02-07 |
| 20130032922 | INTEGRATED HIGH VOLTAGE DIVIDER - An integrated circuit containing a voltage divider having an upper resistor of unsilicided gate material over field oxide around a central opening and a drift layer under the upper resistor, an input terminal coupled to an input node of the upper resistor adjacent to the central opening in the field oxide and coupled to the drift layer through the central opening, a sense terminal coupled to a sense node on the upper resistor opposite from the input node, a lower resistor with a sense node coupled to the sense terminal and a reference node, and a reference terminal coupled to the reference node. A process of forming the integrated circuit containing the voltage divider. | 2013-02-07 |
| 20130032923 | Integrated Inductor - A system and method for providing an integrated inductor with a high Quality factor (Q) is provided. An embodiment comprises a magnetic core that is in a center of a conductive spiral. The magnetic core increases the inductance of the integrated inductor to allow the inductor to be used in applications such as a RF choke. The magnetic core may be formed in the same manner and time as an underbump metallization. | 2013-02-07 |
| 20130032924 | SEMICONDUCTOR DEVICE HAVING CYLINDRICAL LOWER ELECTRODE OF CAPACITOR AND MANUFACTURING METHOD THEREOF - To provide a semiconductor device including: plural capacitors each including a cylindrical lower electrode having an internal wall and an external wall, and an upper electrode that covers the external wall of the lower electrode via a capacitance dielectric film; and a supporting film having a buried portion buried in an internal region surrounded by the internal wall of the lower electrode, and a supporting portion a part of which is positioned within the internal region and remaining parts of which are positioned at outside of the internal region. The supporting portion sandwiches an upper end of the lower electrode at both ends of the upper end by covering the internal wall and the external wall of the upper end of the lower electrode. | 2013-02-07 |
| 20130032925 | SEMICONDUCTOR DEVICE - A semiconductor device comprises a first external terminal having a first size, a plurality of second external terminals each having a second size smaller than the first size, an external terminal area in which the first external terminal and the second external terminals are arranged, and a plurality of wires connecting between the second external terminals and a plurality of circuits formed adjacent to the external terminal area and corresponding to the second external terminals. The second external terminals and the wires constitute a plurality of interfaces. Each of the interfaces includes at least one adjustment portion that adjusts a time constant of the wire so that the wires have the same time constant. At least part of the adjustment portions is located in a margin area produced in the external terminal area by a difference between the first size and the second size. | 2013-02-07 |
| 20130032926 | ADJUSTABLE RESISTOR - An adjustable resistor formed on a first insulating layer of a substrate, including: a first polysilicon layer covered with a second insulating layer of a first thickness, except in a region where the first polysilicon layer is covered with a thin insulator layer of a second thickness smaller than the first thickness; a second polysilicon layer covering the second insulating layer and the thin insulator layer; on each side of the second insulating layer and at a distance from it, a first and a second conductive vias providing access to the terminals of the resistor on the first polysilicon layer; and a third conductive via providing access to a contacting area on the second polysilicon layer. | 2013-02-07 |
| 20130032927 | System for Self-Aligned Contacts - A system for forming self-aligned contacts includes electroplating a first metal contact onto a Group III-V semiconductor substrate, the first metal contact having a greater height than width and having a straight sidewall profile, etching back the semiconductor substrate down to a base layer to expose an emitter semiconductor layer under the first metal contact, conformally depositing a dielectric layer on a vertical side of the first metal contact, a vertical side of the emitter semiconductor layer and on the base layer, anisotropically etching the dielectric layer off of the semiconductor substrate to form a dielectric sidewall spacer on the vertical side of the first metal contact and providing a second metal contact immediately adjacent the dielectric sidewall spacer. | 2013-02-07 |
| 20130032928 | GROUP III NITRIDE COMPOSITE SUBSTRATE - A group III nitride composite substrate includes a support substrate, an oxide film formed on the support substrate, and a group III nitride layer formed on the oxide film. The oxide film may be a film selected from the group consisting of a TiO | 2013-02-07 |
| 20130032929 | METHOD OF PROTECTING DEEP TRENCH SIDEWALL FROM PROCESS DAMAGE - Method of protecting a liner in a previously formed deep trench module from subsequent processing steps, and resulting structure. A deep trench module includes a deep trench with one or more liner films and a fill material in an SOI substrate. A mask layer is patterned to form first and second masks aligned over the liner films on first and second sidewalls of the deep trench, respectively. Further etching creates a polysilicon tab under the first mask which protects the liner film adjacent the first sidewall from being exposed during subsequent etches. The second mask protects its underlying polysilicon from subsequent etches to maintain a conduction strap from SOI layer to deep trench. The masks are removed. An isolation film is deposited on the substrate and planarized to form and isolation region. The resulting structure has a polysilicon tab interposed between the deep trench liner and the isolation region. | 2013-02-07 |
| 20130032930 | SEMICONDUCTOR DEVICE COMPRISING THROUGH-ELECTRODE INTERCONNECT - A semiconductor device having a through electrode excellent in performance as for an electrode and manufacturing stability is provided. There is provided a through electrode composed of a conductive small diameter plug and a conductive large diameter plug on a semiconductor device. A cross sectional area of the small diameter plug is made larger than a cross sectional area and a diameter of a connection plug, and is made smaller than a cross sectional area and a diameter of the large diameter plug. In addition, a protruding portion formed in such a way that the small diameter plug is projected from the silicon substrate is put into an upper face of the large diameter plug. Further, an upper face of the small diameter plug is connected to a first interconnect. | 2013-02-07 |
| 20130032931 | LAYER STRUCTURE WITH EMI SHIELDING EFFECT - A layer structure with an electromagnetic interference (EMI) shielding effect is applicable for reducing an EMI effect caused by signal transmission between through silicon vias, so as to effectively provide the EMI shielding effect between electrical interconnections of a three-dimensional (3D) integrated circuit. By forming EMI-shielding through silicon vias at predetermined positions between the through silicon vias used for signal transmission, a good EMI shielding effect can be attended, and signal distortion possibly caused by the EMI effect can be reduced between different chips or substrates. | 2013-02-07 |
| 20130032932 | BONDED WIRE SEMICONDUCTOR DEVICE - A bonded wire semiconductor device includes a sub-assembly including a semiconductor die having an active face with a set of internal electrical contact elements and an externally exposed set of electrical contact elements. A set of bond wires make respective electrical connections between the internal electrical contact elements and the externally exposed set of electrical contact elements. A molding compound encapsulates the semiconductor die with the active face embedded in the molding compound. The bond wires have the same length. The bond wires are bonded to the internal electrical contact elements and to the externally exposed electrical contact elements at first and second curved arrays and of bond positions respectively. The first and second curved arrays and of bond positions have corresponding concentric shapes. | 2013-02-07 |
| 20130032933 | EPOXY RESIN COMPOSITION FOR OPTICAL SEMICONDUCTOR DEVICE, LEAD FRAME FOR OPTICAL SEMICONDUCTOR DEVICE AND SUBSTRATE FOR OPTICAL SEMICONDUCTOR DEVICE OBTAINED USING THE SAME, AND OPTICAL SEMICONDUCTOR DEVICE - The present invention relates to an epoxy resin composition for an optical semiconductor device, including the following ingredients (A) to (E): (A) an epoxy resin; (B) a curing agent; (C) a white pigment; (D) an inorganic filler; and (E) a silane coupling agent, in which a total content of the ingredient (C) and the ingredient (D) is from 69 to 94% by weight of the whole of the epoxy resin composition, and the ingredient (E) is contained in an amount satisfying the specific conditions. | 2013-02-07 |
| 20130032934 | PACKAGED MICROELECTRONIC ELEMENTS HAVING BLIND VIAS FOR HEAT DISSIPATION - System and method for thermal management in a multi-chip packaged device. A microelectronic unit is disclosed, and includes a semiconductor element having a top surface and a bottom surface remote from the top surface. A semiconductor device including active elements is located adjacent to the top surface. Operation of the semiconductor device generates heat. Additionally, one or more first blind vias extend from the bottom surface and partially into a thickness of the semiconductor element. In that manner, the blind via does not contact or extend to the semiconductor device (defined as active regions of the semiconductor element, and moreover, is electrically isolated from the semiconductor device. A thermally conductive material fills the one or more first blind vias for heat dissipation. Specifically, heat generated by the semiconductor device thermally conducts from the semiconductor element, and is further distributed, transferred and/or dissipated through the one or more first blind vias to other connecting components. | 2013-02-07 |
| 20130032935 | IMPLEMENTING ENHANCED THERMAL CONDUCTIVITY IN STACKED MODULES - A method and structures are provided for implementing enhanced thermal conductivity between a lid and heat sink for stacked modules. A chip lid and lateral heat distributor includes cooperating features for implementing enhanced thermal conductivity. The chip lid includes a groove along an inner side wall including a flat wall surface and a curved edge surface. The lateral heat distributor includes a mating edge portion received within the groove. The mating edge portion includes a bent arm for engaging the curved edge surface groove and a flat portion. The lateral heat distributor is assembled into place with the chip lid, the mating edge portion of the lateral heat distributor bends and snaps into the groove of the chip lid. The bent arm portion presses on the curved surface of the groove, and provides an upward force to push the flat portion against the flat wall surface of the groove. | 2013-02-07 |
| 20130032936 | PACKAGE FOR A MEMS SENSOR AND MANUFACTURING PROCESS THEREOF - A packaged MEMS device, wherein at least two support structures are stacked on each other and are formed both by a support layer and a wall layer coupled to each other and delimiting a respective chamber. The chamber of the first support structure is upwardly delimited by the support layer of the second support structure. A first and a second dice are accommodated in a respective chamber, carried by the respective support layer of the first support structure. The support layer of the second support structure has a through hole allowing wire connections to directly couple the first and the second dice. A lid substrate, coupled to the second support structure, closes the chamber of the second support structure. | 2013-02-07 |
| 20130032937 | SEMICONDUCTOR DEVICE AND ASSOCIATED METHOD - The invention provides a semiconductor device and associated method, which includes a substrate, a first die, multiple sub-package systems surrounding the first die, and a heat spreader. The first die and the sub-package systems are installed on a same surface of the substrate, wherein projections of the first die and each sub-package system on the surface partially overlap, and have a portion not overlapping. Each of the sub-package systems includes an interposer and multiple second dice installed on the interposer by way of flip-chip. The heat spreader includes a protrusion portion and a dissipation plate; the dissipation plate covers the first die and the sub-package systems, and the protrusion portion is set between the dissipation plate and the first die. | 2013-02-07 |
| 20130032938 | THREE DIMENSIONAL SEMICONDUCTOR ASSEMBLY BOARD WITH BUMP/FLANGE SUPPORTING BOARD, CORELESS BUILD-UP CIRCUITRY AND BUILT-IN ELECTRONIC DEVICE - A semiconductor assembly board includes a supporting board, a coreless build-up circuitry and a built-in electronic device. The supporting board includes a bump, a flange and a via hole in the bump. The built-in electronic device extends into the via hole and is electrically connected to the build-up circuitry. The build-up circuitry extends from the flange and the built-in electronic device and provides signal routing for the built-in electronic device. The supporting board provides mechanical support, ground/power plane and heat sink for the coreless build-up circuitry. | 2013-02-07 |
| 20130032939 | CHIP PACKAGE STRUCTURE - A chip package structure includes a flexible substrate having a chip mounting region, a plurality of leads disposed on the flexible substrate, an insulating layer and a chip. Each lead includes a body portion and an inner lead portion connected to each other. The body portion is located outside the chip mounting region and has a thickness greater than that of the inner lead portion. The insulating layer is disposed on the inner lead portions. The chip has an active surface on which a plurality of bumps and a seal ring adjacent to the chip edges are disposed. The chip is mounted within the chip mounting region and electrically connects the flexible substrate by connecting the inner lead portions of the leads with the bumps. The insulating layer is corresponding to the seal ring in position when the chip is electrically connected to the flexible substrate. | 2013-02-07 |
| 20130032940 | CHIP PACKAGE STRUCTURE - A chip package structure includes a chip, a flexible substrate, first leads and second leads. First bumps, second bumps and a seal ring are disposed on an active surface of the chip. The first and second bumps are respectively adjacent to first and second edges of the chip. The seal ring is located between the bumps and the edges. The chip is disposed in a chip mounting region of the flexible substrate. The first and second edges correspond to first and second sides of the chip mounting region respectively. The first leads disposed on the flexible substrate enter the chip mounting region through the first side and extend toward the second side to electrically connect the second bumps respectively. The second leads disposed on the flexible substrate enter the chip mounting region through the second side and extend toward the first side to electrically connect the first bumps respectively. | 2013-02-07 |
| 20130032941 | ROUTING LAYER FOR MITIGATING STRESS IN A SEMICONDUCTOR DIE - A routing layer for a semiconductor die is disclosed. The routing layer includes traces interconnecting integrated circuit bond-pads to UBMs. The routing layer is formed on a layer of dielectric material. The routing layer includes conductive traces arranged underneath the UBMs as to absorb stress from solder bumps attached to the UMBs. Traces beneath the UBMs protect parts of the underlying dielectric material proximate the solder bumps, from the stress. | 2013-02-07 |
| 20130032942 | SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD THEREFOR - A semiconductor device includes a circuit substrate, a first semiconductor chip disposed on the circuit substrate, a plurality of first spacers disposed on the first semiconductor chip, a second semiconductor chip which includes a first adhesive agent layer on a lower face thereof and is disposed on upper portions of the plurality of spacers, a wire which connects the circuit substrate to the first semiconductor chip, and a first sealing material which seals a gap between the first semiconductor chip and the first adhesive agent layer, wherein each height of the plurality of the first spacers is greater than height of the wire relative to an upper face of the first semiconductor chip. | 2013-02-07 |
| 20130032943 | SEMICONDUCTOR DEVICE - A semiconductor device includes a semiconductor chip which includes a first circuit and a second circuit that are spaced apart from each other, without internal wirings electrically connecting the first circuit and the second circuit to each other, a substrate on which the semiconductor chip is disposed, and substrate wirings that are arranged on the substrate and electrically connect the first circuit and the second circuit to each other. | 2013-02-07 |
| 20130032944 | MICROELECTRONIC PACKAGE WITH STACKED MICROELECTRONIC ELEMENTS AND METHOD FOR MANUFACTURE THEREOF - A microelectronic package may include a stacked microelectronic unit including at least first and second vertically stacked microelectronic elements each having a front face facing a top surface of the package. The front face of the first element may be adjacent the top surface, and the first element may overlie the front face of the second element such that at least a portion of the front face of the second element having an element contact thereon extends beyond an edge of the first element. A conductive structure may electrically connect a first terminal at the top surface to an element contact at the front face of the second element, and include a continuous monolithic metal feature extending along the top surface and through at least a portion of an encapsulant, which is between the top surface and the front face of the second element, towards the element contact. | 2013-02-07 |
| 20130032945 | SELF-ALIGNED FINE PITCH PERMANENT ON-CHIP INTERCONNECT STRUCTURES AND METHOD OF FABRICATION - An interconnect structure and methods for making the same include sidewall portions of an interlevel dielectric layer. The sidewall portions have a width less than a minimum feature size for a given lithographic technology and the width is formed by a thickness of the interlevel dielectric layer when conformally formed on vertical surfaces of a mandrel. The sidewall portions form spaced-apart openings. Conductive structures fill the spaced-apart openings and are separated by the sidewall portions to form single damascene structures. | 2013-02-07 |
| 20130032946 | LASER-ASSISTED CLEAVING OF A RECONSTITUTED WAFER FOR STACKED DIE ASSEMBLIES - A method of forming stacked die devices includes attaching first semiconductor die onto a wafer to form a reconstituted wafer, and then bonding second semiconductor die onto the first semiconductor die to form a plurality of singulated stacked die devices on the wafer. A support tape is attached to a bottomside of the second semiconductor die. A dicing tape is attached to the wafer. The wafer is laser irradiated before or after attachment of the dicing tape at intended dicing lanes that align with gaps between the first semiconductor die to mechanically weaken the wafer at the intended dicing lanes, but not cut through the wafer. The dicing tape is pulled to cleave the wafer into a plurality of singulated portions to form a plurality of singulated stacked die devices attached to the singulated wafer portions by the dicing tape. The support tape is removed prior to cleaving. | 2013-02-07 |
| 20130032947 | SEMICONDUCTOR PACKAGE AND METHOD OF MANUFACTURING THE SAME - A semiconductor package that stably protects an internal semiconductor chip from external shocks, and a method of manufacturing the semiconductor package is disclosed. The semiconductor package includes a first semiconductor chip including a first body layer having a first surface, a second surface, and a lateral surface between the first surface and the second surface, and a first protective layer that exposes an edge portion of the first surface and forms a step difference with the first surface; an encapsulation structure that covers a lateral surface of the first body layer and the edge portion of the first surface so as to encapsulate the first semiconductor chip to have a locking structure; and a first conductive terminal formed on the first body layer through the protective layer. | 2013-02-07 |
| 20130032948 | SEMICONDUCTOR DEVICE INCLUDING SUBSTRATE HAVING GROOVES - A semiconductor device including a substrate having grooves is provided. The semiconductor device includes a substrate including a first surface, a second surface opposite to the first surface, an opening penetrating from the first surface to the second surface, and a first groove formed at a side of the opening, a semiconductor chip formed on the opening at the first surface of the substrate and flip-chip bonded to the first surface by a plurality of first external connection terminals, and a molding unit filling a region between the substrate and the semiconductor chip, filling the opening and filling at least a portion of the first groove, and covering the semiconductor chip. | 2013-02-07 |
| 20130032949 | SELF-ALIGNED FINE PITCH PERMANENT ON-CHIP INTERCONNECT STRUCTURES AND METHOD OF FABRICATION - An interconnect structure and methods for making the same include sidewall portions of an interlevel dielectric layer. The sidewall portions have a width less than a minimum feature size for a given lithographic technology and the width is formed by a thickness of the interlevel dielectric layer when conformally formed on vertical surfaces of a mandrel. The sidewall portions form spaced-apart openings. Conductive structures fill the spaced-apart openings and are separated by the sidewall portions to form single damascene structures. | 2013-02-07 |
| 20130032950 | Techniques for Interconnecting Stacked Dies Using Connection Sites - An integrated circuit die includes conductive connection sites located at least on a surface of the integrated circuit die within a contiguous region thereof. The integrated circuit also includes a core circuit located outside the contiguous region. The core circuit is coupled to at least one of the connection sites. | 2013-02-07 |
| 20130032951 | SEMICONDUCTOR DEVICE COMPRISING VARIABLE-SIZED CONTACT, METHOD OF FORMING SAME, AND APPARATUS COMPRISING SAME - A semiconductor device comprises an electrical contact designed to reduce a contact resistance. The electrical contact has a size that varies according to a length of a region where the contact is to be formed. | 2013-02-07 |
| 20130032952 | Semiconductor Device and Method of Forming POP With Stacked Semiconductor Die and Bumps Formed Directly on the Lower Die - A semiconductor device has a first semiconductor wafer mounted to a carrier. A second semiconductor wafer is mounted to the first semiconductor wafer. The first and second semiconductor wafers are singulated to separate stacked first and second semiconductor die. A peripheral region between the stacked semiconductor die is expanded. A conductive layer is formed over the carrier between the stacked semiconductor die. Alternatively, a conductive via is formed partially through the carrier. A bond wire is formed between contact pads on the second semiconductor die and the conductive layer or conductive via. An encapsulant is deposited over the stacked semiconductor die, bond wire, and carrier. The carrier is removed to expose the conductive layer or conductive via and contact pads on the first semiconductor die. Bumps are formed directly on the conductive layer and contact pads on the first semiconductor die. | 2013-02-07 |
| 20130032953 | METHOD OF MANUFACTURING A PLURALITY OF ELECTRONIC ASSEMBLIES - A method of manufacturing a plurality of electronic devices is provided. Each one of a plurality of first conductive terminals on a plurality of integrated circuits formed on a device wafer is connected to a respective one of a plurality of second conductive terminals on a carrier wafer, thereby forming a combination wafer assembly. The combination wafer assembly is singulated between the integrated circuits to form separate electronic assemblies. The combination wafer assembly also allows for an underfill material to be introduced and to cured at wafer level and for thinning of the device wafer at wafer level without requiring a separate supporting substrate. Alignment between the device wafer and the carrier wafer can be tested by conducting a current through first and second conductors in the device and carrier wafers, respectively. | 2013-02-07 |
| 20130032954 | STACKABLE INTEGRATED CIRCUIT PACKAGE SYSTEM - A stacked integrated circuit package-in-package system is provided including forming a first external interconnect; mounting a first integrated circuit die below the first external interconnect; stacking a second integrated circuit die over the first integrated circuit die in an offset configuration not over the first external interconnect; connecting the first integrated circuit die with the first external interconnect; and encapsulating the second integrated circuit die with the first external interconnect and the first integrated circuit die partially exposed. | 2013-02-07 |
| 20130032955 | Low-K Dielectric Layer and Porogen - A system and method for a low-k dielectric layer are provided. A preferred embodiment comprises forming a matrix and forming a porogen within the matrix. The porogen comprises an organic ring structure with fewer than fifteen carbons and a large percentage of single bonds. Additionally, the porogen may have a viscosity greater than 1.3 and a Reynolds numbers less than 0.5. | 2013-02-07 |
| 20130032956 | SEMICONDUCTOR DEVICE AND METHOD FOR MANUFACTURING THE SAME - A method for manufacturing a semiconductor device includes a first photolithography step of forming a first device pattern corresponding to a first pattern, and a plurality of alignment marks corresponding to a plurality of marks, upon a step of exposing the entire device region in one shot using a first mask including the first pattern and the plurality of marks, and a second photolithography step of, after the first photolithography step, forming second device patterns respectively corresponding to second patterns in a plurality of divided regions which form the device region, upon steps of individually exposing the plurality of divided regions using second masks each including the second pattern corresponding thereto. | 2013-02-07 |
| 20130032957 | AERATION SYSTEM - An aeration system including a housing, a fluid inlet at a first end of the housing, an outlet at a second end of the housing, a cylindrical support member rotatably mounted within the housing between the inlet and the outlet, and supported by a plurality of bearings, the support member having an interior surface enclosing an interior cavity, the cavity being in communication with the inlet and the outlet, at least one vane disposed on the interior surface of the support member and extending from the interior surface towards the rotational axis of the support member, the vane including an inner edge positioned such that a gap is defined between the inner edge of the vane and the rotational axis of the support member, at least one gas inlet in communication with the cavity of the support member, and a motive device for rotating the support member within the housing. | 2013-02-07 |
| 20130032958 | APPARATUS AND METHOD OF MANUFACTURING LIGHT GUIDE PLATE - An apparatus for manufacturing light guide plate includes a coater containing UV curable glue, a first pressing roller and a second pressing roller. The first pressing roller and the second pressing roller are located nearby each other and space a predetermined distance from each other. The coater distributes UV curable glue on the surface of the first pressing roller or the second pressing roller. The first pressing roller and the second pressing roller cooperatively press the distributed UV curable glue. At least one of the first pressing roller and the second pressing roller includes a transparent shell and a UV lamp in the transparent shell. The UV lamp emits UV light to the other pressing roller. The UV lamp solidifies the UV curable glue pressed between the first pressing roller and the second pressing roller. | 2013-02-07 |
| 20130032959 | METHOD FOR FORMING OPTICAL FILM - A method for manufacturing an optical film includes providing a molding machine. The molding machine includes a hopper, a first cylindrical roller, a second cylindrical roller, and a UV light source. The first and second cylindrical rollers are located at two opposite sides of a narrow outlet of the hopper and positioned at substantially a same height just below the narrow outlet. Thereafter, a UV-curable material is provided into the hopper, and flows out from the narrow outlet of the hopper. The UV light source is turned on toward the UV-curable material. Furthermore, the first and second cylindrical rollers are rotated to directly press the UV-curable material when the UV-curable material is cured. | 2013-02-07 |
| 20130032960 | MODULAR PIPE FORMATION APPARATUS - A modular plastic pipe formation apparatus, wherein at least two components of the pipe formation apparatus are disposed with respect to at least one or more respective modules. | 2013-02-07 |
| 20130032961 | CONTROL DEVICE AND CONTROL METHOD FOR INJECTION MOLDING MACHINE - To execute a stable pressure control, in a control device for an injection molding machine, a filling/pressure-keeping determining unit determines whether the injection molding machine is performing a pressure keeping operation, an elastic constant identifier acquires, when the filling/pressure-keeping determining unit determines that the pressure keeping operation is in progress, a pressure detection value and a position detection value as operation information of a motor and identifies an elastic constant K based on the acquired pressure detection value and the position detection value, and a pressure-control control-parameter setting unit calculates a proportional gain Ka of a pressure controller such that a product of the proportional gain Ka of the pressure controller and the elastic constant K is smaller than a speed control bandwidth ωsc of a speed controller, and sets the calculated proportional gain Ka to the pressure controller. | 2013-02-07 |
| 20130032962 | POROGEN COMPOSITIONS, METHODS OF MAKING AND USES - The present specification discloses porogen compositions comprising a core material and shell material, methods of making such porogen compositions, methods of forming such porous materials using such porogen compositions, biocompatible implantable devices comprising such porous materials, and methods of making such biocompatible implantable devices. | 2013-02-07 |
| 20130032963 | METHOD FOR PRODUCING POLYPROPYLENE-BASED RESIN FOAMED BLOW-MOLDED ARTICLE - Provided is a method that can improve formability and blow moldability of a foamed parison as compared with conventional production method and can produce a polypropylene-based resin foamed blow-molded article having excellent uniformity of wall thickness over a wide range of its density. The method comprises kneading a polypropylene-based resin with a physical foaming agent, extruding the thus obtained foamable molten resin through a die to obtain a foamed parison in a softened state, placing the foamed parison between molds and then blow-molding the foamed parison and is characterized in that the polypropylene-based resin comprises a polypropylene-based resin (A) satisfying specific requirements (1) to (3) and a polypropylene-based resin (B) satisfying a specific requirement (4), when the polypropylene-based resins (A) and (B) are each subjected to dynamic viscoelasticity measurement in which an oscillation strain is applied thereto at a temperature of 190° C., and that the mixing ratio by weight (A:B) of the resin (A) to the resin (B) is in the range of 100:0.5 to 100:5. | 2013-02-07 |
| 20130032964 | METHOD OF MANUFACTURING MOLDED ARTICLE INCLUDING COMPONENT INSERT-MOLDED IN RESIN MIXED WITH SOLID POWDER - The exemplary embodiment provides a method of manufacturing a molded article including a component insert-molded in a molding material mixed with solid powder. The method includes an injecting step of injecting the molding material and the solid powder into a molding die, an agitating step of agitating the molding material and the solid powder within the molding die to disperse the solid powder in the molding material, and an embedding step of pressing and embedding the component into the agitated mixture of the molding material and the solid powder while vibrating at least one of the component and the molding die. | 2013-02-07 |
| 20130032965 | Method for Hot Isostatic Pressing a Substrate - Disclosed is a method for hot isostatic pressing a substrate. At first, a metal container is provided. Powder is filled in the metal container before the metal container is located in an oven. The metal container is subjected to isostatic pressing that includes heating and pressing. Thus, the metal container shrinks and presses on the powder evenly and turns the powder into a nugget. The metal container is moved out of the oven and broken to release the nugget. A substrate is cut from the nugget. With the hot isostatic pressing, the substrate exhibits only a few flaws and is large, fine, homogenous and strong so that the substrate is not vulnerable to deformation in a high-pressure environment. | 2013-02-07 |
| 20130032966 | METHOD OF MANUFACTURING MOLDED ARTICLE INCLUDING COMPONENT INSERT-MOLDED IN MOLDING MATERIAL MIXED WITH SOLID POWDER - The method of manufacturing a molded article including a component insert-molded in a molding material mixed with solid powder includes an injecting step of injecting the molding material and the solid powder into a molding die, an agitating step of agitating the molding material and the solid powder within the molding die to disperse the solid powder in the molding material, and an embedding step of pressing and embedding the component into an agitated mixture of the molding material and the solid powder. | 2013-02-07 |
| 20130032967 | COLD ETHYLENE OXIDE STERILIZATION OF A BIODEGRADABLE POLYMERIC STENT - Methods of sterilizing medical devices, particularly stents, that include a polymer with ethylene oxide. The polymer may be in the device body or a coating on the device. The method entails exposure such that the temperature of the device does not exceed the glass transition temperature of the polymer in the wet stage, that is as plasticized by the sterilant. The sterilant may include water vapor. | 2013-02-07 |
| 20130032968 | METHOD FOR PREPARING COATED BINDER UNITS AND DEVICE FOR USE THEREIN - A method for preparing coated binder units wherein the coated binder units comprise a core of binder coated with a layer of coating material, wherein the binder is a bituminous binder or a synthetic binder comprising a resin, an oil and optionally a polymer, which method comprises the steps of: (a) supplying the binder and the coating material to an co-extrusion device which comprises an even number of pairs of inner and outer dies, whereby the binder is supplied to the inner dies and the coating material is supplied to the outer dies; (b) co-extruding the binder and the coating material by means of the co-extrusion device, thereby producing streams of extrudate in which the binder is coated with a layer of the coating material; and (c) optionally, shaping the streams of extrudate, into units of the coated binder. The invention further relates to the co-extrusion device. | 2013-02-07 |
| 20130032969 | PERMEABLE MATERIAL COMPACTING APPARATUS AND METHOD - A permeable material compacting method includes positioning permeable material around a mandrel, rotating the permeable material about an axis of the mandrel, longitudinally moving at least one tapered surface against the permeable material and reducing a radial thickness of the permeable material between a surface of the mandrel and the at least one tapered surface. | 2013-02-07 |
| 20130032970 | WHITE POLYMIDE FILM AND MANUFACTURE THEREOF - A process of manufacturing a white polyimide film comprising performing condensation polymerization of monomers comprising diamine and dianhydride components to obtain a solution; adding a dehydrant, a catalyst and a coloration filler into the solution to obtain a precursor solution; coating a layer of the precursor solution on a support; and baking the coated layer of the precursor solution to form a white polyimide film. The diamine component can include 2,2′-bis(trifluoromethyl)benzidine, and the dianhydride component can include 3,3′,4,4′-biphenyltetracarboxylic dianhydride and 2,2-bis[4-(3,4-dicarboxyphenoxy) phenyl]propane dianhydride. The coloration filler can include TiO | 2013-02-07 |
| 20130032971 | METHOD FOR FORMING PATTERNS AND METHOD FOR PRODUCING PATTERNED SUBSTRATES - A resist layer constituted by a resist composition (which may include unavoidable impurities) including a polymerizable compound that includes polyfunctional monomers that become polymers having three dimensional structures by cross linking when polymerized and a polymerization initiating agent which is activated by one of light and an electron beam is formed on a substrate. A surface of a mold having a predetermined pattern of protrusions and recesses is pressed against the resist layer. Light is irradiated onto the resist layer to cure the resist layer. The mold is separated from the resist layer under conditions that the temperature of the resist layer is 40° C. or greater. | 2013-02-07 |
| 20130032972 | INJECTION MOLDING APPARATUS - The injection molding employing a mold that includes a molding surface in which a pin hole is formed, and at least one ejector pin that is inserted through the pin hole and that includes an outer peripheral surface facing an inner peripheral surface of the pin hole; includes closing a mold, injecting material into the mold, setting the material, opening the mold, and extruding the material by making a tip end surface of the at least one ejector pin protrude out of a pin hole. The tip end surface is recessed from the molding surface by a predetermined distance in a direction opposite a direction in which the material is extruded, while injecting the material into the mold. | 2013-02-07 |
| 20130032973 | METHOD AND MANUFACTURING ASSEMBLY FOR SINTERING FUEL CELL ELECTRODES AND IMPREGNATING POROUS ELECTRODES WITH ELECTROLYTE POWDERS BY INDUCTION HEATING FOR MASS PRODUCTION - A method of manufacturing an electrode for a fuel cell, the method comprising forming a powder bed from a predetermined powder, sintering the powder bed at a first predetermined temperature to form a substrate, and in some embodiments subsequently distributing an electrolyte powder on a surface of the substrate, and impregnating the substrate with electrolyte by heating the substrate with the electrolyte powder thereon to a second predetermined temperature so as to melt and wick the electrolyte into the substrate, thereby forming the electrode for the fuel cell, wherein at least one of the sintering and impregnating is performed by applying induction heating to at least one of said powder bed and said substrate. | 2013-02-07 |
| 20130032974 | PERMEABLE MATERIAL COMPACTING METHOD AND APPARATUS - A permeable material compacting method includes, forming a cavity between a membrane and a structure, porting fluid to or from the cavity, positioning permeable material adjacent the membrane, generating a differential pressure across the membrane, deforming the membrane, and decreasing volume of the permeable material | 2013-02-07 |
| 20130032975 | Method for Making a Wafer Level Aluminum Nitride Substrate - Disclosed is a method for making a pure aluminum nitride substrate. At first, aluminum nitride is mixed with a water-resistant material and an adhesive material. The mixture is made into grains in a granulation process. The grains are molded into a nugget in a steel mode by hydraulic pressure. The nugget is subjected to a cold isostatic pressing process. At a low temperature, the water-resistant material and the adhesive material are removed from the nugget. Then, the nugget, boron nitride and nitrogen are introduced into and sintered in an oven, thus providing a pure aluminum nitride substrate. The purity and quality of the aluminum nitride substrate are high. The aluminum nitride substrate can be used in a light-emitting diode. The method is simple, the yield is high, and the heat radiation of the aluminum nitride substrate is excellent. | 2013-02-07 |
| 20130032976 | METHOD OF DIRECTING A GAS FLOW IN A GAS CUTTING TIP - A method of directing a gas flow in a tip of a gas torch includes: directing a flow of gas to an outer passageway of the tip; directing the flow of gas inwardly through at least one intermediate gas passageway; directing the flow of gas to a central gas passageway of the tip; and directing the flow of gas distally through a distal orifice of the tip. | 2013-02-07 |
| 20130032977 | MIST COOLING APPARATUS AND HEAT TREATMENT APPARATUS - The mist cooling apparatus ( | 2013-02-07 |
| 20130032978 | Burner Gland For An Electric Arc Furnace - A burner enclosure for use in locating a burner in an a wall of an electric arc furnace, the burner enclosure includes a plurality of walls wherein each wall includes a serpentine cooling path therein and an inlet located proximal a first edge of each wall and an outlet located proximal a second edge of each wall and wherein the walls are assembled into the burner enclosure so an inlet of one wall can be connected by an elbow to an outlet of an adjoining wall to create a cooling fluid flow path through the entire burner enclosure to improve the performance of the burner in the burner enclosure and to improve the overall efficiency of the electric arc furnace. | 2013-02-07 |
| 20130032979 | DAMPING STRUT FOR A BICYCLE - A damping strut for a bicycle has a hydraulic shock absorber having a damper volume filled with incompressible damping fluid, a pressure application device that detects the current displacement state of the damping strut, and at least one disk valve. When the damping strut is displaced, the damper volume changes so that the damping fluid flows, creating a damping force which counteracts the displacement, through the disk valve. A control piston is coupled to the disk valve in order to vary the degree of opening of the disk valve. Control piston pressure can be applied by the pressure application device with a compressible control fluid, dependent on the displacement state detected by the pressure application device, such that on detection of a pre-determined displacement state of the damping strut, the disk valve is pre-tensioned in the closing direction thereof, so that the damping force is increased. | 2013-02-07 |
| 20130032980 | INSTALLATION AND METHOD FOR CLEANING AND/OR DEBURRING WORKPIECES - To provide an installation for cleaning and/or deburring workpieces, comprising a treatment region configured to enable a cleaning treatment and/or a deburring treatment to be performed on a workpiece therein, a loading device for transferring the workpiece from an outer area of the installation into the treatment region and an unloading device for transferring the workpiece from the treatment region into the outer area of the installation, with which installation there is achieved a high workpiece throughput with a favourable cleaning and/or deburring result, it is proposed that the loading device and/or the unloading device comprises at least one treatment device configured to enable the workpiece to be treated during the transfer between the outer area of the installation and the treatment region of the installation. | 2013-02-07 |
| 20130032981 | COMPRESSED-AIR-OPERATED VACUUM GENERATOR OR VACUUM GRIPPER - The invention relates to a compressed-air-operated vacuum generator or vacuum gripper having at least two vacuum units, wherein each vacuum unit has a suction chamber, an intake opening which opens into the suction chamber, an outflow opening which opens out of the suction chamber, and at least one drive air opening which opens into the outflow opening between the intake opening and the outflow opening, and wherein the vacuum units operate on the basis of at least two different principles (Venturi, Bernoulli, Coanda, vortex, etc.) for generating a negative pressure. | 2013-02-07 |
| 20130032982 | Workpiece-holding unit for installation on machining centers for connecting rods - A workpiece-holding unit for installation on machining centers for connecting rods, comprising a crosspiece which is adapted to be rotatably supported about its axis in front of a machining head of the machining center and has internal, hydraulic longitudinal ducts which communicate with respective hydraulic outlets on the main faces of the crosspiece and are connected to hydraulic feed means. Several workpiece-holding tools are installable on the main faces of the crosspiece and are provided with positioning mechanisms and locking mechanisms for at least one connecting rod, which are hydraulically operated via respective hydraulic lines leading at positions aligned to said hydraulic outlets. | 2013-02-07 |
| 20130032983 | HOOK PORTION OF CLAMP METER - A clamp meter has a main body and a stationary jaw fixed to an end of the main body. A hook portion of the clamp meter includes a movable jaw, a displacing means and a knob. The movable jaw is mounted on the main body corresponding to the position of the stationary jaw. The movable jaw and the stationary jaw together form a closed loop. The displacing means is mounted in the main body and comprises a displaceable rod connected to the movable jaw and a gear set for driving the displaceable rod. The knob is connected to the gear set for driving the displaceable rod and the movable jaw for linear displacement. The movable jaw is activated by the displaceable rod to generate a linear displacement, so that the user can operate the clamp meter more easily for measurement. | 2013-02-07 |
| 20130032984 | Pin Locking Support Fixture - A pin locking apparatus | 2013-02-07 |
| 20130032985 | PORTABLE WORKPIECE STOPPING DEVICE INCLUDING DETAILED METHOD OF USE - A portable workpiece stopping device, attachable to a work surface relative to a primary tool, permitting a repetitive same-length operation to be performed on any number of workpieces, and which allows for interruption of the operation without affecting the essential positioning of the stopping device relative to the primary tool. The stopping device comprises a base plate selectively attachable to a work surface, a rotation plate rotatably coupled to the base plate, an alignment plate adjustably coupled to the rotation plate, a stop plate fixedly coupled to the alignment plate, and a support shelf adjustably coupled to the stop plate. The stopping device can be selectively transitioned from an obstructing position, which blocks the end of a workpiece pressed against the stop plate, thereby allowing the repetitive same-length operation to be performed, to a non-obstructing position which provides for unfettered positioning of any workpiece relative to the primary tool. | 2013-02-07 |
| 20130032986 | Selectable Collect Folder and Folding Method - A printing press is provided. The printing press includes at least one printing unit for printing on a running web, a cutting cylinder for cutting the web into sheets and a folder for folding sheets cut from the web. The folder includes a collect cylinder for accumulating a number of sheets at a collect location, a folding cylinder for folding the accumulated number of sheets received from the collect location to form a folded section, a cam arrangement including a supplementary cam device for controlling the number of sheets collected on the collect cylinder and an actuator for actuating the supplementary cam device. Methods are also provided. | 2013-02-07 |
| 20130032987 | APPARATUS FOR OPENING AND TRANSPORTING A PRODUCT WITH A NON-SYMETRICAL FOLD - A method for transporting newspapers includes the steps of feeding an asymmetrically folded multiple section newspaper into a pocket of a pocket conveyor of an inserting machine, wherein the asymmetrically folded multiple section newspaper has an extended lap having a height of at least 15% of a height of the asymmetrically folded newspaper when unfolded. A face of a first section of the headline side of the newspaper, when fed into the pocket is adjacent a movable wall of the pocket, and a back of a last section of the headline side of the newspaper adjacent a fixed wall of the pocket. The method further comprises feeding one or more inserts from a hopper to the pocket, where the inserts are fed into an opening between newspaper sections, removing the newspapers with the inserts therein from the pocket with a gripper conveyor, and releasing the newspapers with the inserts from the gripper conveyor headline up on a lapped stream conveyor. | 2013-02-07 |
| 20130032988 | SHEET STACKING APPARATUS - When information about weight of a sheet indicates weight less than a predetermined weight, a sheet stacking apparatus configured to align sheets to be stacked on a stacking tray discharges the sheet onto the stacking tray while overlapping the sheet with another sheet by an overlapping unit, and, when the information about the weight of the sheet indicates weight not less than the predetermined weight, the sheet stacking apparatus discharges the sheet onto the stacking tray without overlapping the sheet with another sheet by the overlapping unit. | 2013-02-07 |
| 20130032989 | Sheet Stackable Devices - A sheet stackable device includes a sheet stackable plane. The sheet stackable device includes a first tray and a second tray, each of which is formed in a shape of a flat plate. The first tray includes a first contact part. The second tray is slidable along a slidable direction between a first position, in which the second tray overlaps the first tray, and a second position, in which the second tray is dawn out of the first tray. The second tray includes a second contact part, which is slidable on the first contact part. At least one of the first contact part and the second contact part includes a rack with rack teeth, which are aligned along the slidable direction. An upper plane of the first tray and an upper plane of the second tray in the second position form at least a part of the stackable plane. | 2013-02-07 |
| 20130032990 | IMAGE FORMING SYSTEM AND SHEET CONVEYANCE METHOD - An n image forming system includes an image forming apparatus, a sheet processing apparatus including a post-processing unit to perform post-processing of sheets on a processing tray and a retaining channel disposed to accommodate at least a single sheet while the post-processing unit processes the sheets, and a controller that calculates a target interval time between an interval start sheet and an interval end sheet among the sheets output from the image forming apparatus to the sheet processing apparatus based on at least one of sheet data and post-processing data transmitted from the image forming apparatus to the sheet processing apparatus, and adjusts an interval between discharge of the interval start sheet and the interval end sheet from the image forming apparatus to the sheet processing apparatus in accordance with the target interval time. | 2013-02-07 |
| 20130032991 | SHEET STACKING APPARATUS - A sheet stacking apparatus includes an alignment unit configured to align a sheet stacked on a stacking tray in a width direction which is orthogonal to a direction in which the sheet is discharged. The alignment unit includes first and second alignment members configured to move in the width direction. The first and second alignment members come into contact with side ends in the width direction of the sheet stacked on the stacking tray to align the sheet. When a second sheet of a different length in the width direction from that of a first sheet is stacked while shifted in the width direction on the first sheet which is already stacked on the stacking tray, the sheet stacking apparatus prohibits an alignment operation of the alignment unit on the second sheet. | 2013-02-07 |
