06th week of 2013 patent applcation highlights part 12 |
Patent application number | Title | Published |
20130032792 | Suspension or Solution for Organic Optoelectronic Device, Making Method thereof, and Applications - A suspension or solution for organic optoelectronic device is disclosed in this invention. The composition of the suspension or solution includes at least one kind of micro/nano transition metal oxide and a solvent. The composition of the suspension or solution can selectively include at least one kind of transition metal oxide ions or a precursor of transition metal oxide. Moreover, the making method and applications of the suspension or solution is also disclosed in this invention. | 2013-02-07 |
20130032793 | THIN FILM TRANSISTOR ARRAY PANEL AND MANUFACTURING METHOD THEREOF - Provided is a thin film transistor array panel. The thin film transistor array panel according to exemplary embodiments of the present invention includes: a gate wiring layer disposed on a substrate; an oxide semiconductor layer disposed on the gate wiring layer; and a data wiring layer disposed on the oxide semiconductor layer, in which the data wiring layer includes a main wiring layer including copper and a capping layer disposed on the main wiring layer and including a copper alloy. | 2013-02-07 |
20130032794 | THIN FILM TRANSISTOR AND THIN FILM TRANSISTOR ARRAY PANEL - Provided is a thin film transistor and thin film transistor panel array. The thin film transistor includes: a substrate; a gate electrode disposed on the substrate; a semiconductor layer disposed on the substrate and partially overlapping with the gate electrode; a source electrode and a drain electrode spaced apart from each other with respect to a channel region of the semiconductor layer; an insulating layer disposed between the gate electrode and the semiconductor layer; and a barrier layer disposed between the semiconductor layer and the source electrode and between the semiconductor layer and the drain electrode, in which the barrier layer comprises graphene. An ohmic contact is provided based on the type of material used for the semiconductor layer. | 2013-02-07 |
20130032795 | SEMICONDUCTOR DEVICE - The invention is to provide a structure of a semiconductor device which achieves quick response and high-speed drive by improving on-state characteristics of a transistor, and to provide a highly reliable semiconductor device. In a transistor in which a semiconductor layer, a source and drain electrode layers, a gate insulating film, and a gate electrode are sequentially stacked, a non-single-crystal oxide semiconductor layer containing at least indium, a Group | 2013-02-07 |
20130032796 | SELF-ALIGNED METAL OXIDE TFT WITH REDUCED NUMBER OF MASKS - A method of fabricating MOTFTs on transparent substrates by positioning opaque gate metal on the substrate front surface and depositing gate dielectric material overlying the gate metal and a surrounding area and metal oxide semiconductor material on the dielectric material. Depositing selectively removable etch stop material on the semiconductor material and photoresist on the etch stop material to define an isolation area in the semiconductor material. Removing uncovered portions of the etch stop. Exposing the photoresist from the substrate rear surface using the gate metal as a mask and removing exposed portions leaving the etch stop material overlying the gate metal covered. Etching the semiconductor material to isolate the TFT. Selectively etching the etch stop layer to leave a portion overlying the gate metal defining a channel area. Depositing and patterning conductive material to form source and drain areas on opposed sides of the channel area. | 2013-02-07 |
20130032797 | FIELD-EFFECT TRANSISTOR AND METHOD FOR MANUFACTURING THE SAME - The present invention achieves a formation of a metal oxide film of a thin film transistor with a simplified process. The present invention is concerned with a method for manufacturing a field-effect transistor comprising a gate electrode, a source electrode, a drain electrode, a channel layer and a gate insulating layer wherein the channel layer is formed by using a metal salt-containing composition comprising a metal salt, a polyvalent carboxylic acid having a cis-form structure of —C(COOH)═C(COOH)—, an organic solvent and a water wherein a molar ratio of the polyvalent carboxylic acid to the metal salt is in the range of 0.5 to 4.0. | 2013-02-07 |
20130032798 | OXIDE FOR SEMICONDUCTOR LAYER OF THIN-FILM TRANSISTOR, SPUTTERING TARGET, AND THIN-FILM TRANSISTOR - Disclosed is an oxide for a semiconductor layer of a thin-film transistor, said oxide being excellent in the switching characteristics of a thin-film transistor, specifically enabling favorable characteristics to be stably obtained even in a region of which the ZnO concentration is high and even after forming a passivation layer and after applying stress. The oxide is used in a semiconductor layer of a thin-film transistor, and the aforementioned oxide contains Zn and Sn, and further contains at least one element selected from group X consisting of Al, Hf, Ta, Ti, Nb, Mg, Ga, and the rare-earth elements. | 2013-02-07 |
20130032799 | Apparatus and Methods for De-Embedding Through Substrate Vias - A method includes providing on a substrate having at least two through substrate vias (“TSVs”) a plurality of test structures for de-embedding the measurement of the intrinsic characteristics of a device under test (DUT) including at least two of the TSVs; measuring the intrinsic characteristics [L] for a first and a second test structure on the substrate including two pads coupled with a transmission line of length L; using simultaneous solutions of ABCD matrix or T matrix form equations, and the measured intrinsic characteristics, solving for the intrinsic characteristics of the pads and the transmission lines; de-embedding the measurements of the third and fourth test structures using the intrinsic characteristics of the pads and the transmission lines; and using simultaneous solutions of ABCD matrix or T matrix form equations for BM_L and BM_LX, and the measured intrinsic characteristics, solving for the intrinsic characteristics of the TSVs. | 2013-02-07 |
20130032800 | SEMICONDUCTOR DEVICE - A semiconductor device includes a circuit board including a ground portion, and a semiconductor package disposed on the circuit board. The semiconductor package includes an external connecting pad and an exposed pad. The exposed pad and the ground portion are electrically connected at a first surface of the exposed pad. A semiconductor chip is disposed on a second surface of the exposed pad and electrically connected to the external connecting pad. The first surface of the exposed pad is located external to the semiconductor package, and the second surface of the exposed pad is located within the semiconductor package. A test pad is disposed on the semiconductor chip and is electrically connected to the exposed pad. | 2013-02-07 |
20130032801 | ELECTRONIC DEVICE AND METHOD FOR MANUFACTURING SAME - The electronic device includes a substrate, a first electrode formed over a surface of the substrate, a second electrode located on an opposite side of the first electrode from the substrate so as to face the first electrode, and a functional layer interposed between the first electrode and second electrode and formed by means of anodizing a first polycrystalline semiconductor layer in an electrolysis solution so as to contain a plurality of semiconductor nanocrystals. The electronic device further includes a second polycrystalline semiconductor layer interposed between the first electrode and the functional layer so as to be in close contact with the functional layer. The second polycrystalline semiconductor layer has an anodic oxidization rate in the electrolysis solution lower than that of the first polycrystalline semiconductor layer so as to function as a stop layer for exclusively anodizing the first polycrystalline semiconductor layer. | 2013-02-07 |
20130032802 | THIN-FILM TRANSISTOR ARRAY SUBSTRATE, ORGANIC LIGHT-EMITTING DISPLAY HAVING THE SAME, AND METHOD OF MANUFACTURING THE ORGANIC LIGHT-EMITTING DISPLAY - A thin-film transistor array substrate, an organic light-emitting display having the same, and a method of manufacturing the organic light-emitting display are disclosed. In one embodiment, the thin-film transistor array substrate includes a buffer layer formed on a substrate, a first insulating layer formed on the buffer layer, a pixel electrode formed on the first insulating layer using a transparent conductive material, an intermediate layer that covers an upper side and outer side-surfaces of the pixel electrode and includes a organic light-emitting layer, a gap formed by etching the first insulating layer and the buffer layer at a peripheral of the pixel electrode, and a facing electrode that is formed on an upper side and outer side-surfaces of the pixel electrode to cover the intermediate layer and the gap. | 2013-02-07 |
20130032803 | ORGANIC LIGHT-EMITTING DISPLAY DEVICE AND METHOD OF MANUFACTURING THE SAME - An OLED device includes an active layer on a substrate; a first insulating layer covering the active layer, and including a first opening and a first insulation island in the first opening, separated from an inner surface of the first opening; a gate electrode on the first insulating layer including gate bottom and top electrodes; a pixel electrode on the first insulation island on the same layer as the gate bottom electrode; source and drain electrodes insulated from the gate electrode and electrically connected to the active layer; a second insulating layer between the gate and the source and drain electrodes, and including a second opening exposing the pixel electrode; a light-reflecting portion in the openings, and surrounding the pixel electrode; an intermediate layer on the pixel electrode and including an organic emissive layer; and an opposite electrode facing the pixel electrode with the intermediate layer interposed between them. | 2013-02-07 |
20130032804 | THIN-FILM TRANSISTOR ARRAY SUBSTRATE, ORGANIC LIGHT-EMITTING DISPLAY DEVICE COMPRISING THE THIN-FILM TRANSISTOR ARRAY SUBSTRATE, AND METHOD OF MANUFACTURING THE THIN-FILM TRANSISTOR ARRAY SUBSTRATE - A thin-film transistor (TFT) array substrate includes an active layer on a substrate and a lower electrode of a capacitor on the same level as the active layer, a first insulation layer on the active layer and the lower electrode and having a first gap exposing an area of the lower electrode; a gate electrode of the TFT on the first insulation layer, and an upper electrode of the capacitor on the lower electrode and the first insulation layer, the upper electrode having a second gap that exposes the first gap and a portion of the first insulation layer; a second insulation layer disposed between the gate electrode and source electrode and drain electrodes, and not disposed on the upper electrode, in the first gap of the first insulation layer, or in the second gap of the lower electrode. | 2013-02-07 |
20130032805 | THIN FILM TRANSISTOR ARRAY SUBSTRATE, ORGANIC LIGHT EMITTING DISPLAY DEVICE INCLUDING THE SAME, AND MANUFACTURING METHOD OF THE THIN FILM TRANSISTOR ARRAY SUBSTRATE - A thin film transistor array substrate includes a thin film transistor on a substrate, the thin film transistor including an active layer, a gate electrode, a source electrode, and a drain electrode; a capacitor including a lower electrode in a same layer as the active layer and an upper electrode in a same layer as the gate electrode; a pixel electrode in a same layer as the gate electrode and the upper electrode; a first insulation layer between the active layer and the gate electrode and between the lower electrode and the upper electrode; a second insulation layer on the first insulation layer, a protection layer extending along side surfaces of the lower electrode, and a third insulation layer on the protection layer and exposing the pixel electrode. | 2013-02-07 |
20130032806 | SEMICONDUCTOR DEVICE - Adverse effects of variation in threshold voltage are reduced. In a semiconductor device, electric charge is accumulated in a capacitor provided between a gate and a source of a transistor, and then, the electric charge accumulated in the capacitor is discharged; thus, the threshold voltage of the transistor is obtained. After that, current flows to a load. In the semiconductor device, the potential of one terminal of the capacitor is set higher than the potential of a source line, and the potential of the source line is set lower than the potential of a power supply line and the cathode side potential of the load. | 2013-02-07 |
20130032807 | CIRCUIT BOARD, METHOD OF MANUFACTURING CIRCUIT BOARD, DISPLAY, AND ELECTRONIC UNIT - A circuit board includes: a first wiring layer provided on a substrate; an insulating layer including an opening, the insulating layer being provided on the first wiring layer; a surface-energy control layer provided in a region opposed to the opening of the insulating layer on the first wiring layer, the surface-energy control layer controlling surface energy of the first wiring layer; a semiconductor layer provided in a selective region on the insulating layer; and a second wiring layer on the insulating layer, the second wiring layer being electrically connected to the semiconductor layer, and being electrically connected to the first wiring layer through the opening. | 2013-02-07 |
20130032808 | DISPLAY DEVICE - A display device having a first pixel electrode and a second pixel electrode whose areas are different from each other is provided. In the display device, the first pixel electrode and the second pixel electrode are electrically connected to a first transistor and a second transistor, respectively. Gates of the first transistor and the second transistor are electrically connected to each other. A potential is supplied to the first pixel electrode and the second pixel electrode through a wiring electrically connected to the first transistor and the second transistor. | 2013-02-07 |
20130032809 | Semiconductor Devices with Non-Implanted Barrier Regions and Methods of Fabricating Same - An electronic device includes a silicon carbide layer including an n-type drift region therein, a contact forming a Schottky junction with the drift region, and a p-type junction barrier region on the silicon carbide layer. The p-type junction barrier region includes a p-type polysilicon region forming a P-N heterojunction with the drift region, and the p-type junction barrier region is electrically connected to the contact. | 2013-02-07 |
20130032810 | LED ON SILICON SUBSTRATE USING ZINC-SULFIDE AS BUFFER LAYER - A vertical GaN-based blue LED has an n-type GaN layer that was grown over a ZnS layer that in turn was grown directly on a silicon substrate. In one example, the ZnS layer is a transitional buffer layer that is 50 nm thick, and the n-type GaN layer is at least 2000 nm thick. Growing the n-type GaN layer on the ZnS buffer layer reduces lattice defect density in the n-type layer. The ZnS buffer layer provides a good lattice constant match with the silicon substrate and provides a compound polar template for subsequent GaN growth. After the epitaxial layers of the LED are formed, a conductive carrier is wafer bonded to the structure. The silicon substrate and the ZnS buffer layer are then removed. Electrodes are added and the structure is singulated to form finished LED devices. | 2013-02-07 |
20130032811 | METHOD AND SYSTEM FOR A GAN VERTICAL JFET UTILIZING A REGROWN GATE - A vertical III-nitride field effect transistor includes a drain comprising a first III-nitride material, a drain contact electrically coupled to the drain, and a drift region comprising a second III-nitride material coupled to the drain and disposed adjacent to the drain along a vertical direction. The field effect transistor also includes a channel region comprising a third III-nitride material coupled to the drift region, a gate region at least partially surrounding the channel region, and a gate contact electrically coupled to the gate region. The field effect transistor further includes a source coupled to the channel region and a source contact electrically coupled to the source. The channel region is disposed between the drain and the source along the vertical direction such that current flow during operation of the vertical III-nitride field effect transistor is along the vertical direction. | 2013-02-07 |
20130032812 | METHOD AND SYSTEM FOR A GAN VERTICAL JFET UTILIZING A REGROWN CHANNEL - A vertical III-nitride field effect transistor includes a drain comprising a first III-nitride material, a drain contact electrically coupled to the drain, and a drift region comprising a second III-nitride material coupled to the drain. The field effect transistor also includes a channel region comprising a third III-nitride material coupled to the drain and disposed adjacent to the drain along a vertical direction, a gate region at least partially surrounding the channel region, having a first surface coupled to the drift region and a second surface on a side of the gate region opposing the first surface, and a gate contact electrically coupled to the gate region. The field effect transistor further includes a source coupled to the channel region and a source contact electrically coupled to the source. The channel region is disposed between the drain and the source along the vertical direction such that current flow during operation of the vertical III-nitride field effect transistor is along the vertical direction, and the channel region extends along at least a portion of the second surface of the gate region. | 2013-02-07 |
20130032813 | METHOD AND SYSTEM FOR DOPING CONTROL IN GALLIUM NITRIDE BASED DEVICES - A method of growing a III-nitride-based epitaxial structure includes providing a substrate in an epitaxial growth reactor and heating the substrate to a predetermined temperature. The method also includes flowing a gallium-containing gas into the epitaxial growth reactor and flowing a nitrogen-containing gas into the epitaxial growth reactor. The method further includes flowing a gettering gas into the epitaxial growth reactor. The predetermined temperature is greater than 1000° C. | 2013-02-07 |
20130032814 | METHOD AND SYSTEM FOR FORMATION OF P-N JUNCTIONS IN GALLIUM NITRIDE BASED ELECTRONICS - A semiconductor device includes a III-nitride substrate having a first conductivity type and a first electrode electrically coupled to the III-nitride substrate. The semiconductor device also includes a III-nitride material having a second conductivity type coupled to the III-nitride substrate at a regrowth interface and a p-n junction disposed between the III-nitride substrate and the regrowth interface. | 2013-02-07 |
20130032815 | LIGHT EMITTING DIODE ARRAY AND METHOD FOR MANUFACTURING THE SAME - An LED array includes a substrate, protrusions formed on a top surface of the substrate, and LEDs formed on the top surface of the substrate and located at a top of the protrusions. The LEDs are electrically connected with each other. Each LED includes a connecting layer, an n-type GaN layer, an active layer, and a p-type GaN layer formed on a top of the protrusions in sequence. A bottom surface of the n-type GaN layer connecting the connecting layer has a roughened exposed portion. The bottom surface of the n-type GaN layer has an N-face polarity. | 2013-02-07 |
20130032816 | HIGH ELECTRON MOBILITY TRANSISTORS AND METHODS OF MANUFACTURING THE SAME - High electron mobility transistors (HEMTs) including a substrate and a HEMT stack on the substrate, the HEMT stack including a compound semiconductor layer that includes a 2-dimensional electron gas (2DEG), an upper compound semiconductor layer that has a polarization index higher than a polarization index of the compound semiconductor layer, and a source electrode, a drain electrode, and a gate that are disposed on the upper compound semiconductor layer. The substrate may be a nitride substrate that has a dielectric constant and a thermal conductivity higher than a dielectric constant and a thermal conductivity of a silicon substrate. The substrate may include an insulating layer that has a dielectric constant and a thermal conductivity higher than a dielectric constant and a thermal conductivity of the silicon substrate, a metal layer that is deposited on the insulating layer, and a plate that is attached to the metal layer. | 2013-02-07 |
20130032817 | POWER AMPLIFIER - A power amplifier includes a semiconductor substrate including transistor cells, a drain electrode for the transistor cells located on the semiconductor substrate, a drain pad located on the semiconductor substrate and connected to the drain electrode, an ion-implanted resistance located in the semiconductor substrate and extending along and in contact with the drain pad, a floating electrode located on the semiconductor substrate and in contact with the ion-implanted resistance, and an output matching circuit located outside the semiconductor substrate. The power amplifier further includes a wire connecting the drain pad to the output matching circuit. | 2013-02-07 |
20130032818 | SEMICONDUCTOR DEVICE AND METHOD FOR MANUFACTURING SEMICONDUCTOR DEVICE - A semiconductor device includes a buffer layer that is disposed over a substrate, a high-resistance layer that is disposed over the buffer layer, the high-resistance layer being doped with a transition metal for achieving high resistance, a low-resistance region that is disposed in a portion of the high-resistance layer or over the high-resistance layer, the low-resistance region being doped with an impurity element for achieving low resistance, an electron travel layer that is disposed over the high-resistance layer including the low-resistance region, an electron supply layer that is disposed over the electron travel layer, a gate electrode that is disposed over the electron supply layer, and a source electrode and a drain electrode that are disposed over the electron supply layer. | 2013-02-07 |
20130032819 | SEMICONDUCTOR TRANSISTOR - The semiconductor transistor according the present invention includes an active layer composed of a GaN-based semiconductor and a gate insulating film formed on the active layer. The gate insulating film has a first insulating film including one or more compounds selected from the group consisting of Al | 2013-02-07 |
20130032820 | Optoelectronic Component and Method for Producing an Optoelectronic Component - The invention concerns an optoelectronic component ( | 2013-02-07 |
20130032821 | SCHOTTKY BARRIER DIODE AND METHOD FOR MANUFACTURING THE SAME - A Schottky barrier diode (SBD) is provided, which improves electrical characteristics and optical characteristics by securing high crystallinity by including an n-gallium nitride (GaN) layer and a GaN layer which are doped with aluminum (Al). In addition, by providing a p-GaN layer on the Al-doped GaN layer, a depletion layer may be formed when a reverse current is applied, thereby reducing a leakage current. The SBD may be manufactured by etching a part of the Al-doped GaN layer and growing a p-GaN layer from the etched part of the Al-doped GaN layer. Therefore, a thin film crystal is not damaged, thereby increasing reliability. Also, since dedicated processes for ion implantation and thermal processing are not necessary, simplified process and reduced cost may be achieved. | 2013-02-07 |
20130032822 | SUBSTRATE, SEMICONDUCTOR DEVICE, AND METHOD OF MANUFACTURING THE SAME - A substrate capable of achieving a lowered probability of defects produced in a step of forming an epitaxial film or a semiconductor element, a semiconductor device including the substrate, and a method of manufacturing a semiconductor device are provided. A substrate is a substrate having a front surface and a back surface, in which at least a part of the front surface is composed of single crystal silicon carbide, the substrate having an average value of surface roughness Ra at the front surface not greater than 0.5 nm, a standard deviation σ of that surface roughness Ra not greater than 0.2 nm, an average value of surface roughness Ra at the back surface not smaller than 0.3 nm and not greater than 10 nm, standard deviation σ of that surface roughness Ra not greater than 3 nm, and a diameter D of the front surface not smaller than 110 mm. | 2013-02-07 |
20130032823 | SILICON CARBIDE SEMICONDUCTOR DEVICE - A first layer has a first conductivity type. A second layer is provided on the first layer such that a part of the first layer is exposed, and it has a second conductivity type. First to third impurity regions penetrate the second layer and reach the first layer. Each of the first and second impurity regions has the first conductivity type. | 2013-02-07 |
20130032824 | SILICON CARBIDE SEMICONDUCTOR DEVICE - First, second, fourth, and fifth impurity regions have a first conductivity type, and a third impurity region has a second conductivity type. The first to third impurity regions reach a first layer having the first conductivity type. The fourth and fifth impurity regions are provided on a second layer. First to fifth electrodes are provided on the first to fifth impurity regions, respectively. Electrical connection is established between the first and fifth electrodes, and between the third and fourth electrodes. A sixth electrode is provided on a gate insulating film covering a portion between the fourth and fifth impurity regions. | 2013-02-07 |
20130032825 | Resonant Optical Cavity Semiconductor Light Emitting Device - The present invention is a light emitting device apparatus and method of fabrication. The structure employs a waveguide in the lateral (x) direction formed via materials index, resonant wavelength and/or current-induced index changes. In the vertical (y) direction a resonant optical cavity is formed via distributed Bragg reflector and/or metal mirrors with sufficient reflectivity so as to create a substantial standing wave. The light is thereby constricted to propagate in the longitudinal (z) direction. A tapered output section may be employed to suppress lasing in the longitudinal direction or to losslessly transfer the light from the confined section to a resonant output coupler. Conversely, feedback may be employed to induce lasing in the longitudinal direction by suitable means, such as a periodic variation in the material index, resonant wavelength, gain or loss. The resonant output coupler may be formed by suitable means, such as mirror or cavity modulation. | 2013-02-07 |
20130032826 | Integrated Apparatus Including Driver Chips, a Power Supply and LED Chips on an Isolative Substrate - Disclosed is an integrated apparatus including an isolative substrate, a plurality of driver chips provided on a side of the isolative substrate, a power supply provided on the side of the isolative substrate and electrically connected to the driver chips, and LED chips provided on another side of the isolative substrate and electrically connected to the driver chips. Thus, the driver chips, the power supply and the LED chips are integrated on the isolative substrate. The production is easy. The integrated apparatus is not vulnerable to surges and lightning strikes. Electromagnetic interferences are reduced. Heat radiation of the integrated apparatus is excellent so that the LED chips are protected from thermal effect. | 2013-02-07 |
20130032827 | DISPLAY SUBSTRATE, METHOD OF MANUFACTURING A DISPLAY SUBSTRATE AND LIQUID CRYSTAL DISPLAY DEVICE HAVING A DISPLAY SUBSTRATE - A display substrate for a display device includes a substrate, a switching device, a gate line, a data line, a pixel electrode, a plurality of common electrodes. The switching device includes an active pattern, a gate insulation layer, a gate electrode, a source electrode and a drain electrode. The gate line is electrically connected to the source electrode, and the data line is electrically coupled to the gate electrode. The pixel electrode is electrically connected to the drain electrode, and the common electrodes are disposed on the pixel electrode. A coupling capacitance among the common electrodes and the data line can be prevented and/or reduced to prevent a signal delay of the data line. Further, an aperture ratio of the display substrate can be improved by changing a layout of the data line and the gate line. | 2013-02-07 |
20130032828 | LED LIGHT STRIP MODULE STRUCTURE - A LED light strip module structure includes a substrate and LED dies. The substrate has first and second surfaces. Accommodating cavities are formed on the first surface and extend toward the second surface. Each accommodating cavity has a bottom surface. Bonding metal layers are respectively attached to the bottom surfaces of the accommodating cavities. The LED die includes a crystal layer and a combination metal layer combined together. The LED dies are disposed in the accommodating cavities, respectively, so that the combination metal layer and the bonding metal layer form eutectic bonding. In addition, a diamond film layer may be disposed between the crystal layer and the combination metal layer, so that the LED die and the substrate can possess the stable and secure positioning effect and the thermoconductive speed and effect can be enhanced to lengthen the lifetime of the LED die through the diamond film layer. | 2013-02-07 |
20130032829 | DEPOSITION SOURCE ASSEMBLY, ORGANIC LAYER DEPOSITION APPARATUS, AND METHOD OF MANUFACTURING ORGANIC LIGHT-EMITTING DISPLAY APPARATUS BY USING THE ORGANIC LAYER DEPOSITION APPARATUS - An organic layer deposition apparatus, and a method of manufacturing an organic light-emitting display device by using the organic layer deposition apparatus. Here, the organic layer deposition apparatus includes a deposition source assembly. The deposition source assembly includes a first deposition source for discharging a deposition material, a second deposition material stacked on the first deposition source and discharging a different deposition material than the deposition material discharged from the first deposition source, a second deposition source nozzle unit disposed at a side of the second deposition source to face a deposition target and including a plurality of second deposition source nozzles, and a first deposition source nozzle unit disposed at the side of the second deposition source to face the deposition target and including a plurality of first deposition source nozzles formed to pass through the second deposition source. | 2013-02-07 |
20130032830 | ORGANIC LIGHT EMITTING DISPLAY DEVICE AND METHOD OF MANUFACTURING THE SAME - Discussed are an organic light emitting display device and a method of manufacturing the same in which organic and inorganic films are formed on a polarization plate, and the polarization plate is attached to an organic light emitting panel so that the organic and inorganic films seal the organic light emitting panel, thereby achieving improved polarization and a simple sealing structure. | 2013-02-07 |
20130032831 | ORGANIC LIGHT EMITTING DIODE AND METHOD OF MANUFACTURING - Aspects of the present disclosure provide for manufacturing an organic light emitting diode (OLED) by forming two terminals of the OLED on two substrates of the display, and then depositing a plurality of layers of the OLED on one or both of the two terminals to form a first portion and a second portion of the OLED on each substrate. The two portions are joined together to form an assembled OLED. The deposition of the two portions can be stopped with each portion having approximately half of a common layer exposed. The two portions can then be aligned to be joined together and an annealing process can be employed to join together the two parts of the common layer and thereby form the OLED. | 2013-02-07 |
20130032832 | DISPLAY DEVICE AND METHOD FOR MANUFACTURING DISPLAY DEVICE - A display device includes an electrode layer formed at a predetermined position on a substrate, an insulating film having a through-hole formed on the top of the electrode layer, and a wiring film connected to the electrode layer via the through-hole formed in the insulating film. Based on a surface of the substrate, the through-hole includes a first taper portion having a first taper angle, a second taper portion formed higher than the first taper portion and having a second taper angle different from the first taper angle, and a third taper portion formed higher than the second taper portion and having a third taper angle different from the second taper angle. | 2013-02-07 |
20130032833 | LED MODULE AND LED LAMP HAVING THE LED MODULE - An LED module includes a first dielectric layer, and a first patterned conductive layer having first, second, and third die-bonding pads. Each die-bonding pad includes a pad body having a die-bonding area, and an extension extended from the pad body. The extension of the first die-bonding pad extends in proximity to the die-bonding area of the second die-bonding pad. The extension of the second die-bonding pad extends in proximity to the die-bonding area of the third die-bonding cad. A second dielectric layer disposed on the first patterned conductive layer includes three dielectric members corresponding respectively to the die-bonding pads of the first patterned conductive layer. Each dielectric member includes a chip-receiving hole exposing the die-bonding area of a respective die-bonding pad for attachment of an LED chip thereto, and a wire-passage hole spaced apart from the chip-receiving hole to expose partially the first patterned conductive layer for bonding a wire. | 2013-02-07 |
20130032834 | LED HAVING A LOW DEFECT N-TYPE LAYER THAT HAS GROWN ON A SILICON SUBSTRATE - A vertical GaN-based blue LED has an n-type GaN layer that was grown directly on Low Resistance Layer (LRL) that in turn was grown over a silicon substrate. In one example, the LRL is a low sheet resistance GaN/AlGaN superlattice having periods that are less than 300 nm thick. Growing the n-type GaN layer on the superlattice reduces lattice defect density in the n-type layer. After the epitaxial layers of the LED are formed, a conductive carrier is wafer bonded to the structure. The silicon substrate is then removed. Electrodes are added and the structure is singulated to form finished LED devices. In some examples, some or all of the LRL remains in the completed LED device such that the LRL also serves a current spreading function. In other examples, the LRL is entirely removed so that no portion of the LRL is present in the completed LED device. | 2013-02-07 |
20130032835 | Device with Inverted Large Scale Light Extraction Structures - An interface including roughness components for improving the propagation of radiation through the interface is provided. The interface includes a first profiled surface of a first layer comprising a set of large roughness components providing a first variation of the first profiled surface having a first characteristic scale and a second profiled surface of a second layer comprising a set of small roughness components providing a second variation of the second profiled surface having a second characteristic scale. The first characteristic scale is approximately an order of magnitude larger than the second characteristic scale. The surfaces can be bonded together using a bonding material, and a filler material also can be present in the interface. | 2013-02-07 |
20130032836 | N-TYPE GALLIUM-NITRIDE LAYER HAVING MULTIPLE CONDUCTIVE INTERVENING LAYERS - A vertical GaN-based blue LED has an n-type layer comprising multiple conductive intervening layers. The n-type layer contains a plurality of periods. Each period of the n-type layer includes a gallium-nitride (GaN) sublayer and a thin conductive aluminum-gallium-nitride (AlGaN:Si) intervening sublayer. In one example, each GaN sublayer has a thickness substantially more than 100 nm and less than 1000 nm, and each AlGaN:Si intervening sublayer has a thickness less than 25 nm. The entire n-type layer is at least 2000 nm thick. The AlGaN:Si intervening layer provides compressive strain to the GaN sublayer thereby preventing cracking. After the epitaxial layers of the LED are formed, a conductive carrier is wafer bonded to the structure. The silicon substrate is then removed. Electrodes are added and the structure is singulated to form a finished LED device. Because the AlGaN:Si sublayers are conductive, the entire n-type layer can remain as part of the finished LED device. | 2013-02-07 |
20130032837 | Fluorescent Coating and a Method for Making the Same - Disclosed is a fluorescent coating and a method for making the same. At first, fluorescent powder is mixed with an anti-electrostatic solution. The mixture is cleared of impurities before it is dried and sintered. Thus, the fluorescent powder is coated with the anti-electrostatic material. The fluorescent powder coated with the anti-electrostatic material is plated on a side of a light-emitting diode (“LED”) chip by electrophoresis, thus forming a mixing zone on the side of the LED chip. Hence, the mixing zone is not vulnerable to deterioration or itiolation when it is subjected to heat in use. Accordingly, the life of the LED chip is long, and the illumination of the LED chip is high. | 2013-02-07 |
20130032838 | SEMICONDUCTOR LIGHT EMITTING DEVICE - According to one embodiment, a semiconductor light emitting device having a base, a mounting material and a chip of a semiconductor light emitting element is provided. The mounting material is provided on the base. The chip of the semiconductor light emitting element is fixed onto the base via the mounting material. The chip of the semiconductor light emitting element is provided with a sapphire substrate, an active region, a light shielding portion and anode and cathode electrodes for supplying an electric power to the active region. The active region is provided on the sapphire substrate and has a light emitting layer for emitting light by supplying electric power. The light shielding portion is formed on the sapphire substrate on the side of the mounting material. The light shielding portion prevents the mounting material from being irradiated with the light produced in the light emitting layer. | 2013-02-07 |
20130032839 | LIGHT EMITTING DIODE AND MANUFACTURING METHOD THEREOF - A manufacturing method for an LED with roughened lateral surfaces comprises following steps: providing an LED wafer with an electrically conductive layer disposed thereon; providing a photoresist layer on the electrically conductive layer; roughening a lateral surface of the electrically conductive layer by wet etching; forming a depression in the LED wafer by dry etching and roughening a sidewall of the LED wafer defining the depression; and disposing two pads respectively in the depression and the conducting layer. The disclosure also provides an LED with roughened lateral surfaces. A roughness of the roughened lateral surfaces is measurable in micrometers. | 2013-02-07 |
20130032840 | ORGANIC LIGHT EMITTING DEVICES - Organic light emitting devices are provided. The organic light emitting device may include a substrate having a first refractive index, a first electrode on the substrate, a second electrode disposed between the substrate and the first electrode and having a thickness equal to or greater than one-hundredth of a minimum wavelength of visible light and equal to or smaller than five-hundredths of a maximum wavelength of the visible light, and an organic light emitting layer disposed between the first and second electrodes and having a second refractive index. | 2013-02-07 |
20130032841 | Light-Emitting Device and Lighting Device - A light-emitting device which has various emission colors and can be manufactured efficiently and easily is provided. A first conductive layer formed of a semi-transmissive and semi-reflective conductive film is provided in a first light-emitting element region, so that the intensity of light in a specific wavelength region is increased with a cavity effect. As a result, the light-emitting device as a whole can emit desired light. When the first conductive layer is formed using a material with low electric resistance, voltage drop in a transparent conductive layer in the light-emitting device can be prevented. Accordingly, a light-emitting device with less emission unevenness can be manufactured. By applying such a structure to a white-light-emitting device, desired white light emission or white light emission with an excellent color rendering property can be obtained. Further, a large-area lighting device including a white-light-emitting device with less emission unevenness can be provided. | 2013-02-07 |
20130032842 | LIGHT EMITTING DEVICE PACKAGE AND METHOD OF MANUFACTURING THE SAME - There are provided a light emitting device package and a method of manufacturing the same. The light emitting device package includes a body part including a through hole formed in a thickness direction; at least one light emitting device disposed within the through hole; and a wavelength conversion part filling the through hole and supporting the light emitting device. | 2013-02-07 |
20130032843 | LIGHT EMITTING DIODE PACKAGE AND MANUFACTURING METHOD THEREOF - A light emitting diode (LED) package and a manufacturing method thereof are provided. The LED package includes a substrate including a circuit layer, an LED mounted on the substrate, and a plurality of protruded reflection units disposed in a region excluding an LED mounting region on the substrate and configured to reflect light generated from the LED. | 2013-02-07 |
20130032844 | LIGHT EMITTING PACKAGE - The present invention discloses a light emitting package, comprising: a base; a light emitting device on the base; an electrical circuit layer electrically connected to the light emitting device; a gold layer on the electrical circuit layer; a wire electrically connected between the light emitting device and the gold layer; a screen member having an opening and disposed on the base adjacent to the light emitting device; and a lens covering the light emitting device, wherein a cross-sectional shape of the screen member is substantially rectangular, and a width of the cross-sectional shape of the screen member being larger than a height of the cross sectional shape of the screen member, wherein a bottom surface of the screen member is positioned higher than the light emitting device, and wherein an entire uppermost surface of the screen member is in contact with the lens. | 2013-02-07 |
20130032845 | HIGH TEMPERATURE GOLD-FREE WAFER BONDING FOR LIGHT EMITTING DIODES - A vertical GaN-based LED is made by growing an epitaxial LED structure on a silicon wafer. A silver layer is added and annealed to withstand >450° C. temperatures. A barrier layer (e.g., Ni/Ti) is provided that is effective for five minutes at >450° C. at preventing bond metal from diffusing into the silver. The resulting device wafer structure is then wafer bonded to a carrier wafer structure using a high temperature bond metal (e.g., AlGe) that melts at >380° C. After wafer bonding, the silicon is removed, gold-free electrodes (e.g., Al) are added, and the structure is singulated. High temperature solder (e.g., ZnAl) that is compatible with the electrode metal is used for die attach. Die attach occurs at >380° C. for ten seconds without melting the bond metal or otherwise damaging the device. The entire LED contains no gold, and consequently is manufacturable in a high-volume gold-free semiconductor fabrication facility. | 2013-02-07 |
20130032846 | NON-REACTIVE BARRIER METAL FOR EUTECTIC BONDING PROCESS - A eutectic metal layer (e.g., gold/tin) bonds a carrier wafer structure to a device wafer structure. In one example, the device wafer structure includes a silicon substrate upon which an epitaxial LED structure is disposed. A layer of silver is disposed on the epitaxial LED structure. The carrier wafer structure includes a conductive silicon substrate covered with an adhesion layer. A layer of non-reactive barrier metal (e.g., titanium) is provided between the silver layer and the eutectic metal to prevent metal from the eutectic layer (e.g., tin) from diffusing into the silver during wafer bonding. During wafer bonding, the wafer structures are pressed together and maintained at more than 280° C. for more than one minute. Use of the non-reactive barrier metal layer allows the total amount of expensive platinum used in the manufacture of a vertical blue LED manufactured on silicon to be reduced, thereby reducing LED manufacturing cost. | 2013-02-07 |
20130032847 | DISTRIBUTED CURRENT BLOCKING STRUCTURES FOR LIGHT EMITTING DIODES - An LED device includes a strip-shaped electrode, a strip-shaped current blocking structure and a plurality of distributed current blocking structures. The current blocking structures are formed of an insulating material such as silicon dioxide. The strip-shaped current blocking structure is located directly underneath the strip-shaped electrode. The plurality of current blocking structures may be disc shaped portions disposed in rows adjacent the strip-shaped current blocking structure. Distribution of the current blocking structures is such that current is prevented from concentrating in regions immediately adjacent the electrode, thereby facilitating uniform current flow into the active layer and facilitating uniform light generation in areas not underneath the electrode. In another aspect, current blocking structures are created by damaging regions of a p-GaN layer to form resistive regions. In yet another aspect, current blocking structures are created by etching away highly doped contact regions to form regions of resistive contact between conductive layers. | 2013-02-07 |
20130032848 | OPTOELECTRONIC DEVICE AND METHOD FOR MANUFACTURING THE SAME - An optoelectronic device comprises a semiconductor stack comprising a first semiconductor layer, an active layer and a second semiconductor layer, a first electrode electrically connecting with the first semiconductor layer, a second electrode electrically connecting with the second semiconductor layer, wherein there is a smallest distance D | 2013-02-07 |
20130032849 | LIGHT EMITTING DEVICES - Light-emitting devices are provided, the light-emitting devices include a light-emitting structure layer having a first conductive layer, a light-emitting layer and a second conductive layer sequentially stacked on a first of a substrate, a plurality of seed layer patterns formed apart each other in the first conductive layer; and a plurality of first electrodes formed through the substrate, wherein each of the first electrodes extends from a second side of the substrate to each of the seed layer patterns. | 2013-02-07 |
20130032850 | Light-Emitting Diode Mounted On Transparent Conductive Layers And Manufacturing Method Thereof - A light-emitting diode (LED) and manufacturing method thereof are disclosed. The LED includes a transparent substrate, a plurality of transparent conductive layers, a plurality of metal circuits, and a LED chip. The LED chip is suitable for emitting a light and a portion of the light emits toward the transparent substrate. The manufacturing method of LED includes the following steps. First, a transparent conductive layer is formed on the transparent substrate. Next, a conductive pattern is formed by etching transparent conductive layer. The intersection metal circuit is formed by disposing the metal on a portion of the transparent conductive layer. Finally, the LED chip is disposed on the metal circuit so that the LED chip is electrically connected to the metal circuit. | 2013-02-07 |
20130032851 | OPTOELECTRONIC ARCHITECTURE HAVING COMPOUND CONDUCTING SUBSTRATE - Optoelectronic device modules, arrays optoelectronic device modules and methods for fabricating optoelectronic device modules are disclosed. The device modules are made using a starting substrate having an insulator layer sandwiched between a bottom electrode made of a flexible bulk conductor and a conductive back plane. An active layer is disposed between the bottom electrode and a transparent conducting layer. One or more electrical contacts between the transparent conducting layer and the back plane are formed through the transparent conducting layer, the active layer, the flexible bulk conductor and the insulating layer. The electrical contacts are electrically isolated from the active layer, the bottom electrode and the insulating layer. | 2013-02-07 |
20130032852 | SILICONE RESIN COMPOSITION, ENCAPSULATING MATERIAL, AND LIGHT EMITTING DIODE DEVICE - A silicone resin composition contains a silicon-containing component including a silicon atom to which a monovalent hydrocarbon group selected from a saturated hydrocarbon group and an aromatic hydrocarbon group is bonded and a silicon atom to which an alkenyl group is bonded. The number of moles of alkenyl group per 1 g of the silicon-containing component is 200 to 2000 μmol/g. | 2013-02-07 |
20130032853 | Silver Anti-Tarnishing Agent, Silver Anti-Tarnishing Resin Composition, Silver Anti-Tarnishing Method, And Light-Emitting Diode Using Same - The present invention relates to a silver anti-tarnish agent having, as an effective component, a zinc salt and/or a zinc complex, preferably at least one kind selected from the group consisting of a carboxylic acid zinc salt having a carbon atom number of 3 to 20, a phosphoric acid zinc salt, a phosphate ester zinc salt and a carbonyl compound zinc complex; a silver anti-tarnish method for preventing tarnish of a silver part by applying said silver anti-tarnish agent to the silver part. According to the present invention, tarnish of a silver part such as a silver-plated part due to a sulfur-based gas can be prevented. The present invention is useful particularly as a silver anti-tarnish agent for a light-emitting diode and allows preventing tarnish of a silver part of a light-emitting diode and reduction in illuminance by applying the silver anti-tarnish agent of the present invention to a silver part such as a silver-plated part of a light-emitting diode for covering the silver part. | 2013-02-07 |
20130032854 | Rectirier - The rectifier in this invention is connected in series with two field effect transistor, comprises: the source S | 2013-02-07 |
20130032855 | Semiconductor Arrangement - A semiconductor arrangement includes a first and second controllable vertical n-channel semiconductor chip. Each of the controllable vertical n-channel semiconductor chips has a front side, a rear side opposite the front side, a front side main contact arranged on the front side, a rear side main contact arranged on the rear side, and a gate contact arranged on the front side for controlling an electric current between the front side main contact and the rear side main contact. The rear side contacts of the first and second semiconductor chips are electrically connected to one another. | 2013-02-07 |
20130032856 | SEMICONDUCTOR APPARATUS - A semiconductor apparatus includes: a semiconductor apparatus includes: a first semiconductor layer of a first conductivity type; a second semiconductor layer of a second conductivity type; and a third semiconductor layer of the first conductivity type, wherein: the second semiconductor layer is formed between the first and third semiconductor layers, and the first and second semiconductor layers are in contact with each other; and a first energy level at a bottom edge of a conduction band of the first semiconductor layer is lower than a second energy level at a top edge of a valence band of the second semiconductor layer, and the second energy level at the top edge of the valence band of the second semiconductor layer is substantially the same as a third energy level at a bottom edge of a conduction band of the third semiconductor layer. | 2013-02-07 |
20130032857 | Silicon-Germanium Hydrides and Methods for Making and Using Same - The present invention provides novel silicon-germanium hydride compounds, methods for their synthesis, methods for their deposition, and semiconductor structures made using the novel compounds. | 2013-02-07 |
20130032858 | RARE EARTH OXY-NITRIDE BUFFERED III-N ON SILICON - Rare earth oxy-nitride buffered III-N on silicon includes a silicon substrate with a rare earth oxide (REO) structure, including several REO layers, is deposited on the silicon substrate. A layer of single crystal rare earth oxy-nitride is deposited on the REO structure. The REO structure is stress engineered to approximately crystal lattice match the layer of rare earth oxy-nitride so as to provide a predetermined amount of stress in the layer of rare earth oxy-nitride. A III oxy-nitride structure, including several layers of single crystal rare earth oxy-nitride, is deposited on the layer of rare earth oxy-nitride. A layer of single crystal III-N nitride is deposited on the III oxy-nitride structure. The III oxy-nitride structure is chemically engineered to approximately crystal lattice match the layer of III-N nitride and to transfer the predetermined amount of stress in the layer of rare earth oxy-nitride to the layer of III-N nitride. | 2013-02-07 |
20130032859 | EPITAXIAL EXTENSION CMOS TRANSISTOR - A pair of horizontal-step-including trenches are formed in a semiconductor layer by forming a pair of first trenches having a first depth around a gate structure on the semiconductor layer, forming a disposable spacer around the gate structure to cover proximal portions of the first trenches, and by forming a pair of second trenches to a second depth greater than the first depth. The disposable spacer is removed, and selective epitaxy is performed to form an integrated epitaxial source and source extension region and an integrated epitaxial drain and drain extension region. A replacement gate structure can be formed after deposition and planarization of a planarization dielectric layer and subsequent removal of the gate structure and laterally expand the gate cavity over expitaxial source and drain extension regions. Alternately, a contact-level dielectric layer can be deposited directly on the integrated epitaxial regions and contact via structures can be formed therein. | 2013-02-07 |
20130032860 | HFET with low access resistance - A novel semiconductor power transistor is presented. The semiconductor structure is simple and is based on a Hetero-structure FET structure, where the access regions have been eliminated so as to effectively obtain a lower specific on-resistance, and a higher control on the transport properties of the device, drastically reducing the dispersion phenomena associated with these regions. The present invention can be realized both with polar and non-polar (or semi-polar) materials, without requiring delta doping implantation. It can be fabricated as an enhancement or depletion mode device with much higher control on the device threshold voltage with respect to state-of-the-art HFET devices, and achieving superior RF switching performance. Furthermore, due to the absence of access regions, enhancement mode devices can be realized without discontinuity in the channel conductivity, which results in an even lower on-resistance. | 2013-02-07 |
20130032861 | TOUCH PANEL AND METHOD FOR MANUFACTURING THE SAME - A touch panel includes a first substrate having a plurality of lower electrodes; a second substrate spaced a distance apart from the lower substrate and having a plurality of upper electrodes that correspond to the lower electrodes; a conductive rubber layer interposed between the lower electrodes and the upper electrodes; and a plurality of organic transistors interposed between the lower electrodes and the upper electrodes and to be connected to a top or bottom portion of the conductive rubber layer. | 2013-02-07 |
20130032862 | High Voltage Resistor with High Voltage Junction Termination - Provided is a high voltage semiconductor device. The high voltage semiconductor device includes a substrate that includes a doped well disposed therein. The doped well and the substrate have opposite doping polarities. The high voltage semiconductor device includes an insulating device disposed over the doped well. The high voltage semiconductor device includes an elongate resistor disposed over the insulating device. A non-distal portion of the resistor is coupled to the doped well. The high voltage semiconductor device includes a high-voltage junction termination (HVJT) device disposed adjacent to the resistor. | 2013-02-07 |
20130032863 | INTEGRATED GATE CONTROLLED HIGH VOLTAGE DIVIDER - An integrated circuit containing a gate controlled voltage divider having an upper resistor on field oxide in series with a transistor switch in series with a lower resistor. A resistor drift layer is disposed under the upper resistor, and the transistor switch includes a switch drift layer adjacent to the resistor drift layer, separated by a region which prevents breakdown between the drift layers. The switch drift layer provides an extended drain or collector for the transistor switch. A sense terminal of the voltage divider is coupled to a source or emitter node of the transistor and to the lower resistor. An input terminal is coupled to the upper resistor and the resistor drift layer. A process of forming the integrated circuit containing the gate controlled voltage divider. | 2013-02-07 |
20130032864 | TRANSISTOR WITH BOOT SHAPED SOURCE/DRAIN REGIONS - Devices are formed with boot shaped source/drain regions formed by isotropic etching followed by anisotropic etching. Embodiments include forming a gate on a substrate, forming a first spacer on each side of the gate, forming a source/drain region in the substrate on each side of the gate, wherein each source/drain region extends under a first spacer, but is separated therefrom by a portion of the substrate, and has a substantially horizontal bottom surface. Embodiments also include forming each source/drain region by forming a cavity to a first depth adjacent the first spacer and forming a second cavity to a second depth below the first cavity and extending laterally underneath the first spacers. | 2013-02-07 |
20130032865 | FABRICATION OF FIELD-EFFECT TRANSISTORS WITH ATOMIC LAYER DOPING - Field effect transistors fabricated using atomic layer doping processes are disclosed. In accordance with an embodiment of an atomic layer doping method, a semiconducting surface and a dopant gas mixture are prepared. Further, a dopant layer is grown on the semiconducting surface by applying the dopant gas mixture to the semiconducting surface under a pressure that is less than 500 Torr and a temperature that is between 300° C. and 750° C. The dopant layer includes at least 4×10 | 2013-02-07 |
20130032866 | SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD THEREOF - A transistor includes an island-like semiconductor film over a substrate, and a conductive film forming a gate electrode over the island-like semiconductor film with a gate insulating film interposed therebetween. The semiconductor film includes a channel forming region, a first impurity region forming a source or drain region, and a second impurity region. The channel forming region is overlapped with the gate electrode crossing the island-like semiconductor film. The first impurity region is adjacent to the channel forming region. The second impurity region is adjacent to the channel forming region and the first impurity region. The first impurity region and the second impurity region have different conductivity. The second impurity region and the channel forming region have different conductivity or have different concentration of an impurity element contained in the second impurity region and the channel forming region in a case of having the same conductivity. | 2013-02-07 |
20130032867 | SIGNAL LINE DRIVING CIRCUIT AND LIGHT EMITTING DEVICE - The invention relates to a signal line driving circuit having a first and a second current source circuits, a shift register, and a constant current source for video signal, in which the first current source circuit is disposed in a first latch and the second current source circuit is disposed in a second latch. The first current source circuit includes capacitive means for converting the current supplied from the constant current source for video signal into a voltage, according to a sampling pulse supplied from the shift register, and supplying means for supplying the current corresponding to the converted voltage. | 2013-02-07 |
20130032868 | TRENCH CAPACITOR WITH SPACER-LESS FABRICATION PROCESS - A trench capacitor and method of fabrication are disclosed. The SOI region is doped such that a selective isotropic etch used for trench widening does not cause appreciable pullback of the SOI region, and no spacers are needed in the upper portion of the trench. | 2013-02-07 |
20130032869 | SPLIT-GATE FLASH MEMORY WITH IMPROVED PROGRAM EFFICIENCY - A split gate memory cell is fabricated with a word gate extending below an upper surface of a substrate having the channel region. An embodiment includes providing a band engineered channel with the word gate extending there through. Another embodiment includes forming a buried channel with the word gate extending below the buried channel. | 2013-02-07 |
20130032870 | METHODS OF FORMING A MULTI-TIERED SEMICONDUCTOR DEVICE AND APPARATUSES INCLUDING THE SAME - Methods of forming multi-tiered semiconductor devices are described, along with apparatuses that include them. In one such method, a silicide is formed in a tier of silicon, the silicide is removed, and a device is formed at least partially in a void that was occupied by the silicide. One such apparatus includes a tier of silicon with a void between tiers of dielectric material. Residual silicide is on the tier of silicon and/or on the tiers of dielectric material and a device is formed at least partially in the void. Additional embodiments are also described. | 2013-02-07 |
20130032871 | SEMICONDUCTOR DEVICE HAVING AIR GAP AND METHOD OF FABRICATING THE SAME - A semiconductor device includes tunneling insulating layers on active regions of a substrate, floating gate electrodes on the tunneling insulating layers, an isolation trench within the substrate and the isolation trench defines the active region, spaces the tunneling insulating layers, and isolates the floating gate electrodes. A bottom of the isolation trench is directly in contact with the substrate. The semiconductor device further includes a lower insulating layer on the floating gate electrodes, and a middle insulating layer, an upper insulating layer, and a control gate electrode stacked on the lower insulating layer. The lower insulating layer is configured to hermetically seal a top portion of the isolation trench to define and directly abut an air gap within the isolation trench. | 2013-02-07 |
20130032872 | Non-volatile Memory Cell Having A High K Dielectric And Metal Gate - A non-volatile memory including a substrate of a first conductivity type with first and second spaced apart regions formed therein of a second conductivity type with a channel region therebetween. A polysilicon metal gate word line is positioned over a first portion of the channel region and spaced apart therefrom by a high K dielectric layer. The metal portion of the word line is immediately adjacent to the high K dielectric layer. A polysilicon floating gate is immediately adjacent to and spaced apart from the word line, and positioned over and insulated from another portion of the channel region. A polysilicon coupling gate is positioned over and insulated from the floating gate. A polysilicon erase gate is positioned on another side of and insulated from the floating gate, positioned over and insulated from the second region, and immediately adjacent to but spaced apart from another side of the coupling gate. | 2013-02-07 |
20130032873 | SEMICONDUCTOR MEMORY DEVICE AND METHOD FOR MANUFACTURING THE SAME - According to one embodiment, a semiconductor memory device includes a stacked body, a semiconductor pillar, and a plurality of memory cells. The stacked body includes a plurality of stacked gate electrodes and inter-electrode insulating layers provided between the gate electrodes. The semiconductor pillar punches through the stacked body. The plurality of memory cells is provided in stacking direction. The memory cell includes a charge trap layer provided between the semiconductor pillar and the gate electrode via an air gap. The block insulating layer is provided between the charge trap layer and the gate electrode. Each of the plurality of memory cells is provided with a support portion configured to keep air gap distance between the charge trap layer and the semiconductor pillar. | 2013-02-07 |
20130032874 | METHOD FOR MANUFACTURING NONVOLATILE SEMICONDUCTOR MEMORY DEVICE AND NONVOLATILE SEMICONDUCTOR MEMORY DEVICE - According to one embodiment, a method is disclosed for manufacturing a nonvolatile semiconductor memory device. The device includes a plurality of electrode films stacked along a first axis perpendicular to a major surface of a substrate, a plurality of semiconductor layers penetrating through the electrode films, and a memory film provided between the electrode films and the semiconductor layer. The method can include forming a first stacked body by alternately stacking a plurality of first films and second films. The method can include forming a support unit supporting the first films. The method can include forming a first hole and removing the second films via the first hole to form a second stacked body. The method can include forming a plurality of through holes penetrating through the first films. In addition, the method can include burying the memory film and the semiconductor layers in the through holes. | 2013-02-07 |
20130032875 | SEMICONDUCTOR DEVICES AND METHODS OF FABRICATING THE SAME - One example embodiment of a semiconductor device includes a memory cell array formed on a substrate. The memory cell array includes a gate stack including alternating conductive and insulating layers. A first lower conductive layer in the gate stack has a portion disposed below a first upper conductive layer in the gate stack, and a first contact area of the first lower conductive layer is disposed higher than a second contact area of the first upper conductive layer. The semiconductor device further includes first and second contact plugs extending into the gate stack to contact the first and second contact areas, respectively. | 2013-02-07 |
20130032876 | Replacement Gate ETSOI with Sharp Junction - A transistor structure includes a channel disposed between a source and a drain; a gate conductor disposed over the channel and between the source and the drain; and a gate dielectric layer disposed between the gate conductor and the source, the drain and the channel. In the transistor structure a lower portion of the source and a lower portion of the drain that are adjacent to the channel are disposed beneath and in contact with the gate dielectric layer to define a sharply defined source-drain extension region. Also disclosed is a replacement gate method to fabricate the transistor structure. | 2013-02-07 |
20130032877 | N-CHANNEL TRANSISTOR COMPRISING A HIGH-K METAL GATE ELECTRODE STRUCTURE AND A REDUCED SERIES RESISTANCE BY EPITAXIALLY FORMED SEMICONDUCTOR MATERIAL IN THE DRAIN AND SOURCE AREAS - When forming sophisticated semiconductor devices including high-k metal gate electrode structures and N-channel transistors, superior performance may be achieved by incorporating epitaxially grown semiconductor materials, for instance a strain-inducing silicon/carbon alloy in combination with an N-doped silicon material, which may provide an acceptable sheet resistivity. | 2013-02-07 |
20130032878 | SEMICONDUCTOR DEVICE - According to example embodiments, a semiconductor device includes horizontal patterns stacked on a substrate. The horizontal patterns define an opening through the horizontal patterns. A first core pattern is in the opening. A second core pattern is in the opening on the first core pattern. A first active pattern is between the first core pattern and the horizontal patterns. A second active pattern containing a first element is between the second core pattern and the horizontal patterns. The second active pattern contains the first element at a higher concentration than a concentration of the first element in the second core pattern. | 2013-02-07 |
20130032879 | SEMICONDUCTOR DEVICE AND METHOD FOR FORMING THE SAME - A semiconductor device and a method for forming the same are disclosed. The semiconductor device includes vertical pillars formed by etching a semiconductor substrate and junction regions which are located among the neighboring vertical pillars and spaced apart from one another in a zigzag pattern. As a result, the semiconductor device easily guarantees an electrical passage between the semiconductor substrate and the vertical pillars, such that it substantially prevents the floating phenomenon from being generated, resulting in the prevention of deterioration of the semiconductor device. | 2013-02-07 |
20130032880 | HIGH VOLTAGE DEVICE AND MANUFACTURING METHOD THEREOF - The present invention discloses a high voltage device and a manufacturing method thereof. The high voltage device is formed in a first conductive type substrate, wherein the substrate has an upper surface. The high voltage device includes: a second conductive type buried layer, which is formed in the substrate; a first conductive type well, which is formed between the upper surface and the buried layer; and a second conductive type well, which is connected to the first conductive type well and located at different horizontal positions. The second conductive type well includes a well lower surface, which has a first part and a second part, wherein the first part is directly above the buried layer and electrically coupled to the buried layer; and the second part is not located above the buried layer and forms a PN junction with the substrate. | 2013-02-07 |
20130032881 | Asymmetric Source-Drain Field Effect Transistor and Method of Making - The present invention is related to microelectronic device technologies. A method for making an asymmetric source-drain field-effect transistor is disclosed. A unique asymmetric source-drain field-effect transistor structure is formed by changing ion implantation tilt angles to control the locations of doped regions formed by two ion implantation processes. The asymmetric source-drain field-effect transistor has structurally asymmetric source/drain regions, one of which is formed of a P-N junction while the other one being formed of a mixed junction, the mixed junction being a mixture of a Schottky junction and a P-N junction. | 2013-02-07 |
20130032882 | BI-DIRECTIONAL BLOCKING VOLTAGE PROTECTION DEVICES AND METHODS OF FORMING THE SAME - Bi-directional blocking voltage protection devices and methods of forming the same are disclosed. In one embodiment, a protection device includes an n-well and first and second p-wells disposed on opposite sides of the n-well. The first p-well includes a first P+ region and a first N+ region and the second p-well includes a second P+ region and second N+ region. The device further includes a third P+ region disposed along a boundary of the n-well and the first p-well and a fourth P+ region disposed along a boundary of the n-well and the second p-well. A first gate is disposed between the first N+ region and the third P+ region and a second gate is disposed between the second N+ region and the fourth P+ region. The device provides bi-directional blocking voltage protection during high energy stress events, including in applications operating at very low to medium swing voltages. | 2013-02-07 |
20130032883 | FABRICATION OF FIELD-EFFECT TRANSISTORS WITH ATOMIC LAYER DOPING - Field effect transistors fabricated using atomic layer doping processes are disclosed. In accordance with an embodiment of an atomic layer doping method, a semiconducting surface and a dopant gas mixture are prepared. Further, a dopant layer is grown on the semiconducting surface by applying the dopant gas mixture to the semiconducting surface under a pressure that is less than 500 Torr and a temperature that is between 300° C. and 750° C. The dopant layer includes at least 4×10 | 2013-02-07 |
20130032884 | INTEGRATED CIRCUIT DEVICE HAVING DEFINED GATE SPACING AND METHOD OF DESIGNING AND FABRICATING THEREOF - A device, and method of fabricating and/or designing such a device, including a first gate structure having a width (W) and a length (L) and a second gate structure separated from the first gate structure by a distance greater than: (√{square root over (W*W+L*L)})/10. The second gate structure is a next adjacent gate structure to the first gate structure. A method and apparatus for designing an integrated circuit including implementing a design rule defining the separation of gate structures is also described. In embodiments, the distance of separation is implemented for gate structures that are larger relative to other gate structures on the substrate (e.g., greater than 3 μm | 2013-02-07 |
20130032885 | AREA EFFICIENT GRIDDED POLYSILICON LAYOUTS - Gridded polysilicon semiconductor layouts implement double poly patterning to cut polylines of the layout into polyline segments. Devices are arranged on the polyline segments of a common polyline to reduce the area used to implement a circuit structure relative to conventional gridded polysilicon layout. Stacking of PMOS and NMOS devices is enabled by using double poly patterning to implement additional cuts which form additional polyline segments. Metal layer routing may connect nodes of separate polyline segments. | 2013-02-07 |
20130032886 | Low Threshold Voltage And Inversion Oxide Thickness Scaling For A High-K Metal Gate P-Type MOSFET - A structure has a semiconductor substrate and an nFET and a pFET disposed upon the substrate. The pFET has a semiconductor SiGe channel region formed upon or within a surface of the semiconductor substrate and a gate dielectric having an oxide layer overlying the channel region and a high-k dielectric layer overlying the oxide layer. A gate electrode overlies the gate dielectric and has a lower metal layer abutting the high-k layer, a scavenging metal layer abutting the lower metal layer, and an upper metal layer abutting the scavenging metal layer. The metal layer scavenges oxygen from the substrate (nFET) and SiGe (pFET) interface with the oxide layer resulting in an effective reduction in T | 2013-02-07 |
20130032887 | SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD THEREOF - A manufacturing method for manufacturing a semiconductor device includes depositing a spacer material on a semiconductor substrate, the substrate includes an NMOS region and a PMOS region, each region has a gate formed thereon. The method further includes covering the NMOS region with a first mask, forming a spacer for the PMOS gate by etching the spacer material, forming a recess in the PMOS region by etching, and growing SiGe or SiGe with in-situ-doped B in the recess of the PMOS region to form a PMOS source/drain region. The method further includes performing an anisotropic wet etching on the recess. After growing SiGE or SiGe with in-situ-doped B, the method further includes covering the PMOS region with a second mask and forming a spacer for the NMOS gate by etching the spacer material. The spacer for the PMOS and NMOS gate has a different critical dimension. | 2013-02-07 |
20130032888 | SEMICONDUCTOR DEVICE HAVING INSULATING FILM WITH DIFFERENT STRESS LEVELS IN ADJACENT REGIONS AND MANUFACTURING METHOD THEREOF - An n-channel MISFETQn is formed in an nMIS first formation region of a semiconductor substrate and a p-channel MISFETQp is formed in an adjacent pMIS second formation region of the semiconductor substrate. A silicon nitride film having a tensile stress is formed to cover the n-channel MISFETQn and the p-channel MISFETQp. In one embodiment, the silicon nitride film in the nMIS formation region and the pMIS formation region is irradiated with ultraviolet rays. Thereafter, a mask layer is formed to cover the silicon nitride film in the nMIS formation region and to expose the silicon nitride film in the pMIS formation region. The silicon nitride film in the pMIS formation region is then subjected to plasma processing, which relieves the tensile stress of the silicon nitride film in the pMIS formation region. | 2013-02-07 |
20130032889 | Silicon Chip Having Through Via and Method for Making the Same - The present invention relates to a silicon chip including a silicon substrate, a passivation layer, at least one electrical device and at least one through via. The passivation layer is disposed on a first surface of the silicon substrate. The electrical device is disposed in the silicon substrate, and exposed to a second surface of the silicon substrate. The through via includes a barrier layer and a conductor, and penetrates the silicon substrate and the passivation layer. A first end of the through via is exposed to the surface of the passivation layer, and a second end of the through via connects the electrical device. When a redistribution layer is formed on the surface of the passivation layer, the redistribution layer will not contact the silicon substrate, thus avoiding a short circuit. | 2013-02-07 |
20130032890 | SELF-ADJUSTING LATCH-UP RESISTANCE FOR CMOS DEVICES - CMOS devices ( | 2013-02-07 |
20130032891 | METHOD OF MANUFACTURING AN IC COMPRISING A PLURALITY OF BIPOLAR TRANSISTORS AND IC COMPRISING A PLURALITY OF BIPOLAR TRANSISTORS - A method of manufacturing an integrated circuit comprising bipolar transistors including first and second type bipolar transistors, the method comprising providing a substrate comprising first isolation regions each separated from a second isolation region by an active region comprising a collector impurity of one of the bipolar transistors; forming a base layer stack over the substrate; forming a first emitter cap layer of a first effective thickness over the base layer stack in the areas of the first type bipolar transistor; forming a second emitter cap layer of a second effective thickness different from the first effective thickness over the base layer stack in the areas of the second type bipolar transistor; and forming an emitter over the emitter cap layer of each of the bipolar transistors. An IC in accordance with this method. | 2013-02-07 |