| 06th week of 2014 patent applcation highlights part 50 |
| Patent application number | Title | Published |
|---|
| 20140038297 | Genes and Proteins for the Biosynthesis of the Lantibiotic 107891 - The Invention relates to the field of lantibiotics, and more specifically to the isolation of nucleic acid molecules that code for the enzymes required for the biosynthetic pathway of the lantibiotic 107891 and the homologues thereof. | 2014-02-06 |
| 20140038298 | METHODS AND SYSTEMS FOR NONDISRUPTIVE LOADING OF REAGENTS IN A BODY FLUID WORKSTATION - A method of nondisruptive loading of reagents in a body fluid workstation comprising a plurality of analyzers includes: receiving application information input from a user to an analyzer which needs loading of a reagent; controlling the analyzer to pause dispensing of a reagent at a determined time; and controlling one or more other analyzers in the body fluid workstation to continue testing. | 2014-02-06 |
| 20140038299 | MICROFLUIDIC DEVICE AND METHOD FOR FLUID CLOTTING TIME DETERMINATION - A method for determining clotting time is described, of a fluid medium such as blood.
| 2014-02-06 |
| 20140038300 | Devices, Systems, and Methods for Aiding in the Detection of a Physiological Abnormality - The present invention comprises a method for identifying the presence or absence of a pulmonary embolism using a combination of tests and brightline thresholds. The first test is a blood based test measuring D-Dimer concentration and the second test is a respiratory analysis that determines a carboximetry ratio. If the measured D-Dimer value is at or above a threshold indicative of concern and the carboximetry value is equal to or less than a carboximetry ratio threshold, pulmonary embolism is present. If the measured D-Dimer value is at or above a threshold indicative of concern and the respiratory analysis yields a carboximetry ratio greater than the carboximetry ratio threshold, test results are inconclusive and additional testing is required to determine whether a pulmonary embolism is present. | 2014-02-06 |
| 20140038301 | SELECTIVE CAPTURE AND RELEASE OF ANALYTES - The described subject matter includes techniques and components for minimally invasive, selective capture and release of analytes. An aptamer is selected for its binding affinity with a particular analyte(s). The aptamer is functionalized on a solid phase, for example, microbeads, polymer monolith, microfabricated solid phase, etc. The analyte is allowed to bind to the aptamer, for example, in a microchamber. Once the analyte has been bound, a temperature control sets the temperature to an appropriate temperature at which the captured analyte is released. | 2014-02-06 |
| 20140038302 | METHODS AND KITS FOR DETECTION OF COENZYME Q10 - The invention provides methods for rapid and quantitative extraction and detection of coenzyme Q10 in a sample readily adaptable to high throughput screening methods. The invention further provides reagents and kits for practicing the methods of the invention. | 2014-02-06 |
| 20140038303 | TEST KIT AND METHOD FOR DETECTION OF ADDITIVES IN FUEL COMPOSITIONS - Method for detecting a basic target species in a fuel composition, involving (i) contacting the composition with a solid (for example paper) substrate carrying a spectroscopically active indicator which is capable of reacting with the target species, and (ii) detecting the spectroscopic response of the indicator on or following its contact with the fuel composition. The target species may be a detergent or dispersant additive or a constituent thereof, for example in an automotive fuel. The spectroscopic response may be a colour change, and the indicator may for example be a phenolphthalein indicator such as tetrabromophenolphthalein ethyl ester (HTBPE). Also provided is a test kit for use in the invented method, which may comprise a reference, such as a colour chart, with which to compare the spectroscopic response of the indicator. The indicator-carrying substrate is suitably packaged in a protective atmosphere. | 2014-02-06 |
| 20140038304 | HIGH-TEMPERATURE FURNACE, USE OF A SPINEL CERAMIC AND METHOD FOR CARRYING OUT T(O)C MEASUREMENTS OF SAMPLES - The present invention relates to a high-temperature furnace for T(O)C measurement of a sample, which has a furnace housing which bounds a vaporization space and has a sample opening for the dropwise introduction of the sample and at least one flushing opening for introduction of a flushing liquid. According to the invention, the furnace housing is lined with a spinel ceramic on an inner side facing the vaporization space. By means of the spinel ceramic, the vaporization space is lined with a material which allows particularly high temperatures within the vaporization space and thus very complete combustion and is at the same time very resistant to temperature changes. This allows cleaning with a flushing liquid at essentially the operating temperature of the vaporization space and removal of deposited salts, in particular recrystallized organic salts, from the vaporization space in the flushing liquid in dissolved or undissolved form. Aging of the high-temperature furnace by deposited salts can thereby be avoided or at least significantly retarded. | 2014-02-06 |
| 20140038305 | ARTICLES AND METHODS FOR THE DETECTION AND QUANTIFICATION OF ULTRAVIOLET LIGHT - Formulations, articles and methods for the detection and/or qualification of ultraviolet light. A chemical formulation containing a tetrazolium or formazan complex is used to make a UV sensitive compound. The formulation is used to form a chemical indicator comprising a substrate with the formulation impregnated on or in the substrate. The substrate may be any suitable material and may be coated, uncoated, or laminated. The formulation may be coated on or inserted into a substrate and will form a UV detecting indicator when applied thereto. Depending upon its composition, the formulation will undergo a color change on exposure to different types of ultraviolet radiation, such as UVA, UVB or UVC, and the color change can be correlated to the length of exposure. The indicator can be used to detect and evaluate exposure to ultraviolet light in a variety of settings depending on the specifics of the formulation. | 2014-02-06 |
| 20140038306 | Methods, Systems, and Devices Relating to Open Microfluidic Channels - The various embodiments described herein relate to fabricating and using open microfluidic networks according to methods, systems, and devices that can be used in applications ranging from home-testing, diagnosis, and research laboratories. Open microfluidic networks allow the input, handling, and extraction of fluids or components of the fluid into or out of the open microfluidic network. Fluids can be inserted into an open microfluidic channel by using open sections of the open microfluidic network. Passive valves can be created in the microfluidic network, allowing the creation of logic circuits and conditional flow and volume valves. The fluid can be presented via the microfluidic network to diagnostic and analysis components. Fluids and components of the fluid can be extracted from the open microfluidic network via functional open sections that are easily interfaced with other microfluidic networks or common laboratory tools. | 2014-02-06 |
| 20140038307 | REAGENT VESSEL INSERT, REAGENT VESSELS, METHOD FOR THE CENTRIFUGING OF AT LEAST ONE MATERIAL AND METHOD FOR THE PRESSURE TREATMENT OF AT LEAST ONE MATERIAL - A reagent vessel insert for a reagent vessel for a centrifuge and/or a pressure varying device includes an insert housing formed such that the reagent vessel insert is insertable in a reagent vessel for a centrifuge and/or for a pressure varying device. The reagent vessel insert also includes at least one agitating element arranged in at least one interior volume such that a place and/or position of the at least one agitating element is changeable with respect to the insert housing. The reagent vessel insert is configured such that at least one material filled into the at least one interior volume is agitatable and such that, during an adjustment, at least one subunit of the at least one agitating element contacting at least one holding structure, by which the at least one agitating element is held in at least one semi-stable place and/or at least one semi-stable position. | 2014-02-06 |
| 20140038308 | PROCESS FOR PRODUCING COMPOSITE DEVICE, AND PROCESS FOR BONDING DEVICE FORMED OF TRANSPARENT MATERIAL TO ADHEREND - Provided is a process for producing a composite device comprising a light shielding first member and a light transmissive second member, a first surface of the light shielding first member and a second surface of the light transmissive second member being bonded to each other through intermediation of an ultraviolet curing adhesive, the second surface being larger than the first surface, the process including irradiating a region of the second surface to which region the first surface is not bonded with an ultraviolet ray, wherein a reflective member having a reflective surface with an inclination with respect to the second surface onto the light transmissive second member so that the ultraviolet ray that has transmitted through the second surface is reflected toward the ultraviolet curing adhesive between the second surface and the first surface. | 2014-02-06 |
| 20140038309 | MAGNETIC RANDOM ACCESS MEMORY WITH SYNTHETIC ANTIFERROMAGNETIC STORAGE LAYERS AND NON-PINNED REFERENCE LAYERS - A method for fabricating a synthetic antiferromagnetic device, includes depositing a magnesium oxide spacer layer on a reference layer having a first and second ruthenium layer, depositing a cobalt iron boron layer on the magnesium oxide spacer layer; and depositing a third ruthenium layer on the cobalt iron boron layer, the third ruthenium layer having a thickness of approximately 0-18 angstroms. | 2014-02-06 |
| 20140038310 | MAGNETIC RANDOM ACCESS MEMORY WITH SYNTHETIC ANTIFERROMAGNETIC STORAGE LAYERS - A synthetic antiferromagnetic device includes a reference layer, a magnesium oxide spacer layer disposed on the reference layer, a cobalt iron boron layer disposed on the magnesium oxide spacer layer, and a first ruthenium layer disposed on cobalt iron boron layer, the first ruthenium layer having a thickness of approximately 0 Å to 32 Å. | 2014-02-06 |
| 20140038311 | METHODS FOR ETCHING MATERIALS USED IN MRAM APPLICATIONS - Embodiments of the invention provide methods and apparatus for fabricating magnetic tunnel junction (MTJ) structures on a substrate in magnetoresistive random access memory applications. In one embodiment, a method of forming a MTJ structure on a substrate includes providing a substrate having a insulating tunneling layer disposed between a first and a second ferromagnetic layer disposed on the substrate, wherein the first ferromagnetic layer is disposed on the substrate followed by the insulating tunneling layer and the second ferromagnetic layer sequentially, supplying an ion implantation gas mixture to implant ions into the first ferromagnetic layer exposed by openings defined by the second ferromagnetic layer, and etching the implanted first ferromagnetic layer | 2014-02-06 |
| 20140038312 | FABRICATION OF A MAGNETIC TUNNEL JUNCTION DEVICE - A magnetic tunneling junction device and fabrication method is disclosed. In a particular embodiment, a non-transitory computer-readable medium includes processor executable instructions. The instructions, when executed by a processor, cause the processor to initiate deposition of a capping material on a free layer of a magnetic tunneling junction structure to form a capping layer. The instructions, when executed by the processor, cause the processor to initiate oxidization of a first layer of the capping material to form a first oxidized layer of oxidized material. | 2014-02-06 |
| 20140038313 | SEMICONDUCTOR FABRICATING DEVICE AND METHOD FOR DRIVING THE SAME, AND METHOD FOR FABRICATING MAGNETIC TUNNEL JUNCTION USING THE SAME - In a method for fabricating a magnetic tunnel junction, a first magnetic layer is formed on a substrate, and a tunnel insulating layer is formed on the first magnetic layer. Subsequently, a second magnetic layer is formed on the tunnel insulating layer. In the method, the first magnetic layer is formed by periodically sputtering a magnetic target while a metal target is continuously sputtered. | 2014-02-06 |
| 20140038314 | MAGNETIC RANDOM ACCESS MEMORY (MRAM) WITH ENHANCED MAGNETIC STIFFNESS AND METHOD OF MAKING SAME - A spin toque transfer magnetic random access memory (STTMRAM) element and a method of manufacturing the same is disclosed having a free sub-layer structure with enhanced internal stiffness. A first free sub-layer is deposited, the first free sub-layer being made partially of boron (B), annealing is performed of the STTMRAM element at a first temperature after depositing the first free sub-layer to reduce the B content at an interface between the first free sub-layer and the barrier layer, the annealing causing a second free sub-layer to be formed on top of the first free sub-layer and being made partially of B, the amount of B of the second free sub-layer being greater than the amount of B in the first free sub-layer. Cooling down the STTMRAM element to a second temperature that is lower than the first temperature and depositing a third free sub-layer directly on top of the second free layer, with the third free sub-layer being made partially of boron (B), wherein the amount of B in the third sub-free layer is less than the amount of B in the second free sub-layer. | 2014-02-06 |
| 20140038315 | APPARATUS AND METHOD FOR MEASURING THE DIMENSIONS OF 1-DIMENSIONAL AND 0-DIMENSIONAL NANOSTRUCTURES IN REAL-TIME DURING EPITAXIAL GROWTH - The present invention relates to an apparatus and a method for measuring the dimensions of 1-dimensional and 0-dimensional nanostructures on semiconductor substrates in real-time during epitaxial growth. The method includes either assigning a pre-calculated 3D-model from a data base to the sample or calculating a 3D-model of the sample using the measured optical reflectances of the plurality of different measuring positions of the sample, where calculation or pre-calculation of the 3D-model includes calculation of the interference effects of light reflected from the front and back interfaces of the nano-structure and calculation of the interference effects due to superposition of neighbouring wave-fronts reflected from the nano-structure area and wave-fronts reflected from the substrate area between the nano-structures. | 2014-02-06 |
| 20140038316 | EXAMINATION OF A SILICON SUBSTRATE FOR A SOLAR CELL - The invention relates to a method for examining a wire-sawn silicon substrate for a solar cell. The method includes irradiating the silicon substrate with an infrared radiation, detecting the infrared radiation transmitted through the silicon substrate, and analyzing the detected infrared radiation for characterizing the crystal orientation of the silicon substrate. The invention in addition relates to a device for carrying out such a method, and a method for manufacturing a solar cell. | 2014-02-06 |
| 20140038317 | METHOD FOR FORMING AN ELECTRICAL CONNECTION BETWEEN METAL LAYERS - A method forms an electrical connection between a first metal layer and a second metal layer. The second metal layer is above the first metal layer. A first via is formed between the first metal layer and the second metal layer. A first measure of a number of vacancies expected to reach the first via is obtained. A second via in at least one of the first metal layer and the second metal layer is formed if the measure of vacancies exceeds a first predetermined number. | 2014-02-06 |
| 20140038318 | PATTERN FORMING METHODS AND SEMICONDUCTOR DEVICE MANUFACTURING METHOD - According to one embodiment, a pattern forming method includes forming a self-assembled material on a plurality of first patterns, forming a plurality of second patterns by heating the self-assembled material and causing microphase separation of the self-assembled material, the second patterns corresponding to the first patterns, and calculating positional deviations of respective positions of the second patterns from positions of the corresponding first patterns. When at least one of the positional deviations is larger than a predetermined value, the self-assembled material is adjusted. | 2014-02-06 |
| 20140038319 | METHOD FOR FORMING AN ELECTRICAL CONNECTION BETWEEN METAL LAYERS - A method includes forming a connection between a first metal layer and a second metal layer. The second metal layer is over the first metal layer. A via location for a first via between the first metal layer and the second metal layer is identified. Additional locations for first additional vias are determined. The first additional vias are determined to be necessary for stress migration issues. Additional locations necessary for second additional vias are determined. The second additional vias are determined to be necessary for electromigration issues. The first via and the one of the group consisting of (i) the first additional vias and second additional vias (ii) the first additional vias plus a number of vias sufficient for electromigration issues taking into account that the first additional vias, after taking into account the stress migration issues, still have an effective via number greater than zero. | 2014-02-06 |
| 20140038320 | METHOD OF MANUFACTURING A LIGHT EMITTING DIODE | 2014-02-06 |
| 20140038321 | PHOTOCONDUCTIVE SWITCH PACKAGE - A photoconductive switch is formed of a substrate that has a central portion of SiC or other photoconductive material and an outer portion of cvd-diamond or other suitable material surrounding the central portion. Conducting electrodes are formed on opposed sides of the substrate, with the electrodes extending beyond the central portion and the edges of the electrodes lying over the outer portion. Thus any high electric fields produced at the edges of the electrodes lie outside of and do not affect the central portion, which is the active switching element. Light is transmitted through the outer portion to the central portion to actuate the switch. | 2014-02-06 |
| 20140038322 | Electronic Device and Method of Manufacturing an Electronic Device - An electronic device comprising at least one die stack having at least a first die (D1) comprising a first array of light emitting units (OLED) for emitting light, a second layer (D2) comprising a second array of via holes (VH) and a third die (D3) comprising a third array of light detecting units (PD) for detecting light from the first array of light emitting units (OELD) is provided. The second layer (D2) is arranged between the first die (D1) and the third die (D3). The first, second and third array are aligned such that light emitted from the first array of light emitting units (OLED) passed through the second array of via holes (VH) and is detected by the third array of light detecting units (PD). The first array of light emitting units and/or the third array of light detecting units are manufactured based on standard semiconductor manufacturing processes. | 2014-02-06 |
| 20140038323 | METHOD FOR MANUFACTURING LIGHT EMITTING CHIP - A method for making a light emitting chip package, comprises: providing a substrate; forming a plurality of recesses on the bottom surface of the substrate; forming an etch stop layer on the bottom surface; forming a step hole on the top surface; forming an insulation layer on the top surface; defining a plurality of first through holes in the insulation layer and a plurality of second through holes in the etch stop layer, the number of the first through holes being different from the number of the second through holes; filling the first through holes and the second through holes with metal to respectively form first electrical conductor portions and second electrical conductor portions; forming a patterned electric conductive layer on the insulation layer; arranging a light emitting chip on the electric conductive layer; and encapsulating the light emitting chip with an encapsulation. | 2014-02-06 |
| 20140038324 | MANUFACTURING METHOD OF LIGHT EMITTING APPARATUS - In a manufacturing method of a light emitting apparatus, an array of light emitting elements is formed on a substrate. A first lens-pillar-material layer is formed on the array, and first lens pillars are formed on the light emitting elements of the array by performing a photolithographic process on the first lens-pillar-material layer. A lens-portion-material layer is laminated on the first lens pillar using a dry film resist so that gaps are left between the first lens pillars. A plurality of lens portions that correspond to the first lens pillars are formed by performing a heat treatment on the first lens-portion-material layer so that it is softened and enters the gaps. The first lens pillars and the lens portions constitute a lens array that focuses light emitted by the light emitting elements. | 2014-02-06 |
| 20140038325 | LIGHT-EMITTING DEVICE MANUFACTURING METHOD - A method for manufacturing a light-emitting device comprises retaining a conductor wire so that a straight-line distance between adjacent mounting portions while the conductor is retained is less than a distance along the conductor wire between the adjacent mounting portions; mounting a plurality of light emitting diodes to respective ones of the mounting portions on the retained conductor wire; and after the mounting step, sealing the plurality of light-emitting diodes mounted on the conductor wire. | 2014-02-06 |
| 20140038326 | DISPLAY SUBSTRATE HAVING ARCHED SIGNAL TRANSMISSION LINE AND MANUFACTURE METHOD THEREOF - This invention discloses a display device mother substrate, a display device substrate and a manufacture method of display device substrate thereof. The display device mother substrate includes a first substrate, a second substrate, a first active area circuit and a first transmission line, wherein a first cutting line is defined between the first substrate and the second substrate. The first active area circuit is disposed on the first substrate and is electrically connected to the first transmission line. The first transmission line includes a display line portion, an end line portion and a middle line portion, wherein the display line portion is electrically connected to the first active area circuit. The middle line portion is disposed on the second substrate, wherein two ends of the middle line portion are electrically connected to the display line portion and the end line portion respectively at the first cutting line. The display device mother substrate is cut along the first cutting line to be separated into the first substrate and the second substrate, wherein the middle line portion is also separated from the display line portion and the end line portion. | 2014-02-06 |
| 20140038327 | FRIT SEALING SYSTEM AND METHOD OF MANUFACTURING ORGANIC LIGHT-EMITTING DISPLAY (OLED) APPARATUS USING THE SAME - A frit sealing system and a method of manufacturing an organic light-emitting display (OLED) using the frit sealing system are disclosed. In one embodiment, the frit sealing system includes: a thermal expansion film formed on the second substrate to pressurize the second substrate when heat is applied to the frit and thermal expansion film, wherein the frit is interposed between the first and second substrates and a mask formed on the thermal expansion film. | 2014-02-06 |
| 20140038328 | Method for manufacturing semiconductor light emitting device - A semiconductor light emitting device having high reliability and excellent light distribution characteristics can be provided with an n-electrode arranged on a light extraction surface on the side opposite to the surface whereupon a semiconductor stack is mounted on a substrate. A plurality of convexes are arranged on a first convex region and a second convex region on the light extraction surface. The second convex region adjoins the interface between the n-electrode and the semiconductor stack, between the first convex region and the n-electrode. The base end of the first convex arranged in the first convex region is positioned closer to a light emitting layer than the interface between the n-electrode and the semiconductor stack, and the base end of the second convex arranged in the second convex region is positioned closer to the interface between the n-electrode and the semiconductor stack than the base end of the first convex. | 2014-02-06 |
| 20140038329 | EPITAXIAL GROWTH ON THIN LAMINA - Methods and apparatus are provided for forming an electronic device from a lamina and an epitaxially grown semiconductor material. The method includes providing a donor body comprising a top surface, epitaxially growing a semiconductor material on the top surface and implanting the top surface of the donor body with an ion dosage to form a cleave plane. After implantation, a lamina may be exfoliated from the donor body, wherein the top surface of the donor body becomes a first surface of the lamina. Exfoliating the lamina forms a second surface of the lamina, wherein the first surface is opposite the second surface. A metal support may be constructed on the lamina. | 2014-02-06 |
| 20140038330 | DEVICE FOR FORMING THIN LAYER AND METHOD OF MANUFACTURING ORGANIC LIGHT EMITTING DIODE DISPLAY USING THE SAME - Provided are a device for forming a thin layer that may be applied to mass production and a method of manufacturing a display using the same. The device for forming a thin layer includes a vessel that has a material for forming a thin layer, a multi-nozzle part that is on a substrate and that is connected to the vessel to receive the material for forming the thin layer, which multi-nozzle part includes a plurality of nozzles arranged in parallel at a distance from each other, and a pulse generator that applies a switching voltage to one of the substrate and the multi-nozzle part such that an instantaneous potential difference between at least one of the plurality of nozzles and the substrate is provided, and such that a discharge of the material for forming the thin layer is controlled. | 2014-02-06 |
| 20140038331 | SOLID STATE LIGHTING DEVICE WITH DIFFERENT ILLUMINATION PARAMETERS AT DIFFERENT REGIONS OF AN EMITTER ARRAY - Solid state lighting (SSL) devices and methods of manufacturing such devices. One embodiment of an SSL device comprises a support and an emitter array having a plurality of SSL emitters carried by the support. The emitter array has a central region and a peripheral region outward from the central region. Individual SSL emitters in both the central and the peripheral regions have a primary emission direction along which an intensity of light from the SSL emitters is highest, and the primary emission direction of the SSL emitters in the central region is at least substantially the same direction as the primary emission direction of the SSL emitters in the peripheral region. Additionally, a first coverage area ratio of the SSL emitters in the central region is different than a second coverage area ratio of the SSL emitters in the peripheral region. | 2014-02-06 |
| 20140038332 | BACK PANEL FOR FLAT PANEL DISPLAY APPARATUS, FLAT PANEL DISPLAY APPARATUS COMPRISING THE SAME, AND METHOD OF MANUFACTURING THE BACK PANEL - A back panel for a flat panel display apparatus includes: a pixel electrode disposed on a substrate; a first gate electrode layer of a thin-film transistor (TFT) disposed on the substrate; a second gate electrode layer disposed on the first gate electrode layer and including a semiconductor material; a third gate electrode layer disposed on the second gate electrode layer and including a metal material; a first insulating layer disposed on the third gate electrode layer; an active layer disposed on the first insulating layer and including a transparent conductive oxide semiconductor; a second insulating layer disposed on the active layer; source and drain electrodes disposed connected to the active layer through the second insulating layer; and a third insulating layer covering the source and drain electrodes. The first gate electrode layer and the pixel electrode include a transparent conductive oxide. | 2014-02-06 |
| 20140038333 | DISPLAY DEVICE AND METHOD FOR MANUFACTURING THE SAME - A display device includes a substrate, a first conductive film pattern including a gate electrode and a first capacitor electrode on the substrate, a gate insulating layer pattern on the first conductive film pattern, a polycrystalline silicon film pattern including an active layer and a second capacitor electrode on the gate insulating layer pattern, an interlayer insulating layer on the polycrystalline silicon film pattern, a plurality of first contact holes through the gate insulating layer pattern and the interlayer insulating layer to expose a portion of the first conductive film pattern, a plurality of second contact holes through the interlayer insulating layer to expose a portion of the polycrystalline silicon film pattern, and a second conductive film pattern including a source electrode, a drain electrode, and a pixel electrode on the interlayer insulating layer. | 2014-02-06 |
| 20140038334 | LASER-INDUCED FLAW FORMATION IN NITRIDE SEMICONDUCTORS - An embodiment is a method to induce flaw formation in nitride semiconductors. Regions of a thin film structure are selectively decomposed within a thin film layer at an interface with a substrate to form flaws in a pre-determined pattern within the thin film structure. The flaws locally concentrate stress in the pre-determined pattern during a stress-inducing operation. The stress-inducing operation is performed. The stress-inducing operation causes the thin film layer to fracture at the pre-determined pattern. | 2014-02-06 |
| 20140038335 | INTEGRATED ACOUSTIC TRANSDUCER IN MEMS TECHNOLOGY, AND MANUFACTURING PROCESS THEREOF - A MEMS acoustic transducer, for example, a microphone, includes a substrate provided with a cavity, a supporting structure, fixed to the substrate, a membrane having a perimetral edge and a centroid, suspended above the cavity and fixed to the substrate the membrane configured to oscillate via the supporting structure. The supporting structure includes a plurality of anchorage elements fixed to the membrane, and each anchorage element is coupled to a respective portion of the membrane between the centroid and the perimetral edge of the membrane. | 2014-02-06 |
| 20140038336 | THERMAL DETECTOR, THERMAL DETECTION DEVICE, ELECTRONIC INSTRUMENT, AND THERMAL DETECTOR MANUFACTURING METHOD - A thermal detector manufacturing method includes: forming a sacrificial layer on a structure including an insulating layer; forming a support member on the sacrificial layer; forming on the support member a heat-detecting element; forming a first light-absorbing layer so as to cover the heat-detecting element, and planarizing the first light-absorbing layer; forming a contact hole in a portion of the first light-absorbing layer, subsequently forming a thermal transfer member having a connecting portion that connects to the heat-detecting element and a thermal collecting portion having a surface area greater than that of the connecting portion as seen in plan view; forming a second light-absorbing layer on the first light-absorbing layer; and removing the sacrificial layer to form a cavity between the support member and the structure including the insulating layer formed on the surface of the substrate. | 2014-02-06 |
| 20140038337 | BACKSIDE ILLUMINATED IMAGE SENSOR AND MANUFACTURING METHOD THEREOF - Disclosed is a backside illuminated image sensor including a light receiving element formed in a first substrate, an interlayer insulation layer formed on the first substrate including the light receiving element, a via hole formed through the interlayer insulation layer and the first substrate while being spaced apart from the light receiving element, a spacer formed on an inner sidewall of the via hole, an alignment key to fill the via hole, interconnection layers formed on the interlayer insulation layer in a multilayer structure in which a backside of a lowermost layer of the interconnection layers is connected to the alignment key, a passivation layer covering the interconnection layers, a pad locally formed on a backside of the first substrate and connected to a backside of the alignment key, and a color filter and a microlens formed on the backside of the first substrate corresponding to the light receiving element. | 2014-02-06 |
| 20140038338 | FRONT CONTACT SOLAR CELL WITH FORMED EMITTER - A bipolar solar cell includes a backside junction formed by an N-type silicon substrate and a P-type polysilicon emitter formed on the backside of the solar cell. An antireflection layer may be formed on a textured front surface of the silicon substrate. A negative polarity metal contact on the front side of the solar cell makes an electrical connection to the substrate, while a positive polarity metal contact on the backside of the solar cell makes an electrical connection to the polysilicon emitter. An external electrical circuit may be connected to the negative and positive metal contacts to be powered by the solar cell. The positive polarity metal contact may form an infrared reflecting layer with an underlying dielectric layer for increased solar radiation collection. | 2014-02-06 |
| 20140038339 | PROCESS OF MANUFACTURING CRYSTALLINE SILICON SOLAR CELL - A process of manufacturing a crystalline silicon solar cell includes forming a rough surface on a surface of the crystalline silicon wafer and an Al | 2014-02-06 |
| 20140038340 | METHOD FOR MANUFACTURING SOLAR CELL MODULE PROVIDED WITH AN EDGE SPACE - The solar cell module having a preferable edge space that prevents characteristics of a solar cell such as conversion efficiency from being deteriorated without making processes complicated is provided. In a method for manufacturing a solar cell module including a substrate glass, a first layer formed on the substrate glass and a second layer formed on the first layer, the method includes a step of forming a first edge space having a first width by removing the first layer and the second layer by the first width from an end part of the glass substrate and a step of forming a second edge space by removing only the second layer by a second width from the end part of the glass substrate, and the width of the second edge space is larger than the width of the first edge space. | 2014-02-06 |
| 20140038341 | METHOD OF PRODUCING SEMICONDUCTOR DEVICE, SOLID-STATE IMAGING DEVICE, METHOD OF PRODUCING ELECTRIC APPARATUS, AND ELECTRIC APPARATUS - There is provided a method of producing a semiconductor device. The method includes the steps of: forming a first hard mask having an opening above a substrate; forming a sacrificial film above a side surface of the opening of the first hard mask; forming a second hard mask in the opening having the sacrificial film above the side surface; removing the sacrificial film after the second hard mask is formed; ion implanting a first conductivity-type impurity through the first hard mask; and ion implanting a second conductivity-type impurity through the first and second hard masks. | 2014-02-06 |
| 20140038342 | BACK-ILLUMINATED TYPE SOLID-STATE IMAGING DEVICE - A method for manufacturing a back-illuminated type solid-state imaging device by (a) providing a substrate having, on a front surface side thereof, a semiconductor film on a semiconductor substrate with an insulation film therebetween; (b) forming in the semiconductor substrate a charge accumulation portion of a photoelectric conversion element that constitutes a pixel; (c) forming in the semiconductor film at least some transistors that constitute the pixel; and (d) forming on a rear surface side of the semiconductor substrate a rear surface electrode to which a voltage can be applied. | 2014-02-06 |
| 20140038343 | METHOD FOR MANUFACTURING SOLAR CELL MODULE PROVIDED WITH AN EDGE SPACE - The solar cell module having a preferable edge space that prevents characteristics of a solar cell such as conversion efficiency from being deteriorated without making processes complicated is provided. In a method for manufacturing a solar cell module including a substrate glass, a first layer formed on the substrate glass and a second layer formed on the first layer, the method includes a step of forming a first edge space having a first width by removing the first layer and the second layer by the first width from an end part of the glass substrate and a step of forming a second edge space by removing only the second layer by a second width from the end part of the glass substrate, and the width of the second edge space is larger than the width of the first edge space. | 2014-02-06 |
| 20140038344 | THIN FILM SOLAR CELLS - Embodiments relate to a method including forming a layer of copper zinc tin sulfide (CZTS) on a first layer of molybdenum (Mo) and annealing the CZTS layer and the first Mo layer to form a layer of molybdenum disulfide (MoS | 2014-02-06 |
| 20140038345 | Method of chalcogenization to form high quality cigs for solar cell applications - A method for high temperature selenization of Cu—In—Ga metal precursor films comprises ramping the precursor film to a temperature between about 300 C and about 400 C in a Se containing atmosphere and at a pressure between about 600 torr and 800 torr. A partial selenization is performed at a temperature between about 300 C and about 400 C in a Se-containing atmosphere. The film is then ramped to a temperature between about 400 C and about 550 C in a Se containing atmosphere and at a pressure between about 600 torr and 800 torr. The film is then annealed at a temperature between about 550 C and about 650 C in an inert gas. | 2014-02-06 |
| 20140038346 | THICK-FILM PASTE CONTAINING LEAD-VANADIUM-BASED OXIDE AND ITS USE IN THE MANUFACTURE OF SEMICONDUCTOR DEVICES - The present invention provides a thick-film paste for printing the front side of a solar cell device having one or more insulating layers and a method for doing so. The thick-film paste comprises a source of an electrically conductive metal and a lead-vanadium-based oxide dispersed in an organic medium. The invention also provides a semiconductor device comprising an electrode formed from the thick-film paste. | 2014-02-06 |
| 20140038347 | MANUFACTURING METHOD OF ELECTRODE OF SOLAR CELL - A manufacturing method of an electrode of a solar cell is provided. The manufacturing method of the electrode of the solar cell includes following steps. A laser doping process is performed to form a selective emitter on a substrate. A laser marking process is performed to form alignment markers on the substrate. The laser doping process and the laser marking process are performed in a same process chamber. An electrode screen printing process is performed to form an electrode on the selective emitter according to the alignment markers. Relative displacement between the alignment markers and the laser doping area (the selective emitter) is avoided so as to reduce the error of the subsequent screen printing process. | 2014-02-06 |
| 20140038348 | ETCHANT COMPOSITION AND MANUFACTURING METHOD FOR THIN FILM TRANSISTOR USING THE SAME - An etchant composition includes ammonium persulfate (((NH | 2014-02-06 |
| 20140038349 | DONER SUBSTRATES AND METHODS OF MANUFACTURING ORGANIC LIGHT EMITTING DISPLAY DEVICES USING DONOR SUBSTRATES - A donor substrate may include a base layer, a light to heat conversion layer disposed on the base layer, a buffer layer disposed on the light to heat conversion layer, an organic transfer layer disposed on the buffer layer, and a tightening member disposed on a peripheral portion of the organic transfer layer. The tightening member may include an adhesive film having an adhesion strength controlled by an irradiation of an ultraviolet ray. Process failures for manufacturing an organic light emitting display device may be prevented by the donor substrate, so that the organic light emitting display device may ensure improved performances. | 2014-02-06 |
| 20140038350 | N-Dopant for Carbon Nanotubes and Graphene - A composition and method for forming a field effect transistor with a stable n-doped nano-component. The method includes forming a gate dielectric on a gate, forming a channel comprising a nano-component on the gate dielectric, forming a source over a first region of the nano-component, forming a drain over a second region of the nano-component to form a field effect transistor, and exposing a portion of a nano-component of a field effect transistor to dihydrotetraazapentacene, wherein dihydrotetraazapentacene is represented by the formula: | 2014-02-06 |
| 20140038351 | METHOD FOR MANUFACTURING SEMICONDUCTOR DEVICE - In a transistor including an oxide semiconductor layer, an oxide insulating layer is formed so as to be in contact with the oxide semiconductor layer. Then, oxygen is introduced (added) to the oxide semiconductor layer through the oxide insulating layer, and heat treatment is performed. Through these steps of oxygen introduction and heat treatment, impurities such as hydrogen, moisture, a hydroxyl group, or hydride are intentionally removed from the oxide semiconductor layer, so that the oxide semiconductor layer is highly purified. | 2014-02-06 |
| 20140038352 | Non-volatile Resistive-Switching Memories - Non-volatile resistive-switching memories are described, including a memory element having a first electrode, a second electrode, a metal oxide between the first electrode and the second electrode. The metal oxide switches using bulk-mediated switching, has a bandgap greater than 4 electron volts (eV), has a set voltage for a set operation of at least one volt per one hundred angstroms of a thickness of the metal oxide, and has a leakage current density less than 40 amps per square centimeter (A/cm | 2014-02-06 |
| 20140038353 | SEMICONDUCTOR PACKAGES, METHODS OF MANUFACTURING THE SAME, AND SEMICONDUCTOR PACKAGE STRUCTURES INCLUDING THE SAME - A method of manufacturing a semiconductor package includes preparing a parent substrate including package board parts laterally spaced apart from each other, mounting a first chip including a through-via electrode on each of the package board parts, forming a first mold layer on the parent substrate having the first chips, planarizing the first mold layer to expose back sides of the first chips, etching the exposed back sides of the first chips to expose back sides of the through-via electrodes, forming a passivation layer on the planarized first mold layer, the etched back sides of the first chips, and the back sides of the through-via electrodes, and selectively removing the passivation layer to expose the back sides of the through-via electrodes. | 2014-02-06 |
| 20140038354 | SEMICONDUCTOR PACKAGE AND METHOD OF FABRICATING THE SAME - Disclosed are semiconductor packages and methods of fabricating the same. A method may include preparing a wiring board including a mounting region and a molding region surrounding the mounting region; forming a through-hole penetrating through the wiring board at the mounting region; mounting a semiconductor chip on the mounting region of the wiring board by a flip chip bonding method; and forming a molding covering the molding region of the wiring board and the semiconductor chip and filling the through-hole and a space between the semiconductor chip and the wiring board. The wiring board may have a first surface on which the semiconductor chip is mounted, and a second surface opposite to the first surface. A portion of the molding filling the through-hole has a surface coplanar with the second surface of the wiring board. | 2014-02-06 |
| 20140038355 | Flip-Chip Assembly Process for Connecting Two Components to Each Other - The invention relates to a flip-chip assembly process for connecting two microelectronic components ( | 2014-02-06 |
| 20140038356 | METHOD FOR PLATING A SEMICONDUCTOR PACKAGE LEAD - A method of forming a packaged semiconductor device includes loading an array of package sites in position for saw singulation, saw singulating the array of package sites, and performing a non-electrolytic plating operation on exposed lead tips of individual packages from the array of package sites as the array of package sites is saw singulated. | 2014-02-06 |
| 20140038357 | SINGULATED IC STIFFENER AND DE-BOND PROCESS - A method and apparatus is described for forming and using a stiffener for the production of thinned integrated circuits. In one embodiment, a handle can be bonded to an integrated circuit wafer before the wafer is thinned. Electrical couplings such as mounting balls can be attached to the wafer. Individual dice can be singulated from the wafer by dicing through the wafer and the handle, producing a wafer/handle assembly. The wafer/handle assembly can be mounted to a printed circuit board before the handle is de-bonded. | 2014-02-06 |
| 20140038358 | METHOD FOR CONTACTING AGGLOMERATE TERMINALS OF SEMICONDUCTOR PACKAGES - In fabricating a semiconductor device first layers are formed of sintered bondable and solderable metal on a carrier strip. The first layers are patterned into first pads and second pads. A set of first pads is surrounding each second pad. The first pads are spaced from the second pad by gaps. The patterned layers are formed of agglomerate metal vertically on the first layers of sintered bondable and solderable metal of the first pads and of the second pad. The second layers are formed of sintered bondable and solderable metal vertically on the layers of agglomerate metal of the first pads | 2014-02-06 |
| 20140038359 | Laser-Assisted Cleaving of a Reconstituted Wafer for Stacked Die Assemblies - A method of forming stacked die devices includes attaching first semiconductor die onto a wafer to form a reconstituted wafer, and then bonding second semiconductor die onto the first semiconductor die to form a plurality of singulated stacked die devices on the wafer. A support tape is attached to a bottomside of the second semiconductor die. A dicing tape is attached to the wafer. The wafer is laser irradiated before or after attachment of the dicing tape at intended dicing lanes that align with gaps between the first semiconductor die to mechanically weaken the wafer at the intended dicing lanes, but not cut through the wafer. The dicing tape is pulled to cleave the wafer into a plurality of singulated portions to form a plurality of singulated stacked die devices attached to the singulated wafer portions by the dicing tape. The support tape is removed prior to cleaving. | 2014-02-06 |
| 20140038360 | Apparatus and Methods for Molding Die on Wafer Interposers - Methods and apparatus for performing molding on die on wafer interposers. A method includes receiving an interposer assembly having a die side and an opposite side including two or more integrated circuit dies mounted on the die side of the interposer, the interposer assembly having spaces formed on the die side of the interposer between the two or more integrated circuit dies; mounting at least one stress relief feature on the die side of the interposer assembly in one of the spaces between the two or more integrated circuit dies; and molding the integrated circuit dies using a mold compound, the mold compound surrounding the two or more integrated circuit dies and the at least one stress relief feature. An apparatus is disclosed having integrated circuits mounted on a die side of an interposer, stress relief features between the integrated circuits and mold compound over the integrated circuits. | 2014-02-06 |
| 20140038361 | SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING THE SAME - Even when a stiffener is omitted, the semiconductor device which can prevent the generation of twist and distortion of a wiring substrate is obtained. | 2014-02-06 |
| 20140038362 | Self orienting micro plates of thermally conducting material as component in thermal paste or adhesive - The present invention relates generally to thermally-conductive pastes for use with integrated circuits, and particularly, but not by way of limitation, to self-orienting microplates of graphite. | 2014-02-06 |
| 20140038363 | TSOP WITH IMPEDANCE CONTROL - A semiconductor device of an illustrative embodiment includes a die, a lead frame including a plurality of leads having substantial portions arranged in a lead plane and electrically connected to the die. Most preferably, the package includes at least a substantial portion of one conductive element arranged in a plane positioned adjacent the lead frame and substantially parallel to the lead plane, the conductive element being capacitively coupled to the leads such that the conductive element and at least one of the leads cooperatively define a controlled-impedance conduction path, and an encapsulant which encapsulates the leads and the conductive element. The leads and, desirably, the conductive element have respective connection regions which are not covered by the encapsulant. | 2014-02-06 |
| 20140038364 | METHOD OF ENCAPSULATING A MICROELECTRONIC DEVICE - Method of encapsulating at least one microelectronic device, comprising at least the following steps:
| 2014-02-06 |
| 20140038365 | GRAPHENE-BASED EFUSE DEVICE - A method of forming a semiconductor device includes forming a field-effect transistor (FET), and forming a fuse which includes a graphene layer and is electrically connected to the FET. | 2014-02-06 |
| 20140038366 | METHOD FOR MANUFACTURING FLEXIBLE SEMICONDUCTOR DEVICE HAVING GATE ELECTRODE DISPOSED WITHIN AN OPENING OF A RESIN FILM - There is provided a flexible semiconductor device. The flexible semiconductor device of the present invention comprising a support layer, a semiconductor structure portion formed on the support layer, and a resin film formed on the semiconductor structure portion. The resin film comprises an opening formed by a laser irradiation therein, and also an electroconductive member which is in contact with the surface of the semiconductor structure portion is disposed within the opening of the resin film. | 2014-02-06 |
| 20140038367 | Method and Structure for Integrating Capacitor-less Memory Cell with Logic - Methods for fabricating integrated circuits include fabricating a logic device on a substrate, forming an intermediate semiconductor substrate on a surface of the logic device, and fabricating a capacitor-less memory cell on the intermediate semiconductor substrate. Integrated circuits with capacitor-less memory cells formed on a surface of a logic device are also disclosed, as are multi-core microprocessors including such integrated circuits. | 2014-02-06 |
| 20140038368 | EMBEDDED SILICON GERMANIUM N-TYPE FILED EFFECT TRANSISTOR FOR REDUCED FLOATING BODY EFFECT - A method for fabricating a semiconductor device includes forming a gate stack on an active region of a silicon-on-insulator substrate. The active region is within a semiconductor layer and is doped with an p-type dopant. A gate spacer is formed surrounding the gate stack. A first trench is formed in a region reserved for a source region and a second trench is formed in a region reserved for a drain region. The first and second trenches are formed while maintaining exposed the region reserved for the source region and the region reserved for the drain region. Silicon germanium is epitaxially grown within the first trench and the second trench while maintaining exposed the regions reserved for the source and drain regions, respectively. | 2014-02-06 |
| 20140038369 | METHOD OF FORMING FIN-FIELD EFFECT TRANSISTOR (finFET) STRUCTURE - Various embodiments include methods of forming semiconductor structures. In one embodiment, a method includes: providing a precursor structure including a substrate and a set of fins overlying the substrate; forming a dummy epitaxy between the fins in the set of fins; masking a first group of fins in the set of fins and the dummy epitaxy between the first group of fins in the set of fins; removing the dummy epitaxy to expose a second group of the fins; forming a first in-situ doped epitaxy between the exposed fins; masking the second group of fins in the set of fins and the in-situ doped epitaxy between the second group of fins in the set of fins; unmasking the first group of fins; removing the dummy epitaxy layer between the first group of fins to expose of the first group of fins; and forming a second in-situ doped epitaxy between the exposed fins. | 2014-02-06 |
| 20140038370 | THIN FILM TRANSISTOR SUBSTRATE AND METHOD FOR MANUFACTURING THE SAME - A thin film transistor substrate and a method for manufacturing the same are discussed, in which the thin film transistor comprises a gate line and a data line arranged on a substrate to cross each other; a gate electrode connected with the gate line below the gate line; an active layer formed on the gate electrode; an etch stopper formed on the active layer; an ohmic contact layer formed on the etch stopper; source and drain electrodes formed on the ohmic contact layer; and a pixel electrode connected with the drain electrode. It is possible to prevent a crack from occurring in the gate insulating film during irradiation of the laser and prevent resistance of the gate electrode from being increased. | 2014-02-06 |
| 20140038371 | THIN FILM TRANSISTOR LIQUID CRYSTAL DISPLAY ARRAY SUBSTRATE AND MANUFACTURING METHOD THEREOF - A TFT LCD array substrate and a manufacturing method thereof. The manufacturing method steps are: forming a thin film transistor on a substrate to form a gate line and a gate electrode connected with the gate line on the substrate; forming a gate insulating layer and a semiconductor layer on the gate electrode; forming an ohmic contact layer on the semiconductor layer; forming a transparent pixel electrode layer and a source/drain electrode metal layer in sequence on the resultant substrate, wherein the transparent pixel electrode layer is electrically insulated from the gate line and the gate electrode, and the transparent pixel electrode layer forms an ohmic contact with two sides of the semiconductor layer via the ohmic contact layer; and performing masking and etching with a gray tone mask with respect to the resultant substrate to form a transparent pixel electrode, a source/drain electrode and a data line simultaneously. | 2014-02-06 |
| 20140038372 | COMPOUND SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING THE SAME - Two layers of protection films are formed such that a sheet resistance at a portion directly below the protection film is higher than that at a portion directly below the protection film. The protection films are formed, for example, of SiN film, as insulating films. The protection film is formed to be higher, for instance, in hydrogen concentration than the protection film so that the protection film is higher in refractive index the protection film. The protection film is formed to cover a gate electrode and extend to the vicinity of the gate electrode on an electron supplying layer. The protection film is formed on the entire surface to cover the protection film. According to this configuration, the gate leakage is significantly reduced by a relatively simple configuration to realize a highly-reliable compound semiconductor device achieving high voltage operation, high withstand voltage, and high output. | 2014-02-06 |
| 20140038373 | SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD THEREOF - It is an object of the present invention to provide a semiconductor device where, even in a case of stacking a plurality of semiconductor elements provided over a substrate, the stacked semiconductor elements can be electrically connected through the substrate, and a manufacturing method thereof. According to one feature of the present invention, a method for manufacturing a semiconductor device includes the steps of selectively forming a depression in an upper surface of a substrate or forming an opening which penetrates the upper surface through a back surface; forming an element group having a transistor so as to cover the upper surface of the substrate and the depression, or the opening; and exposing the element group formed in the depression or the opening by thinning the substrate from the back surface. A means for thinning the substrate can be performed by partially removing the substrate by performing grinding treatment, polishing treatment, etching by chemical treatment, or the like from the back surface of the substrate. | 2014-02-06 |
| 20140038374 | METHOD FOR MANUFACTURING CMOS TRANSISTOR - A CMOS transistor and a method for manufacturing the same are disclosed. A semiconductor substrate having at least a PMOS transistor and an NMOS transistor is provided. The source/drain of the PMOS transistor comprises SiGe epitaxial layer. A carbon implantation process is performed to form a carbon-doped layer in the top portion of the source/drain of the PMOS transistor. A silicide layer is formed on the source/drain. A CESL is formed on the PMOS transistor and the NMOS transistor. The formation of the carbon-doped layer is capable of preventing Ge out-diffusion. | 2014-02-06 |
| 20140038375 | SEMICONDUCTOR DEVICE HAVING VERTICAL MOS TRANSISTOR AND METHOD FOR MANUFACTURING THE SEMICONDUCTOR DEVICE - A method for manufacturing a semiconductor device including a vertical MOS transistor, includes forming a trench for shallow trench isolation in a semiconductor substrate, and burying an element isolation insulating film in the trench, forming an insulating film to be a mask for forming a semiconductor pillar, in a region subjected to shallow trench isolation, etching the semiconductor substrate in the region subjected to the shallow trench isolation with the insulating film as a mask, and forming a semiconductor pillar for the vertical MOS transistor, implanting an impurity onto the semiconductor substrate, and forming a lower diffusion layer in the portion shallower than the depth of the shallow trench isolation, and forming a gate insulating film on the semiconductor substrate and the side surface of the semiconductor pillar for the vertical MOS transistor. | 2014-02-06 |
| 20140038376 | Method and Apparatus of Forming ESD Protection Device - The present disclosure provides a semiconductor device having a transistor. The transistor includes a source region, a drain region, and a channel region that are formed in a semiconductor substrate. The channel region is disposed between the source and drain regions. The transistor includes a first gate that is disposed over the channel region. The transistor includes a plurality of second gates that are disposed over the drain region. | 2014-02-06 |
| 20140038377 | COMPOUND SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD THEREOF - A first AlGaN layer formed over a substrate, a second AlGaN layer formed over the first AlGaN layer, an electron transit layer formed over the second AlGaN layer, and an electron supply layer formed over the electron transit layer are provided. A relationship of “0≦x1| 2014-02-06 | |
| 20140038378 | APPARATUS AND METHOD FOR A METAL OXIDE SEMICONDUCTOR FIELD EFFECT TRANSISTOR WITH SOURCE SIDE PUNCH-THROUGH PROTECTION IMPLANT - A metal oxide semiconductor field effect transistor (MOSFET) with source side punch-through protection implant. Specifically, the MOSFET comprises a semiconductor substrate, a gate stack formed above the semiconductor substrate, source and drain regions, and a protection implant. The semiconductor substrate comprises a first p-type doping concentration. The source and drain regions comprise an n-type doping concentration, and are formed on opposing sides of the gate stack in the semiconductor substrate. The protection implant comprises a second p-type doping concentration, and is formed in the semiconductor substrate under the source region and surrounds the source region in order to protect the source region from the depletion region corresponding to the drain region. | 2014-02-06 |
| 20140038379 | DUAL RESISTANCE HEATER FOR PHASE CHANGE DEVICES AND MANUFACTURING METHOD THEREOF - A dual resistance heater for a phase change material region is formed by depositing a resistive material. The heater material is then exposed to an implantation or plasma which increases the resistance of the surface of the heater material relative to the remainder of the heater material. As a result, the portion of the heater material approximate to the phase change material region is a highly effective heater because of its high resistance, but the bulk of the heater material is not as resistive and, thus, does not increase the voltage drop and the current usage of the device. | 2014-02-06 |
| 20140038380 | Multifunctional Electrode - A nonvolatile memory element is disclosed comprising a first electrode, a near-stoichiometric metal oxide memory layer having bistable resistance, and a second electrode in contact with the near-stoichiometric metal oxide memory layer. At least one electrode is a resistive electrode comprising a sub-stoichiometric transition metal nitride or oxynitride, and has a resistivity between 0.1 and 10 Ωcm. The resistive electrode provides the functionality of an embedded current-limiting resistor and also serves as a source and sink of oxygen vacancies for setting and resetting the resistance state of the metal oxide layer. Novel fabrication methods for the second electrode are also disclosed. | 2014-02-06 |
| 20140038381 | THERMALLY CONTROLLED REFRACTORY METAL RESISTOR - A structure and method of fabricating the structure includes a semiconductor substrate having a top surface defining a horizontal direction and a plurality of interconnect levels stacked from a lowermost level proximate the top surface of the semiconductor substrate to an uppermost level furthest from the top surface. Each of the interconnect levels include vertical metal conductors physically connected to one another in a vertical direction perpendicular to the horizontal direction. The vertical conductors in the lowermost level being physically connected to the top surface of the substrate, and the vertical conductors forming a heat sink connected to the semiconductor substrate. A resistor is included in a layer immediately above the uppermost level. The vertical conductors being aligned under a downward vertical resistor footprint of the resistor, and each interconnect level further include horizontal metal conductors positioned in the horizontal direction and being connected to the vertical conductors. | 2014-02-06 |
| 20140038382 | Structure And Method To Realize Conformal Doping In Deep Trench Applications - The specification and drawings present a new method, ASIC and computer/software related product (e.g., a computer readable memory) are presented for realizing conformal doping in embedded deep trench applications in the ASIC. A common SOI substrate with intrinsic or low dopant concentration is used for manufacturing such ASICs comprising a logic area having MOSFETs utilizing, for example, ultra thin body and box technology and an eDRAM area having deep trench capacitors with the conformal doping. | 2014-02-06 |
| 20140038383 | METHOD OF FABRICATING SEMICONDUCTOR DEVICE USING PHOTO KEY - A method of fabricating a semiconductor device includes providing a substrate that is divided into a first region on which a pattern layer is formed and a second region on which a photo key is formed. A silicon layer is formed on the first region and second region of the substrate. The silicon layer is patterned to form a hole exposing a photo key portion of the second region on which the photo key is formed. A buried oxide layer is formed to fill the hole exposing the photo key portion. The silicon layer is patterned by using the photo key formed under the buried oxide layer to form a silicon pattern layer. | 2014-02-06 |
| 20140038384 | Forming Metal-Insulator-Metal Capacitors Over a Top Metal Layer - A plurality of metal layers includes a top metal layer. An Ultra-Thick Metal (UTM) layer is disposed over the top metal layer, wherein no additional metal layer is located between the UTM layer and the top metal layer. A Metal-Insulator-Metal (MIM) capacitor is disposed under the UTM layer and over the top metal layer. | 2014-02-06 |
| 20140038385 | NONVOLATILE MEMORY DEVICES AND METHODS OF FABRICATING THE SAME - Nonvolatile memory devices and methods of fabricating the same, include, forming a transistor in a first region of a substrate, forming a contact which is connected to the transistor, forming an information storage portion, which is disposed two-dimensionally, in a second region of the substrate, sequentially forming a stop film and an interlayer insulating film which cover the contact and the information storage portion, forming a first trench, which exposes the stop film, on the contact, and forming a second trench which extends through the stop film to expose the contact, wherein a bottom surface of the first trench is lower than a bottom surface of the information storage portion. | 2014-02-06 |
| 20140038386 | REDUCING OR ELIMINATING PRE-AMORPHIZATION IN TRANSISTOR MANUFACTURE - A method for fabricating field effect transistors using carbon doped silicon layers to substantially reduce the diffusion of a doped screen layer formed below a substantially undoped channel layer includes forming an in-situ epitaxial carbon doped silicon substrate that is doped to form the screen layer in the carbon doped silicon substrate and forming the substantially undoped silicon layer above the carbon doped silicon substrate. The method may include implanting carbon below the screen layer and forming a thin layer of in-situ epitaxial carbon doped silicon above the screen layer. The screen layer may be formed either in a silicon substrate layer or the carbon doped silicon substrate. | 2014-02-06 |
| 20140038387 | METHOD FOR MANUFACTURING A SEMICONDUCTOR DEVICE - A semiconductor device may include, but is not limited to, a semiconductor substrate having a device isolation groove defining first to fourth device formation portions. The second device formation portion is separated from the first device formation portion. The third device formation portion extends from the first device formation portion. The third device formation portion is separated from the second device formation portion. The fourth device formation portion extends from the second device formation portion. The fourth device formation portion is separated from the first and third device formation portions. The third and fourth device formation portions are positioned between the first and second device formation portions. | 2014-02-06 |
| 20140038388 | METHOD FOR MANUFACTURING A SEMICONDUCTOR-ON-INSULATOR STRUCTURE HAVING LOW ELECTRICAL LOSSES, AND CORRESPONDING STRUCTURE - A manufacturing process for a semiconductor-on-insulator structure having reduced electrical losses and which includes a support substrate made of silicon, an oxide layer and a thin layer of semiconductor material, and a polycrystalline silicon layer interleaved between the support substrate and the oxide layer. The process includes a treatment capable of conferring high resistivity to the support substrate prior to formation of the polycrystalline silicon layer, and then conducting at least one long thermal stabilization on the structure at a temperature not exceeding 950° C. for at least 10 minutes. | 2014-02-06 |
| 20140038389 | PROCESSING METHOD OF SEMICONDUCTOR SUBSTRATE AND PROCESSED SEMICONDUCTOR SUBSTRATE PRODUCT - Provided is a processing method of a semiconductor substrate, including curing an adhesive layer by radiating UV rays at least on portions of a protective film that come into contact with semiconductor device main body parts before the protective film on which a UV curable adhesive layer is formed is attached to the semiconductor substrate having a first face on which a plurality of semiconductor devices, each of which includes the semiconductor device main body part and connection terminal parts, are formed in a state in which the semiconductor devices are separate from each other, and then attaching non-cured portions of the adhesive layer of the protective film to the outer peripheral portion of the semiconductor substrate, and a region of the semiconductor substrate positioned between the semiconductor devices, and bringing cured portions of the adhesive layer of the protective film into contact with the semiconductor device main body parts. | 2014-02-06 |
| 20140038390 | THROUGH SILICON VIA GUARD RING - The present disclosure relates to forming a plurality of through silicon vias guard rings proximate the scribes streets of a microelectronic device wafer. The microelectronic device wafer includes a substrate wherein the through silicon via guard ring is fabricated by forming vias extending completely through the substrate. The through silicon via guard rings act as crack arresters, such that defects caused by cracks resulting from the dicing of the microelectronic wafer are substantially reduced or eliminated. | 2014-02-06 |
| 20140038391 | III-Nitride Wafer Fabrication - A method for fabrication of a III-nitride film over a silicon wafer that includes forming control joints to allow for overall stress relief in the III-nitride film during the growth thereof. | 2014-02-06 |
| 20140038392 | SYSTEMS AND METHODS FOR LASER SPLITTING AND DEVICE LAYER TRANSFER - Methods and systems are provided for the split and separation of a layer of desired thickness of crystalline semiconductor material containing optical, photovoltaic, electronic, micro-electro-mechanical system (MEMS), or optoelectronic devices, from a thicker donor wafer using laser irradiation. | 2014-02-06 |
| 20140038393 | METHOD AND SYSTEM FOR ION-ASSISTED PROCESSING - A method of processing a substrate includes performing a first exposure that comprises generating a plasma containing reactive gas ions in a plasma chamber and generating a bias voltage between the substrate and the plasma chamber. The method also includes providing a plasma sheath modifier having an aperture disposed between the plasma and substrate and operable to direct the reactive gas ions toward the substrate, and establishing a pressure differential between the plasma chamber and substrate region while the reactive gas ions are directed onto the substrate. | 2014-02-06 |
| 20140038394 | METHOD AND APPARATUS OF FORMING COMPOUND SEMICONDUCTOR FILM - A method for forming a compound semiconductor film on a substrate to be processed, which includes: mounting a plurality of substrates to be processed on a substrate mounting jig; loading the substrates to be processed into a processing chamber; and heating the substrates to be processed loaded into the processing chamber; supplying a gas containing one element that constitutes a compound semiconductor, and another gas containing another element that constitutes the compound semiconductor and being different from the one element, into the processing chamber in which the substrates to be processed are loaded; and forming the compound semiconductor film on each of the substrates to be processed. | 2014-02-06 |
| 20140038395 | VAPOR DEPOSITION DEVICE AND VAPOR DEPOSITION METHOD - A vapor deposition device includes a vapor deposition chamber, a heating chamber, a mixing chamber, a first reservoir for storing trichlorosilane gas, and a second reservoir for storing silane gas that reacts with hydrochloric acid gas. The heating chamber communicates with the first reservoir and the mixing chamber, heats the trichlorosilane gas and then supplies the heated gas to the mixing chamber. The mixing chamber communicates with the second reservoir and the vapor deposition chamber, mixes the heated gas supplied from the heating chamber and the silane gas and then supplies the mixed gas to the vapor deposition chamber. A temperature in the heating chamber is higher than a temperature in the mixing chamber. | 2014-02-06 |
| 20140038396 | SEMICONDUCTOR DEVICE AND METHOD FOR MANUFACTURING SAME - According to one embodiment, a semiconductor device includes a substrate, a first stacked body, a memory film, a first channel body, a second stacked body, a gate insulating film and a second channel body. A step part is formed between a side face of the select gate and the second insulating layer. A film thickness of a portion covering the step part of the second channel body is thicker than a film thickness of a portion provided between the second insulating layers of the second channel body. | 2014-02-06 |
