| 06th week of 2014 patent applcation highlights part 23 |
| Patent application number | Title | Published |
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| 20140035596 | DISPLAY APPARATUS AND METHOD FOR DETECTING ERROR FROM VOLTAGE THEREOF - A display apparatus and a method for detecting a voltage error thereof, include a display unit which displays an image, a voltage supply which supplies a voltage to respective elements of the display apparatus, a detector which monitors a plurality of voltages supplied to the respective elements of the display apparatus and detects an error occurring from at least one of the plurality of voltages, and a controller which determines a location where an error has occurred if the error has occurred from at least one of the plurality of voltages according to a detection result of the detector. Thus, the display apparatus and method thereof determine whether a voltage error is present and determine the location of one or more errors without difficulty using a circuit for performing the self diagnosis. | 2014-02-06 |
| 20140035597 | Vehicle With Inductive Measuring Unit For Detecting Position Of Vehicle Part - The invention relates to a vehicle with an inductive measuring unit for detecting the distance between a measuring point P | 2014-02-06 |
| 20140035598 | METHOD FOR CONTACTLESS DETEMRINATION OF ELECTRICAL POTENTIAL USING OSCILLATING ELECTRODE, AND DEVICE - The electrical potential of an object is determined by providing a mechanically oscillating electrode located at a distance from the object and making the electrode mechanically oscillate. A change in a state of electric charge of the electrode over time and amplitudes of at least two frequency components during the change in the state of electric charge over time are determined. Based on the amplitudes, at least one parameter that forms part of the value of a capacitance of an arrangement formed by the electrode and the object is determined, so that the capacitance of the arrangement formed by the electrode and object can be determined based on the parameter. Finally, the electrical potential is determined from the change in the state of electric charge and the capacitance. | 2014-02-06 |
| 20140035599 | CAPACITIVE SENSOR SHEET PRODUCING METHOD AND CAPACITIVE SENSOR SHEET - A capacitive sensor sheet producing method for producing a capacitive sensor sheet uses a base having an insulative base layer on which a binder resin layer including conductive nanowires is formed. The conductive nanowires partially projecting from a surface of the binder resin layer. The method includes removing a binder resin from projections of conductive nanowires partially projected from a plurality of detection electrodes by implementing a surface etching and shaping treatment on a surface of the binder resin layer, or surface ends of at least partial detection electrodes of the plurality of detection electrodes, forming wiring lines of the conductive pattern layer, and connecting the wiring lines to the surface ends of at least partial detection electrodes in the pattern layer. The projections of the conductive nanowires removed the binder resin are put into contact with the connecting portions. | 2014-02-06 |
| 20140035600 | MULTI-FUNCTION SENSOR AND METHOD - A multi-function sensor apparatus includes multiple sensing electrodes and a control circuit adapted to receive signals from each of the sensing electrodes and to deem whether the sensing electrodes are in a touched state or an untouched state. The control circuit also is adapted to selectively provide an output based on the sensor's states and the manner in which the sensors came to be in such states. | 2014-02-06 |
| 20140035601 | ELECTROSTATIC CAPACITANCE DETECTION CIRCUIT AND INPUT DEVICE - An electrostatic capacitance detection circuit includes a charge amplifier that has an operational amplifier in which a capacitor is provided on a feedback path, and into which a signal including detection of electric charge of an inter-electrode capacitor of a sensor electrode and electric charge due to an external noise, and a selection switch that can switch a direction of a capacitor that is connected to input and output terminals of the charge amplifier through a feedback path that switches the direction of the capacitor depending on a direction of electric charge flowing in from a detection-side electrode of the sensor electrode, due to a drive signal applied to the sensor electrode. | 2014-02-06 |
| 20140035602 | ITO PATTERN FOR CAPACITIVE TOUCHSCREEN APPLICATIONS - A capacitive sensing structure is formed from first electrically conductive sensor structures electrically coupled to each other in a first direction, and second electrically conductive sensor structures electrically coupled to each other in a second direction. Each first electrically conductive sensor structure includes a first diamond-shaped central region with electrically coupled first finger structures extending away therefrom. Each second electrically conductive sensor structure includes a second diamond-shaped central region with electrically conducting second finger structures extending away therefrom. Each second finger structure extends between two adjacent ones of the first finger structures. Floating structures may be included within an opening formed in the first diamond shaped central region. Floating structures may further be included between the first and second finger structures. | 2014-02-06 |
| 20140035603 | Printed Stretch Sensor - Disclosed is a patterned article comprising: (1) a deformable nonconductive substrate; (2) an imagewise pattern thereon of a conductive stretchable ink; and (3) an external circuit connecting the imagewise pattern, the external circuit being capable of measuring the electrical resistance across regions of the deformable nonconductive substrate and determining the degree of deformation thereof. | 2014-02-06 |
| 20140035604 | DEVICE AND METHOD FOR DISPENSING FLUID FROM AN INFUSION PUMP - The present disclosure is directed towards a compact, modular infusion pump and a delivery mechanism for accurate dispensing of very small amounts of medication. The infusion pump comprises a tubular, curved medication reservoir, and a flexible, one-piece drive train configured to push very small amounts of medication out of the medication reservoir. A method of measuring a level of medication inside the medication reservoir or cross-checking the accuracy of medication delivery is also described. | 2014-02-06 |
| 20140035605 | Shunt Resistor Integrated in a Connection Lug of a Semiconductor Module and Method for Determining a Current Flowing Through a Load Connection of a Semiconductor Module - A semiconductor module includes a housing, a circuit carrier having an insulation carrier and a metallization layer applied to a side of the insulation carrier, and a connection lug having a first and second load connection sections and a shunt resistor region. The shunt resistor region is electrically arranged between the first and second load connection sections and connected in series with the first and second load connection sections. The shunt resistor region has an ohmic resistance with a temperature coefficient having an absolute value of less than 0.00002/K at a temperature of 20° C. The connection lug in the region of the second load connection section is electrically conductively connected to a first section of the metallization layer by a first cohesive connection. The first load connection section is led out from the housing and has a free end arranged on the outer side of the housing. | 2014-02-06 |
| 20140035606 | TEST PLATFORM - A test platform includes a supporting member, a first slide rail located below the supporting member, and a conductive second slide rail located below the first slide rail for being electrically connected to a power source. A wireless router and an uninterruptible power supply (UPS) electrically connected to the wireless router are mounted on a bottom of the supporting member. A network socket is mounted on the supporting member and electrically connected to the wireless router. A power socket is mounted on the supporting member and electrically connected to the UPS. A number of first wheels are rotatably mounted on the bottom of the supporting member. Each first wheel rests on and rolls along the first slide rail. A number of conductive second wheels are rotatably mounted on a bottom of the UPS. Each second wheel rests on and rolls along the second slide rail. | 2014-02-06 |
| 20140035607 | Handheld Devices, Systems, and Methods for Measuring Parameters - Embodiments of the present disclosure are generally directed to handheld systems, individual components, and methods of using such systems and components for measuring parameters, such as electrical, mechanical, and physical measurement parameters. In one embodiment of the present disclosure, a host handheld device generally includes a measuring system for measuring a first parameter, wherein the first parameter is an electrical parameter, and a receiving system for receiving at least a second parameter from a separate module device. | 2014-02-06 |
| 20140035608 | SYSTEM AND METHOD FOR TESTING AN ELECTRONIC DEVICE - Adapters for electrostatic discharge probe tips are disclosed herein. An embodiment of the adapter includes an attachment device that is attachable to the tip of the probe. A first conductor is affixed to the attachment device so that the first conductor contacts the tip when the attachment device is attached to the tip of the probe. A second conductor extends between the first electrical conductor and a point external to the attachment device. | 2014-02-06 |
| 20140035609 | PROBE CARD WITH SIMPLIFIED REGISTRATION STEPS AND MANUFACTURING METHOD THEREOF - A probe card is provided. The probe card includes a probe module and a first carrier board. The probe module has a plurality of probes. The probe module is disposed on the first carrier board. The first carrier board is at least partially light-transmitted and has a plurality of vias and a plurality of conductive fillers. The vias are filled with the conductive fillers, respectively. The probe module is electrically connected to the conductive fillers. With the first carrier board being partially light-transmitted, not only is it feasible to simplify the steps of registering the probe card and a device under test, but it is also feasible for an inspector to inspect the contact between the probe card and the device under test synchronously. | 2014-02-06 |
| 20140035610 | SYSTEM AND METHOD TO TEST A SEMICONDUCTOR POWER SWITCH - Testing assembly for testing a singulated semiconductor die comprising a power component. The assembly comprises an current input connectable to a current source, for providing a current greater than 50 Amps to the power component; a signal output connectable to a signal analyzer, for receiving signals representing a sensed parameter of the power component sensed when the current is provided; a first contact unit, adapted to support the semiconductor die; a second contact unit, movably mounted relative to the first contact unit; and at least an electrically-conductive resilient sheath, adapted to be sandwiched between the semiconductor die and the second contact unit when the second contact unit is brought toward the semiconductor die during a test, the sheath forming part of an electrical path from the current input through at least a part of the die when thus sandwiched. | 2014-02-06 |
| 20140035611 | POWER SWITCH WAFER TEST METHOD - A wafer test method of a power switch wherein a main IGBT and a current detecting IGBT that detects a current value of the main IGBT are integrally formed on the same semiconductor substrate is such that there is provided resistance means that causes an emitter current of the current detecting IGBT to flow through an emitter terminal of the main IGBT, the main IGBT and current detecting IGBT are energized simultaneously, thereby applying a constant current to a common collector terminal of the main IGBT and current detecting IGBT, and a current ratio (main current/detected current) between a main current of the main IGBT and a detected current of the current detecting IGBT is calculated from the current flowing through the current detecting IGBT, obtained from the voltage across the resistance means, and the constant current. | 2014-02-06 |
| 20140035612 | Method and Measuring Device for Determining a State of a Semiconductor Material of a Chemosensitive Field-Effect Transistor that has been Tested and Delivered by a Manufacturer - The disclosure relates to a method for determining a state of a semiconductor material of a chemosensitive field-effect transistor that has been tested and delivered by a manufacturer. The chemosensitive field-effect transistor includes a source contact, a drain contact, a gate contact of a chemosensitive gate electrode, and a substrate contact. The method includes applying a voltage between the gate contact and a reference potential to the field-effect transistor that has been tested and delivered by the manufacturer. The method further includes detecting a current between the source contact and the substrate contact, and determining the state using the voltage and the current. | 2014-02-06 |
| 20140035613 | IDENTIFICATION CIRCUIT AND METHOD FOR GENERATING AN IDENTIFICATION BIT USING PHYSICAL UNCLONABLE FUNCTIONS - An embodiment of the present invention is an identification circuit installed on an integrated circuit for generating an identification bit, comprising a first circuit to generate a first output signal that is based on random parametric variations in said first circuit, a second circuit to generate a second output signal that is based on random parametric variations in said second circuit, a third circuit capable to be operated in an amplification mode and in a latch mode, wherein in said amplification mode the difference between the first output signal and the second output signal is amplified to an amplified value and, wherein in said latch mode said amplified value is converted into a digital signal. | 2014-02-06 |
| 20140035614 | LOGIC CIRCUITS USING NEURISTORS - Logic circuits using neuristors is described. In an example, a circuit includes a plurality of neuristors each producing an output voltage spike in response to a super-threshold input voltage. A plurality of impedances couple the plurality of neuristors to form at least one input and an output, the output selectively providing an output voltage spike based on a logical operation of at least one input voltage at the at least one input. | 2014-02-06 |
| 20140035615 | SYSTEM FOR TRANSMISSION LINE TERMINATION BY SIGNAL CANCELLATION - A communication system having first and second states for use with a shared transmission line composed of at least two conductors and composed of first and second transmission line segments connected to each other at a single connection point. In the first state, a termination is coupled to the single connection point and is operative to at least attenuate a signal propagated between the first and second segments. In the second state, a driver is coupled to the connection point and is operative to conduct a signal over the first and second segments. | 2014-02-06 |
| 20140035616 | RECONFIGURABLE INTEGRATED CIRCUIT DEVICE AND WRITING METHOD THEREOF - A reconfigurable integrated circuit device includes a memory unit for storing configuration information. The memory unit has a nonvolatile memory transistor having a gate connected to a first wire, a first terminal connected to a second wire, and a second terminal connected to a third wire. The memory unit also includes a switch circuit connected to the third wire. The switch circuit alters the configuration of the integrated circuit device by, for example, opening and closing to make wiring connections or disconnections. The integrated circuit device additionally includes a data supply circuit for supplying bit data and a first power supply circuit for supplying voltages to the first wire for storing bit data in the first nonvolatile memory transistor and for storing bit data as a charge level on the third wire. | 2014-02-06 |
| 20140035617 | SPIN TRANSFER TORQUE BASED MEMORY ELEMENTS FOR PROGRAMMABLE DEVICE ARRAYS - Disclosed herein are semiconductor device arrays, such as, Field Programmable Gate Arrays (FPGAs) and Complex Programmable Logic Arrays (CPLAs) that use high-density Spin Transfer Torque (STT)-based memory elements. STT-based memory elements can either be stand-alone FPGAs/CPLAs, or can be embedded in microprocessors and/or digital signal processing (DSP) system-on-chip (SoC) to provide design flexibility for implementing low power, scalable, secure and reconfigurable hardware architecture. Because the configuration is stored on the FPGA/CPLA die itself, the need for loading the configuration from external storage every time is eliminated when the device is powered on. In addition to instant startup, eliminating configuration I/O traffic results in power savings and possible pin count reduction. Security is greatly improved by eliminating the need to store configuration data in an external memory. | 2014-02-06 |
| 20140035618 | CIRCUIT HAVING PROGRAMMABLE MATCH DETERMINATION FUNCTION, AND LUT CIRCUIT, MUX CIRCUIT AND FPGA DEVICE WITH SUCH FUNCTION AND METHOD OF DATA WRITING - A circuit according to embodiments includes: a plurality of bit-string comparators each of which includes a plurality of single-bit comparators each of which includes first and second input terminals, first and second match-determination terminals, and a memory storing data and inverted data in a pair, the first input terminal being connected to a respective search line, the second input terminal being connected to an inverted search line being paired with the respective search line, and a matching line connecting the first and second match-determination terminals of the single-bit comparators; a pre-charge transistor of which source is connected to a supply voltage line; a common matching line connected to a drain of the pre-charge transistor and the matching lines of the bit-string comparators; and an output inverter of which input is connected to the common matching line. | 2014-02-06 |
| 20140035619 | SEMICONDUCTOR INTEGRATED CIRCUIT, PROGRAMMABLE LOGIC DEVICE, METHOD OF MANUFACTURING SEMICONDUCTOR INTEGRATED CITCUIT - According to one embodiment, a semiconductor integrated circuit includes nonvolatile memory areas, each includes a first nonvolatile memory transistor, a second nonvolatile memory transistor and an output line, the first nonvolatile memory transistor includes a first source diffusion region, a first drain diffusion region and a first control gate electrode, the second nonvolatile memory transistor includes a second source diffusion region, a second drain diffusion region and a second control gate electrode, the output line connected the first drain diffusion region and the second drain diffusion region, and logic transistor areas, each includes a logic transistor, the logic transistor includes a third source diffusion region, a third drain diffusion region and a first gate electrode. | 2014-02-06 |
| 20140035620 | LOGIC GATE - A logic gate including a first resistive non-volatile memory device and a second resistive non-volatile memory device is provided. When top electrodes of the first and the second resistive non-volatile memory devices are coupled to an output terminal of the logic gate, bottom electrodes of the first and the second resistive non-volatile memory devices are respectively coupled to a first input terminal and a second input terminal of the logic gate. When the bottom electrodes of the first and the second resistive non-volatile memory devices are coupled to the output terminal of the logic gate, the top electrodes of the first and the second resistive non-volatile memory devices are respectively coupled to the first input terminal and the second input terminal of the logic gate. | 2014-02-06 |
| 20140035621 | INVERTER, NAND GATE, AND NOR GATE - Disclosed are an inverter, a NAND gate, and a NOR gate. The inverter includes: a pull-up unit constituted by a second thin film transistor outputting a first power voltage to an output terminal according to a voltage applied to a gate; a pull-down unit constituted by a fifth thin film transistor outputting a ground voltage to the output terminal according to an input signal applied to a gate; and a pull-up driver applying a second power voltage or the ground voltage to the gate of the second thin film transistor according to the input signal. | 2014-02-06 |
| 20140035622 | INVERTER, NAND GATE, AND NOR GATE - Disclosed are an inverter, a NAND gate, and a NOR gate. The inverter includes: a pull-up unit constituted by a second thin film transistor outputting a first power voltage to an output terminal according to a voltage applied to a gate; a pull-down unit constituted by a fifth thin film transistor outputting a ground voltage to the output terminal according to an input signal applied to a gate; and a pull-up driver applying a second power voltage or the ground voltage to the gate of the second thin film transistor according to the input signal. | 2014-02-06 |
| 20140035623 | COMPARATOR WITH TRANSITION THRESHOLD TRACKING CAPABILITY - A comparator is provided having a voltage generator, having an output terminal for providing a reference voltage. The comparator also has a buffer unit, providing an output signal according to a first input signal and the reference voltage; wherein the voltage generator provides the reference voltage according to a second input signal, and the output signal represents a compare result of the first and second input signals. | 2014-02-06 |
| 20140035624 | CIRCUIT - In accordance with various embodiments, a circuit is provided, including an output node, a first potential varying stage, which is designed to couple the output node to a supply potential in reaction to an input signal, and a second potential varying stage, which is designed to couple the output node to the supply potential if the difference between the potential of the output node and the supply potential lies below a predefined threshold value. | 2014-02-06 |
| 20140035625 | METHOD AND APPARATUS FOR CONSTANT OUTPUT IMPEDANCE, VARIABLE PRE-EMPHASIS DRIVE - A population of drivers is provided in parallel to a driver output and a population of pre-emphasis path drivers is provided in parallel to the driver output. The population of drivers is updated and the population of pre-emphasis path drivers is updated in an inverse relation to the updating of the population of pre-emphasis path drivers. Optionally, the population of drivers has an initial value of n and the population of pre-emphasis path drivers has an initial value of m, and the sum of n and m is P. Optionally, the updated population of n is n′ and the updated population of m is m′, and n′ is approximately equal to P−m′. | 2014-02-06 |
| 20140035626 | System and Method for Bootstrapping a Switch Driver - In accordance with an embodiment, a driver circuit includes a low-side driver having a first output configured to be coupled to a control node of a first semiconductor switch, and a reference input configured to be coupled to a reference node of the first semiconductor switch. The low-side driver also includes a first capacitor coupled between an output node of the first semiconductor switch and a first node, a first diode coupled between the first node and a first power input of the driver, and a second capacitor coupled between the first power input of the low-side driver and the reference node of the first semiconductor switch. | 2014-02-06 |
| 20140035627 | SiC Proportional Bias Switch Driver Circuit with Current Transformer - A switch bias system is provided that includes a silicon on carbide (SiC) bipolar junction transistor (BJT) switch comprising a base, emitter, and collector; an energy storage circuit coupled to the collector of the SiC BJT switch, the energy storage circuit supplying current flow to the collector of the SiC BJT switch; a current transformer circuit coupled to the emitter, the current transformer circuit configured to sense current flow through the emitter of the SiC BJT switch; and a proportional bias circuit configured to generate a bias current to the base of the SiC BJT switch, the bias current set to a proportion of the sensed current flow through the emitter of the SiC BJT switch. | 2014-02-06 |
| 20140035628 | Regulator Using Smart Partitioning - A disclosed apparatus includes a converter for receiving a supply and regulating a load. The converter uses a gate driver that is controlled by a controller via a control loop. The control loop controls the converter in response to a feedback signal. The controller is located on a first integrated circuit and the gate driver is located on as second integrated circuit. A process geometry of the first integrated circuit is finer than a process geometry of the second integrated circuit. | 2014-02-06 |
| 20140035629 | DRIVER APPARATUS FOR SWITCHING ELEMENTS - In a driver apparatus for driving a voltage-controlled switching element, an absolute value of a voltage difference between a voltage at a reference terminal that is one of terminals of a current path of the switching element and a voltage at the switching control terminal of the switching element is clamped at a clamping voltage greater than a threshold voltage. A voltage greater than the threshold voltage applied to the switching control terminal allows the switching element to be turned on. When the current flowing through the switching element becomes equal to or greater than a clamp threshold after the switching element transitions from an off-state to an on-state, a voltage-drop-rate at which the absolute value is decreased to the clamping voltage is decreased. | 2014-02-06 |
| 20140035630 | VERTICALLY INTEGRATED SYSTEMS - Embodiments of the present invention provide an integrated circuit system including a first active layer fabricated on a front side of a semiconductor die and a second pre-fabricated layer on a back side of the semiconductor die and having electrical components embodied therein, wherein the electrical components include at least one discrete passive component. The integrated circuit system also includes at least one electrical path coupling the first active layer and the second pre-fabricated layer. | 2014-02-06 |
| 20140035631 | TUNABLE CAPACITANCE CONTROL CIRCUIT AND TUNABLE CAPACITANCE CONTROL METHOD - Disclosed herein are a tunable capacitance control circuit and a tunable capacitance control method. The tunable capacitance control method is a tunable capacitance control method by a tunable capacitance control circuit including an MIM capacitor, a plurality of FET switches, and a control unit, wherein the control unit outputs control signals allowing only one of the plurality of (n) FET switches to be switched on and the remaining (n-1) FET switches to be switched off to the plurality of FET switches, thereby obtaining a desired tunable capacitance value. | 2014-02-06 |
| 20140035632 | PHASE-LOCKED LOOP - A phase-locked loop for generating an output signal including a signal generator arranged to generate an output, a comparison unit arranged to compare the output with a reference signal so as to provide a digital signal, and a loop filter arranged to generate a control signal for controlling the signal generator in dependence on the digital signal. The loop filter includes a proportional path having a digital filter arranged to generate a first component of the control signal for controlling the phase of the output generated by the signal generator, and an analogue integral path arranged to generate a second component of the control signal for controlling the frequency of the output generated by the signal generator. | 2014-02-06 |
| 20140035633 | AUTONOMOUS INITIALIZATION METHOD OF FACING PORT OF SEMICONDUCTOR INTEGRATED CIRCUIT AND SEMICONDUCTOR INTEGRATED CIRCUIT - On a transmission path connecting a first semiconductor integrated circuit that is started by a system management apparatus and a second semiconductor integrated circuit that is not started by the system management apparatus, when connection of the first semiconductor integrated circuit to the second semiconductor integrated circuit is detected, after being turned to a first signal state for detecting a valid lane, each lane on the transmission path is turned to a second signal state corresponding to each bit of initial setting code. In the second semiconductor integrated circuit, the first and second signal states are detected for each lane of the transmission path. Based on the detected signal state, after detecting the first signal state, the second signal state is detected and each bit value of the initial setting code is decoded. Based on the decoded initial setting code, an initialization process is executed. | 2014-02-06 |
| 20140035634 | POWER ON RESET GENERATION CIRCUITS IN INTEGRATED CIRCUITS - Integrated Circuits (ICs) comprising circuits configured to generate a power on reset (POR) pulse are disclosed. An IC comprises a power supply sense circuit configured to generate a sense signal in response to a transition of a power supply signal from a first level to a second level, and a pulse generation circuit coupled with the power supply sense circuit. The pulse generation circuit is configured to generate a power on reset (POR) pulse of a threshold duration based on the sense signal. The IC further includes a reset generation circuit coupled with the pulse generation circuit to receive the POR pulse. The reset generation circuit is configured to generate a reset pulse based on the POR signal and of at least one control signal, where the reset pulse is configured to be utilized to perform a reset of one or more elements of the integrated circuit. | 2014-02-06 |
| 20140035635 | APPARATUS FOR GLITCH-FREE CLOCK SWITCHING AND A METHOD THEREOF - The invention relates to an apparatus and a method for glitch-free clock switching. In one embodiment this is accomplished by a first clock source, one or more second clock source and a clock switching control device configured to synchronize the receive input clock from the first clock source and the second clock source, and output at least one of the them according to control signal selection. | 2014-02-06 |
| 20140035636 | CLOCK SYNCHRONIZATION CIRCUIT - A method of synchronizing clock signals may include generating a replicated delay associated with a delay of a clock signal path. The clock signal path may be associated with communication of a slave clock signal by a master block of a circuit to a slave block of the circuit. The method may further include selecting the slave clock signal from one of multiple clock signals based on the replicated delay. Each of the multiple clock signals may have a same frequency and a different phase. | 2014-02-06 |
| 20140035637 | REFERENCE CLOCK COMPENSATION FOR FRACTIONAL-N PHASE LOCK LOOPS (PLLS) - In one embodiment, a method includes determining a phase difference between a reference clock and a feedback clock in even and odd cycles for a phase lock loop (PLL). The even and odd cycles are alternating clock periods. A delta value based on the phase difference is determined. The method then adjusts a division value used by a divider to generate the feedback clock during the even cycle based on the delta value where the delta value is of a first polarity. Also, the method adjusts the division value used by the divider to generate the feedback clock during the odd cycle based on the delta value where the delta value is of a second polarity. | 2014-02-06 |
| 20140035638 | SYSTEM AND METHOD FOR CLOCK SIGNAL GENERATION - A clock signal generation system is provided that includes a clock signal generating circuit arranged to provide a first clock signal having a selectable first clock rate; a divider circuit connected to receive the first clock signal and arranged to generate, depending on a division factor, a second clock signal from the first clock signal, having a constant second clock rate and being synchronized with the first clock signal; and a controller module connected to the divider circuit and arranged to change the division factor when a different first clock rate is selected, to keep the second clock rate constant and the second clock signal synchronized with the first clock signal. | 2014-02-06 |
| 20140035639 | SEMICONDUCTOR DEVICE GENERATING INTERNAL CLOCK SIGNAL HAVING HIGHER FREQUENCY THAN THAT OF INPUT CLOCK SIGNAL - Disclosed herein is a device that includes: a plurality of delay circuits each including an input node, an output node, a first power node and a second power node, and a control circuit. The delay circuits are coupled in series with the input node of a leading delay circuit receiving a first clock signal and the output node of a last delay circuit producing a second clock signal. The control circuit coupled to receive the first and second clock signals to control an operating voltage supplied between the first and second power lines. The first power nodes of the delay circuits are connected in common to the first power line, and the second power nodes the delay circuits are connected in common to the second power line. | 2014-02-06 |
| 20140035640 | APPARATUSES AND METHODS FOR ALTERING A FORWARD PATH DELAY OF A SIGNAL PATH - Apparatuses and methods related to altering the timing of command signals for executing commands is disclosed. One such method includes calculating a forward path delay of a clock circuit in terms of a number of clock cycles of an output clock signal provided by the clock circuit and adding a number of additional clock cycles of delay to a forward path delay of a signal path. The forward path delay of the clock circuit is representative of the forward path delay of the signal path and the number of additional clock cycles is based at least in part on the number of clock cycles of forward path delay. | 2014-02-06 |
| 20140035641 | DUAL MODE PHASE DETECTION - A method of measuring a phase difference for use in a phase locked loop (PLL) that includes a binary phase detector (BPD), a time-to-digital converter (TDC) and a signal generator, the phase difference being that between a reference signal and a generated signal output from the signal generator. The method includes inputting the reference signal and the generated signal into the TDC; measuring the magnitude of the phase difference at the TDC; if the measured magnitude of the phase difference is less than a threshold value, operating the PLL according to a first operational mode in which the output of the BPD controls the signal generator; and if the measured magnitude of the phase difference is greater than the threshold value, operating the PLL according to a second operational mode in which the output of the TDC and the BPD controls the signal generator. | 2014-02-06 |
| 20140035642 | Techniques for Aligning and Reducing Skew in Serial Data Signals - A circuit includes first and second aligner circuits and a deskew circuit. The first aligner circuit is operable to align a first input serial data signal with a control signal to generate a first aligned serial data signal. The second aligner circuit is operable to align a second input serial data signal with the control signal to generate a second aligned serial data signal. The deskew circuit is operable to reduce skew between the first and the second aligned serial data signals to generate first and second output serial data signals. | 2014-02-06 |
| 20140035643 | EQUALIZED RISE AND FALL SLEW RATES FOR A BUFFER - Aspects of the invention provide for equalizing rise and fall slew rates at an output for a buffer. In one embodiment, a method includes: measuring, simultaneously, rise and fall slew rates at an input of the buffer and rise and fall slew rates at the output of the buffer; generating a slew reference based on at least one of the rise slew rate or the fall slew rate at the input of the buffer; comparing the rise slew rate and the fall slew rate at the output of the buffer to the slew reference; and generating at least one of a rise control signal or a fall control signal for adjusting at least one of the rise slew rate or the fall slew rate at the output of the buffer. | 2014-02-06 |
| 20140035644 | ADAPTIVE MULTI-STAGE SLACK BORROWING FOR HIGH PERFORMANCE ERROR RESILIENT COMPUTING - Adaptive scaling digital techniques attempt to place the system close to the timing failure so as to maximize energy efficiency. Rapid recovery from potential failures is usually by slowing the system clock and/or providing razor solutions (instruction replay.) These techniques compromise the throughput. This application presents a technique to provide local in-situ fault resilience based on dynamic slack borrowing. This technique is non-intrusive (needs no architecture modification) and has minimal impact on throughput. | 2014-02-06 |
| 20140035645 | SYSTEM AND METHOD TO PERFORM SCAN TESTING USING A PULSE LATCH WITH A BLOCKING GATE - A system and method to perform scan testing using a pulse latch with a blocking gate is disclosed. In a particular embodiment, a scan latch includes a pulse latch operable to receive data while a pulse clock signal has a first logical clock value and a blocking gate coupled to an output of the pulse latch. The blocking gate is operable to propagate the data from the output of the pulse latch while the pulse clock signal has a second logical clock value. | 2014-02-06 |
| 20140035646 | Phase Shift Generating Circuit - A phase shift generation circuit has an edge detector for generating first and second edge signals indicating first and second edges of an input pulse signal. The circuit comprises a divide by N circuit that divides the frequency of a first clock signal by N. The circuit comprises a pulse counter, which receives the first edge signal and the second clock signal, and outputs a group of signals representing the number of the second clock pulses between occurrences of the first edge signal. The circuit has a first recycling timer that outputs a group of pulses as a uniformly spaced group across the period of the input pulse. The circuit also has a second recycling timer that outputs a group of pulses as a uniformly spaced group across the period of the input pulse. The first and second recycling timers are used to generate a phase shifted output pulse. | 2014-02-06 |
| 20140035647 | APPARATUS AND METHOD FOR ENHANCING STABILITY OF ELECTRONIC DEVICE HAVING A HIGH-ACCURACY CLOCK - An embodiment relates to an apparatus and method for enhancing stability of electronic device having a high-accuracy clock. Specifically, there is disclosed a controller for an electronic device, including a control core configured to generate a signal for controlling operation of the electronic device, an internal clock source coupled to the control core and configured to provide a high-speed internal (HSI) clock signal to the control core to act as a drive signal, and at least one timing-sensitive component coupled to an external clock source of the controller and configured to receive a high-speed external (HSE) clock signal generated by an external clock source to act as a drive signal. There is further disclosed a method for driving such kind of controller. According to an embodiment, the high-clock-accuracy requirement and the stability and robustness requirement can be satisfied simultaneously. | 2014-02-06 |
| 20140035648 | TIMER MATCH DITHERING - A counter/timer circuit and a method of operating the counter/timer circuit are described. In one embodiment, a method of operating a counter/timer circuit involves determining a match condition by comparing a count value of the counter/timer circuit with a value stored in a match register of the counter/timer circuit and delaying an assertion of the match condition based on a value programmed in a match companion register of the counter/timer circuit. The match companion register is associated with the match register. Other embodiments are also described. | 2014-02-06 |
| 20140035649 | TUNED RESONANT CLOCK DISTRIBUTION SYSTEM - A tunable clock distribution system that includes a clock network including an inductive circuit and a capacitive circuit where at least one of the capacitive circuit or the inductive circuit is tunable. The tunable clock distribution system may further include a driving circuit and a phase determiner. The driving circuit may be configured to receive a clock signal and to distribute a resonant clock signal based on the clock signal to the clock network. The phase determiner may be configured to receive the clock signal and the resonant clock signal and to determine whether the clock signal and the resonant clock signal have a predetermined phase difference. When the clock signal and the resonant clock signal do not have the predetermined phase difference, the phase determiner may be configured to tune at least one of the capacitive circuit or the inductive circuit. | 2014-02-06 |
| 20140035650 | LOW-LATENCY, FREQUENCY-AGILE CLOCK MULTIPLIER - In a first clock frequency multiplier, multiple injection-locked oscillators (ILOs) having spectrally-staggered lock ranges are operated in parallel to effect a collective input frequency range substantially wider than that of a solitary ILO. After each input frequency change, the ILO output clocks may be evaluated according to one or more qualifying criteria to select one of the ILOs as the final clock source. In a second clock frequency multiplier, a flexible-injection-rate injection-locked oscillator locks to super-harmonic, sub-harmonic or at-frequency injection pulses, seamlessly transitioning between the different injection pulse rates to enable a broad input frequency range. The frequency multiplication factor effected by the first and/or second clock frequency multipliers in response to an input clock is determined on the fly and then compared with a programmed (desired) multiplication factor to select between different frequency-divided instances of the frequency-multiplied clock. | 2014-02-06 |
| 20140035651 | Sensor Circuit for Detecting the Setting of an Integrated Circuit - Methods and apparatus selecting settings for circuits according to various aspects of the present invention may operate in conjunction with a measurement element connected to the circuit. The circuit may include a voltage source adapted to supply a voltage to the measurement element. The voltage may be substantially independent of the characteristics of the measurement element. The circuit may further include a measurement sensor responsive to a current in the measurement element. The measurement sensor may generate a control signal according to the current in the measurement element. | 2014-02-06 |
| 20140035652 | SIGNAL DIRECTING MEANS FOR DIVIDING AN INPUT SIGNAL INTO AT LEAST TWO OUTPUT SIGNALS OR COMBINING AT LEAST TWO INPUT SIGNALS INTO ONE OUTPUT SIGNAL - The present invention relates to a signal directing means ( | 2014-02-06 |
| 20140035653 | CAPACITANCE SENSING DEVICE AND TOUCHSCREEN - There are provided a capacitance sensing device and a touchscreen, the capacitance sensing device including a driving circuit unit allowing a capacitor to be charged and discharged; and an integrating circuit unit integrating charges stored in the capacitor, wherein the integrating circuit unit integrates the charges stored in the capacitor to thereby output a first voltage having a positive polarity and a second voltage having a negative polarity. | 2014-02-06 |
| 20140035654 | CONSTANT ON-TIME SWITCHING CONVERTERS WITH SLEEP MODE AND CONTROL METHODS THEREOF - A constant on-time switching converter includes a switching circuit, an on-time control circuit, a comparing circuit and a logic circuit. The switching circuit has a first switch and is configured to provide an output voltage to a load. The on-time control circuit generates an on-time control signal to control the on-time of the first switch. The comparing circuit compares the output voltage of the switching circuit with a reference signal and generates a comparison signal. The logic circuit generates a control signal to control the first switch based on the on-time control signal and the comparison signal. When the switching frequency of the switching circuit approaches an audible range, the switching converter enters into a sleep mode, the on-time control signal is reduced to increase the switching frequency of the switching circuit. | 2014-02-06 |
| 20140035655 | MATRIX-STAGES SOLID STATE ULTRAFAST SWITCH - A semiconductor switching device for switching high voltage and high current. The semiconductor switching device includes a control-triggered stage and one or more auto-triggered stages. The control-triggered stage includes a plurality of semiconductor switches, a breakover switch, a control switch, a turn-off circuit, and a capacitor. The control-triggered stage is connected in series to the one or more auto-triggered stages. Each auto-triggered stage includes a plurality of semiconductor switches connected in parallel, a breakover switch, and a capacitor. The control switch provides for selective turn-on of the control-triggered stage. When the control-triggered stage turns on, the capacitor of the control-triggered stage discharges into the gates of the plurality of semiconductor switches of the next highest stage to turn it on. Each auto-triggered stage turns on in a cascade fashion as the capacitor of the adjacent lower stage discharges or as the breakover switches of the auto-triggered stages turn on. | 2014-02-06 |
| 20140035656 | SEMICONDUCTOR DEVICE - According to one embodiment, a semiconductor device includes: a first switching element; a first interconnection; a first resistor; and a second interconnection. The first switching element includes a first control terminal, a first electrode terminal, and a first conductor terminal. The second switching element includes a second control terminal, a second electrode terminal, and a second conductor terminal. The first interconnection includes a first through a fourth interterminal interconnections. The first resistor is connected at a first end to the first control terminal. The second resistor is connected at a first end to the second control terminal and is connected at a second end to a second end of the first resistor. The second interconnection is provided between the first electrode terminal and the second electrode terminal and/or between the first control terminal and the second control terminal. | 2014-02-06 |
| 20140035657 | PREVENTING REVERSE CONDUCTION - In one embodiment, a circuit includes a resistance including first and second terminals. The first terminal of the resistance is coupled to ground. The circuit also includes a first switching element including first, second, and third terminals. The first terminal of the first switching element is coupled to an output of an integrated circuit and the second terminal of the first switching element is coupled to a voltage supply of the integrated circuit. Additionally, the circuit includes a second switching element including first, second, and third terminals. The first terminal of the second switching element is coupled to an enable input of the integrated circuit. Furthermore, the second terminal of the second switching element is coupled to the third terminal of the first switching element and to the second terminal of the resistance. Moreover, the third terminal of the second switching element is coupled to the ground. | 2014-02-06 |
| 20140035658 | POWER SEMICONDUCTOR DEVICE MODULE - A power semiconductor device module includes a plurality of inverters, each having a first transistor and a second transistor that are interposed in series between a first potential and a second potential and that operate complementarily. The plurality of inverters are assembled into a module. Only one predetermined inverter of the plurality of inverters is configured to detect temperatures of the first and second transistors, and control terminals for detection of the temperatures of the first and second transistors protrude from sides of the module. | 2014-02-06 |
| 20140035659 | SYSTEM AND METHOD FOR CONTROLLING VOLTAGE RAMPING FOR AN OUTPUT OPERATION IN A SEMICONDUCTOR MEMORY DEVICE - A voltage driving circuit comprises a current bias generating unit and a voltage driving unit. The current bias generating unit is configured to receive a mode signal and to generate a mode selection current in response to the mode signal. The voltage driving unit is coupled to the current bias generating unit, and is configured to receive the mode selection current and to drive an output voltage at a slew rate that is set according to the mode selection current. The voltage driving unit can include a plurality of stages, where each stage is configured to drive the output voltage at a respective different slew rate according to the mode signal. | 2014-02-06 |
| 20140035660 | Dual Mode Tilted-Charge Devices And Methods - A method for providing and operating a device in a first mode as a light-emitting transistor and in a second mode as a high speed electrical transistor, including the following steps: providing a semiconductor base region of a first conductivity type between semiconductor emitter and collector regions of a second semiconductor type; providing, in the base region, a quantum size region; providing, in the base region between the quantum size region and the collector region, a carrier transition region; applying a controllable bias voltage with respect to the base and collector regions to control depletion of carriers in at least the carrier transition region; and applying signals with respect to the emitter, base, and collector regions to operate the device as either a light-emitting transistor or a high speed electrical transistor, depending on the controlled bias signal. | 2014-02-06 |
| 20140035661 | AN INTEGRATED CIRCUIT AND METHOD FOR CONTROLLING LOAD ON THE OUTPUT FROM ON-CHIP VOLTAGE GENERATION CIRCUITRY - An integrated circuit and method are provided for controlling variation in the voltage output from on-chip voltage generation circuitry. The integrated circuit comprises voltage generation circuitry configured to operate from a supplied input voltage and to generate at an output node an on-chip voltage supply different to the supplied input voltage. A circuit block is then arranged to receive the on-chip voltage supply generated by the voltage generation circuitry, during operation of the circuit block the circuit block presenting a varying load on the output node. Oscillation circuitry is also coupled to the output node to provide an additional load on the output node, and is configured to produce an oscillation signal whose frequency varies as the value of the on-chip voltage supply varies. Control circuitry is configured to be responsive to a trigger condition to adjust the additional load provided on the output node by the oscillation circuitry. This provides a particularly simple and effective mechanism for providing an additional load on the output node which can be altered with the aim of offsetting variation in the load on the output node presented by the circuit block, thus allowing the variation in the voltage output from the on-chip voltage generation circuitry to be controlled. | 2014-02-06 |
| 20140035662 | SEMICONDUCTOR MEMORY DEVICE AND METHOD FOR OPERATING THE SAME - A semiconductor device includes a power supply voltage level/slope detection unit configured to detect a level of a power supply voltage and a slope of a power supply voltage curve, and output a power supply voltage level/slope detection signal, a pumping voltage detection unit configured to detect a level of a pumping voltage based on a reference pumping level to output a pumping detection signal, an oscillation signal generation unit configured to generate an oscillation signal in response to the pumping detection signal and the power supply voltage level/slope detection signal, and a pumping unit configured to generate the pumping voltage by performing a charge pumping operation in response to the oscillation signal. | 2014-02-06 |
| 20140035663 | Boosting Circuit - A boosting circuit, includes an output circuit including a first transmission circuit, transmitting charges of a first boosting node to a first output node according to a first transmission control signal, a detection circuit, detecting the voltage level of the first output node, and a pre-charge circuit pre-charging the first boosting node according a detection signal of the detection circuit; a first pump circuit includes a second transmission circuit, transmitting charges to a second output node according to a second transmission control signal, and a first capacitance unit, coupled to the first boosting node, boosting the voltage level of the first boosting node according to charges transmitted in the second output node; and a control circuit, coupled to the output circuit and the first pump circuit, controls the second transmission control signal according to the voltage level of the first output node. | 2014-02-06 |
| 20140035664 | VOLTAGE PROVIDING CIRCUIT - A voltage providing circuit includes a first circuit, a second circuit coupled with the first circuit, and a third circuit coupled with the second circuit. The first circuit is configured to receive a first input signal and to generate a first output signal. The second circuit is configured to receive the first input signal and the first output signal as inputs and to generate a second output signal. The third circuit is configured to receive the second output signal and to generate an output voltage. | 2014-02-06 |
| 20140035665 | Two-Stage Class AB Operational Amplifier - The invention relates to a two stage class AB operational amplifier ( | 2014-02-06 |
| 20140035666 | Op-R, A Solid State Filter - The device described herein proposes an electronic active filter void of capacitors and inductors. The circuit utilizes only operational amplifiers (OP-Amp) and resistors, hence the name Op-R. Although capable of being constructed of lumped circuit elements this filter is intended for integrated circuit (IC) applications. Filtering of signals can be accommodated from dc through the UHF frequency range depending on the selected op-amp ICs. Low pass, band pass, high pass, as well as band reject frequency responses are achievable. Although the circuits described herein are single input-single output, multiple inputs and outputs present no difficulty, being limited only chip space. Temperature and production spread variations are also considered within the realm of tenability. | 2014-02-06 |
| 20140035667 | Differential Source Follower having 6dB Gain with Applications to WiGig Baseband Filters - Sallen-Key filters require an operational amplifier with a large input impedance and a small output impedance to meet the external filter characteristics. This invention eliminates the need for internal feedback path for stability and increases the gain of a source follower which has characteristics matching the operational amplifier in the Sallen-Key filter. The source follower provides 6 dB of AC voltage gain and is substituted for the operational amplifier in the Sallen-Key filter. The Sallen-Key filter requires a differential configuration to generate all the required signals with their compliments and uses these signals in a feed forward path. Furthermore, since the source follower uses only two n-channel stacked devices, the headroom voltage is maximized to several hundred millivolts for a 1.2V voltage supply in a 40 nm CMOS technology. Thus, the required 880 MHz bandwidth of the Sallen-Key filter can be easily met using the innovative source follower. | 2014-02-06 |
| 20140035668 | CASCADED CLASS D AMPLIFIER WITH IMPROVED LINEARITY - An amplifier includes a first stage, a second stage coupled to the first stage, and a summation circuit. The first stage is configured to receive an analog input signal, convert the analog input signal to a digital signal, and output an intermediate analog output signal in response to the digital signal. The second stage is configured to output a second analog intermediate output signal based on a scaled pulse width modulation quantization error of the first stage. The summation circuit is configured to combine the first and second analog intermediate output signals to generate an amplified output signal. | 2014-02-06 |
| 20140035669 | Differential Stacked Output Stage for Power Amplifiers - A power amplifier system includes a transistor stack and an upper portion. The upper portion includes an LC tank. The LC tank is configured to generate selected harmonics to mitigate voltage stress and facilitate amplifier efficiency. The transistor stack includes serial connected input transistors and upper transistors. The input transistors are configured to receive an input signal and the upper transistors are configured to provide an amplifier output signal. The LC tank is configured to provide the selected harmonics to at least gates of the upper transistors. | 2014-02-06 |
| 20140035670 | FET PAIR BASED PHYSICALLY UNCLONABLE FUNCTION (PUF) CIRCUIT WITH A CONSTANT COMMON MODE VOLTAGE - A FET pair based physically unclonable function (PUF) circuit with a constant common mode voltage and methods of use are disclosed. The circuit includes a first n-type field effect transistor (NFET) and a second NFET. The circuit also includes a first load resistor coupled to the first NFET by a first p-type field effect transistor (PFET) and a second load resistor coupled to the second NFET by a second PFET. The circuit further comprises a closed loop, wherein the closed loop creates a constant common mode voltage. | 2014-02-06 |
| 20140035671 | SENSE AMPLIFIER AND ELECTRONIC APPARATUS USING THE SAME - A sense amplifier according to the present invention for detecting a potential difference of signals input to a first input terminal and a second input terminal, includes a first means for applying voltages corresponding to threshold voltages of first and second transistors to gate-source voltages of the first and second transistors, and a second means for transferring signals input to the first and second input terminals to gates of the first and second transistors. In this case, a threshold variation of the first and second transistors is corrected. | 2014-02-06 |
| 20140035672 | LEVEL SHIFTING CIRCUIT WITH ADAPTIVE FEEDBACK - An amplifier has a first pull-up path coupled between a voltage supply node and an output node, and a pull-down path coupled between the output node and a ground supply node. A second pull-up path is coupled between the voltage supply node and the output node. The second pull-up path is actuated by a feedback signal and biased by a biasing signal. An inverter circuit is operable to invert the signal at the amplifier output node to generate the feedback signal. A biasing circuit is configured to generate the biasing signal. The biasing circuit is configured to control a relative strength of the pull-down path to the second pull-up path, wherein the pull-down path is stronger than the second pull-up path in a manner that is consistently present over all PVT corners. | 2014-02-06 |
| 20140035673 | MULTIMODE DIFFERENTIAL AMPLIFIER BIASING SYSTEM - Differential power amplifier circuitry includes a differential transistor pair, an input transformer, and biasing circuitry. The base contact of each transistor in the differential transistor pair may be coupled to the input transformer through a coupling capacitor. The coupling capacitors may be designed to resonate with the input transformer about a desired frequency range, thereby passing desirable signals to the differential transistor pair while blocking undesirable signals. The biasing circuitry may include a pair of emitter follower transistors, each coupled at the emitter to the base contact of each one of the transistors in the differential transistor pair and adapted to bias the differential transistor pair to maximize efficiency and stability. | 2014-02-06 |
| 20140035674 | CONDITIONALLY-STABLE OPERATIONAL AMPLIFIER WITH TUNABLE WIDEBAND BUFFERS - A method for processing signals may include, in a conditionally-stable operational amplifier, shifting the gain curve of the conditionally-stable operational amplifier to a desired position, by buffering at least one output signal from at least one transconductance module within the conditionally-stable operational amplifier using a buffer. The desired position of the gain curve may be associated with a desired feedback factor. The shifting of the gain may take place without shifting a corresponding phase. The tuning of the buffer may be based on the desired position of the gain curve which is derived from feedback factor value(s) specified by an application. A phase corresponding to the desired position of the gain curve at 0 dB frequency may be greater than a threshold phase. The buffering may be tuned using at least one tunable wideband buffer so that the corresponding phase at 0 dB frequency remains higher than the threshold phase. | 2014-02-06 |
| 20140035675 | Amplifier for a Wireless Receiver - Amplifier ( | 2014-02-06 |
| 20140035676 | Doherty Power Amplifier and Implementation Method Thereof - The present invention discloses a Doherty power amplifier and an implementation method thereof. A peak amplifying circuit of the Doherty power amplifier comprises a radio frequency switching circuit configured to control turn-on of the peak amplifying circuit; wherein a last stage carrier amplifier of a carrier amplifying circuit of the power amplifier uses a HVHBT device, and a last stage peak amplifier of the peak amplifying circuit of the power amplifier uses a GaN device. The present invention avoids the shortcoming when the peak branches in the Doherty power amplifier are turned on ahead of time, decreases power consumption of the peak amplifier and improves the batch efficiency of the whole Doherty power amplifier. | 2014-02-06 |
| 20140035677 | Doherty Power Amplifier and Implementation Method Thereof - The present invention discloses a Doherty power amplifier and a method for implementing the Doherty power amplifier. The Doherty power amplifier includes a peak amplifying branch and a carrier amplifying branch, wherein, the peak amplifying branch includes a radio frequency switch, and the radio frequency switch is configured to control on/off of a last stage peak power amplifier in the peak amplifying branch; wherein, a high voltage heterojunction bipolar transistor (HVHBT) device is adopted for a last stage carrier power amplifier of the carrier amplifying branch, and a laterally diffused metal oxide semiconductor (LDMOS) device is adopted for the last stage peak power amplifier of the peak amplifying branch of the power amplifier. By the present invention, it avoids that the peak power consumption is increased when the peak power amplifier is on ahead of time and enhances the efficiency of the whole power amplifier. | 2014-02-06 |
| 20140035678 | Power Amplifier Apparatus and Power Amplifier Circuit - The present invention relates to a power amplifier apparatus and a power amplifier circuit. The power amplifier circuit uses a Doherty circuit structure, uses a High Electron Mobility Transistor (HEMT) power amplifier to implement a Carrier amplifier with the Doherty circuit structure, and uses a Laterally Diffused Metal Oxide Semiconductor Field Effect Transistor (LDMOS) to implement a Peak amplifier. With the power amplifier apparatus and power amplifier circuit of the present invention, the power amplifier efficiency is improved. | 2014-02-06 |
| 20140035679 | Power Amplifier Device and Power Amplifier Circuit Thereof - The present invention relates to a power amplifier apparatus and power amplifier circuit thereof, and the power amplifier circuit uses the Doherty circuit structure, and the power amplifier circuit uses high voltage heterojunction bipolor transistor (HVHBT) power amplifiers to achieve a carrier amplifier and a peak amplifier of the Doherty circuit structure. The power amplifier apparatus and power amplifier circuit thereof in the present invention improves the efficiency of the power amplification. | 2014-02-06 |
| 20140035680 | Power Amplifier Apparatus and Power Amplifier Circuit - The present invention relates to a power amplifier apparatus and a power amplifier circuit thereof, the power amplifier circuit uses Doherty circuit structure, and it uses a high voltage heterojunction bipolar transistor (HVHBT) power amplifier to achieve a Carrier amplifier with the Doherty circuit structure, and uses a high electron mobility transistor (HEMT) power amplifier to achieve a Peak amplifier with the Doherty circuit structure. The power amplifier apparatus and a power amplifier circuit thereof in the present invention improves the efficiency of the power amplifier. | 2014-02-06 |
| 20140035681 | MULTI-FREQUENCY MULTI-STANDARD RECONFIGURABLE DOHERTY AMPLIFIER - A method and system for designing and implementing a reconfigurable Doherty amplifier system are disclosed. In one embodiment, a design method includes determining, using a processor, a first set of ABCD transmission parameters of a first output compensation network in a main path of a Doherty amplifier for the case where an auxiliary amplifier of the Doherty amplifier is off. The method further includes determining, using a processor, a second set of ABCD transmission parameters of a second output compensation network in an auxiliary path of the Doherty amplifier based on the first set of ABCD transmission parameters. | 2014-02-06 |
| 20140035682 | Wideband and Reconfigurable Doherty Based Amplifier - The present disclosure provides a power amplifier comprising a main amplifier and an auxiliary amplifier. The power amplifier is configured to deliver an output power P | 2014-02-06 |
| 20140035683 | INTEGRATED CIRCUIT - According to one embodiment, provided are an amplifier transistor configured to amplify an input signal; a biasing circuit configured to set a bias voltage in such a manner as to allow the amplifier transistor to perform amplification; an electrostatic protective circuit configured to set the bias voltage for the amplifier transistor in such a manner as to make the amplifier transistor to turn off based on voltage to be applied to the amplifier transistor; and a switching circuit configured to switch the bias voltage for the amplifier transistor based on a power supply condition. | 2014-02-06 |
| 20140035684 | CONTROL CIRCUIT AND APPARATUS FOR DIGITALLY CONTROLLED OSCILLATOR - There are provided a control circuit for a digitally controlled oscillator and a control apparatus for a digitally controlled oscillator using the same. The control circuit for a digitally controlled oscillator includes: a peak detection circuit detecting amplitude of a signal output from the digitally controlled oscillator; and a transconductance control circuit comparing an output of the peak detection circuit with a predetermined reference signal to control a transconductance value of a negative transconductance circuit included in the digitally controlled oscillator. | 2014-02-06 |
| 20140035685 | RESONATOR DEVICE, ELECTRONIC DEVICE, ELECTRONIC APPARATUS, AND MOBILE OBJECT - A resonator device includes a base substrate having a fixation section to be attached to a mounting board and a free end, a resonator element having one end connected to a connection section located on the free end side of the base substrate, and a lid member adapted to airtightly seal the resonator element in a space between the lid member and the base substrate. | 2014-02-06 |
| 20140035686 | METHOD FOR VARYING OSCILLATION FREQUENCY OF HIGH FREQUENCY OSCILLATOR - The switching element is provided in a state of being electromagnetically coupled to the cavity resonator of the high frequency oscillator; the bias voltage applying terminal is connected to one electrode of the switching element; another electrode of the switching element is electrically connected to the cavity resonator (the anode shell in FIG. | 2014-02-06 |
| 20140035687 | DISTRIBUTION SYSTEM FOR OPTICAL REFERENCE - A system for distributing a reference oscillator signal includes a clock having a reference oscillator and a femtosecond laser stabilized by the reference oscillator. The system also includes at least one beamsplitter configured to split the femtosecond laser. The system further includes one or more remote nodes that are spaced from the clock. The remote nodes are configured to generate reference signals based on the split femtosecond laser. | 2014-02-06 |
| 20140035688 | OSCILLATOR - There is provided an oscillator providing a clock signal having a uniform duty ratio by generating a toggled voltage by charging and discharging a capacitor with a voltage irrespective of a temperature from a band gap circuit. The oscillator includes: a band gap circuit providing a band gap reference voltage having a pre-set voltage level; a voltage-current conversion unit converting the band gap reference voltage from the band gap circuit into a current; a charging/discharging unit charging/discharging the converted current and providing a triangle wave signal; and a T flip-flop logically operating a pulse signal according to a maximum value of the triangle wave signal from the charging/discharging unit and providing a clock signal having a fixed duty. | 2014-02-06 |
| 20140035689 | SEMICONDUCTOR DEVICE AND CONTROL METHOD THEREOF - The present invention provides a semiconductor device including a first terminal and a second terminal respectively coupled to both ends of a crystal resonator, an inverter circuit having an input coupled to the first terminal and an output coupled to the second terminal, a feedback resistor which couples between the first terminal and the second terminal, a variable capacitor coupled to at least one of the first and second terminals, and a control circuit. The control circuit performs control to increase both of the drive capability of the inverter circuit and the capacitance value of the variable capacitor in a second mode rather than a first mode. | 2014-02-06 |
| 20140035690 | VOLTAGE CHANGE COMPENSATION TYPE OSCILLATOR AND METHOD OF COMPENSATING ERROR OF OSCILLATOR - The present invention relates to a voltage change compensation type oscillator and a method of compensating an error of an oscillator, which includes a voltage level detecting unit; a current level adjusting unit; and an oscillating core unit for generating and outputting a clock signal by receiving a power supply voltage and an output current of the current level adjusting unit, wherein the current level adjusting unit adjusts the output current in proportion to an increase of the voltage level detected by the voltage level detecting unit, thus remarkably reducing a frequency error of the clock signal in spite of changes in voltage. | 2014-02-06 |
| 20140035691 | CAPACITIVE DIVIDER STRUCTURE - A capacitive divider structure, comprising: a first plurality of capacitive devices, each being selectively controlled in accordance with a first input control signal so as to alter the effective capacitance of the capacitive divider structure by a first amount; a second plurality of capacitive devices coupled in parallel with the first plurality of capacitive devices, each being selectively controlled in accordance with a second input control signal so as to alter the effective capacitance of the capacitive divider structure by a second amount; and at least one series capacitive device arranged in series with the second plurality of capacitive devices, such that the second amount is less than the first amount. | 2014-02-06 |
| 20140035692 | OPTIMIZED MULTI-LEVEL FINITE STATE MACHINE WITH REDUNDANT DC NODES - A method and system for eliminating/suppressing long transition runs over a communications channel is disclosed. The method may include providing modulation coding based on a multi-level finite state machine (ML-FSM) having a periodic structure, the periodic structure being defined by a predetermined number of time frames. The ML-FSM may include a plurality of penalty-free edges for connecting nodes in one time frame to nodes at the same level in a subsequent time frame and a plurality of penalty edges for connecting nodes in one time frame to nodes at an upper level in the subsequent time frame. The method may further include utilizing the ML-FSM based modulation coding to facilitate data transmission over the communications channel. | 2014-02-06 |
| 20140035693 | METHOD AND APPARATUS FOR IMPLEMENTING HIGH-ORDER MODULATION SCHEMES USING LOW-ORDER MODULATORS - A processing device includes a plurality of modulators, the plurality of modulators performing modulation according to a first modulation scheme, a combiner configured to combine outputs from the plurality of modulators, and a signal processor configured to receive a bit stream and convert the bit stream into a plurality of input signals for the plurality of modulators such that the combiner generates a modulated output according to a second modulation scheme. The plurality of modulators may be low order modulators and a modulation schemes of the modulated output may include, for example, rotated quadrature phase shift keying (QPSK), pulse amplitude modulation (PAM), high order quadrature amplitude modulation (QAM), and multi-resolution high order quadrature amplitude modulation (M-QAM). | 2014-02-06 |
| 20140035694 | PHASED ARRAY ANTENNA AND PHASE CONTROL METHOD THEREFOR - In a phased array antenna that has a configuration in which a plurality of antenna panels, in each of which a plurality of antenna elements are arrayed, are connected in the form of a plane and that radiates power transmission microwaves in the arrival direction of a pilot signal sent from an electric-power receiving facility (rectenna system), by controlling the phases of signals input to and output from the antenna elements. An arithmetic processing section, which is provided in each of the antenna panels, calculates the phase shifts of power transmission microwaves to be radiated from the antenna elements. Then, the phase information indicating the phase shifts calculated by the arithmetic processing section is sent to at least three adjacent antenna panels by a transmission and reception section provided in each of the antenna panels. | 2014-02-06 |
| 20140035695 | FREQUENCY AGILE HIGH POWER MICROWAVE GENERATOR - A Multi-Cycle Digital High Power Microwave (MCD-HPM) source includes a microwave transmission line (MTL) to which a plurality electrically charged thin film transmission lines (TFTL's) are connected by switches. The switches are activated in sequence to generate a square wave at a microwave output frequency. The activation signal is controlled by a free space time delay, which can vary the timing and/or routing of the activation signal by modifying at least one free space element, thereby adjusting the switch activation timing and varying the output frequency. In embodiments, the switches are photo-conducting switches, the activation signal is a laser beam, and the switch timing is varied by reorienting and/or repositioning mirrors and/or other elements in the free space time delay. The elements can be manually adjusted, or mounted on motorized stages and automatically controlled. Optical amplifiers can be included to compensate for losses in the time delay elements. | 2014-02-06 |
