| 06th week of 2014 patent applcation highlights part 18 |
| Patent application number | Title | Published |
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| 20140035092 | RADIO FREQUENCY ISOLATION FOR SOI TRANSISTORS - According to one example embodiment, a structure includes at least one SOI (semiconductor-on-insulator) transistor situated over a buried oxide layer, where the buried oxide layer overlies a bulk substrate. The structure further includes an electrically charged field control ring situated over the buried oxide layer and surrounding the at least one SOI transistor. A width of the electrically charged field control ring is greater than a thickness of the buried oxide layer. The electrically charged field control ring reduces a conductivity of a surface portion of the bulk substrate underlying the field control ring, thereby reducing RF coupling of the at least one SOI transistor through the bulk substrate. The structure further includes an isolation region situated between the electrically charged field control ring and the at least one SOI transistor. A method to achieve and implement the disclosed structure is also provided. | 2014-02-06 |
| 20140035093 | Integrated Circuit Interposer and Method of Manufacturing the Same - Systems and methods are provided for an interposer for coupling two or more integrated circuit dies to a circuit package. A first integrated circuit portion is disposed on a first location of a single semiconductor substrate. A second integrated circuit portion is disposed on a second location of the single semiconductor substrate, where the second integrated circuit portion is electrically isolated from the first integrated circuit portion along a first axis. The first and second integrated circuit portions are configured to provide an electrical coupling to two or more corresponding top die integrated circuits across a second axis that is perpendicular to the first axis. | 2014-02-06 |
| 20140035094 | SEMICONDUCTOR STRUCTURE - One or more embodiments relate to a semiconductor structure, comprising: a silicon rubber layer; and a semiconductor layer overlying the silicon rubber layer. | 2014-02-06 |
| 20140035095 | SEMICONDUCTOR PACKAGE AND METHOD FOR FABRICATING BASE FOR SEMICONDUCTOR PACKAGE - The invention provides a semiconductor package and a method for fabricating a base for a semiconductor package. The semiconductor package includes a conductive trace embedded in a base. A semiconductor device is mounted on the conductive trace via a conductive structure. | 2014-02-06 |
| 20140035096 | METHOD FOR CONTROLLING ELECTRICAL PROPERTY OF PASSIVE DEVICE DURING FABRICATION OF INTEGRATED COMPONENT AND RELATED INTEGRATED COMPONENT - A method for controlling an electrical property of a passive device during a fabrication of an integrated component includes providing a substrate, manufacturing the passive device on the substrate, measuring the electrical property of the passive device to obtain a measuring result, determining at least one layout pattern corresponding to at least one later manufacturing process by the measuring result for adjusting the electrical property of the passive device, and continuing the rest of the fabrication including the at least one later manufacturing process of the integrated component. | 2014-02-06 |
| 20140035097 | SEMICONDUCTOR PACKAGE HAVING AN ANTENNA AND MANUFACTURING METHOD THEREOF - A semiconductor package and a manufacturing method thereof are provided. The semiconductor package includes a first substrate, a second substrate, an interposer substrate, a semiconductor chip, a package body and a first antenna layer. The first substrate comprises a grounding segment. The interposer substrate is disposed between the second substrate and the first substrate. The semiconductor chip is disposed on the second substrate. The package body encapsulates the second substrate, the semiconductor chip and the interposer substrate, and has a lateral surface and an upper surface. The first antenna layer is formed on the lateral surface and the upper surface of the package body, and electrically connected to the grounding segment. | 2014-02-06 |
| 20140035098 | SOLID-STATE SUPERCAPACITOR - Embodiments of the present disclosure relate to a solid-state supercapacitor. The solid-state supercapacitor includes a first electrode, a second electrode, and a solid-state ionogel structure between the first electrode and the second electrode. The solid-state ionogel structure prevents direct electrical contact between the first electrode and the second electrode. Further, the solid-state ionogel structure substantially fills voids inside the first electrode and the second electrode. | 2014-02-06 |
| 20140035099 | INTEGRATED CIRCUITS WITH METAL-INSULATOR-METAL (MIM) CAPACITORS AND METHODS FOR FABRICATING SAME - Integrated circuits with metal-insulator-metal (MIM) capacitors and methods for fabricating such integrated circuits are provided. In an embodiment, an integrated circuit includes a dielectric material layer overlying a semiconductor substrate. A surface conditioning layer overlies the dielectric material layer. Further, a metal layer is formed directly on the surface conditioning layer. A MIM capacitor is positioned on the metal layer. The MIM capacitor includes a first conductive layer formed directly on the metal layer with a smooth upper surface, an insulator layer formed directly on the smooth upper surface of the first conductive layer, and a second conductive layer formed directly on the insulator layer with a smooth lower surface. | 2014-02-06 |
| 20140035100 | PLANAR INTERDIGITATED CAPACITOR STRUCTURES AND METHODS OF FORMING THE SAME - A planar interdigitated capacitor structure, methods of forming, and devices including, the same. The device includes first and second planar electrode structures including respective first and second pluralities of planar continuous rectangular plate electrode elements formed above a semiconductor substrate and extending continuously in first and second orthogonal directions substantially parallel to a plane of the substrate, and first and second conductors interconnecting the respective first and second pluralities of planar electrode elements parallel to a third axis substantially normal to the plane of the substrate. The first and second planar electrode structures are arranged with respective continuous rectangular plate electrode elements of each planar electrode structure interleaved and substantially parallel with each other between the first and second conductors. The device also includes a dielectric material between the first planar electrode structure and the second planar electrode structure. | 2014-02-06 |
| 20140035101 | DIELECTRICS CONTAINING AT LEAST ONE OF A REFRACTORY METAL OR A NON-REFRACTORY METAL - Electronic apparatus and methods of forming the electronic apparatus may include one or more insulator layers having a refractory metal and a non-refractory metal for use in a variety of electronic systems and devices. Embodiments can include electronic apparatus and methods of forming the electronic apparatus having a tantalum aluminum oxynitride film. The tantalum aluminum oxynitride film may be structured as one or more monolayers. The tantalum aluminum oxynitride film may be formed using atomic layer deposition. Metal electrodes may be disposed on a dielectric containing a tantalum aluminum oxynitride film. | 2014-02-06 |
| 20140035102 | POWER DEVICE INTEGRATION ON A COMMON SUBSTRATE - A semiconductor structure for facilitating an integration of power devices on a common substrate includes a first insulating layer formed on the substrate and an active region having a first conductivity type formed on at least a portion of the first insulating layer. A first terminal is formed on an upper surface of the structure and electrically connects with at least one other region having the first conductivity type formed in the active region. A buried well having a second conductivity type is formed in the active region and is coupled with a second terminal formed on the upper surface of the structure. The buried well and the active region form a clamping diode which positions a breakdown avalanche region between the buried well and the first terminal. A breakdown voltage of at least one of the power devices is a function of characteristics of the buried well. | 2014-02-06 |
| 20140035103 | GROUP III NITRIDE CRYSTAL PRODUCTION METHOD AND GROUP III NITRIDE CRYSTAL - Provided is a high-quality Group III nitride crystal of excellent processability. A Group III nitride crystal is produced by forming a film is composed of an oxide, hydroxide and/or oxyhydroxide containing a Group III element by heat-treating a Group III nitride single crystal at 1000° C. or above, and removing the film. | 2014-02-06 |
| 20140035104 | GERMANIUM ON INSULATOR APPARATUS - In an implementation, a Germanium on insulator apparatus is fabricated by forming a patterned masking layer on a Silicon on insulator (SOI) layer that leaves a portion of the SOI layer exposed, implanting Germanium onto the exposed portion of the SOI layer to form a Silicon-Germanium island, depositing amorphous Germanium over the Silicon-Germanium island and the patterned masking layer, removing the patterned masking layer and the amorphous Germanium that was deposited onto the patterned masking layer to produce a Silicon-Germanium composite stripe, and annealing the Silicon-Germanium composite stripe to crystallize the amorphous Germanium in the Silicon-Germanium composite stripe. | 2014-02-06 |
| 20140035105 | SEMICONDUCTOR DEVICE, METHOD FOR MANUFACTURING SEMICONDUCTOR DEVICE, AND BASE MEMBER FOR SEMICONDUCTOR DEVICE FORMATION - According to one embodiment, a method for manufacturing a semiconductor device includes forming semiconductor layers in a plurality of first regions on a semiconductor wafer. The plurality of first regions are separated from each other. The method includes forming elements in the semiconductor layers. The method includes bonding an insulating plate made of an inorganic material in a second region on the semiconductor wafer. The second region excludes the first regions. The method includes performing singulation for each of the semiconductor layers by cutting the semiconductor wafer and the insulating plate along a dicing line configured to pass through only the second region. | 2014-02-06 |
| 20140035106 | MULTIPLE SEAL-RING STRUCTURE FOR THE DESIGN, FABRICATION, AND PACKAGING OF INTEGRATED CIRCUITS - A semiconductor circuit design includes an outer seal-ring and an inner seal-ring for each sub-section of the design that may potentially be cut into separate die. The use of multiple seal-rings permits a single circuit design and fabrication run to be used to support flexibly packaging different product releases having different numbers of integrated circuit blocks per packaged unit. | 2014-02-06 |
| 20140035107 | DOUBLE SEAL RING - A double seal ring for an integrated circuit, the double seal ring includes a first seal ring surrounding the integrated circuit and a second seal ring spaced from the first seal ring. The double seal ring further includes two connectors connecting the first seal ring and the second seal ring, wherein the first seal ring, the second seal ring, and the two connectors form a closed loop. A method of forming a double seal ring for an integrated circuit includes forming a first seal ring surrounding the integrated circuit and forming a second seal ring spaced from the first seal ring. The method further includes forming two connectors connecting the first seal ring and the second seal ring, wherein the first seal ring, the second seal ring, and the two connectors form a closed loop. | 2014-02-06 |
| 20140035108 | SEMICONDUCTOR INTEGRATED CIRCUIT AND PATTERN LAYOUTING METHOD FOR THE SAME - A semiconductor integrated circuit and a pattern lay-outing method for the same are disclosed, which can suppress bending or partial drop-out of a dummy pattern even when a mechanical stress acts on the dummy pattern in CMP. The semiconductor integrated circuit includes predetermined functional areas and a dummy pattern formed in a space area. The space area is positioned between predetermined functional areas. The dummy pattern includes a first metal portion formed in the shape of a frame and defining an outer edge of the dummy pattern, a second metal portion positioned on an inner periphery side of the first metal portion and formed so as to be continuous with the first metal portion, and a plurality of non-forming areas positioned in an area where the second metal portion is not formed on the inner periphery side of the first metal portion. | 2014-02-06 |
| 20140035109 | METHOD AND STRUCTURE OF FORMING BACKSIDE THROUGH SILICON VIA CONNECTIONS - A method, and the resulting structure, to make a thinned substrate with backside redistribution wiring connected to through silicon vias of varying height. The method includes thinning a backside of a substrate to expose through silicon vias. Then a thick insulator stack, including an etch stop layer, is deposited and planarized. With a planar insulating surface in place, openings in the insulator stack can be formed by etching. The etch stop layer in the dielectric stack accommodates the differing heights vias. The etch stop is removed and a conductor having a liner is formed in the opening. The method gives a unique structure in which a liner around the bottom of the through silicon via remains in tact. Thus, the liner of the via and a liner of the conductor meet to form a double liner at the via/conductor junction. | 2014-02-06 |
| 20140035110 | SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD OF SAME - A semiconductor device includes a semiconductor substrate; an insulating film arranged on the semiconductor substrate; an electrode that contacts a portion of a side surface of the insulating film; a first passivation film that is arranged extending from the electrode to the insulating film, and contacts a surface of the insulating film, and contacts a surface of the electrode; and a second passivation film that is arranged on the first passivation film. A difference between a linear expansion coefficient of the first passivation film and a linear expansion coefficient of the insulating film is smaller than a difference between the linear expansion coefficient of the first passivation film and a linear expansion coefficient of the electrode, and a position where the first passivation film contacts a boundary between the electrode and the insulating film is positioned lower than an upper surface of the insulating film. | 2014-02-06 |
| 20140035111 | LAYOUT CONFIGURATION FOR MEMORY CELL ARRAY - A layout configuration for a memory cell array includes at least a comb-like doped region having a first conductivity type and a fishbone-shaped doped region having a second conductivity type. The second conductivity type and the first conductivity type are complementary. Furthermore, the comb-like doped region and the fishbone-shaped doped region are interdigitated. | 2014-02-06 |
| 20140035112 | SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD THEREOF - A semiconductor device includes a first semiconductor element; a first thick plate portion that is electrically connected to an electrode on a lower surface side of the first semiconductor element, and is formed by a conductor; a second semiconductor element that is arranged such that a main surface of the second semiconductor element faces a main surface of the first semiconductor element; a second thick plate portion that is electrically connected to an electrode on a lower surface side of the second semiconductor element, and is formed by a conductor; a third thick plate portion that is electrically connected to an electrode on an upper surface side of the first semiconductor element, and is formed by a conductor; a fourth thick plate portion that is electrically connected to an electrode on an upper surface side of the second semiconductor element, and is formed by a conductor; a first thin plate portion that is provided on the second thick plate portion, is formed by a conductor, and is thinner than the second thick plate portion; and a second thin plate portion that is provided on the third thick plate portion, is formed by a conductor, and is thinner than the third thick plate portion. The first thin plate portion and the second thin plate portion are fixed together and electrically connected. | 2014-02-06 |
| 20140035113 | PACKAGING AND METHODS FOR PACKAGING - A packaged integrated device can include a die attach pad having a top surface and a bottom surface. A plurality of leads physically and electrically separated from the die attach pad can be positioned at least partially around the perimeter of the die attach pad. An integrated device die can be mounted on the top surface of the die attach pad. A package body can cover the integrated device die and at least part of the plurality of leads, and at least a portion of the bottom surface of each of the plurality of leads can be exposed through the package body. A plating layer can cover substantially the entire width of an etched lower portion of the outer end of each lead and at least the exposed portion of the bottom surface of each lead. | 2014-02-06 |
| 20140035114 | SEMICONDUCTOR PACKAGE STRUCTURE AND METHOD - In one embodiment, a semiconductor package structure includes a substrate having a well region extending from a major surface. An interposer structure is attached to the substrate within the well region. The interposer structure has a major surface that is substantially co-planar with the major surface of the substrate. An electrical device is directly attached to the substrate and the interposer structure. The interposer structure can be an active device, such as a gate driver integrated circuit, or passive device structure, such as an impedance matching network. | 2014-02-06 |
| 20140035115 | SEMICONDUCTOR DEVICE - A semiconductor device includes any one of a lead frame having a die pad portion and a circuit board, one or more semiconductor elements, a copper wire, an encapsulating member. The one or more semiconductor elements are mounted on any one of the die pad portion of the lead frame and the circuit board. The copper wire electrically connects electrical joints provided on any one of the lead frame and the circuit board to an electrode pad provided on the semiconductor element. The encapsulating member encapsulates the semiconductor element and the copper wire. The electrode pad provided on the semiconductor element is formed from palladium. The copper wire has a copper purity of 99.99% by mass or more and an elemental sulfur content of 5 ppm by mass or less. | 2014-02-06 |
| 20140035116 | Top Exposed Semiconductor Chip Package - A semiconductor package and it manufacturing method includes a lead frame having a die pad, and a source lead with substantially a V groove disposed on a top surface. A semiconductor chip disposed on the die pad. A metal plate connected to a top surface electrode of the chip having a bent extension terminated in the V groove in contact with at least one of the V groove sidewalls. | 2014-02-06 |
| 20140035117 | Explosion-Protected Semiconductor Module - A semiconductor module includes an electrically conductive lower contact piece and an electrically conductive upper contact piece spaced apart from one another in a vertical direction. The module further includes a semiconductor chip having a first load connection and a second load connection. The semiconductor chip is electrically conductively connected by the second load connection to the lower contact piece, and electrically conductively connected to the upper contact piece by at least one bonding wire bonded to the first load connection. An explosion protection means is arranged between the first load connection and the upper contact piece and into which each of the bonding wires is embedded over at least 80% or over at least 90% of its length. | 2014-02-06 |
| 20140035118 | Semiconductor Module Arrangement and Method for Producing and Operating a Semiconductor Module Arrangement - A semiconductor module arrangement includes a semiconductor module having a top side, an underside opposite the top side, and a plurality of electrical connection contacts formed at the top side. The semiconductor module arrangement additionally includes a printed circuit board, a heat sink having a mounting side, and one or a plurality of fixing elements for fixing the printed circuit board to the heat sink. Either a multiplicity of projections are formed at the underside of the semiconductor module and a multiplicity of receiving regions for receiving the projections are formed at the mounting side of the heat sink, or a multiplicity of projections are formed at the mounting side of the heat sink and a multiplicity of receiving regions for receiving the projections are formed at the underside of the semiconductor module. In any case, each of the projections extends into one of the receiving regions. | 2014-02-06 |
| 20140035119 | ELECTRONIC SEMI - CONDUCTOR DEVICE INTENDED FOR MOUNTING IN A PRESSED STACK ASSEMBLY, AND A PRESSED STACK ASSEMBLY COMPRISING SUCH DEVICE - A semi-conductor electronic device for mounting in a pressed stack assembly. The device comprises a box comprising a lower plate, an upper plate and a lateral wall mechanically connecting the lower plate to the upper plate, the lower and upper plates being electrically conductive, several semi-conductor components, each component comprising a first electrode and a second electrode, the first electrodes being electrically connected to the lower plate and the second electrodes being electrically connected to the upper plate, and elastic parts positioned between the components and a supporting plate chosen from the lower plate and the upper plate. The device comprises, in addition, an intermediate sealing wall positioned inside the box, between the components and the elastic parts, the intermediate sealing wall electrically connecting the components, the intermediate sealing wall being adapted to separate the components from an electrically insulating cooling liquid, adapted to circulate around the elastic parts, between the intermediate sealing wall and the supporting plate. | 2014-02-06 |
| 20140035120 | SEMICONDUCTOR UNIT - A semiconductor unit includes an insulation layer, a conductive layer bonded to one side of the insulation layer, a semiconductor device mounted on the conductive layer, a cooler thermally coupled to the other side of the insulation layer, a first bus bar having a bonding surface bonded to the semiconductor device or the conductive layer and a non-bonding surface that is the part of the first bus bar other than the bonding surface, and a second bus bar having a bonding surface bonded to the semiconductor device or the conductive layer and a non-bonding surface that is the part of the second bus bar other than the bonding surface. The second bus bar has a greater ratio of the area of the bonding surface to the area of the non-bonding surface than the first bus bar. The second bus bar has a lower electric resistance than the first bus bar. | 2014-02-06 |
| 20140035121 | ENHANCED STACKED MICROELECTRONIC ASSEMBLIES WITH CENTRAL CONTACTS AND IMPROVED THERMAL CHARACTERISTICS - A microelectronic assembly includes a dielectric element that has oppositely-facing first and second surfaces and first and second apertures extending between the surfaces. The dielectric element further includes conductive elements. First and second microelectronic elements are stacked one on top of the another. The second microelectronic element has a plurality of contacts at a surface, which is spaced from the first surface of the dielectric element. Leads extend from contacts of the first and second microelectronic elements through respective apertures to at least some of the conductive elements. A heat spreader is thermally coupled to at least one of the first microelectronic element or the second microelectronic element. | 2014-02-06 |
| 20140035122 | POWER SEMICONDUCTOR DEVICE - A power semiconductor device includes: a mold unit that includes a power semiconductor element, a base plate, and a mold unit, the power semiconductor element being mounted on one surface of the base plate, a convex portion being formed on an other surface of the base plate, the convex portion including a plurality of grooves, the mold unit having a mold resin with which the power semiconductor element is sealed in such a manner as to expose the convex portion; a plurality of radiation fins inserted into the grooves, respectively, and fixedly attached to the base plate by swaging; and a metal plate that includes a opening into which the convex portion is inserted, the metal plate being arranged between the mold unit and the radiation fins with the convex portion inserted into the opening, wherein the metal plate includes a protrusion that protrudes from an edge of the opening and that digs into a side surface of the convex portion when the convex portion is inserted into the opening. | 2014-02-06 |
| 20140035123 | SEMICONDUCTOR DEVICE AND METHOD FOR MANUFACTURING SEMICONDUCTOR DEVICE - A semiconductor device includes: a semiconductor element; a substrate; a metal plate; and a plurality of spherical particles. The substrate has the semiconductor element mounted thereon. The metal plate has one surface and the other surface that face each other, and the substrate is provided on the one surface. The plurality of spherical particles each has a spherical outer shape, and a part of the spherical outer shape is buried in the other surface of the metal plate. With such a configuration, there can be obtained a semiconductor device that allows promotion of heat dissipation from the semiconductor element, and a method for manufacturing the semiconductor device. | 2014-02-06 |
| 20140035124 | SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD OF SAME - An semiconductor device includes a semiconductor substrate; a metal layer arranged above the semiconductor substrate; a first passivation film that contacts at least a portion of one side surface of the metal layer; and a second passivation film that is arranged extending from the first passivation film to the metal layer, and contacts an upper surface of the first passivation film, and contacts at least a portion of an upper surface of the metal layer. | 2014-02-06 |
| 20140035125 | SEMICONDUCTOR MANUFACTURING METHOD, SEMICONDUCTOR STRUCTURE AND PACKAGE STRUCTURE THEREOF - A semiconductor manufacturing method includes providing a carrier having a metallic layer, wherein the metallic layer comprises a plurality of base areas and a plurality of outer lateral areas; forming a first photoresist layer; forming a plurality of bearing portions; removing the first photoresist layer to reveal the bearing portions, each bearing portion comprises a bearing surface having a first area and a second area; forming a second photoresist layer for revealing the first areas of the bearing surfaces; forming a plurality of connection portions, wherein the first areas of the bearing surfaces are covered by the connection portions to make each connection portion connect with each bearing portion to form a snap bump; removing the outer lateral areas of the metallic layer to make the base areas form a plurality of under bump metallurgy layers. | 2014-02-06 |
| 20140035126 | SEMICONDUCTOR MANUFACTURING METHOD AND SEMICONDUCTOR STRUCTURE THEREOF - A semiconductor manufacturing method includes providing a substrate having a metallic layer that includes a first metal layer and a second metal layer, the first metal layer comprises plural base areas and plural first outer lateral areas, the second metal layer comprises plural second base areas and plural second outer lateral areas; forming a first photoresist layer; forming plural bearing portions; removing the first photoresist layer; forming a second photoresist layer; forming plural connection portions, each connection portion comprises a first connection layer and a second connection layer; removing the second photoresist layer to reveal the connection portions and the bearing portions; removing the first outer lateral areas; reflowing the second connection layers to form plural composite bumps; removing the second outer lateral areas to make the first base areas and the second base areas form plural under bump metallurgy layers. | 2014-02-06 |
| 20140035127 | CHIP PACKAGE AND A METHOD FOR MANUFACTURING A CHIP PACKAGE - A method for manufacturing a chip package is provided. The method includes: forming an electrically insulating material over a chip side; selectively removing at least part of the electrically insulating material thereby forming a trench in the electrically insulating material, depositing electrically conductive material in the trench wherein the electrically conductive material is electrically connected to at least one contact pad formed over the chip side; forming an electrically conductive structure over the electrically insulating material, wherein at least part of the electrically conductive structure is in direct physical and electrical connection with the electrically conductive material; and depositing a joining structure over the electrically conductive structure. | 2014-02-06 |
| 20140035128 | SEMICONDUCTOR SEAL RING - Among other things, a semiconductor seal ring and method for forming the same are provided. The semiconductor seal ring comprises a plurality of dielectric layers formed over a semiconductor substrate upon which a semiconductor device is formed. A plurality of conductive layers is arranged among at least some of the plurality of dielectric layers. An upper conductive layer is formed over the plurality of dielectric layers. An upper passivation layer is formed over the upper conductive layer to isolate the upper conductive layer from conductive debris resulting from a die saw process along a die saw cut line. In an example, a first columnar region comprising a first portion of the conductive layers is electrically isolated from the semiconductor device because the first columnar region is disposed relatively close to the die saw cut line and thus can be exposed to conductive debris which can cause undesired short circuits. | 2014-02-06 |
| 20140035129 | THIN INTEGRATED CIRCUIT CHIP-ON-BOARD ASSEMBLY AND METHOD OF MAKING - An integrated circuit assembly includes an insulating layer having a having a first surface and a second surface, where the first surface of the insulating layer is less than 10 microns below an upper plane of the integrated circuit assembly. An active layer contacts the first surface of the insulating layer. A metal bond pad is electrically connected to the active layer and formed on the second surface of the insulating layer, and is also electrically connected to a printed circuit board. A method of fabricating an integrated circuit assembly includes coupling a handle wafer to the active layer of a semiconductor-on-insulator wafer, removing the substrate of the semiconductor-on-insulator, forming a bond pad connecting to the active layer on the exposed insulator surface, bonding the bond pad to a printed circuit board using a solder bump, and removing the handle wafer. | 2014-02-06 |
| 20140035130 | PACKAGING METHOD USING SOLDER COATING BALL AND PACKAGE MANUFACTURED THEREBY - Disclosed herein a packaging method including: (A) forming a plurality of pads and another circuit pattern on a substrate; (B) forming a second dry film pattern including opening exposing the pad; (C) mounting a solder coating ball in the opening of the second dry film pattern; (D) performing a reflow process on the solder coating ball in order to allow the solder coating ball to have a modified pattern; (E) delaminating the second dry film pattern; and (F) forming a solder pattern including the modified pattern of the solder coating ball in a solder to mount a chip on the substrate using the solder pattern. | 2014-02-06 |
| 20140035131 | SEMICONDUCTOR DEVICES HAVING MULTI-BUMP ELECTRICAL INTERCONNECTIONS AND METHODS FOR FABRICATING THE SAME - A method may include providing a substrate including a chip pad, forming on the substrate a solder stack including at least two solder layers which are stacked and at least one intermediate layer interposed between the at least two solder layers. The solder stack can be reflowed to form a bump stack that is electrically connected to the chip pad. The bump stack may include at least two solder bumps which are stacked and the at least one intermediate layer interposed between the at least two solder bumps. Related structures are also disclosed. | 2014-02-06 |
| 20140035132 | SURFACE MOUNT CHIP - A surface mount chip including, on the side of a surface, first and second pads of connection to an external device, wherein, in top view, the first pad has an elongated general shape, and the second pad is a point-shaped pad which is not aligned with the first pad. | 2014-02-06 |
| 20140035133 | SEMICONDUCTOR PACKAGE CONTAINING SILICON-ON-INSULATOR DIE MOUNTED IN BUMP-ON-LEADFRAME MANNER TO PROVIDE LOW THERMAL RESISTANCE - Thermal transfer from a silicon-on-insulator (SOI) die is improved by mounting the die in a bump-on-leadframe manner in a semiconductor package, with solder or other metal bumps connecting the active layer of the SOI die to metal leads used to mount the package on a printed circuit board or other support structure. | 2014-02-06 |
| 20140035134 | DENSE INTERCONNECT WITH SOLDER CAP (DISC) FORMATION WITH LASER ABLATION AND RESULTING SEMICONDUCTOR STRUCTURES AND PACKAGES - Dense interconnect with solder cap (DISC) formation with laser ablation and resulting semiconductor structures and packages are described. For example, a method of fabricating a semiconductor structure includes forming an insulative material stack above a plurality of solder bump landing pads. The solder bump landing pads are above an active side of a semiconductor die. A plurality of trenches is formed in the insulative material stack by laser ablation to expose a corresponding portion of each of the plurality of solder bump landing pads. A solder bump is formed in each of the plurality of trenches. A portion of the insulative material stack is then removed. | 2014-02-06 |
| 20140035135 | SOLDER BUMP FOR BALL GRID ARRAY - A solder bump structure for a ball grid array (BGA) includes at least one under bump metal (UBM) layer and a solder bump formed over the at least one UBM layer. The solder bump has a bump width and a bump height and the ratio of the bump height over the bump width is less than 1. | 2014-02-06 |
| 20140035136 | Embedded Package Security Tamper Mesh - Systems and methods for embedded tamper mesh protection are provided. The embedded tamper mesh includes a series of protection bond wires surrounding bond wires carrying sensitive signals. The protection bond wires are positioned to be vertically higher than the signal bond wires. The protection wires may be bonded to outer contacts on the substrate while the signal bond wires are bonded to inner contacts, thereby creating a bond wire cage around the signal wires. Methods and systems for providing package level protection are also provided. An exemplary secure package includes a substrate having multiple contacts surrounding a die disposed on an upper surface of the substrate. A mesh die including a series of mesh die pads is coupled to the upper surface of the die. Bond wires are coupled from the mesh die pads to contacts on the substrate thereby creating a bond wire cage surrounding the die. | 2014-02-06 |
| 20140035137 | SEMICONDUCTOR PACKAGE AND METHOD OF FORMING THE SAME - Semiconductor packages are disclosed. In a semiconductor package, a package board may include a hole. A mold layer may cover an upper portion of the package board and extend through the hole to cover at least a portion of a bottom surface of the package board. Each of the sidewalls of a lower mold portion may have a symmetrical structure with respect to the hole penetrating the package board, such that a warpage phenomenon of the semiconductor package may be reduced. | 2014-02-06 |
| 20140035138 | PACKAGE STRUCTURE HAVING EMBEDDED SEMICONDUCTOR COMPONENT AND FABRICATION METHOD THEREOF - A package structure having an embedded semiconductor component, includes: a chip having an active surface with electrode pads and an inactive surface opposite to the active surface; a first insulating protection layer having a chip mounting area for the chip to be mounted thereon via the active surface thereof; a plurality of connection columns disposed in the first insulating protection layer at positions corresponding to the electrode pads and electrically connected to the electrode pads via solder bumps; an encapsulant formed on one surface of the first insulating protection layer having the chip mounted thereon for encapsulating the chip; and a built-up structure formed on the other surface of the first insulating protection layer and the connection columns. Due to the bending resistance of the encapuslant, the warpage of the built-up structure is prevented. | 2014-02-06 |
| 20140035139 | SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING THE SAME - To prevent cracking in a passivation film by oxidation of an antireflection film, a semiconductor device includes a metal wiring layer for a pad, an insulating layer which is provided so as to cover the metal wiring layer and which includes an opening portion from which a part of a surface of the metal wiring layer is exposed. The metal wiring layer includes a first metal layer, and a second metal layer which is provided over the first metal layer except for the opening portion and which is thinner than the first metal layer. The metal wiring layer has a groove portion in a predetermined region except for the opening portion. The first metal layer protrudes, in an eaves shape, to the groove portion. The second metal layer on a side wall inside the groove portion is thinner than the second metal layer outside the groove portion. | 2014-02-06 |
| 20140035140 | Semiconductor Structure and Method for Manufacturing the Same - A semiconductor structure and a method for manufacturing the same are provided. The method comprises following steps. A first silicon-containing conductive material is formed on a substrate. A second silicon-containing conductive material is formed on the first silicon-containing conductive material. The first silicon-containing conductive material and the second silicon-containing conductive material have different dopant conditions. The first silicon-containing conductive material and the second silicon-containing conductive material are thermally oxidized for turning the first silicon-containing conductive material wholly into an insulating oxide structure, and the second silicon-containing conductive material into a silicon-containing conductive structure and an insulating oxide layer. | 2014-02-06 |
| 20140035141 | SELF ALIGNED BORDERLESS CONTACT - A method of fabricating a semiconductor structure having a borderless contact, the method including providing a first semiconductor device adjacent to a second semiconductor device, the first and second semiconductor devices being formed on a semiconductor substrate, depositing a non-conductive liner on top of the semiconductor substrate and the first and second semiconductor devices, depositing a contact level dielectric layer on top of the non-conductive liner, etching a contact hole in the contact-level dielectric between the first semiconductor device and the second semiconductor device, and selective to the non-conductive liner, converting a portion of the non-conductive liner exposed in the contact hole into a conductive liner; and forming a metal contact in the contact hole. | 2014-02-06 |
| 20140035142 | PROFILE CONTROL IN INTERCONNECT STRUCTURES - The profile of a via can be controlled by forming a profile control liner within each via opening that is formed into a dielectric material prior to forming a line opening within the dielectric material. The presence of the profile control liner within each via opening during the formation of the line opening prevents rounding of the corners of a dielectric material portion that is present beneath the line opening and adjacent the via opening. | 2014-02-06 |
| 20140035143 | METHOD OF REDUCING CONTACT RESISTANCE OF A METAL - A structure for an integrated circuit with reduced contact resistance is disclosed. The structure includes a substrate, a cap layer deposited on the substrate, a dielectric layer deposited on the cap layer, and a trench embedded in the dielectric layer. The trench includes an atomic layer deposition (ALD) TaN or a chemical vapor deposition (CVD) TaN deposited on a side wall of the trench, a physical vapor deposition (PVD) Ta or a combination of the PVD Ta and a PVD TaN deposited on the ALD TaN or CVD TaN, and a Cu deposited on the PVD Ta or the combination of the PVD Ta and the PVD TaN deposited on the ALD TaN or the CVD TaN. The structure further includes a via integrated into the trench at bottom of the filled trench. | 2014-02-06 |
| 20140035144 | Semiconductor Devices Having Through Electrodes and Methods of Fabricating the Same - Provided are semiconductor devices having through electrodes and methods of fabricating the same. The method includes providing a substrate including top and bottom surfaces facing each other, forming a hole and a gap extending from the top surface of the substrate toward the bottom surface of the substrate, the gap surrounding the hole and being shallower than the hole, filling the hole with an insulating material, forming a metal interconnection line on the top surface of the substrate on the insulating material, recessing the bottom surface of the substrate to expose the insulating material, removing the insulating material to expose the metal interconnection line via the hole, filling the hole with a conductive material to form a through electrode connected to the metal interconnection line, recessing the bottom surface of the substrate again to expose the gap, and forming a lower insulating layer on the bottom surface of the substrate. | 2014-02-06 |
| 20140035145 | SEMICONDUCTOR DEVICE - A semiconductor device includes a GaAs substrate having a first major surface and a second major surface opposite to each other; a nickel diffusion barrier disposed on the first major surface of the GaAs substrate. The nickel diffusion barrier consists of a single layer of Pd. A nickel-containing layer is disposed on the nickel diffusion barrier and the nickel diffusion barrier is interposed between the first major surface of the GaAs substrate and the nickel-containing layer. The nickel diffusion barrier prevents nickel from diffusing from the nickel-containing layer into the GaAs substrate. | 2014-02-06 |
| 20140035146 | METAL WIRING OF SEMICONDUCTOR DEVICE AND METHOD FOR MANUFACTURING THE SAME - A metal wiring for applying a voltage to a semiconductor component of a semiconductor device, the semiconductor device comprising a low voltage applying region adjacent to a high voltage applying region, is provide. The metal wiring includes: an isolator region, a first lower metal layer electrically connected to the semiconductor component, a first upper metal layer configured to be electrically connected to an external power supply, and a plurality of inter-metal dielectric layers deposited between the first lower metal layer and the first upper metal layer, each of the plurality of inter-metal dielectric layers comprising at least one contact plug for providing an electrical connection between the first lower metal layer and the first upper metal layer. | 2014-02-06 |
| 20140035147 | SEMICONDUCTOR DEVICE AND METHOD FOR FABRICATING THE SAME - A method for fabricating a semiconductor device includes forming a first interlayer dielectric layer having a conductive contact, forming a sacrifice layer having a conductive interconnection over the first interlayer dielectric layer such that the conductive interconnection is contacted with the conductive contact, removing the sacrifice layer, and forming a recess by removing a part of the conductive contact exposed by the conductive interconnection. | 2014-02-06 |
| 20140035148 | Bump on Pad (BOP) Bonding structure - The embodiments described above provide enlarged overlapping surface areas of bonding structures between a package and a bonding substrate. By using elongated bonding structures on either the package and/or the bonding substrate and by orienting such bonding structures, the bonding structures are designed to withstand bonding stress caused by thermal cycling to reduce cold joints. | 2014-02-06 |
| 20140035149 | METHOD OF PATTERNING A SEMICONDUCTOR DEVICE HAVING IMPROVED SPACING AND SHAPE CONTROL AND A SEMICONDUCTOR DEVICE - A semiconductor device includes a semiconductor substrate, a first active region in the semiconductor substrate, and a second active region in the semiconductor substrate. The semiconductor device further includes a first conductive line over the semiconductor substrate electrically connected to the first active region and having a first end face adjacent to the second active region, and the first end face having an image log slope of greater than 15 μm | 2014-02-06 |
| 20140035150 | METAL CORED SOLDER DECAL STRUCTURE AND PROCESS - A method and system of producing metal cored solder structures on a substrate which includes: providing a decal having a plurality of apertures, the apertures being tapered from a top surface to a bottom surface; positioning a carrier beneath the bottom of the decal, the carrier having cavities located in alignment with the apertures of the decal; positioning the decal on the carrier having the decal bottom surface in contact with the carrier top surface to form feature cavities defined by the decal apertures and the carrier cavities; positioning a plurality of metal elements in the feature cavities; filling the feature cavities with molten solder and cooling the solder; separating the decal from the carrier to partially expose metal core solder contacts; positioning the metal core solder contacts on receiving elements of a substrate; and exposing the metal core solder contacts on the substrate. | 2014-02-06 |
| 20140035151 | INTEGRATED CIRCUITS AND METHODS FOR FABRICATING INTEGRATED CIRCUITS USING DOUBLE PATTERNING PROCESSES - Integrated circuits and methods for fabricating integrated circuits are provided. One method includes creating a master pattern layout including first and second adjacent cells. The first adjacent cell has a first border pin with a first routing line. The second adjacent cell has a second border pin with a second routing line. The first and second routing lines overlap to define an edge-edge stitch to couple the first and second border pins. The master pattern layout is decomposed into sub-patterns. | 2014-02-06 |
| 20140035152 | Methods for Cell Phasing and Placement in Dynamic Array Architecture and Implementation of the Same - A semiconductor chip is defined to include a logic block area having a first chip level in which layout features are placed according to a first virtual grate, and a second chip level in which layout features are placed according to a second virtual grate. A rational spatial relationship exists between the first and second virtual grates. A number of cells are placed within the logic block area. Each of the number of cells is defined according to an appropriate one of a number of cell phases. The appropriate one of the number of cell phases causes layout features in the first and second chip levels of a given placed cell to be aligned with the first and second virtual grates as positioned within the given placed cell. | 2014-02-06 |
| 20140035153 | RECONSTITUTED WAFER-LEVEL PACKAGE DRAM - A microelectronic package includes first and second encapsulated microelectronic elements, each of which includes a semiconductor die having a front face and contacts thereon. An encapsulant contacts at least an edge surface of each semiconductor die and extends in at least one lateral direction therefrom. Electrically conductive elements extend from the contacts and over the front face to locations overlying the encapsulant. The first and second microelectronic elements are affixed to one another such that one of the front or back surfaces of one of the first and second semiconductor dies is oriented towards one of the front or back surfaces of the other of the first and second semiconductor dies. A plurality of electrically conductive interconnects extend through the encapsulants of the first and second microelectronic elements and are electrically connected with at least one semiconductor die of the first and second microelectronic elements by the conductive elements. | 2014-02-06 |
| 20140035154 | CHIP PACKAGE AND A METHOD FOR MANUFACTURING A CHIP PACKAGE - A chip package is provided, the chip package including: a chip including at least one contact pad formed on a chip front side; an encapsulation material at least partially surrounding the chip and covering the at least one contact pad; and at least one electrical interconnect formed through the encapsulation material, wherein the at least one electrical interconnect is configured to electrically redirect the at least one contact pad from a chip package first side at the chip front side to at least one solder structure formed over a chip package second side at a chip back side. | 2014-02-06 |
| 20140035155 | DEVICE WITH INTEGRATED POWER SUPPLY - Semiconductor devices and methods for forming a semiconductor device are disclosed. The semiconductor device includes a die. The die includes a die substrate having first and second major surfaces. The semiconductor device includes a power module disposed below the second major surface of the die substrate. The power module is electrically coupled to the die through through silicon via (TSV) contacts. | 2014-02-06 |
| 20140035156 | METHOD OF FABRICATING A SEMICONDUCTOR PACKAGE - A method of fabricating a semiconductor package is provided, including: disposing a semiconductor element on a carrier; forming an encapsulant on the carrier to encapsulant the semiconductor element; forming at least one through hole penetrating the encapsulant; forming a hollow conductive through hole in the through hole and, at the same time, forming a circuit layer on an active surface of the semiconductor element and the encapsulant; forming an insulating layer on the circuit layer; and removing the carrier. By forming the conductive through hole and the circuit layer simultaneously, the invention eliminates the need to form a dielectric layer before forming the circuit layer and dispenses with the conventional chemical mechanical polishing (CMP) process, thus greatly improving the fabrication efficiency. | 2014-02-06 |
| 20140035157 | SEMICONDUCTOR PACKAGE, MANUFACTURING METHOD THEREOF, AND SEMICONDUCTOR PACKAGE MANUFACTURING MOLD - There is provided a semiconductor package including: at least one internal lead having at least one electronic component mounted on a surface thereof; a molding unit sealing the electronic component and the internal lead; at least one external lead extending from the internal lead and protruding outwardly from ends of the molding unit; and a stopper provided on the external lead. | 2014-02-06 |
| 20140035158 | Integrated Semiconductor Device and Wafer Level Method of Fabricating the Same - The present disclosure provides one embodiment of a stacked semiconductor device. The stacked semiconductor device includes a first substrate; a first bond pad over the first substrate; a second substrate including a second electrical device fabricated thereon; a second bond pad over the second electrical device over the second substrate, the second bond pad electrically connecting to the second electrical device; a second insulation layer over the second bond pad having a top surface, the second insulation layer being bonded toward the first bond pad of the first substrate; and a through-substrate-via (“TSV”) extending from a surface opposite to the first bond pad through the first substrate and through the top surface of the second insulation layer to the second bond pad. | 2014-02-06 |
| 20140035159 | MULTILEVEL INTERCONNECT STRUCTURES AND METHODS OF FABRICATING SAME - A multilevel interconnect structure for a semiconductor device includes an intermetal dielectric layer with funnel-shaped connecting vias. The funnel-shaped connecting vias are provided in connection with systems exhibiting submicron spacings. The architecture of the multilevel interconnect structure provides a low resistance connecting via. | 2014-02-06 |
| 20140035160 | TWO-TRACK CROSS-CONNECT IN DOUBLE-PATTERNED STRUCTURE USING RECTANGULAR VIA - An integrated circuit may be formed by forming a first interconnect pattern in a first plurality of parallel route tracks, and forming a second interconnect pattern in a second plurality of parallel route tracks, in which the second plurality of route tracks are alternated with the first plurality of route tracks. The first interconnect pattern includes a first lead pattern and the second interconnect pattern includes a second lead pattern, such that the route track containing the first lead pattern is immediately adjacent to the route track containing the second lead pattern. Metal interconnect lines are formed in the first interconnect pattern and the second interconnect pattern. A stretch crossconnect is formed in a vertical connecting level, such as a via or contact level, which electrically connects only the first lead and the second lead. The stretch crossconnect is formed concurrently with other vertical interconnect elements. | 2014-02-06 |
| 20140035161 | SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING THE SAME - A semiconductor device includes a first wiring board, a second semiconductor chip, and a second seal. The first wiring board includes a first substrate, a first semiconductor chip, and a first seal. The first semiconductor chip is disposed on the first substrate. The first seal is disposed on the first substrate. The first seal surrounds the first semiconductor chip. The first seal has the same thickness as the first semiconductor chip. The second semiconductor chip is stacked over the first semiconductor chip. The first semiconductor chip is between the second semiconductor chip and the first substrate. The second semiconductor chip is greater in size in plan view than the first semiconductor chip. The second seal seals at least a first gap between the first semiconductor chip and the second semiconductor chip. | 2014-02-06 |
| 20140035162 | Interface Substrate with Interposer - An interface substrate is disclosed which includes an interposer having through-semiconductor vias. An upper and a lower organic substrate are further built around the interposer. The disclosed interface substrate enables the continued use of low cost and widely deployed organic substrates for semiconductor packages while providing several advantages. The separation of the organic substrate into upper and lower substrates enables the cost effective matching of fabrication equipment. By providing an opening in one of the organic substrates, one or more semiconductor dies may be attached to exposed interconnect pads coupled to through-semiconductor vias of the interposer, enabling the use of flip chips with high-density microbump arrays and the accommodation of dies with varied bump pitches. By providing the opening specifically in the upper organic substrate, a package-on-package structure with optimized height may also be provided. | 2014-02-06 |
| 20140035163 | Semiconductor Package with Interface Substrate Having Interposer - An interface substrate is disclosed which includes an interposer having through-semiconductor vias. An upper and a lower organic substrate are further built around the interposer. The disclosed interface substrate enables the continued use of low cost and widely deployed organic substrates for semiconductor packages while providing several advantages. The separation of the organic substrate into upper and lower substrates enables the cost effective matching of fabrication equipment. By providing an opening in one of the organic substrates, one or more semiconductor dies may be attached to exposed interconnect pads coupled to through-semiconductor vias of the interposer, enabling the use of flip chips with high-density microbump arrays and the accommodation of dies with varied bump pitches. By providing the opening specifically in the upper organic substrate, a package-on-package structure with optimized height may also be provided. | 2014-02-06 |
| 20140035164 | Semiconductor Device and Method of Fabricating the Same - A semiconductor device includes a via structure having a top surface with a planar portion and a protrusion portion that is surrounded by the planar portion, and includes a conductive structure including a plurality of conductive lines contacting at least a part of the top surface of the via structure. | 2014-02-06 |
| 20140035165 | Pierced Substrate on Chip Module Structure - The present invention provides a pierced substrate on chip module structure comprising a first substrate. A chip is configured on the first substrate, with a first contact pad and a sensing area. A second substrate is disposed on the first substrate and the chip, with a concave structure, at least one through hole structure and a second contact pad, wherein the chip is disposed within the concave structure, and the first contact pad and the sensing area are exposed over the through hole structure. The first contact is coupled to the second contact pad via a wire. A transparent material is disposed on the second substrate, substantially aligning to the sensing area. A lens holder is disposed on the second substrate, and a lens is located on the top of the lens holder, substantially aligning to the transparent material and the sensing area. | 2014-02-06 |
| 20140035166 | SEMICONDUCTOR DEVICE STACK WITH BONDING LAYER AND WIRE RETAINING MEMBER - In a semiconductor device of the present invention, a second semiconductor chip is stacked on a first semiconductor chip having a plurality of bonding pads in its central region, with a bonding layer interposed therebetween. A plurality of wires respectively connected to the plurality of bonding pads of the first semiconductor chip are led out to the outside over a peripheral edge of the first semiconductor chip by passing through a space between the first and second semiconductor chips. A retaining member for retaining at least a subset of the plurality of wires is provided in a region on the first semiconductor chip including a middle point between the bonding pads and the peripheral edge of the first semiconductor chip by using a material different from the bonding layer so that the subset of the wires is positioned generally at a center of the spacing between the first semiconductor chip and the second semiconductor chip. | 2014-02-06 |
| 20140035167 | METHOD FOR PRODUCING A BONDING PAD FOR THERMOCOMPRESSION BONDING, AND BONDING PAD - A method produces a bonding pad for thermocompression bonding. The method includes providing a carrier material having semiconductor structures, wherein an outermost edge layer of the carrier material is a wiring metal layer configured to make electrical contact with the semiconductor structures. The method also includes depositing a single-layered bonding metal layer directly on a surface of the wiring metal layer to produce the bonding pad. | 2014-02-06 |
| 20140035168 | BONDING PAD FOR THERMOCOMPRESSION BONDING, PROCESS FOR PRODUCING A BONDING PAD AND COMPONENT - A bonding pad for thermocompression bonding of a carrier material to a further carrier material includes a base layer and a top layer. The base layer is made of metal, is deformable, and is connected to the carrier material. The metal is nickel-based. The top layer is metallic and is connected directly to the base layer. The top layer is arranged at least on a side of the base layer which faces away from the carrier material. The top layer has a smaller layer thickness than the base layer. In at least one embodiment, the top layer has a greater oxidation resistance than the base layer. | 2014-02-06 |
| 20140035169 | TOP CORNER ROUNDING OF DAMASCENE WIRE FOR INSULATOR CRACK SUPPRESSION - A structure and method for fabricating the structure that provides a metal wire having a first height at an upper surface. An insulating material surrounding said metal wire is etched to a second height below said first height of said upper surface. The metal wire from said upper surface, after etching said insulating material, is planarized to remove sufficient material from a lateral edge portion of said metal wire such that a height of said lateral edge portion is equivalent to said second height of said insulating material surrounding said metal wire. | 2014-02-06 |
| 20140035170 | SEMICONDUCTOR DEVICE AND PROGRAMMING METHOD - The present invention include a semiconductor device and a method therefor, the method includes disposing a sheet-shaped resin at a side opposite to the chip mounting portion mounting semiconductor chips to be mounted on the chip mounting portion, and forming a resin sealing portion between the sheet-shaped resin and the chip mounting portion, to seal the semiconductor chips. According to an aspect of the present invention, it is possible to provide a semiconductor device and a fabrication method therefor, by which it is possible to reduce the size of the package and to prevent the generation of an unfilled portion in a resin sealing portion or a filler-removed portion or to prevent the exposure of wire from the resin sealing portion. | 2014-02-06 |
| 20140035171 | SEMICONDUCTOR DEVICE AND DISPLAY DEVICE HAVING ALIGNMENT MARK - An exemplary display device includes a transparent substrate and a semiconductor device bonded to the transparent substrate. The transparent substrate includes a first alignment mark. The semiconductor device includes a substrate and a second alignment mark positioned on the substrate. The second alignment mark includes a first pattern structure positioned on the substrate and a second pattern structure positioned on the first pattern structure. The first pattern structure includes a plurality of first non-transparent marks. The second pattern structure includes a second pattern surrounded by the first non-transparent marks. The second pattern is an alignable shape that corresponds to a shape of the first alignment mark on the transparent substrate. | 2014-02-06 |
| 20140035172 | SELF-SUPPORTING WINE AERATORS AND PROTECTIVE COVERS THEREFORE - A liquid aerator includes (i) a porous diffuser; (ii) a stem connected to the porous diffuser; (iii) an insert connected to the stem; and (iv) a manual air pump connected sealingly to the insert, the manual air pump configured such that the aerator can be set onto a supporting structure with the stem and the porous diffuser extending upwardly from the manual air pump. | 2014-02-06 |
| 20140035173 | Method And Apparatus To Generate Bubbles In A Material - A system and method of injecting a gas enriched and/or emulsified first liquid into a second liquid is disclosed. The injection can cause generation of a high density of bubbles having a mean diameter of a selected size. The mean diameter of the bubbles can be selected and varied based on the characteristics of the injection system. | 2014-02-06 |
| 20140035174 | METHOD FOR ACCESSING OPTICAL FIBRES INCLUDED IN AN OPTICAL MODULE OF AN OPTICAL FIBRE TRANSMISSION CABLE - A method is proposed for access to optical fibres contained in an optical module, with a flexible structure for example, of an optical fibre transmission cable. The optical module includes a protective sheath in which the optical fibres are housed. Such a method includes: extracting the optical module from the transmission cable; degrading a portion to be stripped of the sheath of the optical module by heating to a specific temperature, for a predetermined duration; and accessing the optical fibres by stripping the portion to be stripped that has been degraded. | 2014-02-06 |
| 20140035175 | METHOD OF FORMING SINGLE-MODE POLYMER WAVEGUIDE ARRAY ASSEMBLY - High accuracy positioning relative to an absolute reference position (guide pin holes in ferrules, etc.) is provided for a plurality of cores constituting a polymer waveguide array for connection to ferrules at ends of a plurality of these assemblies to form a single-mode polymer waveguide array assembly. A method for forming a single-mode polymer waveguide array assembly enables a plurality of cores constituting a polymer waveguide array to be positioned with high accuracy. Also provided is a combination of process molds (an initial process mold and intermediate process mold) used in the processes unique to the present methods. | 2014-02-06 |
| 20140035176 | CONTACT LENS MANUFACTURING METHOD - In manufacturing a contact lens, a contact lens mould arrangement in which the engagement between the mould halves is unconstrained and at least one mould half is sufficiently pliable or flexible that during the curing of the contact lens composition at one mold half may move or flex relative to the other to define a post-cure mould cavity of smaller volume than the pre-cure mould cavity and during which the curvatures of the first and/or second mould surfaces are allowed to change provides a significantly more efficient manufacturing process and enables one mould half to be readily utilized as a blister cup for contact lens packaging. | 2014-02-06 |
| 20140035177 | DEVICES AND METHODS FOR THE PRODUCTION OF MICROFIBERS AND NANOFIBERS HAVING ONE OR MORE ADDITIVES - Described herein are apparatuses and methods of creating fibers, such as microfibers and nanofibers, which include additives that modify one or more properties of the produced fibers. The methods discussed herein employ centrifugal forces to transform material into fibers. Apparatuses that may be used to create fibers are also described. | 2014-02-06 |
| 20140035178 | SYSTEMS AND METHODS OF SUPPLYING MATERIALS TO A ROTATING FIBER PRODUCING DEVICE - Described herein are apparatuses and methods of creating fibers, such as microfibers and nanofibers. The methods discussed herein employ centrifugal forces to transform material into fibers. Apparatuses that may be used to create fibers are also described. Use of material transfer conduits allows the continuous production of fibers without the need to stop the process to refill the fiber producing device. | 2014-02-06 |
| 20140035179 | DEVICES AND METHODS FOR THE PRODUCTION OF MICROFIBERS AND NANOFIBERS - Described herein are apparatuses and methods of creating fibers, such as microfibers and nanofibers, that include additives that modify one or more properties of the produced fibers. The methods discussed herein employ centrifugal forces to transform material into fibers. Apparatuses that may be used to create fibers are also described. Fiber producing devices with features that enhance fiber production and adaptability to different types of fiber are described. | 2014-02-06 |
| 20140035180 | SINGLE STAGE LUTEIN ESTER EXTRACTION FROM TAGETES SPECIES-MARIGOLD FLOWER MEAL - A single stage straight forward process for extraction and isolation of lutein ester from the dried petals of marigold flowers Tagetes species using the carbondioxide as the supercritical fluid was developed. The pressure maintained for the extraction was up to 625 bar and at temperature up to 750 Centigrade. Lutein ester of high strength and purity up to 70% was achieved for the first time in single stage from the dried petals of marigold flowers-Tagetes species while enrichment of the lutein ester content up to 98% was achieved by crystallization of the lutein ester obtained from supercritical carbon dioxide extract (SCFE). The high strength and purified lutein ester isolated by supercritical fluid-single stage extraction process are free from saturated fat, oil, waxy impurities and serve as a safe source of nutritional supplement for human consumption and color additive for human foods. | 2014-02-06 |
| 20140035181 | SYSTEM FOR SURFACE PROFILING OF POURED CONCRETE SLABS - Apparatus for creating a step or break in level of a poured concrete building slab, said apparatus comprising a length of section of suitable height and closed or open cross-sectional shape supported upon a plurality of discrete chairs which are, in turn, fixed to supporting formwork by suitable fastenings; said chairs being unitary or comprising height-adjustable elements; said section providing level references to which the surfaces of the higher and lower parts of said concrete slab are finished and acting as a riser between the two said surfaces; said section and said chairs being left in place in said concrete slab following its curing. | 2014-02-06 |
| 20140035182 | AUGMENTED THREE-DIMENSIONAL PRINTING - A variety of techniques are disclosed for visual and functional augmentation of a three-dimensional printer. | 2014-02-06 |
| 20140035183 | METHOD FOR THE PRODUCTION OF A BODY IMPLANT AND BODY IMPLANT - A method for production of a body implant ( | 2014-02-06 |
| 20140035184 | EXTENDED RELEASE BIODEGRADABLE OCULAR IMPLANTS - Biodegradable implants sized and suitable for implantation in an ocular region or site and methods for treating ocular conditions. The implants provide an extended release of an active agent at a therapeutically effective amount for a period of time between 50 days and one year, or longer. | 2014-02-06 |
| 20140035185 | METHOD FOR FORMING HOLLOW FIBER BUNDLES - A method of forming a plurality of hollow fibers includes the step of providing an elongated flexible substantially continuous fiber and coating an outer surface of the fiber with a hollow fiber material. The hollow fiber material is cured or hardened. A gap is created between the outer surface of the support fiber and the inner surface of the coating layer defined thereon. The coated support fiber is cut into a plurality of fiber segments each having exposed ends. The support fiber segments are removed from the coating layer so as to provide a plurality of hollow fibers. | 2014-02-06 |
| 20140035186 | FIELD JOINT COATING MATERIAL AND A PROCESS FOR MAKING A FIELD JOINT - The invention relates to a field joint coating material based on a fast curable olefin liquid formulation and a process of making a field joint wherein this coating material is used. | 2014-02-06 |
| 20140035187 | STRIPPER ROLL FOR USE WITH CALENDERING DRIVES PROCESSING ELASTOMERIC MIXES - A method and apparatus are provided for automatic and hands-free threading of an elastomeric mix into a calender set of rolls comprising one or more pairs of rolls that have a nip between them. A stripper roll is positioned next to one of the rolls forming the nip and is rotated so that the outer surface of the stripper roll moves in a direction opposite to the outer surface of the adjacent roll. The stripper roll removes all or a desired portion of the elastomeric mix from the adjacent roll and causes the same to transfer to another roll. Variables such as e.g., the relative surface speed of the stripper roll, diameter of the stripper roll, and distance of the outer surface of the stripper roll from the adjacent roll can be manipulated to control the amount of the elastomeric mix that is stripped by the stripper roll. | 2014-02-06 |
| 20140035188 | BIASING WEDGE FOR USE WITH CALENDERING DRIVES PROCESSING ELASTOMERIC MIXES - A method and apparatus are provided for automatic and hands-free threading of an elastomeric mix into a calender set of rolls comprising one or more pairs of rolls that have a nip between them. A wedge is provided with a tip that is positioned downstream from the nip and at a predetermined distance from the nip. As the rolls of the nip are rotated, the tip of the edge removes all, or a desired portion of, the elastomeric mix from a first roll of the nip so as to transfer the elastomeric mix to a second roll of the nip. The tip of the wedge may be placed into contact with the first roll. The wedge may also have an arcuate surface, shaped e.g., like the outer surface of the first roll, and positioned a predetermined distance from the outer surface of the first roll. | 2014-02-06 |
| 20140035189 | EXTRUSION DEVICE AND METHOD FOR INFLUENCING WALL THICKNESSES OF AN EXTRUDED PLASTIC PROFILE - The invention relates to an extrusion device and an extrusion method for the extrusion of plastic profiles ( | 2014-02-06 |
| 20140035190 | DIVIDED CONDUIT EXTRUSION DIE AND METHOD FOR ONE OR MORE MATERIAL LAYERS - An apparatus and method are provided for making a conduit divided into channels by one or more strip-shaped substrates. The channels may be used for cables, such as fiber optic cables, coaxial cables, electrical cables, electrical wiring, and the like. Each divided conduit provides channels that allow e.g., cables to be pulled through without snagging or excessive heat build-up due to friction. In addition, the divided conduits do not allow contact or alternation losses between adjacent cables in other channels of the conduit. | 2014-02-06 |
| 20140035191 | THREE DIMENSIONAL NETTED STRUCTURE - A three-dimensional netted structure having an upper surface, a lower surface, two side surfaces a left end surface, and a right end surface, including at least a plurality of filaments helically and randomly entangled and thermally bonded together, wherein the filaments are formed out of a thermoplastic resin by extrusion molding followed by cooling with a liquid; and the netted structure is four-surface molded, the upper surface, the lower surface and the two side surfaces being molded. An apparatus and a method for manufacturing the three-dimensional netted structure. | 2014-02-06 |
