| 06th week of 2014 patent applcation highlights part 17 |
| Patent application number | Title | Published |
|---|
| 20140034992 | SEMICONDUCTOR LIGHT EMITTING ELEMENT AND METHOD FOR MANUFACTURING THE SAME | 2014-02-06 |
| 20140034993 | SEMICONDUCTOR DEVICE AND METHOD FOR MANUFACTURING THE SAME - A semiconductor device according to an embodiment includes a heat dissipation member having a first upper surface, the first upper surface being provided with grooves formed on the first upper surface; a bonding member provided on the heat dissipation member and burying the grooves; and a wiring substrate provided on the bonding member, the wiring substrate having a second upper surface and a lower surface opposite to the second upper surface, the wiring substrate including a semiconductor unit and a bonding electrode, the semiconductor unit being provided on the second upper surface and including a light emitting layer, the bonding electrode being provided on the lower surface, the bonding electrode being bonded to the heat dissipation member via the bonding member. | 2014-02-06 |
| 20140034994 | METHOD FOR MANUFACTURING LIGHT EMITTING DEVICE, AND LIGHT EMITTING DEVICE - A method for manufacturing a light-emitting device, comprising: forming, over a substrate, a plurality of multilayered light-emitting structures each including a first electrode, a light-emitting layer, and a second electrode; forming, in the substrate, a plurality of grooves that surround the multilayered light-emitting structures individually; forming, over the substrate, a sealing film that covers the multilayered light-emitting structures and the grooves; and separating the multilayered light-emitting structures from one another after forming the sealing film, by cutting the substrate such that, in each groove, part of the sealing film covering a given inner side surface of the groove remains, the given inner side surface being adjacent to any of the multilayered light-emitting structures. | 2014-02-06 |
| 20140034995 | ACTIVE EDGE STRUCTURES PROVIDING UNIFORM CURRENT FLOW IN INSULATED GATE TURN-OFF THYRISTORS - An insulated gate turn-off thyristor, formed as a die, has a layered structure including a p+ layer (e.g., a substrate), an n− layer, a p-well, vertical insulated gate regions formed in the p-well, and n+ regions between the gate regions, so that vertical NPN and PNP transistors are formed. The thyristor is formed of a matrix of cells. Due to the discontinuity along the edge cells, a relatively large number of holes are injected into the n− epi layer and drift into the edge p-well, normally creating a higher current along the edge and lowering the breakover voltage of the thyristor. To counter this effect, the dopant concentration of the n+ region(s) near the edge is reduced to reduce the NPN transistor beta and current along the edge, thus increasing the breakover voltage. Alternatively, a deep trench may circumscribe the edge cells to provide isolation from the injected holes. | 2014-02-06 |
| 20140034996 | ESD CLAMP WITH AUTO BIASING UNDER HIGH INJECTION CONDITIONS - In a dual direction ESD protection circuit formed from multiple base-emitter fingers that include a SiGe base region, and a common sub-collector region, the I-V characteristics are adjusted by including P+ regions to define SCR structures that are operable to sink positive and negative ESD pulses, and adjusting the layout and distances between regions and the number of regions. | 2014-02-06 |
| 20140034997 | BIPOLAR PUNCH-THROUGH SEMICONDUCTOR DEVICE AND METHOD FOR MANUFACTURING SUCH A SEMICONDUCTOR DEVICE - A method for manufacturing a bipolar punch-through semiconductor device is disclosed, which includes providing a wafer having a first and a second side, wherein on the first side a high-doped layer of the first conductivity type having constant high doping concentration is arranged; epitaxially growing a low-doped layer of the first conductivity type on the first side; performing a diffusion step by which a diffused inter-space region is created at the inter-space of the layers; creating at least one layer of the second conductivity type on the first side; and reducing the wafer thickness within the high-doped layer on the second side so that a buffer layer is created, which can include the inter-space region and the remaining part of the high-doped layer, wherein the doping profile of the buffer layer decreases steadily from the doping concentration of the high-doped region to the doping concentration of the drift layer. | 2014-02-06 |
| 20140034998 | Semiconductor Device with Laterally Varying Doping Concentrations - A semiconductor device includes a semiconductor body including a first surface having a normal direction defining a vertical direction, a first n-type semiconductor region arranged below the first surface and having a first maximum doping concentration and a second n-type semiconductor region arranged below the first n-type semiconductor region and including, in a vertical cross-section, two spaced apart first n-type portions each adjoining the first n-type semiconductor region, having a maximum doping concentration which is higher than the first maximum doping concentration and having a first minimum distance to the first surface, and a second n-type portion adjoining the first n-type semiconductor region, having a maximum doping concentration which is higher than the first maximum doping concentration and a second minimum distance to the first surface which is larger than the first minimum distance. A p-type second semiconductor layer forms a pn-junction with the second n-type portion. | 2014-02-06 |
| 20140034999 | POWER DEVICE INTEGRATION ON A COMMON SUBSTRATE - A semiconductor structure for facilitating an integration of power devices on a common substrate includes a first insulating layer formed on the substrate and an active region having a first conductivity type formed on at least a portion of the first insulating layer. A first terminal is formed on an upper surface of the structure and electrically connects with at least one other region having the first conductivity type formed in the active region. A buried well having a second conductivity type is formed in the active region and is coupled with a second terminal formed on the upper surface of the structure. The buried well and the active region form a clamping diode which positions a breakdown avalanche region between the buried well and the first terminal. A breakdown voltage of at least one of the power devices is a function of characteristics of the buried well. | 2014-02-06 |
| 20140035000 | Source and Drain Doping Profile Control Employing Carbon-Doped Semiconductor Material - Carbon-doped semiconductor material portions are formed on a subset of surfaces of underlying semiconductor surfaces contiguously connected to a channel of a field effect transistor. Carbon-doped semiconductor material portions can be formed by selective epitaxy of a carbon-containing semiconductor material layer or by shallow implantation of carbon atoms into surface portions of the underlying semiconductor surfaces. The carbon-doped semiconductor material portions can be deposited as layers and subsequently patterned by etching, or can be formed after formation of disposable masking spacers. Raised source and drain regions are formed on the carbon-doped semiconductor material portions and on physically exposed surfaces of the underlying semiconductor surfaces. The carbon-doped semiconductor material portions locally retard dopant diffusion from the raised source and drain regions into the underlying semiconductor material regions, thereby enabling local tailoring of the dopant profile, and alteration of device parameters for the field effect transistor. | 2014-02-06 |
| 20140035001 | COMPOUND SEMICONDUCTOR STRUCTURE - A semiconductor structure ( | 2014-02-06 |
| 20140035002 | HIGH BREAKDOWN VOLTAGE SEMICONDUCTOR DEVICE - Semiconductor regions are alternately arranged in a parallel pn layer in which an n-type region and a p-type region are alternately arranged parallel to the main surface of a semiconductor substrate. Pitch between n drift region and p partition region of a second parallel pn layer in an edge termination region is two thirds of pitch between n drift region and p partition region of a first parallel pn layer in an active region. At boundaries between main SJ cells and fine SJ cells at four corners of the semiconductor substrate having rectangular shape in plan view, ends of two pitches of main SJ cells face the ends of three pitches of fine SJ cells. In this way, it is possible to reduce the influence of a process variation and thus reduce mutual diffusion between n drift region and p partition region of the fine SJ cell. | 2014-02-06 |
| 20140035003 | Protection Device for Normally-On and Normally-Off High Electron Mobility Transistors - A transistor device includes a compound semiconductor body, a normally-on high electron mobility field effect transistor (HEMT) formed in the compound semiconductor body and a protection device monolithically integrated in the same compound semiconductor body as the normally-on HEMT. The normally-on HEMT has a source, a drain, a gate, and a threshold voltage. The protection device has a source and a drain each shared with the normally-on HEMT, a gate and a positive threshold voltage that is less than a difference of the threshold voltage of the normally-on HEMT and a gate voltage used to turn off the normally-on HEMT. The protection device is operable to conduct current in a reverse direction when the normally-on HEMT is switched off. A transistor device including a normally-off HEMT and a monolithically integrated protection device is also provided. | 2014-02-06 |
| 20140035004 | SEMICONDUCTOR DEVICE - According to one embodiment, a semiconductor device has a first nitride semiconductor layer, a second nitride semiconductor layer provided on the first nitride semiconductor layer and formed of a non-doped or n-type nitride semiconductor having a band gap wider than that of the first nitride semiconductor layer, a heterojunction field effect transistor having a source electrode, a drain electrode, and a gate electrode, a Schottky barrier diode having an anode electrode and a cathode electrode, and first and second element isolation insulating layers. The first element isolation insulating layer has a first end contacting with the drain electrode and the anode electrode, and a second end located in the first nitride semiconductor layer. The second element isolation insulating layer has a third end contacting with the cathode electrode, and a fourth end located in the first nitride semiconductor layer. | 2014-02-06 |
| 20140035005 | Monolithic Integrated Group III-V and Group IV Device - According to one disclosed embodiment, a monolithic vertically integrated composite device comprises a double sided semiconductor substrate having first and second sides, a group IV semiconductor layer formed over the first side and comprising at least one group IV semiconductor device, and a group III-V semiconductor body formed over the second side and comprising at least one group III-V semiconductor device electrically coupled to the at least one group IV semiconductor device. The composite device may further comprise a substrate via and/or a through-wafer via providing electric coupling. In one embodiment, the group IV semiconductor layer may comprise an epitaxial silicon layer, and the at least one group IV semiconductor device may be a combined FET and Schottky diode (FETKY) fabricated on the epitaxial silicon layer. In one embodiment, the at least one group semiconductor device may be a III-nitride high electron mobility transistor (HEMT). | 2014-02-06 |
| 20140035006 | DETECTION APPARATUS, DETECTION SYSTEM, AND METHOD FOR MANUFACTURING DETECTION APPARATUS - A detection apparatus includes a plurality of pixels and a plurality of signal wires arranged on a substrate, in which each of the plurality of pixels includes a switch element arranged on the substrate and a conversion element arranged on the switch element, the conversion element includes a first electrode which is arranged on the switch element and electrically connected to the switch element and a semiconductor layer arranged over a plurality of the first electrodes, and a plurality of the switch elements is electrically connected to the plurality of signal wires, and the detection apparatus further includes a constant potential wire which is supplied with a constant potential, in which the first electrode is electrically connected to the constant potential wire in apart of pixels among the plurality of pixels. | 2014-02-06 |
| 20140035007 | Gas Sensor for Determining Substances Contained in a Gas Mixture and Method for Producing such a Sensor - The present disclosure relates to a gas sensor for determining substances contained in a gas mixture, comprising a substrate on which a source electrode, a drain electrode and a gate electrode are arranged, at least one electrically insulating layer being arranged between the substrate and the gate electrode, the gate electrode comprising an electrically conductive ceramic material, and the gate electrode having a range of variation of its thickness that is greater than or equal to one quarter of its total thickness. Such a gas sensor may have in particular improved measuring characteristics and, furthermore, allow itself to be produced in an improved way. The present disclosure also relates to a method for producing such a gas sensor. | 2014-02-06 |
| 20140035008 | CMOS WITH CHANNEL P-FINFET AND CHANNEL N-FINFET HAVING DIFFERENT CRYSTALLINE ORIENTATIONS AND PARALLEL FINS - An integrated circuit includes at least one single-crystal fin having a first crystal orientation. The integrated circuit also includes at least one single-crystal fin having a second crystal orientation. The single-crystal fin having the first crystal orientation and the single-crystal fin having the second crystal orientation are substantially parallel. | 2014-02-06 |
| 20140035009 | SEMICONDUCTOR DEVICE STRUCTURES AND METHODS OF FORMING SEMICONDUCTOR STRUCTURES - A method of patterning a semiconductor film is described. According to an embodiment of the present invention, a hard mask material is formed on a silicon film having a global crystal orientation wherein the semiconductor film has a first crystal plane and second crystal plane, wherein the first crystal plane is denser than the second crystal plane and wherein the hard mask is formed on the second crystal plane. Next, the hard mask and semiconductor film are patterned into a hard mask covered semiconductor structure. The hard mask covered semiconductor structured is then exposed to a wet etch process which has sufficient chemical strength to etch the second crystal plane but insufficient chemical strength to etch the first crystal plane. | 2014-02-06 |
| 20140035010 | INTEGRATED CIRCUIT HAVING A REPLACEMENT GATE STRUCTURE AND METHOD FOR FABRICATING THE SAME - A method for fabricating an integrated circuit includes forming a temporary gate structure on a semiconductor substrate. The temporary gate structure includes a temporary gate material disposed between two spacer structures. The method further includes forming a first directional silicon nitride liner overlying the temporary gate structure and the semiconductor substrate, etching the first directional silicon nitride liner overlying the temporary gate structure and the temporary gate material to form a trench between the spacer structures, while leaving the directional silicon nitride liner overlying the semiconductor substrate in place, and forming a replacement metal gate structure in the trench. An integrated circuit includes a replacement metal gate structure overlying a semiconductor substrate, a silicide region overlying the semiconductor substrate and positioned adjacent the replacement gate structure; a directional silicon nitride liner overlying a portion of the replacement gate structure; and a contact plug in electrical communication with the silicide region. | 2014-02-06 |
| 20140035011 | METHODS AND DEVICES FOR FORMING NANOSTRUCTURE MONOLAYERS AND DEVICES INCLUDING SUCH MONOLAYERS - Methods for forming or patterning nanostructure arrays are provided. The methods involve formation of arrays on coatings comprising nanostructure association groups, formation of arrays in spin-on-dielectrics, solvent annealing after nanostructure deposition, patterning using resist, and/or use of devices that facilitate array formation. Related devices for forming nanostructure arrays are also provided, as are devices including nanostructure arrays (e.g., memory devices). Methods for protecting nanostructures from fusion during high temperature processing also are provided. | 2014-02-06 |
| 20140035012 | LIGHT SENSOR HAVING IR CUT INTERFERENCE FILTER WITH COLOR FILTER INTEGRATED ON-CHIP - Techniques are described to furnish a light sensor that includes a patterned IR interference filter integrated with a patterned color pass filter. In one or more implementations, the light sensor includes a substrate having a surface. An IR interference filter configured to block infrared light is disposed over the surface of the substrate. The light sensor also includes one or more color pass filters placed above or below the IR interference filter. The color pass filters are configured to filter visible light to pass light in a limited spectrum of wavelengths to the one or more photodetectors. | 2014-02-06 |
| 20140035013 | Novel CMOS Image Sensor Structure - Provided is a method of fabricating an image sensor device. The method includes providing a first substrate having a radiation-sensing region disposed therein. The method includes providing a second substrate having a hydrogen implant layer, the hydrogen implant layer dividing the second substrate into a first portion and a second portion. The method includes bonding the first portion of the second substrate to the first substrate. The method includes after the bonding, removing the second portion of the second substrate. The method includes after the removing, forming one or more microelectronic devices in the first portion of the second substrate. The method includes forming an interconnect structure over the first portion of the second substrate, the interconnect structure containing interconnect features that are electrically coupled to the microelectronic devices. | 2014-02-06 |
| 20140035014 | OTP MEMORY CELL AND FABRICATING METHOD THEREOF - A one-time programmable (OTP) memory cell is provided, which includes: a well of a first conductivity type; a gate insulating layer formed on the well and including first and second fuse regions; a gate electrode of a second conductivity type formed on the gate insulating layer, the second conductivity type being opposite in electric charge to the first conductivity type; a junction region of the second conductivity type formed in the well and arranged to surround the first and second fuse regions; and an isolation layer formed in the well between the first fuse region and the second fuse region. | 2014-02-06 |
| 20140035015 | APPARATUS RELATING TO A MEMORY CELL HAVING A FLOATING BODY - An apparatus is disclosed for a memory cell having a floating body. A memory cell may include a transistor over an insulation layer, the transistor including a source, and a drain. The memory cell may also include a floating body including a first region positioned between the source and the drain, a second region positioned remote from each of the source and drain, and a passage extending through the insulation layer and coupling the first region to the second region. Additionally, the memory cell may include a bias gate at least partially surrounding the second region and configured for operably coupling to a bias voltage. Furthermore, the memory cell may include a plurality of dielectric layers, wherein each outer vertical surface of the second region has a dielectric layer of the plurality adjacent thereto. | 2014-02-06 |
| 20140035016 | SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING THE SAME - Provided is a semiconductor device including, on the same semiconductor substrate, a transistor element, a capacitor, and a resistor. The capacitor is formed on an active region, and the resistor is formed on an element isolation region, both formed of the same polysilicon film. By CMP or etch-back, the surface is ground down while planarizing the surface until a resistor has a desired thickness. Owing to a difference in height between the active region and the element isolation region, a thin resistor and a thick upper electrode of the capacitor are formed to prevent passing through of a contact. | 2014-02-06 |
| 20140035017 | NONVOLATILE MEMORY DEVICE AND METHOD OF FORMING THE SAME - A nonvolatile memory device has a first active region and a second active region defined in a substrate by a device isolation layer, a Metal Oxide Silicon Field-Effect Transistor (MOSFET) disposed on the first active region and including a first electrode pattern, and a Metal Oxide Silicon (MOS) capacitor disposed on the second active region and including a second electrode pattern, and in which the first electrode pattern is narrower in the widthwise direction of the channel of the MOSFET than the first active region. | 2014-02-06 |
| 20140035018 | SEMICONDUCTOR DEVICES INCLUDING VERTICAL TRANSISTORS AND METHODS OF FABRICATING THE SAME - A semiconductor device includes a first capacitor in a trench of a semiconductor substrate and an active pillar disposed on the semiconductor substrate opposite the first capacitor. The active pillar includes first region, first channel region, second region, second channel region and third region, sequentially stacked. A pillar connection pattern electrically connects the first capacitor to a first source region. A first gate electrode is disposed on a sidewall of the first channel region. A common drain region is disposed in the second region, and a common bit line is disposed on a sidewall of the common drain region. A second gate electrode is disposed on a sidewall of the second channel region, and a second source region is disposed in the third region. A second capacitor is disposed on a top surface of the second source region opposite the second channel region. | 2014-02-06 |
| 20140035019 | SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING THE SAME - A semiconductor device includes an interlayer insulating layer having openings, contact plugs formed in lower parts of the openings, wherein the contact plugs include a first conductive layer, and bit lines formed in upper parts of the openings and coupled to the contact plugs, wherein the bit lines include a second conductive layer. | 2014-02-06 |
| 20140035020 | Method of Forming an Embedded Memory Device - The present disclosure describes a method of forming a memory device. The method includes receiving a wafer substrate, forming a poly stack pattern on the wafer substrate, performing an ion implantation process to form a source and a drain in the wafer substrate, forming a memory gate and a control gate in the defined poly stack pattern, and forming a control gate in the control poly stack pattern. Forming the memory gate further includes performing a memory gate recess to bury the memory gate in an oxide layer. | 2014-02-06 |
| 20140035021 | Memory Devices Comprising Word Line Structures, At Least One Select Gate Structure, and a Plurality Of Doped Regions - Disclosed is a method of forming memory devices employing halogen ion implantation and diffusion processes. In one illustrative embodiment, the method includes forming a plurality of word line structures above a semiconducting substrate, each of the word line structures comprising a gate insulation layer, performing an LDD ion implantation process to form LDD doped regions in the substrate between the word line structures, performing a halogen ion implantation process to implant atoms of halogen into the semiconducting substrate between the word line structures, and performing at least one anneal process to cause at least some of the atoms of halogen to diffuse into the gate insulation layers on adjacent word line structures. | 2014-02-06 |
| 20140035022 | NONVOLATILE SEMICONDUCTOR MEMORY DEVICE - A nonvolatile semiconductor memory device includes a charge storage layer on a first insulating film, a second insulating film which is provided on the charge storage layer, formed of layers, and a control gate electrode on the second insulating film. The second insulating film includes a bottom layer (A) provided just above the charge storage layer, a top layer (C) provided just below the control gate electrode, and a middle layer (B) provided between the bottom layer (A) and the top layer (C). The middle layer (B) has higher barrier height and lower dielectric constant than both the bottom layer (A) and the top layer (C). The average coordination number of the middle layer (B) is smaller than both the average coordination number of the top layer (C) and the average coordination number of the bottom layer (A). | 2014-02-06 |
| 20140035023 | NONVOLATILE MEMORY DEVICE AND METHOD FOR FABRICATING THE SAME - A nonvolatile memory device includes a stacked structure disposed over a substrate and having a plurality of interlayer dielectric layers and conductive layers that are alternately stacked, a plurality of holes formed to pass through the stacked structure to expose the substrate, a first memory layer and a second memory layer formed separately in a circumference of each hole, and a first channel layer and a second channel layer formed respectively on the first and second memory layers. | 2014-02-06 |
| 20140035024 | NONVOLATILE MEMORY DEVICE AND METHOD FOR FABRICATING THE SAME - A method for fabricating a nonvolatile memory device includes forming a stacked structure over a substrate defining a cell area and a peripheral area and having a source region, the stacked structure including interlayer dielectric layers and sacrifice layers, forming channel layers connected to the substrate through the stacked structure of the cell area, forming a first slit in the stacked structure of the cell area, forming a second slit in the stacked structure, the second slit including a first portion and a second portion, removing the sacrifice layers exposed through the first and second slits, forming conductive layers to fill spaces from which the sacrifice layers are removed, forming an insulating layer in the second slit, and forming a source contact by burying a conductive material in the first portion of the second slit having the insulating layer formed therein. | 2014-02-06 |
| 20140035025 | NONVOLATILE MEMORY DEVICE AND METHOD FOR FABRICATING THE SAME - A nonvolatile memory device includes a plurality of channel connection layers formed over a substrate; a first gate electrode layer filling a space between the plurality channel connection layers; a gate dielectric layer interposed between each of the channel connection layers and the first gate electrode layer; a stacked structure formed over the plurality channel connection layers and the first gate electrode layer, the stacked structure including a plurality of interlayer dielectric layers and a plurality second gate electrode layers, which are alternately stacked; a pair of channel layers, formed through the stacked structure and connected to each channel connection layer of the plurality of channel connection layers; and a memory layer interposed between each of the channel layers and each of the second gate electrode layers. | 2014-02-06 |
| 20140035026 | SEMICONDUCTOR MEMORY DEVICES AND METHODS OF FABRICATING THE SAME - A semiconductor memory device and a method of fabricating the same. The device includes a plurality of gates vertically stacked on a top surface of a substrate with an epitaxial layer formed in the substrate, a vertical channel vertically penetrating the gates to be electrically connected to the epitaxial layer, and a memory layer provided between the vertical channel and the gates. The epitaxial layer has a top surface positioned at a level between a bottom surface of the lowermost one of the gates and the top surface of the substrate. | 2014-02-06 |
| 20140035027 | SEMICONDUCTOR DEVICE AND A MANUFACTURING METHOD THEREOF - A lamination pattern having a control gate electrode, a first insulation film thereover, and a second insulation film thereover is formed over a semiconductor substrate. A memory gate electrode is formed adjacent to the lamination pattern. A gate insulation film is formed between the control gate and the semiconductor substrate. A fourth insulation film, including a lamination film of a silicon oxide film, a silicon nitride film, and another silicon oxide film, is formed between the memory gate electrode and the semiconductor substrate and between the lamination pattern and the memory gate electrode. At the sidewall on the side of the lamination pattern adjacent to the memory gate electrode, the first insulation film is retreated from the control gate electrode and the second insulation film, and the upper end corner portion of the control gate electrode is rounded. | 2014-02-06 |
| 20140035028 | SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD THEREOF - The invention provides a semiconductor device and its manufacturing method in which a memory transistor and a plurality of thin film transistors that have gate insulating films with different thicknesses are fabricated over a substrate. The invention is characterized by the structural difference between the memory transistor and the plurality of thin film transistors. Specifically, the memory transistor and some of the plurality of thin film transistors are provided to have a bottom gate structure while the other thin film transistors are provided to have a top gate structure, which enables the reduction of characteristic defects of the transistor and simplification of its manufacturing process. | 2014-02-06 |
| 20140035029 | SEMICONDUCTOR DEVICE AND METHOD FOR FABRICATING THE SAME - A semiconductor device including a semiconductor substrate of a first conductivity type and an epitaxial layer of the first conductivity type disposed thereon is disclosed. Pluralities of first and second trenches are alternately arranged in the epitaxial layer. First and second doped regions of the first conductivity type are formed in the epitaxial layer and surrounding each first trench. A third doped region of a second conductivity type is formed in the epitaxial layer and surrounding each second trench. A first dopant in the first doped region has diffusivity larger than that of a second dopant in the second doped region. A method for fabricating a semiconductor device is also disclosed. | 2014-02-06 |
| 20140035030 | SEMICONDUCTOR DEVICE - According to one embodiment, in a semiconductor device, a semiconductor laminated body includes a first semiconductor region of a first conductivity type and a second semiconductor region of the first conductivity type provided on the first semiconductor region and having a higher concentration of impurities than that of the first semiconductor region. A third semiconductor region includes a side surface and a lower end, the side surface and the lower end are surrounded by the semiconductor laminated body. A fourth semiconductor region of a second conductivity type is provided between the semiconductor laminated body and the third semiconductor region. A fifth semiconductor region of the first conductivity type is in contact with an outside surface of the semiconductor laminated body opposite to an inside surface of the semiconductor laminated body, the inside surface is in contact with the fourth semiconductor region. | 2014-02-06 |
| 20140035031 | SEMICONDUCTOR DEVICE AND METHOD OF FABRICATING THE SAME - According to one embodiment, a semiconductor device, including a semiconductor layer including a first region and a second region isolated from the first region, a source in a surface of the first region, a drain in a surface of the second region, a back-gate in the surface of the source, a gate insulator on a surface of the first region, an end of a drain side of the back-gate being located closer to the drain side than an end of the drain side of the source, a gate insulator on a surface of the semiconductor layer between the first region and the second region, a gate electrode on the gate insulator, a source electrode being contacted to both the source and the back-gate, and a drain electrode being contacted to the drain area. | 2014-02-06 |
| 20140035032 | POWER DEVICE INTEGRATION ON A COMMON SUBSTRATE - A semiconductor structure for facilitating an integration of power devices on a common substrate includes a first insulating layer formed on the substrate and an active region having a first conductivity type formed on at least a portion of the first insulating layer. A first terminal is formed on an upper surface of the structure and electrically connects with at least one other region having the first conductivity type formed in the active region. A buried well having a second conductivity type is formed in the active region and is coupled with a second terminal formed on the upper surface of the structure. The buried well and the active region form a clamping diode which positions a breakdown avalanche region between the buried well and the first terminal. A breakdown voltage of at least one of the power devices is a function of characteristics of the buried well. | 2014-02-06 |
| 20140035033 | SEMICONDUCTOR DEVICE AND FABRICATION METHOD THEREOF - A semiconductor device and a fabrication method thereof are provided. The semiconductor device includes a P type well region and an N type well region formed in a substrate, a gate insulating layer having a non-uniform thickness and formed on the P type well region and the N type well region, a gate electrode formed on the gate insulating layer, a P type well pick-up region formed in the P type well region, and a field relief oxide layer formed in the N type well region between the gate electrode and the drain region. | 2014-02-06 |
| 20140035034 | LATERAL-DIFFUSED METAL OXIDE SEMICONDUCTOR DEVICE (LDMOS) AND FABRICATION METHOD THEREOF - A lateral-diffused metal oxide semiconductor device (LDMOS) includes a substrate, a first deep well, at least a field oxide layer, a gate, a second deep well, a first dopant region, a drain and a common source. The substrate has the first deep well which is of a first conductive type. The gate is disposed on the substrate and covers a portion of the field oxide layer. The second deep well having a second conductive type is disposed in the substrate and next to the first deep well. The first dopant region having a second conductive type is disposed in the second deep well. The doping concentration of the first dopant region is higher than the doping concentration of the second deep well. | 2014-02-06 |
| 20140035035 | INSULATED GATE BIPOLAR TRANSISTOR STRUCTURE HAVING LOW SUBSTRATE LEAKAGE - A high voltage metal-oxide-semiconductor laterally diffused device (HV LDMOS), particularly an insulated gate bipolar junction transistor (IGBT), and a method of making it are provided in this disclosure. The device includes a semiconductor substrate, a gate structure formed on the substrate, a source and a drain formed in the substrate on either side of the gate structure, a first doped well formed in the substrate, and a second doped well formed in the first well. The gate, source, second doped well, a portion of the first well, and a portion of the drain structure are surrounded by a deep trench isolation feature and an implanted oxygen layer in the silicon substrate. | 2014-02-06 |
| 20140035036 | SEMICONDUCTOR DEVICE - A lateral semiconductor device including a semiconductor substrate; a buried oxide layer formed on the semiconductor substrate, and an active layer formed on the buried oxide layer. The active layer includes a first conductivity type well region, a second conductivity type well region, and a first conductivity type drift region interposed between the first conductivity type well region and the second conductivity type well region. A region where current flows because of carriers moving between the first conductivity type well region and the second conductivity type well region, and a region where no current flows are formed alternately between the first conductivity type well region and the second conductivity type well region, in a direction perpendicular to a carrier moving direction when viewed in a plan view. | 2014-02-06 |
| 20140035037 | EMBEDDED SILICON GERMANIUM N-TYPE FILED EFFECT TRANSISTOR FOR REDUCED FLOATING BODY EFFECT - A semiconductor device includes a gate stack formed on an active region in a p-type field effect transistor (pFET) portion of a silicon-on-insulator (SOI) substrate. The SOI substrate includes a n-type field effect transistor (nFET) portion. A gate spacer is formed over the gate stack. A source region and a drain region are formed within a first region and a second region, respectively, of the pFET portion of the semiconductor layer including embedded silicon germanium (eSiGe). A source region and a drain region are formed within a first region and a second region, respectively, of the nFET portion of the semiconductor layer including eSiGe. The source and drain regions within the pFET portion includes at least one dimension that is different from at least one dimension of the source and drain regions within the nFET portion. | 2014-02-06 |
| 20140035038 | Structure And Method To Realize Conformal Doping In Deep Trench Applications - The specification and drawings present a new method, ASIC and computer/software related product (e.g., a computer readable memory) are presented for realizing conformal doping in embedded deep trench applications in the ASIC. A common SOI substrate with intrinsic or low dopant concentration is used for manufacturing such ASICs comprising a logic area having MOSFETs utilizing, for example, ultra thin body and box technology and an eDRAM area having deep trench capacitors with the conformal doping. | 2014-02-06 |
| 20140035039 | ELECTROSTATIC DISCHARGE (ESD) GUARD RING PROTECTIVE STRUCTURE - An electrostatic discharge (ESD) protection circuit structure includes several diffusion regions and a MOS transistor. The circuit structure includes a first diffusion region of a first type (e.g., P-type or N-type) formed in a first well of the first type, a second diffusion region of the first type formed in the first well of the first type, and a first diffusion region of a second type (e.g., N-type or P-type) formed in a first well of the second type. The first well of the second type is formed in the first well of the first type. The MOS transistor is of the second type and includes a drain formed by a second diffusion region of the second type formed in a second well of the second type bordering the first well of the first type. | 2014-02-06 |
| 20140035040 | TUNNEL FIELD EFFECT TRANSISTOR - A TFET transistor includes an intrinsic channel, source and drain extension regions, source and drain conductive regions, a gate surmounting the channel and laid out such that an end of the channel is not covered by the gate. The transistor includes a first arrangement for forming an isolating space between the sides of the gate and the source conductive region including a first and a second dielectric spacer. The extension region has a thickness strictly greater than that of the channel such that the extension region has an increased thickness opposite the gate dielectric layer. The first face of the first spacer is in contact with the side of the gate followed by the side of the gate dielectric layer such that the first face covers the whole of the side of the layer. | 2014-02-06 |
| 20140035041 | TECHNIQUES AND CONFIGURATIONS FOR STACKING TRANSISTORS OF AN INTEGRATED CIRCUIT DEVICE - Embodiments of the present disclosure provide techniques and configurations for stacking transistors of a memory device. In one embodiment, an apparatus includes a semiconductor substrate, a plurality of fin structures formed on the semiconductor substrate, wherein an individual fin structure of the plurality of fin structures includes a first isolation layer disposed on the semiconductor substrate, a first channel layer disposed on the first isolation layer, a second isolation layer disposed on the first channel layer, and a second channel layer disposed on the second isolation layer, and a gate terminal capacitively coupled with the first channel layer to control flow of electrical current through the first channel layer for a first transistor and capacitively coupled with the second channel layer to control flow of electrical current through the second channel layer for a second transistor. Other embodiments may be described and/or claimed. | 2014-02-06 |
| 20140035042 | METHOD FOR MANUFACTURING A TRANSISTOR OF A SEMICONDUCTOR MEMORY DEVICE - A transistor of a semiconductor memory device including a semiconductor substrate having a plurality of active regions and a device isolation region, a plurality of first and second trench device isolation layers, which are arranged alternately with each other on the device isolation region of the semiconductor substrate, the first trench device isolation layers having a first thickness corresponding to a relatively high step height, and the second trench device isolation layers having a second thickness corresponding to a relatively low step height, a recess region formed in each of the active regions by a predetermined depth to have a stepped profile at a boundary portion thereof, the recess region having a height higher than that of the second trench device isolation layers to have an upwardly protruded portion between adjacent two second trench device isolation layers, a gate insulation layer, and a plurality of gate stacks formed on the gate insulation layer to overlap with the stepped profile of the respective active regions and the protruded portion of the relevant recess region. | 2014-02-06 |
| 20140035043 | FinFETs with Multiple Fin Heights - An integrated circuit structure includes a semiconductor substrate, and a FinFET over the semiconductor substrate. The FinFET includes a semiconductor fin; a gate dielectric on a top surface and sidewalls of the semiconductor fin; a gate electrode on the gate dielectric; and a source/drain region at an end of the semiconductor fin. A first pair of shallow trench isolation (STI) regions includes portions directly underlying portions of the source/drain regions, wherein the first pair of STI regions is separated by, and adjoining a semiconductor strip. The first pair of STI regions further has first top surfaces. A second pair of STI regions comprises portions directly underlying the gate electrode, wherein the second pair of STI regions is separated from each other by, and adjoining, the semiconductor strip. The second pair of STI regions has second top surfaces higher than the first top surfaces. | 2014-02-06 |
| 20140035044 | FIELD-EFFECT TRANSISTOR AND MANUFACTURING METHOD THEREOF - Disclosed are a field-effect transistor and a manufacturing method thereof. The disclosed field-effect transistor includes: a semiconductor substrate; a source ohmic metal layer formed on one side of the semiconductor substrate; a drain ohmic metal layer formed on another side of the semiconductor substrate; a gate electrode formed between the source ohmic metal layer and the drain ohmic metal layer, on an upper portion of the semiconductor substrate; an insulating film formed on the semiconductor substrate's upper portion including the source ohmic metal layer, the drain ohmic metal layer and the gate electrode; and a plurality of field electrodes formed on an upper portion of the insulating film, wherein the insulating film below the respective field electrodes has different thicknesses. | 2014-02-06 |
| 20140035045 | Method of Manufacturing Dummy Gates of a Different Material as Insulation between Adjacent Devices - Embodiments of the present invention include a semiconductor structure including two transistor structures separated by a dummy gate of a different material and methods for forming said structure. Embodiments including forming sacrificial gates on a semiconductor substrate, forming spacers on the sacrificial gates, forming source/drain regions adjacent to two sacrificial gates separated by a third sacrificial gate, and replacing the third sacrificial gate with an insulating material. The insulating material replacing the third sacrificial gate may serve as a dummy gate to electrically isolate nearby source/drain regions. Embodiments further include forming sacrificial gates on a semiconductor substrate, forming spacers on the sacrificial gates, forming source/drain regions adjacent to two sacrificial gates separated by a third sacrificial gate, and replacing the two sacrificial gates with metal gates while leaving the third sacrificial gate in place to serve as a dummy gate. | 2014-02-06 |
| 20140035046 | SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD OF SEMICONDUCTOR DEVICE - A manufacturing method of a semiconductor device according to a disclosed embodiment includes: implanting a first impurity into a first region of a semiconductor substrate, forming a semiconductor layer on the semiconductor substrate, forming a trench in the semiconductor layer and the semiconductor substrate, forming an isolation insulating film in the trench, implanting a second impurity into a second region of the semiconductor layer, forming a first gate insulating film and a first gate electrode in the first region, forming a second gate insulating film and a second gate electrode in the second region, forming a first source region and a first drain region at both sides of the first gate electrode, and forming a second source region and a second drain region at both sides of the second gate electrode. | 2014-02-06 |
| 20140035047 | POWER DEVICE INTEGRATION ON A COMMON SUBSTRATE - A semiconductor structure for facilitating an integration of power devices on a common substrate includes a first insulating layer formed on the substrate and an active region having a first conductivity type formed on at least a portion of the first insulating layer. A first terminal is formed on an upper surface of the structure and electrically connects with at least one other region having the first conductivity type formed in the active region. A buried well having a second conductivity type is formed in the active region and is coupled with a second terminal formed on the upper surface of the structure. The buried well and the active region form a clamping diode which positions a breakdown avalanche region between the buried well and the first terminal. A breakdown voltage of at least one of the power devices is a function of characteristics of the buried well. | 2014-02-06 |
| 20140035048 | SEMICONDUCTOR DEVICE AND METHOD OF FABRICATING THE SAME - Provided are a semiconductor device and a method of fabricating the same. The device may include a transistor on a substrate comprising a gate insulating pattern, a gate electrode and an impurity region, a shared contact plug electrically connected to the gate electrode and the impurity region, and an etch-stop layer between side surfaces of the gate electrode and the shared contact. The shared contact plug may include a first conductive pattern electrically connected to the first impurity region and a second conductive pattern electrically connected to the gate electrode, and a top surface of the first conductive pattern may be higher than a top surface of the gate electrode. | 2014-02-06 |
| 20140035049 | SEMICONDUCTOR DEVICE AND FABRICATING METHOD THEREOF - A semiconductor device and a fabricating method thereof are provided. The semiconductor device is formed on a substrate and includes a first first-type metal-oxide-semiconductor field effect transistor (MOSFET) and a second first-type MOSFET. The first first-type MOSFET includes a first gate structure, a first source area and a first drain area on the substrate. The second first-type MOSFET includes a second gate structure, a second source area, and a second drain area on the substrate. A first pocket implant process is applied to the first first-type MOSFET via a first photomask, while a second pocket implant process is applied to the second first-type MOSFET via a second photomask. The first and second gate structures are facing different directions. | 2014-02-06 |
| 20140035050 | SEMICONDUCTOR DEVICES HAVING A DIFFUSION BARRIER LAYER AND METHODS OF MANUFACTURING THE SAME - Methods of manufacturing a semiconductor device include forming a gate insulation layer including a high-k dielectric material on a substrate that is divided into a first region and a second region; forming a diffusion barrier layer including a first metal on a second portion of the gate insulation layer in the second region; forming a diffusion layer on the gate insulation layer and the diffusion barrier layer; and diffusing an element of the diffusion layer into a first portion of the gate insulation layer in the first region. | 2014-02-06 |
| 20140035051 | SEMICONDUCTOR DEVICE AND ASSOCIATED METHODS - A semiconductor device and process of fabricating the same, the semiconductor device including a semiconductor substrate, a gate insulating layer on the semiconductor substrate, a gate electrode having sidewalls, on the gate insulating layer, first spacers on the sidewalls of the gate electrode, a source/drain region in the semiconductor substrate, aligned with the sidewalls, a silicide layer on the gate electrode, a silicide layer on the source/drain region, and second spacers covering the first spacers and end parts of a surface of the silicide layer on the source drain region. | 2014-02-06 |
| 20140035052 | ELECTRONIC DEVICE INCLUDING A TAPERED TRENCH AND A CONDUCTIVE STRUCTURE THEREIN - An electronic device can include a semiconductor layer, and a trench extending into the semiconductor layer and having a tapered shape. In an embodiment, the trench includes a wider portion and a narrower portion. The electronic device can include a doped semiconductor region that extends to a narrower portion of the trench and has a dopant concentration greater than a dopant concentration of the semiconductor layer. In another embodiment, the electronic device can include a conductive structure within a relatively narrower portion of the trench, and a conductive electrode within a relatively wider portion of the trench. In another embodiment, a process of forming the electronic device can include forming a sacrificial plug and may allow insulating layers of different thicknesses to be formed within the trench. | 2014-02-06 |
| 20140035053 | FINFET CELL ARCHITECTURE WITH INSULATOR STRUCTURE - A finFET block architecture includes a first set of semiconductor fins having a first conductivity type, and a second set of semiconductor fins having a second conductivity type. An inter-block insulator is placed between outer fins of the first and second sets. A patterned gate conductor layer includes a first plurality of gate traces extending across the set of fins in the first block without crossing the inter-block insulator, and a second plurality of gate traces extending across the set of fins in the second block without crossing the inter-block insulator. Patterned conductor layers over the gate conductor layer are arranged in orthogonal layout patterns, and include an inter-block connector arranged to connect gate traces in the first and second blocks. | 2014-02-06 |
| 20140035054 | Device and Methods for Small Trench Patterning - A semiconductor device and methods for small trench patterning are disclosed. The device includes a plurality of gate structures and sidewall spacers, and an etch buffer layer disposed over the sidewall spacers. The etch buffer layer includes an overhang component disposed on the upper portion of the sidewall spacers with an edge that extends laterally. The width between the edges of adjacent overhang components is narrower than the width between adjacent sidewall spacers. | 2014-02-06 |
| 20140035055 | SEMICONDUCTOR INTEGRATED CIRCUIT DEVICE AND METHOD FOR MANUFACTURING SEMICONDUCTOR INTEGRATED CIRCUIT DEVICE - MISFETs after the 32 nm technology node have a High-k gate insulating film and a metal gate electrode. Such MISFETs have the problem that the absolute value of the threshold voltage of n-MISFET and p-MISFET inevitably increases by the subsequent high temperature heat treatment. The threshold voltage is therefore controlled by forming various threshold voltage adjusting metal films on a High-k gate insulating film and introducing a film component from them into the High-k gate insulating film. The present inventors have however revealed that lanthanum or the like introduced into the High-k gate insulating film of the n-MISFET is likely to transfer to the STI region by the subsequent heat treatment. | 2014-02-06 |
| 20140035056 | SRAM Cell Connection Structure - A Static Random Access Memory (SRAM) cell includes a first pull-up transistor and a second pull-up transistor, and a first pull-down transistor and a second pull-down transistor forming cross-latched inverters with the first pull-up transistor and the second pull-up transistor. A conductive feature includes a first leg having a first longitudinal direction, wherein the first leg interconnects a drain of the first pull-up transistor and a drain of the first pull-down transistor. The conductive feature further includes a second leg having a second extending direction. The first longitudinal direction and the second extending direction are un-perpendicular and un-parallel to each other. The second leg interconnects the drain of the first pull-up transistor and a gate of the second pull-up transistor. | 2014-02-06 |
| 20140035057 | INTEGRATED CIRCUITS WITH ALIGNED (100) NMOS AND (110) PMOS FINFET SIDEWALL CHANNELS - An integrated circuit device that includes a plurality of multiple gate FinFETs (MuGFETs) is disclosed. Fins of different crystal orientations for PMOS and NMOS MuGFETs are formed through amorphization and crystal regrowth on a direct silicon bonded (DSB) hybrid orientation technology (HOT) substrate. PMOS MuGFET fins are formed with channels defined by fin sidewall surfaces having (110) crystal orientations. NMOS MuGFET fins are formed with channels defined by fin sidewall surfaces having (100) crystal orientations in a Manhattan layout with the sidewall channels of the different PMOS and NMOS MuGFETs aligned at 0° or 90° rotations. | 2014-02-06 |
| 20140035058 | Semiconductor Devices and Methods of Manufacturing the Same - Methods of manufacturing a semiconductor device include forming a thin layer on a substrate including a first region and a second region and forming a gate insulating layer on the thin layer. A lower electrode layer is formed on the gate insulating layer and the lower electrode layer disposed in the second region is removed to expose the gate insulating layer in the second region. Nitrogen is doped into an exposed portion of the gate insulating layer and the thin layer disposed under the gate insulating layer. An upper electrode layer is formed on the lower electrode layer remaining in the first region and the exposed portion of the gate insulating layer. The upper electrode layer, the lower electrode layer, the gate insulating layer and the thin layer are partially removed to form first and second gate structures in the first and second regions. The process may be simplified. | 2014-02-06 |
| 20140035059 | SEMICONDUCTOR DEVICE HAVING METALLIC SOURCE AND DRAIN REGIONS - Semiconductor devices having metallic source and drain regions are described. For example, a semiconductor device includes a gate electrode stack disposed above a semiconducting channel region of a substrate. Metallic source and drain regions are disposed above the substrate, on either side of the semiconducting channel region. Each of the metallic source and drain regions has a profile. A first semiconducting out-diffusion region is disposed in the substrate, between the semiconducting channel region and the metallic source region, and conformal with the profile of the metallic source region. A second semiconducting out-diffusion region is disposed in the substrate, between the semiconducting channel region and the metallic drain region, and conformal with the profile of the metallic drain region. | 2014-02-06 |
| 20140035060 | SEMICONDUCTOR STRUCTURE AND METHOD OF FABRICATION THEREOF WITH MIXED METAL TYPES - A semiconductor structure includes a first PMOS transistor element having a gate region with a first gate metal associated with a PMOS work function and a first NMOS transistor element having a gate region with a second metal associated with a NMOS work function. The first PMOS transistor element and the first NMOS transistor element form a first CMOS device. The semiconductor structure also includes a second PMOS transistor that is formed in part by concurrent deposition with the first NMOS transistor element of the second metal associated with a NMOS work function to form a second CMOS device with different operating characteristics than the first CMOS device. | 2014-02-06 |
| 20140035061 | HIGH SHEET RESISTOR IN CMOS FLOW - An integrated circuit containing CMOS gates and a counterdoped polysilicon gate material resistor which has a body region that is implanted concurrently with the NSD layers of the NMOS transistors of the CMOS gates and concurrently with the PSD layers of the PMOS transistors of the CMOS gates, and has a resistor silicide block layer over the body region which is formed of separate material from the sidewall spacers on the CMOS gates. A process of forming an integrated circuit containing CMOS gates and a counterdoped polysilicon gate material resistor which implants the body region of the resistor concurrently with the NSD layers of the NMOS transistors of the CMOS gates and concurrently with the PSD layers of the PMOS transistors of the CMOS gates, and forms a resistor silicide block layer over the body region of separate material from the sidewall spacers on the CMOS gates. | 2014-02-06 |
| 20140035062 | TRANSISTOR DEVICE AND A METHOD OF MANUFACTURING SAME - A transistor device is provided that includes a substrate, a first channel region formed in a first portion of the substrate and being doped with a dopant of a first type of conductivity, a second channel region formed in a second portion of the substrate and being doped with a dopant of a second type of conductivity, a gate insulating layer formed on the first channel region and on the second channel region, a dielectric capping layer formed on the gate insulating layer, a first gate region formed on the dielectric capping layer over the first channel region, and a second gate region formed on the dielectric capping layer over the second channel region, wherein the first gate region and the second gate region are made of the same material, and wherein one of the first gate region and the second gate region comprises an ion implantation. | 2014-02-06 |
| 20140035063 | SEMICONDUCTOR DEVICE AND METHOD FOR MANUFACTURING THE SAME - A configuration of a lateral transistor suited for the hybrid-integration (BiCMOS) of a high-performance lateral transistor (HCBT) and a CMOS transistor, and a method for manufacturing the lateral transistor. A semiconductor device includes a HCBT | 2014-02-06 |
| 20140035064 | SEMICONDUCTOR STRUCTURES AND METHODS OF MANUFACTURE - Semiconductor structures and methods of manufacture are disclosed herein. Specifically, disclosed herein are methods of manufacturing a high-voltage metal-oxide-semiconductor field-effect transistor and respective structures. A method includes forming a field-effect transistor (FET) on a substrate in a FET region, forming a high-voltage FET (HVFET) on a dielectric stack over a over lightly-doped diffusion (LDD) drain in a HVFET region, and forming an NPN on the substrate in an NPN region. | 2014-02-06 |
| 20140035065 | HIGH-FREQUENCY DEVICE INCLUDING HIGH-FREQUENCY SWITCHING CIRCUIT - A high-frequency device having a switching circuit including a semiconductor substrate; a first high-frequency input/output terminal; a second high-frequency input/output terminal; a control signal input terminal; a power terminal; a ground terminal; an insulating portion disposed on a main surface of the semiconductor substrate; and a voltage-applying electrode for applying a predetermined positive voltage from the power electrode to the semiconductor substrate, wherein the switching circuit includes a field-effect transistor disposed in an active region of the semiconductor substrate. | 2014-02-06 |
| 20140035066 | Non-Planar FET and Manufacturing Method Thereof - The present invention provides a non-planar FET which includes a substrate, a fin structure, a sub spacer, a gate, a dielectric layer and a source/drain region. The fin structure is disposed on the substrate. The sub spacer is disposed only on a middle sidewall of the fin structure. The gate is disposed on the fin structure. The dielectric layer is disposed between the fin structure and the gate. The source/drain region is disposed in the fin structure. The present invention further provides a method of forming the same. | 2014-02-06 |
| 20140035067 | NATIVE DEVICES HAVING IMPROVED DEVICE CHARACTERISTICS AND METHODS FOR FABRICATION - A method for fabricating a native device is presented. The method includes forming a gate structure over a substrate starting at an outer edge of an inner marker region, where the gate structure extends in a longitudinal direction, and performing MDD implants, where each implant is performed using a different orientation with respect to the gate structure, performing pocket implants, where each implant is performed using a different orientation with respect to the gate structure, and concentrations of the pocket implants vary based upon the orientations. A transistor fabricated as a native device, is presented, which includes an inner marker region, an active outer region which surrounds the inner marker region, a gate structure coupled to the inner marker region, and first and second source/drain implants located within the active outer region and interposed between the first source/drain implant and the second source/drain implant. | 2014-02-06 |
| 20140035068 | Transistor having replacement metal gate and process for fabricating the same - A transistor is fabricated by removing a polysilicon gate over a doped region of a substrate and forming a mask layer over the substrate such that the doped region is exposed through a hole within the mask layer. An interfacial layer is deposited on top and side surfaces of the mask layer and on a top surface of the doped region. A layer adapted to reduce a threshold voltage of the transistor and/or reduce a thickness of an inversion layer of the transistor is deposited on the interfacial layer. The layer includes metal, such as aluminum or lanthanum, which diffuses into the interfacial layer, and also includes oxide, such as hafnium oxide. A conductive plug, such as a metal plug, is formed within the hole of the mask layer. The interfacial layer, the layer on the interfacial layer, and the conductive plug are a replacement gate of the transistor. | 2014-02-06 |
| 20140035069 | FIELD EFFECT TRANSISTOR HAVING A TROUGH CHANNEL - The present invention is directed to a field effect transistor having a trough channel structure. The transistor comprises a semiconductor substrate of a first conductivity type having a trough structure therein with the trough structure extending along a first direction; an insulating layer formed on top of the trough structure; a gate formed on top of the insulator layer in a second direction perpendicular to the first direction and extending over and into the trough structure with a gate dielectric layer interposed therebetween; a source and a drain of a second conductivity type opposite to the first conductivity type formed in the trough structure on opposite sides of the gate. | 2014-02-06 |
| 20140035070 | METAL OXIDE SEMICONDUCTOR TRANSISTOR - A MOS transistor including a silicon substrate, a first gate structure and a second gate structure disposed on the silicon substrate is provided. The first gate structure and the second gate structure each includes a high-k dielectric layer disposed on the silicon substrate, a barrier layer disposed on the high-k dielectric layer, and a work function layer disposed on and contacted with the barrier layer. The MOS transistor further includes a dielectric material spacer. The dielectric material spacer is disposed on the barrier layer of each of the first gate structure and the second gate structure and surrounding the work function layer of each of the first gate structure and the second gate structure. | 2014-02-06 |
| 20140035071 | Substrate with Multiple Encapsulated Devices - A device with multiple encapsulated functional layers, includes a substrate, a first functional layer positioned above a top surface of the substrate, the functional layer including a first device portion, a first encapsulating layer encapsulating the first functional layer, a second functional layer positioned above the first encapsulating layer, the second functional layer including a second device portion, and a second encapsulating layer encapsulating the second functional layer. | 2014-02-06 |
| 20140035072 | HYBRID MEMS BUMP DESIGN TO PREVENT IN-PROCESS AND IN-USE STICTION - A micro-electro-mechanical systems (MEMS) device and method for forming a MEMS device is provided. A proof mass is suspended a distance above a surface of a substrate by a fulcrum. A pair of sensing plates are positioned on the substrate on opposing sides of the fulcrum. Metal bumps are associated with each sensing plate and positioned near a respective distal end of the proof mass. Each metal bump extends from the surface of the substrate and generally inhibits charge-induced stiction associated with the proof mass. Oxide bumps are associated with each of the pair of sensing plates and positioned between the respective sensing plate and the fulcrum. Each oxide bump extends from the first surface of the substrate a greater distance than the metal bumps and acts as a shock absorber by preventing the distal ends of the proof mass from contacting the metal bumps during shock loading. | 2014-02-06 |
| 20140035073 | MAGNETO-RESISTIVE ELEMENT - A magneto-resistive element has a memory layer, which has magnetic anisotropy along a direction perpendicular to its surface and variable magnetization directions, a reference layer, which has magnetic anisotropy along a direction perpendicular to its surface and a fixed magnetization direction, and a tunnel barrier layer, which is formed between the memory layer and the reference layer. The memory layer is composed of Co | 2014-02-06 |
| 20140035074 | Multilayers Having Reduced Perpendicular Demagnetizing Field Using Moment Dilution for Spintronic Applications - A magnetic element is disclosed that has a composite free layer with a FM1/moment diluting/FM2 configuration wherein FM1 and FM2 are magnetic layers made of one or more of Co, Fe, Ni, and B and the moment diluting layer is used to reduce the perpendicular demagnetizing field. As a result, lower resistance x area product and higher thermal stability are realized when perpendicular surface anisotropy dominates shape anisotropy to give a magnetization perpendicular to the planes of the FM1, FM2 layers. The moment diluting layer may be a non-magnetic metal like Ta or a CoFe alloy with a doped non-magnetic metal. A perpendicular Hk enhancing layer interfaces with the FM2 layer and may be an oxide to increase the perpendicular anisotropy field in the FM2 layer. A method for forming the magnetic element is also provided. | 2014-02-06 |
| 20140035075 | MAGNETIC TUNNEL JUNCTION DEVICE - A magnetic tunnel junction device includes a Synthetic Anti-Ferromagnetic (SAF) layer, a first free layer, and second free layer. The magnetic tunnel junction device further includes a spacer layer between the first and second free layers. The first free layer is magneto-statically coupled to the second free layer. A thickness of the spacer layer is at least 4 Angstroms. | 2014-02-06 |
| 20140035076 | Magnetoresistive Device Having Semiconductor Substrate and Preparation Method Therefor - The present invention relates to a magnetoresistance device using a semiconductor substrate and a method for manufacturing the same. The magnetoresistance device includes: a semiconductor substrate; an oxidation layer disposed on a surface of the semiconductor substrate; electrodes disposed on the oxidation layer; and at least one diode connected between at least two of the electrodes. The magnetoresistance device of the present invention has excellent performances of a high field magnetoresistance characteristic and high sensitivity at low magnetic field, and has advantages of low power consumption, simple device structure, low cost and simple manufacturing process. | 2014-02-06 |
| 20140035077 | Photovoltaic Device Including Semiconductor Nanocrystals - A photovoltaic device includes a semiconductor nanocrystal and a charge transporting layer that includes an inorganic material. The charge transporting layer can be a hole or electron transporting layer. The inorganic material can be an inorganic semiconductor. | 2014-02-06 |
| 20140035078 | Substrate Connection Type Module Structure - The present invention provides a substrate connection type module structure comprising a substrate with a through hole structure and a first contact pad. A chip is configured on the through hole structure of the substrate, with a second contact pad and a sensing area. The first contact pad is coupled to the second contact pad via a wire. A second substrate is electrically connected to the first substrate. The second substrate and the chip are located at the same layer. A lens holder is disposed on the substrate, and a lens is located on the top of the lens holder. A transparent material is disposed within the lens holder. The lens is substantially aligning to the transparent material and the sensing area. | 2014-02-06 |
| 20140035079 | Window Type Camera Module Structure - The present invention provides a window type camera module structure comprising a first substrate. A chip is configured on the first substrate, with a first contact pad and a sensing area. A second substrate is disposed on the first substrate, with a through hole structure and a second contact pad, wherein the chip is disposed within the through hole structure. The first contact is coupled to the second contact pad via a wire. A lens holder is disposed on the second substrate, and a lens is located on the top of the lens holder. A transparent material is disposed on the lens holder or the second substrate. The lens is substantially aligning to the transparent material and the sensing area. | 2014-02-06 |
| 20140035080 | Wafer Level Camera Module Structure - The present invention provides a wafer level camera module structure comprising a chip with a sensing area. A TSV structure is formed by passing through from the top surface to the bottom surface of the chip. A transparent material is disposed on the chip, with at least one conductive via structure formed therein and a trace form thereon. A lens holder is disposed on the transparent material, and a lens is located on the top of the lens holder. The lens is substantially aligning to the transparent material and the sensing area. | 2014-02-06 |
| 20140035081 | Substrate Inside Type Module Structure - The present invention provides a module structure of substrate inside type comprising a first substrate with a concave structure. A chip is configured on the concave structure of the first substrate, with a first contact pad and a sensing area. A second substrate is disposed on the first substrate, with at least one through hole structure and a second contact pad. The first contact is coupled to the second contact pad via a wire. The second substrate includes a first portion embedded into the module structure, and a second portion extended to outside of the module structure. A lens holder is disposed on the second substrate, and a lens is located on the top of the lens holder. A transparent material is disposed within the lens holder or the second substrate. The lens is substantially aligning to the transparent material and the sensing area. | 2014-02-06 |
| 20140035082 | Elevated Photodiodes with Crosstalk Isolation - A device includes a plurality of isolation spacers, and a plurality of bottom electrodes, wherein adjacent ones of the plurality of bottom electrodes are insulated from each other by respective ones of the plurality of isolation spacers. A plurality of photoelectrical conversion regions overlaps the plurality of bottom electrodes, wherein adjacent ones of the plurality of photoelectrical conversion regions are insulated from each other by respective ones of the plurality of isolation spacers. A top electrode overlies the plurality of photoelectrical conversion regions and the plurality of isolation spacers. | 2014-02-06 |
| 20140035083 | Elevated Photodiode with a Stacked Scheme - A device includes an image sensor chip having formed therein an elevated photodiode, and a device chip underlying and bonded to the image sensor chip. The device chip has a read out circuit electrically connected to the elevated photodiode. | 2014-02-06 |
| 20140035084 | METHOD OF DIRECT TILING OF AN IMAGE SENSOR ARRAY - A method of making a tiled array of semiconductor dies includes aligning and flattening. One end of each semiconductor die has attached thereto a respective printed circuit board. The aligning aligns the semiconductor dies into the tiled array in such a way that the semiconductor dies rest on a vacuum plate and the one end of each die extends beyond an edge of the vacuum plate. The flattening flattens the semiconductor dies against the vacuum plate with a vacuum after the semiconductor dies are aligned. | 2014-02-06 |
| 20140035085 | PHOTOELECTRIC CONVERSION DEVICE AND MANUFACTURING METHOD THEREOF - A photoelectric conversion device is provided which is capable of improving the light condensation efficiency without substantially decreasing the sensitivity. The photoelectric conversion device has a first pattern provided above an element isolation region formed between adjacent two photoelectric conversion elements, a second pattern provided above the element isolation region and above the first pattern, and microlenses provided above the photoelectric conversion elements with the first and the second patterns provided therebetween. The photoelectric conversion device further has convex-shaped interlayer lenses in optical paths between the photoelectric conversion elements and the microlenses, the peak of each convex shape projecting in the direction from the electro-optical element to the microlens. | 2014-02-06 |
| 20140035086 | SOLID-STATE IMAGE SENSOR - A solid-state image sensor includes a semiconductor layer having photoelectric conversion portions, and a wiring structure arranged on a side of a first face of the semiconductor layer, and receives light from a side of a second face of the semiconductor layer. The wiring structure includes a reflection portion having a reflection surface reflecting light transmitted through the semiconductor layer from the second face toward the first face, toward the semiconductor layer, and an insulation film located between the reflection surface and the first face. The sensor includes a first dielectric film arranged to contact the first face, and a second dielectric film arranged between the insulation film and the first dielectric film and having a refractive index different from refractive indices of the first dielectric film and the insulation film. | 2014-02-06 |
| 20140035087 | ETCHING NARROW, TALL DIELECTRIC ISOLATION STRUCTURES FROM A DIELECTRIC LAYER - Methods of forming isolation structures are disclosed. A method of forming isolation structures for an image sensor array of one aspect may include forming a dielectric layer over a semiconductor substrate. Narrow, tall dielectric isolation structures may be formed from the dielectric layer. The narrow, tall dielectric isolation structures may have a width that is no more than 0.3 micrometers and a height that is at least 1.5 micrometers. A semiconductor material may be epitaxially grown around the narrow, tall dielectric isolation structures. Other methods and apparatus are also disclosed. | 2014-02-06 |
| 20140035088 | SEMICONDUCTOR IMAGE SENSOR MODULE, METHOD FOR MANUFACTURING THE SAME AS WELL AS CAMERA AND METHOD FOR MANUFACTURING THE SAME - A semiconductor image sensor module | 2014-02-06 |
| 20140035089 | PAD DESIGN FOR CIRCUIT UNDER PAD IN SEMICONDUCTOR DEVICES - Embodiments of a semiconductor device that includes a semiconductor substrate and a cavity disposed in the semiconductor substrate that extends at least from a first side of the semiconductor substrate to a second side of the semiconductor substrate. The semiconductor device also includes an insulation layer disposed over the first side of the semiconductor substrate and coating sidewalls of the cavity. A conductive layer including a bonding pad is disposed over the insulation layer. The conductive layer extends into the cavity and connects to a metal stack disposed below the second side of the semiconductor substrate. A through silicon via pad is disposed below the second side of the semiconductor substrate and connected to the metal stack. The through silicon via pad is position to accept a through silicon via. | 2014-02-06 |
| 20140035090 | TRENCH SCHOTTKY DIODE - A trench Schottky diode is described, which has a highly doped substrate of a first conductivity type and an epitaxial layer of the same conductivity type that is applied to the substrate. At least two trenches are introduced into the epitaxial layer. The epitaxial layer is a stepped epitaxial layer that has two partial layers of different doping concentrations. | 2014-02-06 |
| 20140035091 | Electrostatic Discharge Protection Circuit Including a Distributed Diode String - An integrated circuit includes first and second terminals. The integrated circuit further includes a first plurality of diodes arranged in series between the first terminal and a power supply terminal and a second plurality of diodes arranged in series between the second terminal and the power supply terminal. The integrated circuit also includes a conductor configured to couple a first node within the first plurality of diodes to a second node within the second plurality of diodes. The first node is located between a first diode of the first plurality of diodes and a last diode of the first plurality of diodes, and the second node is located between a first diode of the second plurality of diodes and a last diode of the second plurality of diodes. | 2014-02-06 |
