| 06th week of 2015 patent applcation highlights part 65 |
| Patent application number | Title | Published |
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| 20150039895 | SYSTEM AND METHOD FOR AUTHENTICATION FOR FIELD REPLACEABLE UNITS - A method and apparatus of a network element that authenticates a field replaceable unit of the network element is described. The network element authenticates a field replaceable unit of the network element by generating a nonce. In addition, the network element generates a signature using a nonce and a private encryption key that is securely stored in the field replaceable unit. The network element further verifies the signature using a public encryption key that is a pair to the private encryption key and is not securely stored in the field replaceable unit. If the field replaceable unit is verified, the network element uses the field replaceable unit to operate the network element. Otherwise, the network element disables the field replaceable unit. | 2015-02-05 |
| 20150039896 | SYSTEM AND METHOD FOR POOL-BASED IDENTITY GENERATION AND USE FOR SERVICE ACCESS - A computer-implemented system and method for pool-based identity generation and use for service access is disclosed. The method in an example embodiment includes seeding an identity generator with a private key; retrieving independently verifiable data corresponding to a service consumer; using the independently verifiable data to create signed assertions corresponding to the service consumer; generating a non-portable identity document associated with the service consumer, the identity document including the signed assertions; signing the identity document with the private key; and conveying the signed identity document to the service consumer via a secure link. | 2015-02-05 |
| 20150039897 | INFORMATION PROCESSING APPARATUS, PROGRAM, STORAGE MEDIUM AND INFORMATION PROCESSING SYSTEM - Provided is an information processing apparatus including a reception unit that receives a request for access to an IC chip from an application having access right information for accessing to the IC chip, an acquisition unit that acquires an authentication information for authenticating the application from an external server based on the access right information contained the request for access received by the reception unit, an authentication unit that authenticates the application based on the authentication information obtained by the acquisition unit, and a control unit that controls an access of the application to the IC chip based on an authentication result by the authentication unit. | 2015-02-05 |
| 20150039898 | METHOD FOR AUTHENTICATING A DEVICE INCLUDING A PROCESSOR AND A SMART CARD BY PATTERN GENERATION - A method for authenticating a device comprising a processor and a smart card. A user unlocks the smart card using a PIN code. A secret key Kc of the smart card and the PIN code of the smart card is transmitted to the processor. The processor performs a cryptographic calculation using a secret key Kp of the processor, the PIN code, and Kc. A pattern is generated from the cryptographic calculation by the processor and transmitted to the user. The pattern generated by the device is compared to a pattern memorized by the user. | 2015-02-05 |
| 20150039899 | METHOD FOR ENCRYPTING A PLURALITY OF DATA IN A SECURE SET - A server-implemented method encrypting at least two pieces of indexed data as lists of elements, each element belonging to a finite set of indexed symbols on an alphabet. The data is encrypted to form a protected set, including: the server randomly generates, for each datum, a corresponding encoding function; if at least one element that constitutes a datum is the symbol of the alphabet, the server determines the image of the symbol of the alphabet via the encoding function corresponding to the datum to obtain a codeword coordinate and adds the codeword coordinate to an indexed set corresponding to the element of the alphabet; then the server completes the indexed set with error-inducing points; the server randomly reindexes the elements of the indexed set corresponding to the symbol of the alphabet; and the server adds the indexed set to the protected set. The method can identify an individual. | 2015-02-05 |
| 20150039900 | PROGRAM EXECUTION METHOD AND DECRYPTION APPARATUS - A method for program execution in a system including a decryption apparatus that prevents external referencing and an information processing apparatus communicating therewith and accessing first and third storage areas, includes: the decryption apparatus detecting a series of commands from a command group obtained by decrypting at least a portion of a program stored in the first storage area; obfuscating and storing the series of commands to a second storage area storing the decrypted portion and within the first storage area; assigning, when an execution request is received from the information processing apparatus, the third storage area having a capacity equivalent to any one series of commands; and storing to the third storage area, a series of certain commands stored in the second area and obtained by canceling obfuscation of the commands that correspond to the execution request; and the information processing unit executing the series of certain commands. | 2015-02-05 |
| 20150039901 | FIELD LEVEL DATABASE ENCRYPTION USING A TRANSIENT KEY - Embodiments of the present invention disclose a method, system, and computer program product for implementing user specific encryption in a database system. A computer receives a query statement including a user specific key and data, the data including data needing encryption and non-encrypted data. The computer encrypts the data needing encryption using the user specific key. The computer inserts both the encrypted data and the non-encrypted data into a table row in a database. The computer creates a hash of the user specific key, and stores the hash of the user specific key in the table row with the data. | 2015-02-05 |
| 20150039902 | DIGEST OBFUSCATION FOR DATA CRYPTOGRAPHY - Execution of an obfuscation application may cause a computing device to translate bits of a hashed value according to a sparse bit selection pattern, the sparse bit pattern including a translation of bits of the hashed value into reordered bit unit groupings sized according to a numeric base of a digit cypher; and generate an obfuscated value using the translated bit unit groupings of the hashed value as indices into the digit cypher, the digit cypher including a mapping of the indices to output values in the numeric base. The obfuscation application may further cause the device to receive a target value to be obfuscated in data records received from a data source, hash the target value using a hashing module to create the hashed value, in some cases truncate the hashed value, and replace the target value in the data records with the obfuscated value. | 2015-02-05 |
| 20150039903 | MASKING QUERY DATA ACCESS PATTERN IN ENCRYPTED DATA - A method for encrypting a database includes the following step. Keywords in the database are encrypted to obtain encrypted search tags for the keywords. A table of reverse indices is generated for the encrypted search tags. A table of cross keyword indices is generated. A method for searching in an encrypted database includes the following steps. A search is formulated as a conjunct of two or more atomic search queries. One of the conjuncts is selected as a primary atomic search query. Search capabilities are generated for a secondary atomic search query using the primary atomic search query and the secondary atomic search query. Such methods mask query data and the actual composition of the database to reduce computation complexity and privacy leakage. | 2015-02-05 |
| 20150039904 | INFORMATION PROCESSING APPARATUS, INFORMATION PROCESSING METHOD, AND PROGRAM - Speed-up of a cryptographic process by software (program) is realized. A data processing unit which executes a data process according to a program defining a cryptographic process sequence is included, and the data processing unit, according to the program, generates a bit slice expression data based on a plurality of plain text data items which are encryption process targets and a bit slice expression key based on a cryptographic key of each plain text data item, generates a whitening key and a round key based on the bit slice expression key, executes the cryptographic process including operation and movement processes of a block unit of the bit slice expression data, and an operation using the round key, as a process according to a cryptographic algorithm Piccolo, and generates the plurality of encrypted data items corresponding to the plurality of plain text data items by the reverse conversion of the data with respect to the cryptographic process results. | 2015-02-05 |
| 20150039905 | SYSTEM FOR PROCESSING AN ENCRYPTED INSTRUCTION STREAM IN HARDWARE - A system and method of processing an encrypted instruction stream in hardware is disclosed. Main memory stores the encrypted instruction stream and unencrypted data. A central processing unit (CPU) is operatively coupled to the main memory. A decryptor is operatively coupled to the main memory and located within the CPU. The decryptor decrypts the encrypted instruction stream upon receipt of an instruction fetch signal from a CPU core. Unencrypted data is passed through to the CPU core without decryption upon receipt of a data fetch signal. | 2015-02-05 |
| 20150039906 | SYSTEMS AND METHODS FOR LONG UNIVERSAL RESOURCE LOCATOR COMPRESSION - Methods and systems for managing universal resource locators (URLs) at a server include receiving, at the server, a search query from a client device; creating, by the server, a compressed hash value based on the search query; processing, by the server, the search query to yield a search result; and transmitting the compressed hash value to the client for storage in a browser history. | 2015-02-05 |
| 20150039907 | Method of Adapting a Uniform Access Indexing Process to a Non-Uniform Access Memory, and Computer System - Method and apparatus for constructing an index that scales to a large number of records and provides a high transaction rate. New data structures and methods are provided to ensure that an indexing algorithm performs in a way that is natural (efficient) to the algorithm, while a non-uniform access memory device sees IO (input/output) traffic that is efficient for the memory device. One data structure, a translation table, is created that maps logical buckets as viewed by the indexing algorithm to physical buckets on the memory device. This mapping is such that write performance to non-uniform access SSD and flash devices is enhanced. Another data structure, an associative cache is used to collect buckets and write them out sequentially to the memory device as large sequential writes. Methods are used to populate the cache with buckets (of records) that are required by the indexing algorithm. Additional buckets may be read from the memory device to cache during a demand read, or by a scavenging process, to facilitate the generation of free erase blocks. | 2015-02-05 |
| 20150039908 | System and Method for Securing A Credential Vault On A Trusted Computing Base - A method for utilizing a secure credential vault on a mobile computing device includes: prompting a user for and receiving from the user a credential vault password; prompting a user for and receiving a near-field communication (NFC) security token from a NFC-enabled device; verifying the credential vault password and the received NFC security token; and opening a secure session with the secure credential vault in response to successful verification. | 2015-02-05 |
| 20150039909 | COMMAND EXECUTING METHOD, MEMORY CONTROLLER AND MEMORY STORAGE APPARATUS - A command executing method for a memory storage apparatus is provided. The method includes grouping logical addresses into logical address groups and assigning a key for each of the logical address groups independently. The method also includes receiving a write command and write data corresponding to the write command and temporarily storing the write data into a buffer memory. The method further includes executing the write command, enabling a direct memory access once to transfer the write data from the buffer memory to a writable non-volatile memory module of the memory apparatus and encrypting each sector data of the write data with keys corresponding to the logical address groups that the logical address storing the sector data belong to. | 2015-02-05 |
| 20150039910 | SIDE CHANNEL POWER ATTACK DEFENSE WITH PSEUDO RANDOM CLOCK OPERATION - Apparatus and methods are provided for defending an electronic circuit secret algorithm and secret parameter values against a side-attack. In an example, a method can include receiving first one or more parameters for altering a clock signal of the electronic device at a non-volatile memory register, and altering a frequency of the clock signal of the electronic device during execution of an authentication routine according to the first one or more parameters. | 2015-02-05 |
| 20150039911 | COMPLIMENTARY BIT SLICING SIDE CHANNEL ATTACK DEFENSE - This document discusses, among other things, systems and methods to communicate data over a data bus during a first period of a clock signal with a uniform power distribution, including providing a complimentary bit state of the data during a first portion of the first period of the clock signal and providing an actual bit state of the data during a second portion of the first period of the clock signal. In an example, the first period can include first, second, third, and fourth portions, and the systems and methods can include providing a complimentary bit state of the data during first and fourth portions of the first period of the clock signal and an actual bit state of the data during a second portion of the first period of the clock signal. | 2015-02-05 |
| 20150039912 | Homomorphic Database Operations Apparatuses, Methods and Systems - The HOMOMORPHIC DATABASE OPERATIONS APPARATUSES, METHODS AND SYSTEMS (“HEDO”) transform transaction storage requests and homomorphic model queries using HEDO components into homomorphic model query results. In some implementations, the disclosure provides a processor-implemented method of securely querying a shared homomorphically encrypted data repository and performing cross-table homomorphic joins. | 2015-02-05 |
| 20150039913 | Electronic Control Unit - Disclosed is an electronic control unit capable of identifying an abnormality in a power supply voltage without narrowing the operating voltage range, and having minimal effects on cost and the circuit mounting surface area. The ECU includes a microcomputer containing an input terminal VCCin and an input terminal Vrin, a power supply IC that supplies a power supply voltage VCC to the input terminal VCCin, and as a reference-voltage-generator circuit a voltage-divider resistor and a voltage-divider resistor configuring a voltage-dividing circuit that outputs a sub-divided voltage Vc is sub-divided from the power supply voltage VCC, a capacitor coupled at one end to the input terminal Vrin and coupled on at the other end to ground, and a voltage isolation element coupled between the voltage-dividing circuit and the input terminal Vrin. | 2015-02-05 |
| 20150039914 | APPARATUS AND METHOD FOR ESTIMATING POWER CONSUMPTION - A power consumption estimation apparatus searches for an accessory apparatus that is mounted in a computing system that is connected through the Internet, receives a power consumption value of the accessory apparatus and a correlation value on an accessory apparatus combination basis from a power consumption and load amount information providing server, and estimates power consumption of the computing system using the power consumption value of the accessory apparatus and the correlation value on an accessory apparatus combination basis. | 2015-02-05 |
| 20150039915 | SERVER POWER SYSTEM - A server power system includes a backboard with a plurality of hard disk drive (HDD) units, a number of motherboards, and a number of power cables. The numbers of the HDD units, the motherboards, and the power cables are the same. Each HDD unit includes a number of HDDs. Each HDD of one HDD unit is coupled to a corresponding motherboard through a corresponding power cable. Each power cable includes a motherboard interface and an HDD interface. A ground pin and a power pin of the HDD interface are connected to a ground pin and a power pin of the motherboard interface correspondingly. The motherboard interface of each power cable is coupled to a power interface of the corresponding motherboard. The number of the power cables is selected to make the HDDs of each HDD unit coupled to the HDD interfaces of the corresponding power cables. | 2015-02-05 |
| 20150039916 | DATA PROCESSING SYSTEM WITH PROTOCOL DETERMINATION CIRCUITRY - A semiconductor device includes a processing system including a section of power domain circuitry and a section of coin cell power domain circuitry. The coin cell power domain circuitry is configured to, when power is initially provided to the coin cell power domain circuitry, using power provided by a power management circuit as feedback to determine that the power management circuit provides the power in response to a power request signal being a toggle signal, and determine that the power management circuit provides the power in response to the power request signal being a pulse signal. | 2015-02-05 |
| 20150039917 | INFORMATION PROCESSING DEVICE, ACTIVATION METHOD, AND COMPUTER PROGRAM PRODUCT - According to one embodiment, an information processing device includes a receiver, a search controller and a request transmitter. The receiver is configured to receive an activation request relative to a first device from a requesting device connected to a first network. The first device is connected to a second network. The search controller is configured to search for a second device in an activated state among a plurality of devices connected to the second network based on device state information indicative of a state of each of the devices. The request transmitter is configured to request the searched second device to transmit the activation request to the first device. | 2015-02-05 |
| 20150039918 | RACK SERVER SYSTEM AND OPERATION METHOD APPLICABLE THERETO - A rack server system and an operating method applicable thereto are provided. The rack server system includes a battery backup unit (BBU) and at least one server. The operating method includes: communicating the server and the BBU with each other; the BBU providing a status information and a previous self-discharging test information to the server for the server to judge a status of the BBU; and providing power from the BBU to the server and adjusting a loading of the server according to the status information of the BBU when an input power is interrupted. | 2015-02-05 |
| 20150039919 | DIRECTED WAKEUP INTO A SECURED SYSTEM ENVIRONMENT - Embodiments of processors, methods, and systems for directed wakeup into a secured system environment are disclosed. In one embodiment, a processor includes a decode unit, a control unit, and a messaging unit. The decode unit is to receive a secured system environment wakeup instruction. The control unit is to cause wake-inhibit indicator to be set for each of a plurality of responding logical processor to be kept in a sleep state. The messaging unit is to send a wakeup message to the plurality of responding logical processors, wherein the wakeup message is to be ignored by each of the plurality of responding logical processors for which the wake-inhibit indicator is set. | 2015-02-05 |
| 20150039920 | REDUCING POWER CONSUMPTION OF UNCORE CIRCUITRY OF A PROCESSOR - In one embodiment, a multi-core processor includes multiple cores and an uncore, where the uncore includes various logic units including a cache memory, a router, and a power control unit (PCU). The PCU can clock gate at least one of the logic units and the cache memory when the multi-core processor is in a low power state to thus reduce dynamic power consumption. | 2015-02-05 |
| 20150039921 | MEMORY SYSTEM AND MEMORY CHIP - A memory system includes a memory which asserts a high-power-consumption operation output when an amount of the power consumption is high in internal operations in respective operations, and a controller which has an interface function between a host and the memory and receives the high-power-consumption operation output. The controller switches an operation mode thereof to a low power consumption mode when the high-power-consumption operation output is asserted. | 2015-02-05 |
| 20150039922 | DYNAMIC LOW POWER STATES CHARACTERIZATION - An optimal idle state of a processor is selected using dynamically derived parameters. For example, the idle state is selected from a group of possible idle power states. A current detector is arranged to perform power measurements of the processor and to report a total power consumption of the processor for each time value of a range of discrete values for each possible idle power state. A calibration unit is arranged to communicate with the current detector and the processor, and to automatically activate a calibration sequence that is used to produce data from which idle power state is optimal for the processor for an estimated idle period. | 2015-02-05 |
| 20150039923 | METHOD OF CONTROLLING SDIO DEVICE AND RELATED SDIO SYSTEM AND SDIO DEVICE - Described in embodiments herein are techniques for placing a secure digital input output (SDIO) device in a sleep mode and waking up the SDIO device from the sleep mode. In accordance with an embodiment, a method of controlling the SDIO device comprising: writing a control value into a register of the SDIO device; allowing the SDIO device to switch to a first operation mode based on the control value written into the register; sending a first signal to the SDIO device through a first data terminal of the SDIO device; and allowing the SDIO device to switch to a second operation mode based on the first signal. | 2015-02-05 |
| 20150039924 | Field device - A field device with a microprocessor and a display and/or operating module, which can be disconnected from the field device, with the microprocessor showing an energy saving module, in which the display and/or operating module are switched off, with the waking circuit being provided, which generates a waking signal when the display and/or operating module are disconnected from the field device or connected thereto. | 2015-02-05 |
| 20150039925 | COMPUTING DEVICE AND METHOD FOR ADJUSTING AN OPERATING STATUS OF A COMPUTING DEVICE - The computing device calculates a battery level of a battery of the computing device when the computing device is powered by direct current (DC) electricity of the battery. The computing device adjusts an operating system (OS) of the computing device to a sleep mode when the battery is in a warming state. The computing device activates a watchdog (WDT) of a basic input output system (BIOS) to count a predetermined time and saves data into the storage device before the predetermined time ends. | 2015-02-05 |
| 20150039926 | DELAY SYSTEM AND METHOD FOR SERVER - A system of delaying the shutdown of a server, the server including a data processing unit connected to an external power supply unit. The delay system includes a delay controlling unit, a first discharging unit, and a second discharging unit. The delay controlling unit is coupled to the data processing unit and thus the external power supply unit. On shutdown, the first discharging unit discharges to provide power for data processing unit, the second discharging unit is invoked to continue supplying power for a necessary period when the discharging voltage value of the first discharging unit is found to be less than a predetermined voltage value. | 2015-02-05 |
| 20150039927 | Device Under Test Data Processing Techniques - A data processing unit has a time information provider for processing a clock or a strobe signal, configured to provide a digitized clock or strobe time information on the basis of the clock or strobe signal and at least one data extraction unit, coupled to the time information provider and configured to select data from a sequence of data samples of a data signal depending on the digitized clock or strobe time information. | 2015-02-05 |
| 20150039928 | DATA PROCESSING METHOD AND APPARATUS - A data processing method and apparatus are provided. The data processing apparatus includes a converter module and a control module. The converter module receives a clock signal through a pin, and decides a bit value of the first data according to a length of a corresponding period of the clock signal. The control module determines whether to perform a bit writing operation for writing the bit value into a memory according to the clock signal and the first data. | 2015-02-05 |
| 20150039929 | Method and Apparatus for Forming Software Fault Containment Units (SWFCUS) in a Distributed Real-Time System - The invention relates to a method for limiting the effects of software errors in a distributed real-time system in which a plurality of distributed application systems are executed simultaneously, wherein each application system forms an encapsulated software fault containment unit (SWFCU), wherein an SWFCU comprises the software of a distributed application system, said software being executed on one or more virtual computer nodes and one or more dedicated computer nodes, and exchanging messages via one or more encapsulated virtual communication systems, wherein a communication system consists of communication controllers, switching units and physical connections, and wherein the direct effects of a software error of an SWFCU remain limited to the SWFCU. | 2015-02-05 |
| 20150039930 | MULTI-TENANT DISASTER RECOVERY MANAGEMENT SYSTEM AND METHOD FOR INTELLIGENTLY AND OPTIMALLY ALLOCATING COMPUTING RESOURCES BETWEEN MULTIPLE SUBSCRIBERS - A Multi-Tenant Disaster Recovery Management System and method for intelligently and optimally allocating computing resources between multiple subscribers, the system comprising: one or more Multi-Tenant Disaster Recovery Management Server logically connected to one or more Production Site and one or more cloud based Disaster Recovery Site; a Network connecting said Multi-Tenant Disaster Recovery Management Server with said Production Site and said cloud based Disaster Recovery Site, wherein said Multi-Tenant Disaster Recovery Management Server is provided with at least one Disaster Recovery (DR) Manager Module, at least one Drill Scheduler Module, at least one Drill Executor Module, at least one WS Interface Module, at least one Usage Monitor Module and at least one Report Manager Module. | 2015-02-05 |
| 20150039931 | REPLAYING JOBS AT A SECONDARY LOCATION OF A SERVICE - Jobs submitted to a primary location of a service within a period of time before and/or after a fail-over event are determined and are resubmitted to a secondary location of the service. For example, jobs that are submitted fifteen minutes before the fail-over event and jobs that are submitted to the primary network before the fail-over to the second location is completed are resubmitted at the secondary location. After the fail-over event occurs, the jobs are updated with the secondary network that is taking the place of the primary location of the service. A mapping of job input parameters (e.g. identifiers and/or secrets) from the primary location to the secondary location are used by the jobs when they are resubmitted to the secondary location. Each job determines what changes are to be made to the job request based on the job being resubmitted. | 2015-02-05 |
| 20150039932 | ARBITRATION SUSPENSION IN A SAS DOMAIN - Systems and methods presented herein provide for managing connections in a SAS domain comprising at least first and second expanders. The first expander detects a failure of the initiator and indicates a change in the SAS domain to the second expander. The second expander detects an increase in arbitration wait time for a connection between the initiator and the target device, determines a race condition exists in the second expander, denies the connection between the initiator and the target device, directs the target device to wait for another connection, performs a discovery of the domain based on the discovery request from the first expander, and prevents a subsequent connection by the target device to the initiator after discovery completes. | 2015-02-05 |
| 20150039933 | STORAGE DEVICE AND MEMORY ACCESSING METHOD FOR A STORAGE DEVICE - A storage device and memory accessing method configure two separate memory units, each with dedicated I/O channel, accessible by two controllers, each corresponding to an interface connected to a host, and allows the storage device to establish at least two connections to the different hosts. As more than one connection is established between the storage device and the hosts at the same time, a first controller has both read and write accessibility to a first memory unit and a second controller has both read and write accessibility to a second memory unit, while the first controller has read-only accessibility to the second memory unit and the second controller has read-only accessibility to the second memory unit. | 2015-02-05 |
| 20150039934 | ACCOUNTING FOR DATA THAT NEEDS TO BE REBUILT OR DELETED - A method begins by a dispersed storage (DS) processing module identifying a plurality of encoded data slices requiring rebuilding. The method continues with the DS processing module determining an amount of reserve memory required for storage of rebuilt slices for the identified plurality of encoded data slices requiring rebuilding. The method continues with the DS processing module updating memory utilization information to include the amount of reserve memory required. The method continues with the DS processing module indicating the memory utilization. The method continues with the DS processing module obtaining rebuilt slices. The method continues with the DS processing module storing the rebuilt slices in the memory and updating the memory utilization information. | 2015-02-05 |
| 20150039935 | SOLID STATE DRIVE ARRAY PERFORMANCE AND RELIABILITY - A computing device collects wear life data of a first and a second solid state drive, wherein each solid state drive includes at least one stride, and wherein wear life data is data which includes information regarding wear and deterioration of each stride of each solid state drive. Based on the collected wear life data, the computing device determines the first solid state drive contains more high usage strides than the second solid state drive, wherein a high usage stride is a stride containing high usage data. The computing device then re-allocates data from at least one high usage stride of the first solid state drive to a stride of the second solid state drive, wherein the re-allocated data includes parity data. | 2015-02-05 |
| 20150039936 | DISTRIBUTED STORAGE NETWORK WITH ALTERNATIVE FOSTER STORAGE APPROACHES AND METHODS FOR USE THEREWITH - A method includes encoding input data into a plurality of slices. The plurality of slices are sent to a plurality of distributed storage and task execution units for storage, the plurality of distributed storage and task execution units being located at a corresponding plurality of sites A storage failure is detected corresponding to at least one of the plurality of slices corresponding to at least one of the plurality of the distributed storage and task execution units and at least one of the corresponding plurality of sites A foster storage approach is determined. At least one alternative distributed storage and task execution unit is selected in accordance with the foster storage approach. At least one foster slice is generated corresponding to the at least one of the plurality of slices. The at least one foster slice is sent to the at least one alternative distributed storage and task execution unit. | 2015-02-05 |
| 20150039937 | IMAGE FORMING APPARATUS, IMAGE FORMING APPARATUS CONTROL METHOD, AND RECORDING MEDIUM - An image forming apparatus configured to operate in a first power state and a second power state that uses less power than the first power state, in which error information for identifying processing that resolves an error detected during initialization processing is associated and registered in a storage unit, and processing for resolving the detected error is executed based on the error information registered in the storage unit. | 2015-02-05 |
| 20150039938 | Systems and Methods for Retiring and Unretiring Cache Lines - The systems and methods described herein may provide a flush-retire instruction for retiring “bad” cache locations (e.g., locations associated with persistent errors) to prevent their allocation for any further accesses, and a flush-unretire instruction for unretiring cache locations previously retired. These instructions may be implemented as hardware instructions of a processor. They may be executable by processes executing in a hyper-privileged state, without the need to quiesce any other processes. The flush-retire instruction may atomically flush a cache line implicated by a detected cache error and set a lock bit to disable subsequent allocation of the corresponding cache location. The flush-unretire instruction may atomically flush an identified cache line (if valid) and clear the lock bit to re-enable subsequent allocation of the cache location. Various bits in the encodings of these instructions may identify the cache location to be retired or unretired in terms of the physical cache structure. | 2015-02-05 |
| 20150039939 | System and Method for Secure Remote Diagnostics - An information handling system includes a processor and a management controller separate from the processor. The management controller is operable to boot the information handling system to a system service management module, direct the system service management module to execute diagnostics code on the processor and to store a result from the execution of the diagnostics code in a predetermined memory location. The management controller is also operable to retrieve the result from the predetermined memory location. | 2015-02-05 |
| 20150039940 | PROCESSOR DESIGN VERIFICATION - A system and method for verifying that a processor design having caches conforms to a specific memory model. The caches might not be maintained coherent in real time. Specifically, the system and method make use of a checker that conforms to the memory model, a time-stamping scheme, and a store buffering scheme to identify a bug(s) in the processor design that violates the memory model and/or loads an incorrect value in response to a load instruction. | 2015-02-05 |
| 20150039941 | Testing Coordinator - A system for testing two or more applications associated with a computerized process may include a central repository, a user interface and a testing coordinator. The central repository may be used to store at least one test case each including a test data set and two or more sets of test scripts. The user interface may facilitate a selection of one or more test cases for use by the testing coordinator. The testing coordinator may be configured to test the operation of the computerized process by initiating testing of a first application by a first test tool using the test data set and a first set of scripts and initiating testing of the second application by the second test tool using the test data set and the second set of scripts from the selected test case. In some cases, the first test tool is incompatible with the second test tool. | 2015-02-05 |
| 20150039942 | DASHBOARD PERFORMANCE ANALYZER - Described herein is a technology for a dashboard used for visualizing data. In some implementations, a dashboard with one or more dashboard item is provided. Performance of the dashboard is evaluated to determine a load time of the dashboard. Possible suggestions for improving performance of the dashboard are provided if performance issues are determined from evaluating performance of the dashboard. | 2015-02-05 |
| 20150039943 | SYSTEM, METHOD, AND COMPUTER READABLE MEDIUM FOR UNIVERSAL SOFTWARE TESTING - An automated software testing and validation system allows testing of a software application under test (SAUT) regardless of the dynamic nature of the SAUT. An abstracted set of hierarchal or linear objects model certain regions of the SAUT. Automated test scripts utilize theses regions to intuitively navigate and identify potions of the SAUT to automate. The scripts can also access specific SAUT elements contain within each defined region. These elements can then be used to invoke actions or verify outputs there from. The system uses a set of rich identification rules embodied in the system which allow the user to configure the identification of any element within the abstracted region. The rules are customizable to allow the user to configure the desired level of loose coupling between the automated scripts and the target element to adapt the scripts to the nature of the SAUT. | 2015-02-05 |
| 20150039944 | System and Method of High Integrity DMA Operation - A system and method for direct memory access (DMA) operation provides for receiving DMA requestors, assigning the received DMA requestors to one or more of a plurality of DMA engines for processing the received DMA requestors, and if one of the received DMA requestors is a safety requestor, assigning the safety requestor to at least two DMA engines of the plurality of DMA engines for processing the safety requestor, disabling a bus interface for coupling at least one DMA engine of the at least two DMA engines to memories, comparing the outputs of the at least two DMA engines, and generating an error message if the comparison of the outputs of the at least two DMA engines are different from each other. | 2015-02-05 |
| 20150039945 | DATA PROCESSOR DEVICE FOR HANDLING A WATCHPOINT AND METHOD THEREOF - Upon detecting an occurrence of a watchpoint event for debugging a computer processing system, at least a portion of at least one message in a trace message buffer is flushed when a characteristic of the at least one of the messages matches a specified characteristic. | 2015-02-05 |
| 20150039946 | METHOD AND SYSTEM FOR A HIGH AVAILABILITY FRAMEWORK - A method for providing a high availability framework, comprises executing a first component of the high availability framework within a shared kernel based on a first operating system, executing a second component of the high availability framework within a first userland of the first operating system, and executing a third component of the high availability framework within a second userland of a second operating system, wherein the second operating system is an older version of the first operating system. The method further comprises monitoring, by a health service of the shared kernel, the first operating system and a first application executing within the first userland; and monitoring, by the health service, the second operating system and a second application executing within the second userland. | 2015-02-05 |
| 20150039947 | APPLICATION INFORMATION SPECIFIABLE BY USERS AND THIRD PARTIES - Example systems and methods of generating and distributing user-specified application information are presented. In one example, an informational code to be generated during execution of a software application is accessed. A character string specified by a first user of the software application that is descriptive of the informational code is received. The informational code and the character string are stored in a data storage device, which stores a plurality of information codes in association with corresponding character strings for the software application. The informational code is received in response to the first information code being generated during execution of the software for a second user. The character string is retrieved from the data storage device after the execution of the application based on the informational code, and transmitted for display to the second user. | 2015-02-05 |
| 20150039948 | DATA STORAGE DEVICE AND OPERATING METHOD THEREOF - A data storage device includes: a nonvolatile memory device comprising a plurality of memory blocks, each including a plurality of pages; and a controller suitable for controlling an operation of the nonvolatile memory device in response to a request from an external device, wherein the controller determines whether or not a memory block including damaged pages in which stored data are damaged occurs in the memory blocks, sets a memory block including the damaged pages to an invalid memory block based on the determination result, and regenerates free pages of the memory block set as the invalid memory block into a valid memory block. | 2015-02-05 |
| 20150039949 | DRIVE TRAIN CONTROL - Various techniques relating to drive train control are disclosed. In an embodiment, in a first mode of operation communication between a controller and a submodule of the drive train takes place via a first communication channel and optionally additionally via a second communication channel. In a second mode of operation, upon failure of the first communication channel, communication with the submodule of the drive train takes place via the second communication channel. | 2015-02-05 |
| 20150039950 | APPARATUS FOR CAPTURING RESULTS OF MEMORY TESTING - A method to produce a description file of Joint Test Action Group (JTAG) capture-shift test data registers to be used to interpret a test result of a memory included in an integrated circuit structure that is configured for testing integrated circuit memory. A computer extracts, from a first data file, the names a memory built in self test instance, a memory built in self test port name, and a name of a first memory. The first data file controls the hierarchical and architectural arrangement of components of an integrated circuit. The first data file describes a hierarchical order of an architectural arrangement of the components, electrical pathways, and connections between the components and the electrical pathways of an integrated circuit design. The computer adds the extracted names into the description file such that the description file is configured to interpret a test result of a memory. | 2015-02-05 |
| 20150039951 | APPARATUS AND METHOD FOR ACQUIRING DATA OF FAST FAIL MEMORY - An apparatus and method for acquiring data of fast fail memory includes a pattern generator for generating a pattern to be recorded to a device under test (DUT) and receiving DUT data from the DUT; a data transmitter for sending the DUT data and the pattern generated so as to correspond thereto to a failure analyzer from the pattern generator; and a failure analyzer for analyzing the DUT data and the pattern generated so as to correspond to the DUT data, which are received from the data transmitter, thus producing failure analysis information. The data transmitter (FIFO) able to advance the failure analysis time allows failure analysis to be performed before completion of testing, thereby shortening the total failure analysis time and overcoming hardware limitations for failure analysis. | 2015-02-05 |
| 20150039952 | CIRCUIT ARRANGEMENT AND METHOD WITH MODIFIED ERROR SYNDROME FOR ERROR DETECTION OF PERMANENT ERRORS IN MEMORIES - A circuit arrangement for detecting memory errors is provided. The circuit arrangement comprises a memory ( | 2015-02-05 |
| 20150039953 | SYSTEM FOR SIMULTANEOUSLY DETERMINING MEMORY TEST RESULT - A system for simultaneously determining a memory test result includes a pattern generation part generating a pattern signal for testing so as to transmit the signal through an address line and a command line; a delay part receiving read data through a first data line from a closest memory device that is disposed closer to the system and to receive read data through a second data line from a farthest memory device that is disposed farther from the system; and a determination part simultaneously determining the read data of the closest memory device and the read data of the farthest memory device, which are simultaneously output from the delay part, using a determination clock, wherein the delay part recognizes the read data of the closest memory device and the read data of the farthest memory device. | 2015-02-05 |
| 20150039954 | Adaptive Electrical Testing of Wafers - Methods and systems for determining one or more parameters for electrical testing of a wafer are provided. One method includes determining electrical test paths through a device being formed on a wafer and physical layout components in different layers of the device corresponding to each of the electrical test paths. The method also includes determining one or more parameters of electrical testing for the wafer based on one or more characteristics of the electrical test paths. In addition, the method includes acquiring information for one or more characteristics of a physical version of the wafer. The information is generated by performing an inline process on the physical version of the wafer. The method further includes altering at least one of the one or more parameters of the electrical testing for the wafer based on the acquired information. | 2015-02-05 |
| 20150039955 | Systems and methods for Analog, Digital, Boundary Scan, and SPI Automatic Test Equipment - An Integrated Automatic Test Equipment that provides the test program development environments and execution of test programs for the assembled Print Circuit Boards. This test equipment includes Microsoft Windows PC executable programs, a digital/analog/SPI test controller, and a JTAG controller for boundary scan test. Both test controllers are attached to PC via USB ports for receiving test commands and replying test results. Test program development allows user to specify the rest stimulus and the expected test response for both digital test and boundary scan test. In addition to perform standalone tests, digital tester and boundary scan tester can drive and detect test signals to and from each other. The combination of digital test function and boundary scan test function can increase PCB production line test fault coverage. | 2015-02-05 |
| 20150039956 | TEST MUX FLIP-FLOP CELL FOR REDUCED SCAN SHIFT AND FUNCTIONAL SWITCHING POWER CONSUMPTION - A new flip-flop cell that is more efficient in scan chain configuration includes a multiplexer, storage element (e.g., a flip-flop), an inverter, and multiple logic gates. The flip-flop cell is configured to receive both a test signal and a data input signal and select one of the two to pass to the storage element based on a scan enable signal that indicates either a capture mode or a scan shift mode. In capture mode, the data input signal is passed to the storage element, and the internal outputs of the flip-flop are supplied to the logic gates. Based on the internal outputs and scan enable signal, the logic gates disable either one of two outputs of the flip-flop cell. In capture mode, a test flip-flop cell output is disabled. In scan shift mode, a standard function flip-flop cell output is disabled. | 2015-02-05 |
| 20150039957 | DYNAMIC BUILT-IN SELF-TEST SYSTEM - A method of performing a dynamic built-in self-test (BIST). The method includes performing a first test of a circuit on a semiconductor chip. The first test includes a first switch factor. The circuit during the first test is monitored with one or more sensors. A first sensor value of one or more sensors monitoring the circuit is determined. It is also determined whether the first sensor value is within a range of a programmable constant. A second switch factor is determined in response to determining that the first sensor value outside the range of the programmable constant. | 2015-02-05 |
| 20150039958 | METHOD AND DEVICE ENABLING A DYNAMIC BUNDLE SIZE HARQ MECHANISM - A method, device and computer program product for transmitting data blocks in an LTE or similar wireless communication system supporting HARQ and TTI bundling, with dynamic TTI bundle sizing is provided. Each TTI bundle includes a number of redundancy versions of a data block, for example differently encoded versions of the data block which can be combined together in accordance with Type-II HARQ. Plural TTI bundles can be transmitted as necessary in accordance with HARQ, for example in response to a NACK. The present technology involves adjusting the TTI bundle size for a given HARQ process, wherein at least two TTI bundles have different sizes. In various embodiments, the TTI bundle size progressively decreases with retransmissions so that the last TTI bundle is not excessively large, thereby reducing resource waste. TTI bundle size adjustment may be implemented in the uplink, downlink, or both. | 2015-02-05 |
| 20150039959 | METHOD FOR DECODING A CORRECTING CODE WITH MESSAGE PASSING, IN PARTICULAR FOR DECODING LDPC CODES OR TURBO CODES - A method for iteratively decoding a word of a correcting code by an iterative decoding algorithm in the course of which, for each bit of said code word, at least one extrinsic information item is generated at each iteration, includes the following steps: an initial step of decoding by means of said iterative decoding algorithm; simultaneously, for each bit of said code word, a step of developing a criterion representing the number of oscillations of at least one extrinsic information item or of one extrinsic information item with regard to another extrinsic information item; if the decoding does not converge; a step of modifying the value of the bit of said code word for which said number of oscillations is highest; and, an additional step of decoding said at least one modified code word by means of said iterative decoding algorithm. | 2015-02-05 |
| 20150039960 | ENCODING AND DECODING TECHNIQUES USING LOW-DENSITY PARITY CHECK CODES - Some embodiments include apparatus and methods for encoding message information. Such apparatus and methods can include using a parity check matrix of a low-density parity check (LDPC) code to generate a first matrix having an upper triangular sub-matrix. Parity information to encode the message information can be generated based on the first matrix if a total number of rows of the upper triangular sub-matrix is equal to the rank of the parity check matrix. If the total number of rows of the upper triangular sub-matrix is less than the rank of the parity check matrix, then a triangularization operation can be performed on a second sub-matrix of the first matrix to generate a second matrix. Parity information to encode the message information can be generated based on the second matrix. Other embodiments including additional apparatus and methods are described. | 2015-02-05 |
| 20150039961 | TURBO ENCODING ON A PARALLEL PROCESSOR - Methods and arrangements for parallelizing turbo encoding computations. At least one processor is provided. turbo encoding computations are split into first and second parts. Using at least one processor, the computations of the first part are performed. Thereafter, using the at least one processor, the computations of the second part are performed, the second part correcting output provided by the computations of the first part. One of the first and second parts comprises computations performed in parallel and the other of the first and second parts comprises computations performed not in parallel. Other variants and embodiments are broadly contemplated herein. | 2015-02-05 |
| 20150039962 | Methods, apparatus, and systems for coding with constrained interleaving - Serially-concatenated codes are formed in accordance with the present invention using a constrained interleaver. The constrained interleaver cause the minimum distance of the serial concatenated code to increase above the minimum distance of the inner code alone by adding a constraint that forces some or all of the distance of the outer code onto the serially-concatenated code. This allows the serially-concatenated code to be jointly optimized in terms of both minimum distance and error coefficient to provide significant performance advantages. Constrained interleaving can be summarized in that it: 1) uses an outer code that is a block code or a non-recursive convolutional code, and as such, there are multiple codewords present in the constrained interleaver, 2) selects a desired MHD, 3) selects an interleaver size and a set of predefined interleaver constraints to prevent undesired (low-distance) error events so as to achieve the desired MHD, and 4) performs uniform interleaving among the allowable (non-constrained) positions, to thereby maximize or otherwise improve the interleaver gain subject to the constraints imposed to maintain the desired MHD. | 2015-02-05 |
| 20150039963 | Encoding and decoding using constrained interleaving - Serially-concatenated codes are formed in accordance with the present invention using a constrained interleaver. The constrained interleaver cause the minimum distance of the serial concatenated code to increase above the minimum distance of the inner code alone by adding a constraint that forces some or all of the distance of the outer code onto the serially-concatenated code. This allows the serially-concatenated code to be jointly optimized in terms of both minimum distance and error coefficient to provide significant performance advantages. These performance advantages allow a noise margin target to be achieved using simpler component codes and a much shorter interleaver than was needed when using prior art codes such as Turbo codes. Decoders are also provided. Both encoding and decoding complexity can be lowered, and interleavers can be made much shorter, thereby shortening the block lengths needed in receiver elements such as equalizers and other decision-directed loops. Also, other advantages are provided such as the elimination of a error floor present in prior art serially-concatenated codes. That allows the present invention to achieve much higher performance at lower error rates such as are needed in optical communication systems. | 2015-02-05 |
| 20150039964 | Methods, apparatus, and systems for coding with constrained interleaving - Serially-concatenated codes are formed in accordance with the present invention using a constrained interleaver. The constrained interleaver cause the minimum distance of the serial concatenated code to increase above the minimum distance of the inner code alone by adding a constraint that forces some or all of the distance of the outer code onto the serially-concatenated code. This allows the serially-concatenated code to be jointly optimized in terms of both minimum distance and error coefficient to provide significant performance advantages. Constrained interleaving can be summarized in that it: 1) uses an outer code that is a block code or a non-recursive convolutional code, and as such, there are multiple codewords present in the constrained interleaver, 2) selects a desired MHD, 3) selects an interleaver size and a set of predefined interleaver constraints to prevent undesired (low-distance) error events so as to achieve the desired MHD, and 4) performs uniform interleaving among the allowable (non-constrained) positions, to thereby maximize or otherwise improve the interleaver gain subject to the constraints imposed to maintain the desired MHD. | 2015-02-05 |
| 20150039965 | Methods, apparatus, and systems for coding with constrained interleaving - Serially-concatenated codes are formed in accordance with the present invention using a constrained interleaver. The constrained interleaver cause the minimum distance of the serial concatenated code to increase above the minimum distance of the inner code alone by adding a constraint that forces some or all of the distance of the outer code onto the serially-concatenated code. This allows the serially-concatenated code to be jointly optimized in terms of both minimum distance and error coefficient to provide significant performance advantages. Constrained interleaving can be summarized in that it: 1) uses an outer code that is a block code or a non-recursive convolutional code, and as such, there are multiple codewords present in the constrained interleaver, 2) selects a desired MHD, 3) selects an interleaver size and a set of predefined interleaver constraints to prevent undesired (low-distance) error events so as to achieve the desired MHD, and 4) performs uniform interleaving among the allowable (non-constrained) positions, to thereby maximize or otherwise improve the interleaver gain subject to the constraints imposed to maintain the desired MHD. | 2015-02-05 |
| 20150039966 | Encoding and decoding using constrained interleaving - Serially-concatenated codes are formed in accordance with the present invention using a constrained interleaver. The constrained interleaver cause the minimum distance of the serial concatenated code to increase above the minimum distance of the inner code alone by adding a constraint that forces some or all of the distance of the outer code onto the serially-concatenated code. This allows the serially-concatenated code to be jointly optimized in terms of both minimum distance and error coefficient to provide significant performance advantages. These performance advantages allow a noise margin target to be achieved using simpler component codes and a much shorter interleaver than was needed when using prior art codes such as Turbo codes. Decoders are also provided. Both encoding and decoding complexity can be lowered, and interleavers can be made much shorter, thereby shortening the block lengths needed in receiver elements such as equalizers and other decision-directed loops. Also, other advantages are provided such as the elimination of a error floor present in prior art serially-concatenated codes. That allows the present invention to achieve much higher performance at lower error rates such as are needed in optical communication systems. | 2015-02-05 |
| 20150039967 | MEMORY DEVICE HAVING ADJUSTABLE REFRESH PERIOD AND METHOD OF OPERATING THE SAME - A memory device includes a plurality of rows of memory cells, a refresh period determination unit, and a refresh control unit. The plurality of rows of memory cells includes a first row and one or more second rows. The refresh period determination unit is configured to set a refresh period according to read data from the first row. A refresh control unit is configured to control refreshing the one or more second rows based on the refresh period and to control obtaining the read data from the first row based on an adjustment interval. | 2015-02-05 |
| 20150039968 | ERROR CODE MANAGEMENT IN SYSTEMS PERMITTING PARTIAL WRITES | 2015-02-05 |
| 20150039969 | STORING DATA IN A DIRECTORY-LESS DISPERSED STORAGE NETWORK - A method begins by a dispersed storage (DS) processing module of a dispersed storage network (DSN) sending a plurality of sets of encoded data slices to DSN memory for storage in accordance with a plurality of sets of DSN data addresses. The method continues with the DS processing module generating retrieval data that is based on a data object number and data storage information. The method continues with the DS processing module dispersed storage error encoding the retrieval data to produce a set of encoded retrieval data slices and generating a set of DSN retrieval data addresses based on the data name and on retrieval data storage information. The method continues with the DS processing module sending the set of encoded retrieval data slices to the DSN memory for storage in accordance with the set of DSN retrieval data addresses. | 2015-02-05 |
| 20150039970 | SYSTEMS AND METHODS OF STORING DATA - A method of writing data includes receiving a data page to be stored in a data storage device and initiating an encode operation to encode the data page. The encode operation generates first encoded data and a first portion of the first encoded data is stored to the first physical page of the data storage device. The method includes initiating storage of a second portion of the first encoded data to a second physical page of the data storage device. The method also includes initiating a decode operation to recover the data page. The decode operation uses a representation of the first portion of the first encoded data that is read from the first physical page without using any data from the second physical page. | 2015-02-05 |
| 20150039971 | RAID STORAGE SYSTEMS HAVING ARRAYS OF SOLID-STATE DRIVES AND METHODS OF OPERATION - RAID storage systems and methods adapted to enable the use of NAND flash-based solid-state drives. The RAID storage system includes an array of solid-state drives and a controller operating to combine the solid-state drives into a logical unit. The controller utilizes data striping to form data stripe sets comprising data (stripe) blocks that are written to individual drives of the array, utilizes distributed parity to write parity data of the data stripe sets to individual drives of the array, and writes the data blocks and the parity data to different individual drives of the array. The RAID storage system detects the number of data blocks of at least one of the data stripe sets and then, depending on the number of data blocks detected, may invert bit values of the parity data or add a dummy data value of “1” to the parity value. | 2015-02-05 |
| 20150039972 | APPARATUS, SYSTEM AND METHOD FOR MERGING CODE LAYERS FOR AUDIO ENCODING AND DECODING AND ERROR CORRECTION THEREOF - Apparatus, system and method for encoding and decoding ancillary code for digital audio, where multiple encoding layers are merged. The merging allows a greater number of ancillary codes to be embedded into the encoding space, and further introduces efficiencies in the encoding process. Utilizing certain error correction techniques, the decoding of ancillary code may be improved and made more reliable. | 2015-02-05 |
| 20150039973 | TRANSMITTER APPARATUS AND SIGNAL PROCESSING METHOD THEREOF - A transmitter apparatus and a receiver apparatus are provided. The transmitter apparatus includes: an encoder configured to generate a low density parity check (LDPC) by performing LDPC encoding; an interleaver configured to interleave the LDPC codeword; and a modulator configured to map the interleaved LDPC codeword onto a modulation symbol. The modulator maps a bit included in a predetermined group from among a plurality of groups constituting the LDPC codeword onto a predetermined bit in the modulation symbol. | 2015-02-05 |
| 20150039974 | TRANSMISSION APPARATUS AND ASSOCIATED METHOD OF ENCODING TRANSMISSION DATA - An encoder and decoder using LDPC-CC (Low Density Parity Check—Convolutional Codes) is disclosed. In the encoder ( | 2015-02-05 |
| 20150039975 | ERROR CORRECTION DEVICE AND ERROR CORRECTION METHOD - According to one embodiment, an error correction device includes a syndrome processing unit, a generation unit, and a search processing unit. The syndrome processing unit generates a syndrome value based on received data. The generation unit generates t (t is a maximum number of correctable bits) coefficient values of an error position polynomial based on the syndrome value. The search processing unit calculates a root of the error position polynomial, with a concurrency of computation being equal to or greater than “2”, by using the coefficient values of the error position polynomial, when a number of error bits is not more than a predetermined value s (1<=s| 2015-02-05 | |
| 20150039976 | Efficient Error Correction of Multi-Bit Errors - A circuitry for error correction includes a plurality of subcircuits for determining intermediate values Zw | 2015-02-05 |
| 20150039977 | Method And Apparatus For Error Detection In A Communication System - A method processes a data packet in a first sequence of disjoint original segments of the same length. The method includes modifying a first of the original segments of the first sequence by modifying one or more symbols therein. A start of the data packet is located in the first of the original segments and is positioned after a first digital data symbol therein. The method also includes modifying a last of the original segments of the first sequence by modifying one or more digital data symbols therein. An end of the data packet is located in the last of the original segments and is located before the last digital data symbol therein. The method also includes determining a remainder sequence by effectively performing a polynomial division on a second sequence of disjoint segments that are derived from the first sequence. Each segment of the second sequence corresponds to and is derived from one of the original segments of the first sequence. The segments of the second sequence have the length of the original segments of the first sequence. A first of the derived segments of the second sequence is the modified first of the original segments. A last of the derived segments of the second sequence is derived from the modified last of the original segments. | 2015-02-05 |
| 20150039978 | Systems and Methods for Hybrid Priority Based Data Processing - The present inventions are related to systems and methods for data processing, and more particularly to systems and methods for priority based data processing. | 2015-02-05 |
| 20150039979 | METHOD AND APPARATUS FOR CONCEALING ERROR IN COMMUNICATION SYSTEM - A method and an apparatus for concealing an error of an apparatus for receiving an audio frame in a communication system are provided. The includes determining whether the error occurs in a current audio frame that is received from a transmitter, determining whether the audio frame includes a signal that corresponds to a preset specific frequency when the error occurs, setting a gain of the signal that corresponds to the specific frequency to be lower than a preset limit value if the audio frame includes the signal, and concealing the error of the current audio frame based on a previous audio frame of the audio frame in which the error occurs and the gain of the signal that corresponds to the set specific frequency. | 2015-02-05 |
| 20150039980 | METHOD AND SYSTEM OF CONSUMER ACTIVITY TRACKING - Consumer activity tracking. Example embodiments include: providing a first web page to a consumer's from a first entity, the first web page showing a product; placing a first beacon packet on the consumer, the first beacon packet indicating the consumer was shown the product by way of first web page; providing a second web page to the consumer, the providing the second web page from a second entity, the second web page showing the product, and a request for the second web page does not include attribution of the request; initiating acquisition of the product by the consumer by way of an acquisition web page provided from the second entity; determining, by the second entity, that the consumer was shown the product by way of the first web page prior to initiating acquisition by the consumer; and attributing advertising credit to the first entity responsive to the determining. | 2015-02-05 |
| 20150039981 | EMBEDDED SYSTEM WEB SERVER - A method for implementing a web server in an embedded system is provided. Registration information is received at the web server in the embedded system from a plurality of objects. Each object provides a link to itself in the registration information. The registration information is stored in a registry as a list of links mapped to the objects. A web page is dynamically generated at runtime by the web server based on the registration information in the registry to provide a user interface including a visual depiction of the links on the web page. The web page is provided to a web browser external to the embedded system such that the objects are accessible to the web browser based on the links through the user interface. | 2015-02-05 |
| 20150039982 | REAL-TIME SHARED WEB BROWSING AMONG SOCIAL NETWORK CONTACTS - A determination is made that each of at least two social network contacts involved in a social messaging interaction initiate a separate web search associated with the social messaging interaction. A separate set of web search results returned to each of the at least two social network contacts is captured in association with each initiated separate web search. A combined live search results view that includes each captured separate set of web search results is provided to each of the at least two social network contacts. The combined live search results view provides navigation to web content returned to other social network contacts. | 2015-02-05 |
| 20150039983 | SYSTEM AND METHOD FOR CUSTOMIZING A USER INTERFACE - Described is a system and method for customizing a user interface. A method according to one embodiment of the present invention comprises receiving a given content item and scoring the given content item. When the score exceeds a threshold, at least a portion of the given content is highlighted. The given content item is displayed with at least the portion of the given content item highlighted. | 2015-02-05 |
| 20150039984 | TABLE FORMAT MULTI-DIMENSIONAL DATA TRANSLATION METHOD AND DEVICE - The invention includes a first process of inserting one row below each row of a column heading of an original table, inserting one column to the right of each column of a row heading, and entering a corresponding ID into each cell of the inserted row or column; a second process of inserting one row between the column heading and data portion, inserting one column between the row heading and data portion, and entering an ID of the dimension when inserted cells indicate a value of a dimension, entering no data when inserted cells indicate a measure, and entering an ID of a measure into a cell at the intersection of the inserted row and column when column headings and row headings indicate dimension's values; and a third process of identifying a dimension, value thereof, or measure corresponding to each cell of the data portion of the created template table. | 2015-02-05 |
| 20150039985 | ASSOCIATING MENTIONED ITEMS BETWEEN DOCUMENTS - A document processor for associating mentioned items with each other in two documents. A conversion unit converts at least a portion of mentioned items expressed in table format among the mentioned items included in the two documents. An association processing unit associates mentioned items with each other in the two documents including at least some mentioned items converted to text format. The conversion unit converts each of a plurality of cells included in the mentioned items expressed in table format to separate mentioned items in text format. | 2015-02-05 |
| 20150039986 | COLLABORATION SYSTEM AND METHOD - A system to provide an environment for two or more people to collaborate on a project, share experiences, or meet new people. An administrator (which may also be a user or group moderator) can use a smart phone application or web browser to create a new group that one or more users may be a member. The administrator may use software on a computer to generate a symbol associated with this group. | 2015-02-05 |
| 20150039987 | SYSTEMS AND METHODS FOR DATA ENTRY - Systems and methods are disclosed for inputting data into a computing device, and particularly for presenting form content on a computing device having a limited viewing area for receiving input from a user. A protocol or other data is obtained that specifies a plurality of fields into which input data can be entered. Each field is associated with a field group. The field group specifies an ordering of all fields assigned to the field group. The fields are presented in series, one at a time, on a display screen of the computing device. The presentation occurs according to an ordering specified in the field group. Input data is received as it is entered into each field of the plurality of fields during a data entry session. The input data is incorporated into form data corresponding to the data entry session. The form data is made accessible to a third-party application. | 2015-02-05 |
| 20150039988 | FORM PROCESSING - The present disclosure provides a form processing method and terminal. Instead of using the cursor to locate an input box at a form, the present techniques fix a position of the cursor at the form and move the form at a touchscreen to coincide an information inputting position at a to-be-processed input box with the position of the cursor at the touchscreen. The present techniques facilitate a terminal to input the information received from the user into the to-be-processed input box to achieve the purpose of using the form to collect information. The present techniques are not required to assign lots of processes for clicking by the user to trigger the touchscreen and moving the cursor and only need to assign processes of moving the form. Thus, the present techniques reduce the processes required for processing the form and effectively save terminal resources. | 2015-02-05 |
| 20150039989 | ENTRY OF VALUES INTO MULTIPLE FIELDS OF A FORM USING TOUCH SCREENS - An aspect of the present disclosure facilitates users of touch screens to conveniently provide values for fields of a form. In an embodiment, a mapping is maintained to map symbols to corresponding profiles, with each profile being defined to specify a respective value for each of a corresponding set of fields. A form is sent for display on a touch screen, and a user is permitted to perform a touch action constituting a sequence of touch points (and representing input symbol) on the touch screen. The mapping is examined to determine a first symbol matching the input symbol, and a first profile corresponding to the first symbol is identified. The form is then auto-filled with values specified by the first profile. The user can continue interaction with the form with such auto-filled values. | 2015-02-05 |
| 20150039990 | ELECTRONIC CONTENT MANAGEMENT WORKFLOW WITH DOCUMENT VERSIONING - A method for managing an electronic document (ED) using an electronic content management (ECM) system, including: receiving a submission comprising the ED; generating a unique identifier (UID), a first version number, and a first mapping linking the UID and the first version number to the ED; inserting a first symbol corresponding to the UID and the first version number into the ED; generating a first archived document corresponding to the ED and comprising the first symbol; distributing the first archived document; receiving a submission comprising a revised version of the ED from a user; generating a second version number and a second mapping linking the UID and the second version number to the revised version; inserting a second symbol corresponding to the UID and the second version number into the revised version; and generating a second archived document corresponding to the revised version and comprising the second symbol. | 2015-02-05 |
| 20150039991 | CREATION SYSTEM FOR PRODUCING SYNCHRONISED SOUNDTRACKS FOR ELECTRONIC MEDIA CONTENT - A method of creating, with a hardware system, a synchronised soundtrack for an item of electronic media content in which the playback of the soundtrack is synchronised with the user's reading speed. The method generates a graphical user interface (GUI) on a display comprising a reading display pane displaying at least a portion of the electronic media content in a reading format and a linear progression display pane displaying a linear progression of a range of reading position identifiers corresponding to at least a portion of the electronic media content displayed on the first display pane. User interaction with a GUI of the interface is used to configure audio data for each new audio region of the soundtrack. Both the reading display pane and linear progression display pane are simultaneously updated with graphical representations of the newly configured audio region showing an association between the audio region and the corresponding text region in the electronic media content to which it relates. | 2015-02-05 |
| 20150039992 | MECHANISM FOR SETTING ASCENT AND BASELINE FOR HTML ELEMENTS - A method for rendering a document on a web browser includes receiving a portion of text within the document to be rendered on a web browser and determining a maximum height of the portion of text. A spacer element is inserted into the portion of text, where the spacer element has a height greater than the maximum height of the portion of text. A vertical position of the portion of text and the spacer element is adjusted by an offset, where a baseline of the portion of text is determined from the height of the spacer element and the offset. The portion of text is rendered on the web browser based at least in part on the baseline. | 2015-02-05 |
| 20150039993 | DISPLAY DEVICE AND DISPLAY METHOD - According to one embodiment, a display device includes a display, a recognition controller, a converter, a browser and a display processor. The recognition controller is configured to analyze broadcast video comprising a two-dimensional code and to recognize the two-dimensional code. The converter is configured to convert the recognized two-dimensional code into address information. The browser is configured to access a web page indicated by the address information and to display the web page on a browser screen. The display processor is configured to display a screen of the broadcast video and the browser screen on the display at the same time. | 2015-02-05 |
| 20150039994 | COLOR-BASED DESIGNS - In one example, a method performed on a computing system includes receiving a first query for a product, receiving an input that comprises a collection of colors, determining, based at least in part on the input, one or more candidate color palettes, presenting the one or more candidate color palettes on a web site, receiving a selection that specifies one of the candidate color palettes as a selected color palette, providing, on the web site, a list of products based at least in part on the first query and the selected color palette and adjusting the list of products in real-time as a user moves a camera on a mobile device and provides new color input. | 2015-02-05 |
