06th week of 2015 patent applcation highlights part 45 |
Patent application number | Title | Published |
20150037892 | RECOMBINATION SYSTEM - The present invention relates to a method for carrying out recombination at a target locus. | 2015-02-05 |
20150037893 | PATHOGEN RESISTANT PLANT CELLS AND METHODS OF MAKING - The present invention relates to genetically modified plant cells that have reduced expression or activity of at least one amino acid efflux transporter and/or at least one mineral efflux transporter compared to levels of expression or activity of the at least one amino acid efflux transporter or mineral efflux transporter in an unmodified plant cell. The present invention also relates to genetically modified plant cells that have increased expression or activity of at least one amino acid influx transporter and/or at least one mineral influx transporter compared to levels of expression or activity of the at least one amino acid influx transporter or mineral influx transporter in an unmodified plant cell. | 2015-02-05 |
20150037894 | SORPTION EXOTHERMICITY MEASUREMENT DEVICE AND SORPTION EXOTHERMICITY MEASUREMENT METHOD - A sorption exothermicity measurement device ( | 2015-02-05 |
20150037895 | Hydrocarbon Detector Based on Carbon Nanotubes - Hydrocarbon detectors having CNTs coated with an amphiphilic coating capable of sequestering an active molecule are provided. In one aspect, a hydrocarbon detection device is provided. The hydrocarbon detector device includes a plurality of CNTs dispersed in a polar solvent, wherein each of the CNTs is coated with an amphiphilic coating having molecules with a hydrophilic moiety and a hydrophobic moiety, and wherein the coating creates a hydrophobic environment proximal to a surface of each of the CNTs; and one or more hydrophobic active molecules sequestered in the hydrophobic environment proximal to the surface of each of the CNTs. | 2015-02-05 |
20150037896 | Sample Distribution - A method is described for distributing samples within an automated analyzer from a linear arrangement of sample vessels to a processing plate in a two-dimensional n×m arrangement wherein samples are sorted, followed by transfer with a pipetting device with a linear arrangement to a processing vessel in a two-dimensional n×m arrangement and subsequent processing of samples using a second pipetting device which has a two-dimensional n×m arrangement. | 2015-02-05 |
20150037897 | METHOD OF ANALYZING A SAPPHIRE ARTICLE - A method of removing material from a sapphire article is described. In particular, the method comprises the step of providing an initial sapphire layer and reducing the thickness of the layer while not significantly increasing the surface roughness of the layer, Cover plates for electronic device and methods of preparing them are also disclosed, along with a method of analyzing a sapphire article produced by the present method. | 2015-02-05 |
20150037898 | DEVICES AND METHODS OF DETERMINING DISTURBANCE VARIABLE-CORRECTED ANALYTE CONCENTRATIONS - Devices and methods are provided for determining concentration of at least one analyte in a body fluid sample such as blood, especially a blood glucose concentration. In the methods, a test element is provided that has at least one reagent element configured so as to carry out at least one optically detectable detection reaction in the presence of the analyte. The body fluid sample is applied to the test element and a time course of at least one optical measurement variable of the reagent element is detected. At least one first time interval of the time course of the optical measurement variable is used to determine at least one disturbance variable value in the body fluid sample, in particular a concentration of a disturbance variable such as hematocrit. At least one second time interval of the time course is used to determine analyte concentration. The at least one disturbance variable value can be used to correct/compensate the analyte concentration. | 2015-02-05 |
20150037899 | BORATE DETECTOR COMPOSITION AND ASSAY SOLUTION - A composition and an assay solution for the determination of dissolved borate concentration comprising a catechol dye, a solubilizing agent, and a buffer are described. The composition and assay solution may further comprise a solubilizing agent. The catechol dye acts as a chemical borate sensor. The chemical borate sensor changes its optical properties upon binding to borate. The multivalent cation chelator binds multivalent cations present in a sample being analyzed. The buffer prevents changes in pH. The solubilizing agent aids in solubilizing the catechol dye, multivalent cation chelator, and/or the buffer. | 2015-02-05 |
20150037900 | Point of Care Cyanide Test Device and Kit - A device, method, and test kit for rapidly detecting cyanide in a sample. The inventive device comprises a container comprising a sample chamber and a sensor chamber separated by a selectively permeable barrier. The sample chamber contains a reagent for releasing cyanide from the sample, and the sensor chamber contains a cyanide detector comprising a conductive polymer which absorbs the released cyanide, generating a change in signal. Signals can be viewed colorimetrically or transmitted to a LCD/LED panel wherein the cyanide measurement readout is displayed. | 2015-02-05 |
20150037901 | METHODS AND KITS FOR QUANTITATIVE DETERMINATION OF TOTAL ORGANIC ACID CONTENT IN A COOLANT - The invention relates to methods and kits for determining the total organic acid content in a coolant sample. | 2015-02-05 |
20150037902 | NANOCALORIMETER DEVICE AND METHODS OF OPERATING THE SAME - A nanocalorimeter device includes a head that defines first dispensing regions configured to receive first drops of first liquids and a cover that defines second dispensing regions corresponding to the first dispensing regions and configured to receive second drops of second liquids. The first and second dispensing regions form corresponding nanocalorimeter cells when the cover is connected to the head, each nanocalorimeter cell thereby containing first and second drops which are combined during a measurement run into a merged drop. The nanocalorimeter device further includes mini-bars pre-dispensed in the second dispensing regions, respectively, each mini-bar including a high magnetic permeability material. A magnetic driver is configured to generate a rotating magnetic field around the nanocalorimeter cells, where the rotating magnetic field causes the mini-bars to spin, mixing the first and second liquids in the merged drop within each nanocalorimeter cell. | 2015-02-05 |
20150037903 | DEVICE AND METHOD FOR DRIED FLUID SPOT ANALYSIS - A lab-on-chip-based system is described for the direct and multiple sampling, control of the volume, fluid filtration, biochemical reactions, sample transfer, and dried spot generation on the conventional and commercial cards for dried fluid spot. Within an all-in-one integrated holder, the invention allows the complete process required to ensure a quantitative analysis of blood, plasma or any other fluids, modification and enrichment of molecule subsets, and formation of a dried fluid spot on the specific spot location of a passive cellulose, non-cellulose, absorbent, or non-absorbent membrane material sampling. | 2015-02-05 |
20150037904 | INTERFACE DESIGNED WITH DIFFERENTIAL PUMPING AND BUILT-IN FIGURE OF MERIT METHOD TO MONITOR CHAMBERS WHERE ENVIRONMENTALLY SENSITIVE SAMPLES ARE PREPARED AND TRANSFERRED FOR ANALYSIS - In some embodiments, a system may function to transfer samples in a controlled environment. The system may include a sample container configured to convey a sample from a first device to a second device. The first device may be under pressure and the second device may be under vacuum. The second device may include a load chamber which functions to accept the sample from the sample container. The second device may include a pump chamber coupled to the load chamber using a conduit such that the pump chamber is in fluid communication with the load chamber as required. The second device may include a high vacuum pump coupled to the pump chamber. The second device may include a vacuum pump coupled to the pump chamber through the high vacuum pump in sequence. The second device may include an orifice sized to significantly restrict the flow of fluids through the conduit coupling the pump chamber to the load chamber, wherein the orifice is configured to allow for a transition from a viscous into a molecular flow. | 2015-02-05 |
20150037905 | RISK MARKERS FOR CARDIOVASCULAR DISEASE - Provided herein methods for determining whether a subject, particularly a human subject, is at risk of developing, having, or experiencing a complication of cardiovascular disease, and methods of treating subjects who are identified by the current methods of being at risk for cardiovascular disease. In one embodiment, the method comprises determining levels of one or more oxidized apolipoprotein A-I related biomolecules in a bodily sample from the subject. Also, provided are kits and reagents for use in the present methods. Also provided are methods for monitoring the status of cardiovascular disease in a subject or the effects of therapeutic agents on subjects with cardiovascular disease. Such method comprising determining levels of one or more oxidized apolipoprotein A-I related molecules in bodily samples taken from the subject over time or before and after therapy. | 2015-02-05 |
20150037906 | ODOR ADSORBENT MATERIAL, ODOR DETECTION KIT, AND METHOD FOR USING SAME - An odor adsorbent material, an odor detection kit, and a method for using the same for rapidly identifying a facility where binding of an odor component had occurred among facilities used in a distribution route of a commodity. The odor detection kit includes at least two pieces of an odor adsorbent material, a package section that includes at least two storage sections and is configured to store the odor adsorbent material, and a sheet section. The odor detection kit is installed in a facility. At least one of the pieces of the odor adsorbent material is exposed to open space in the facility, recovered therefrom, and sealed and stored. At the time of testing, occurrence of odor emission in the facility is determined by comparing odor components adsorbed by each of the pieces of the odor adsorbent material. | 2015-02-05 |
20150037907 | METHODS AND KITS FOR DETECTION OF ACTIVE MALIGNANY - Various embodiments of methods and kits are disclosed for detection and/or diagnosis of cancer (e.g., active malignancy) in a subject patient by analyzing a first sample of the subject patient's albumin-containing extracellular fluid (e.g., blood serum). Some embodiments comprise analyzing a second sample of the subject patient's albumin-containing extracellular fluid obtained between 2 and 90 days (e.g., between 5 and 30 days) after the first sample. | 2015-02-05 |
20150037908 | NEW METHOD FOR RAPID DETECTION OF HEPATOCYTE GROWTH FACTOR IN BIOLOGICAL FLUIDS - The present invention relates to a method for determining the presence, absence or amount of biologically active HGF in a sample, comprising the steps (i) bringing the sample in contact with a first porous solid phase comprising a HGF binding component of the extracellular matrix or cell membrane, and an indicator composition comprising bromothymol blue and a quaternary ammonium compound; and (ii) correlating the colour of the porous solid phase with the presence, absence or amount of biologically active HGF in the sample. It further relates to a device comprising a first porous solid phase comprising at least one HGF-binding component of the extracellular matrix or cell membrane, and an indicator composition comprising bromothymol blue and a quaternary ammonium compound. | 2015-02-05 |
20150037909 | Electronic Nose or Tongue Sensors - The present invention relates to a sensor for an electronic tongue or nose for analysing a sample or detecting a target. The sensor comprises a support, on one surface of which a plurality of sensitive areas are located, each sensitive area comprising at least one receptor and being capable of transmitting a measurable signal generated by the interaction of at least one constituent of the sample or one target with at least one receptor. The sensor is characterised in that it comprises at least three sensitive areas that differ from one another in terms of their respective receptor compositions, at least one of the sensitive areas comprising a mixture of at least two different receptors, while the two other sensitive areas each comprise at least one of the two receptors. | 2015-02-05 |
20150037910 | METHOD OF MANUFACTURING ORGANIC ELECTROLUMINESCENT ELEMENT - A method of manufacturing an organic electroluminescent element including: a first manufacturing process of stacking at least a first electrode layer, a dielectric layer, and a second electrode layer on a substrate in this order, the organic electroluminescent element having a light-emitting portion that is in contact with an inner surface of a concave portion formed to penetrate the dielectric layer; measuring a brightness distribution of the organic electroluminescent element while causing the light-emitting portion to emit light by applying a voltage to the first electrode layer and the second electrode layer of the organic electroluminescent element manufactured in the first manufacturing process, and obtaining uneven brightness information of the organic electroluminescent element; and a second manufacturing process of adjusting concave portion density on the basis of the uneven brightness information obtained in the brightness distribution measurement process, and reducing uneven brightness of the organic electroluminescent element. | 2015-02-05 |
20150037911 | SUBSTRATE TREATMENT APPARATUS, SUBSTRATE TREATMENT METHOD, AND NON-TRANSITORY STORAGE MEDIUM - A substrate treatment apparatus configured such that substrates in a same lot are distributed by a delivery mechanism into a plurality of unit blocks, each unit block including a solution treatment module, an ultraviolet irradiation module, and a substrate carrying mechanism, the apparatus includes: an illuminance detection part that detects an illuminance of a light source of the ultraviolet irradiation module; and a control part that controls, when an illuminance detection value of the ultraviolet irradiation module in one unit block among the plurality of unit blocks becomes a set value or less, the delivery mechanism to stop delivery of a substrate to the one unit block and deliver subsequent substrates to another unit block, and the ultraviolet irradiation module to perform irradiation on substrates which have already been delivered to the one unit block with an irradiation time adjusted to a length according to the illuminance detection value. | 2015-02-05 |
20150037912 | METHOD FOR MANUFACTURING TRANSISTOR - A hydrogen barrier layer is selectively provided over an oxide semiconductor layer including hydrogen and hydrogen is selectively desorbed from a given region in the oxide semiconductor layer by conducting oxidation treatment, so that regions with different conductivities are formed in the oxide semiconductor layer. After that, a channel formation region, a source region, and a drain region can be formed with the use of the regions with different conductivities formed in the oxide semiconductor layer. | 2015-02-05 |
20150037913 | MILLIMETER WAVE WAFER LEVEL CHIP SCALE PACKAGING (WLCSP) DEVICE AND RELATED METHOD - Various embodiments include wafer level chip scale package (WLCSP) structures and methods of tuning such structures. In some embodiments, the WLCSP structure includes: a printed circuit board (PCB) trace connection including at least one PCB ground connection connected with a PCB ground plane; a set of ground solder balls each contacting the printed circuit board trace connection; a set of chip pads contacting each of the ground solder balls in the set of ground solder balls; a chip ground plane connecting the set of chip pads; and a signal interconnect interposed between two of the set of ground solder balls, the signal interconnect including: a signal trace connection electrically isolated from the PCB ground plane; a signal ball contacting the signal PCB trace connection; a chip pad contacting the signal ball, and a signal trace connection on a chip contacting the chip pad. | 2015-02-05 |
20150037914 | METHOD FOR MANUFACTURING TESTED APPARATUS AND METHOD FOR MANUFACTURING SYSTEM INCLUDING TESTED APPARATUS - Disclosed herein is a method for manufacturing a tested apparatus that includes forming a stacked structure that includes a plurality of first semiconductor chips stacked over a semiconductor wafer. The semiconductor wafer comprises a plurality of second semiconductor chips that are arranged in matrix of a plurality of rows and columns. Each of the first semiconductor chips is stacked over and electrically connected to a different one of the second semiconductor chips. The method further includes contacting a probe card to at least one of the first semiconductor chips to perform a first test operation on a corresponding one of the second semiconductor chips with an intervention of the at least one of the first semiconductor chips so that a plurality of tested apparatus each comprising a pair of first and second semiconductor chips stacked with each other is derived. | 2015-02-05 |
20150037915 | METHOD AND SYSTEM FOR LASER FOCUS PLANE DETERMINATION IN A LASER SCRIBING PROCESS - In embodiments, a method of laser scribing a mask disposed over a semiconductor wafer includes determining a height of the semiconductor over which a mask layer is disposed prior to laser scribing the mask layer. In one embodiment the method includes: determining a height of the semiconductor wafer under the mask in a dicing street using an optical sensor and patterning the mask with a laser scribing process. The laser scribing process focuses a scribing laser beam at a plane corresponding to the determined height of the semiconductor wafer in the dicing street. Examples of determining the height of the semiconductor wafer can include directing a laser beam to the dicing street of the semiconductor wafer, which is transmitted through the mask and reflected from the wafer, and identifying an image on a surface of the wafer under the mask with a camera. | 2015-02-05 |
20150037916 | LOCAL SEAL FOR ENCAPSULATION OF ELECTRO-OPTICAL ELEMENT ON A FLEXIBLE SUBSTRATE - An electroluminescent display or lighting product incorporates a panel comprising a collection of distinct light-emitting elements formed on a substrate. A plurality of distinct local seals are formed over respective individual light-emitting elements or groups of light-emitting elements. Each local seal is formed by depositing a low melting temperature glass powder suspension or paste using inkjet technology, and fusing the glass powder using a scanning laser beam having a tailored beam profile. The local seal may be used in conjunction with a continuous thin film encapsulation structure. Optical functions can be provided by each local seal, including refraction, filtering, color shifting, and scattering. | 2015-02-05 |
20150037917 | METHOD FOR MANUFACTURING LIGHT-EMITTING ELEMENT - In a system light-emitting device, a nitride semiconductor layer including a light-emitting layer is stacked on an optically transmissive substrate, and a reflective electrode including an Ag layer is stacked on the semiconductor layer. As annealing, a first annealing step that is a preceding step and a second annealing step that is a succeeding step are performed. In the first annealing step, the annealing is performed using inert gas of nitrogen gas as ambient gas. In the second annealing step, the annealing is performed using gas including oxygen gas as ambient gas. The two-stages of the annealing are performed, whereby occurrence of wrinkles on the Ag layer can be reduced, and surface roughness can be reduced. | 2015-02-05 |
20150037918 | METHODS OF FABRICATING LIGHT EMITTING DIODES BY MASKING AND WET CHEMICAL ETCHING - An LED includes a mesa having a Group III Nitride mesa face and a mesa sidewall, on an underlying LED structure. The mesa face includes Group III Nitride surface features having tops that are defined by mask features, having bottoms, and having sides that extend along crystal planes of the Group III Nitride. The mask features may include a two-dimensional array of dots that are spaced apart from one another. Related fabrication methods are also disclosed. | 2015-02-05 |
20150037919 | METHOD OF MANUFACTURING SEMICONDUCTOR LASER - A method of manufacturing a semiconductor laser according to an aspect of the present invention includes (a) sequentially epitaxially growing a first cladding layer, an active layer and a second cladding layer on a semiconductor substrate composed of InP or GaAs and having a plane index of (100), (b) forming a plurality of growth start surfaces having a plane index greater than (100) in an upper surface of the second cladding layer, and (c) epitaxially growing a third cladding layer containing zinc in the plurality of growth start surfaces of the second cladding layer. | 2015-02-05 |
20150037920 | CHEMICAL VAPOR DEPOSITION APPARATUS AND METHOD OF FORMING SEMICONDUCTOR EPITAXIAL THIN FILM USING THE SAME - A chemical vapor deposition apparatus includes: a reaction chamber including an inner tube having a predetermined volume of an inner space, and an outer tube tightly sealing the inner tube; a wafer holder disposed within the inner tube and on which a plurality of wafers are stacked at predetermined intervals; and a gas supply unit including at least one gas line supplying an external reaction gas to the reaction chamber, and a plurality of spray nozzles communicating with the gas line to spray the reaction gas to the wafers, whereby semiconductor epitaxial thin films are grown on the surfaces of the wafers, wherein the semiconductor epitaxial thin film grown on the surface of the wafer includes a light emitting structure in which a first-conductivity-type semiconductor layer, an active layer, and a second-conductivity-type semiconductor layer are sequentially formed. | 2015-02-05 |
20150037921 | METHOD FOR MANUFACTURING ACOUSTIC WAVE DEVICE - A method for manufacturing acoustic wave devices includes forming power supply lines along boundaries between chip regions on a main surface of a collective substrate on which interdigital transducer (IDT) electrodes and pad electrodes are formed; providing substantially frame-shaped first support members, each including a first opening in which one of the IDT electrodes is located and including first through-holes in a region in which the pad electrodes are formed; providing second support members outside the first support members; providing a lid member including second through-holes at positions overlapping the first through-holes on top surfaces of the first support members; and forming terminal electrodes in the first through-holes and the second through-holes by electroplating. The collective substrate, the first support members, the second support members, and the lid member form enclosed spaces in which the power supply lines are sealed. | 2015-02-05 |
20150037922 | TECHNIQUES FOR IMPROVED IMPRINTING OF SOFT MATERIAL ON SUBSTRATE USING STAMP INCLUDING UNDERFILLING TO LEAVE A GAP AND PULSING STAMP - A method for imparting a pattern to a flowable resist material on a substrate entails providing a resist layer so thin that during a stamp wedging process, the resist never completely fills the space between the substrate and the bottom surface of a stamp between wedge protrusions, leaving gap everywhere therebetween. A gap remains between the resist and the extended surface of the stamp. If the resist layer as deposited is somewhat thicker than the targeted amount, it will simply result in a smaller gap between resist and tool. The presence of a continuous gap assures that no pressure builds under the stamp. Thus, the force on the protrusions i determined only by the pressure above the stamp and is well controlled, resulting in well-controlled hole sizes. The gap prevents resist from being pumped entirely out of any one region, and thus prevents any regions from being uncovered of resist. The stamp can be pulsed in its contact with the substrate, repeatedly deforming the indenting protrusions. Several pulses clears away any scum layer better than does a single press, as measured by an etch test comparison of the degree to which a normal etch for a normal duration etches away substrate material. A method for imparting a pattern to a flowable resist material on a substrate entails providing a resist layer so thin that during a stamp wedging process, the resist never completely fills the space between the substrate and the bottom surface of a stamp between wedge protrusions, leaving a gap everywhere therebetween. A gap remains between the resist and the extended surface of the stamp. | 2015-02-05 |
20150037923 | METHODS TO SELECTIVELY TREAT PORTIONS OF A SURFACE USING A SELF-REGISTERING MASK - Processes increase light absorption into silicon wafers by selectively changing the reflective properties of the bottom portions of light trapping cavity features. Modification of light trapping features includes: deepening the bottom portion, increasing the curvature of the bottom portion, and roughening the bottom portion, all accomplished through etching. Modification may also be by the selective addition of material at the bottom of cavity features. Different types of features in the same wafers may be treated differently. Some may receive a treatment that improves light trapping while another is deliberately excluded from such treatment. Some may be deepened, some roughened, some both. No alignment is needed to achieve this selectively. The masking step achieves self-alignment to previously created light trapping features due to softening and deformation in place. | 2015-02-05 |
20150037924 | METHODS OF MANUFACTURING LIGHT TO CURRENT CONVERTER DEVICES - Processes for making light to current converter devices are provided. The processes can be used to make light to current converter devices having P-N junctions located on only the top surface of the cell, located on the top surface and symmetrically or asymmetrically along a portion of the inner surface of the via holes, located on the top surface and full inner surface of the via holes, or located on the top surface, full inner surface of the via holes, and a portion of the bottom surface of the cell. The processes may isolate the desired P-N junction by etching the emitter, forming a via hole after forming the emitter, using a barrier layer to protect portions of the emitter from etching, or using a barrier layer to prevent the emitter from being formed on portions of the substrate. | 2015-02-05 |
20150037925 | METHOD OF FABRICATING A SUPERLATTICE STRUCTURE - A method of fabricating a superlattice structure requires that atoms of a first III-V semiconductor compound be introduced into a vacuum chamber such that the atoms are deposited uniformly on a substrate. Atoms of at least one additional III-V compound are also introduced such that the atoms of the two III-V compounds form a repeating superlattice structure of alternating thin layers. Atoms of a surfactant are also introduced into the vacuum chamber while the III-V semiconductor compounds are being introduced, or immediately thereafter, such that the surfactant atoms act to improve the quality of the resulting SL structure. The surfactant is preferably bismuth, and the III-V semiconductor compounds are preferably GaSb along with either InAs or InAsSb; atoms of each material are preferably introduced using molecular beam epitaxy. The resulting superlattice structure is suitably used to form at least a portion of an IR photodetector. | 2015-02-05 |
20150037926 | Apparatus and Methods for Continuous Flow Synthesis of Semiconductor Nanowires - Apparatuses and methods for synthesizing nanoscale materials are provided, including semiconductor nanowires. Precursor solutions include mixed reagent precursor solutions of metal and chalcogenide precursors and a catalyst, where such solutions are liquid at room temperature. The precursor solutions are mixed by dividing a solution flow into multiple paths and converging the paths to form a uniform solution. A thermally controlled reactor receives the uniform solution to form semiconductor nanowires. Various electronic, optical, and sensory devices may employ the semiconductor nanowires described herein, for example. | 2015-02-05 |
20150037927 | METHOD FOR PRODUCING THE PENTANARY COMPOUND SEMICONDUCTOR CZTSSE DOPED WITH SODIUM - A method for producing a layered stack for manufacturing a thin film solar cell having a compound semiconductor of the type Cu | 2015-02-05 |
20150037928 | VAPOR DEPOSITION MASK, METHOD FOR PRODUCING VAPOR DEPOSITION MASK DEVICE AND METHOD FOR PRODUCING ORGANIC SEMICONDUCTOR ELEMENT - A method for producing a vapor deposition mask capable of satisfying both enhancement in definition and reduction in weight even when a size is increased, a method for producing a vapor deposition mask device capable of aligning the vapor deposition mask to a frame with high precision, and a method for producing an organic semiconductor element capable of producing an organic semiconductor element with high definition are provided. A metal mask provided with a slit, and a resin mask that is positioned on a front surface of the metal mask and has openings corresponding to a pattern to be produced by vapor deposition arranged by lengthwise and crosswise in a plurality of rows, are stacked. | 2015-02-05 |
20150037929 | APPARATUS AND METHOD FOR TREATING A SUBSTRATE - Provided are a substrate treating apparatus and method of manufacturing a phase-change layer having superior deposition characteristics. The substrate treating method of manufacturing a phase-change memory includes forming a bottom electrode on a substrate on which a pattern is formed, performing surface treating for removing impurities generated or remaining on a surface of the substrate while the bottom electrode is formed, performing nitriding on the surface of the substrate from which the impurities are removed, and successively depositing a phase-change layer and a top electrode on the bottom electrode. The substrate treating apparatus for manufacturing a phase-change memory includes a load lock chamber into/from which a plurality of substrates are loaded or unloaded, the load lock chamber being converted between an atmosphere state and a vacuum state, a nitriding chamber in which nitriding is performed on a surface of a substrate on which a bottom electrode is disposed, the nitriding chamber being coupled to one side of a plurality of sides of the vacuum transfer chamber, and a process chamber in which a phase-change layer is deposited on the surface of the substrate on which nitriding is performed in the nitriding process chamber, the process chamber being coupled to one of the plurality of sides of the vacuum transfer chamber. | 2015-02-05 |
20150037930 | METHOD OF MANUFACTURING A SEMICONDUCTOR HETEROEPITAXY STRUCTURE - A method of manufacturing a semiconductor structure includes the steps of depositing a layer of semiconductor oxide on a base semiconductor layer, scavenging oxygen from the layer of semiconductor oxide and recrystallizing the oxygen scavenged layer of semiconductor oxide as a semiconductor heteroepitaxy layer. | 2015-02-05 |
20150037931 | METHOD OF MANUFACTURING SEMICONDUCTOR DEVICE - A method of manufacturing a semiconductor device includes forming a stack of films including a conductive film layer above a semiconductor substrate; patterning the stack of films by dry etching; and cleaning including generation of plasma in an ambient including BCl | 2015-02-05 |
20150037932 | SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD THEREOF - A semiconductor device which includes an oxide semiconductor and has favorable electrical characteristics is provided. In the semiconductor device, an oxide semiconductor film and an insulating film are formed over a substrate. Side surfaces of the oxide semiconductor film are in contact with the insulating film. The oxide semiconductor film includes a channel formation region and regions containing a dopant between which the channel formation region is sandwiched. A gate insulating film is formed on and in contact with the oxide semiconductor film. A gate electrode with sidewall insulating films is formed over the gate insulating film. A source electrode and a drain electrode are formed in contact with the oxide semiconductor film and the insulating film. | 2015-02-05 |
20150037933 | SEMICONDUCTOR DEVICE AND METHOD FOR MANUFACTURING THE SAME - It is an object to provide a highly reliable semiconductor device including a thin film transistor whose electric characteristics are stable. In addition, it is another object to manufacture a highly reliable semiconductor device at low cost with high productivity. In a semiconductor device including a thin film transistor, a semiconductor layer of the thin film transistor is formed with an oxide semiconductor layer to which a metal element is added. As the metal element, at least one of metal elements of iron, nickel, cobalt, copper, gold, manganese, molybdenum, tungsten, niobium, and tantalum is used. In addition, the oxide semiconductor layer contains indium, gallium, and zinc. | 2015-02-05 |
20150037934 | SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD THEREOF - The semiconductor device includes a gate electrode over a substrate, a gate insulating layer over the gate electrode, an oxide semiconductor layer over the gate insulating layer, and a source electrode and a drain electrode over the oxide semiconductor layer. A length of part of an outer edge of the oxide semiconductor layer from an outer edge of the source electrode to an outer edge of the drain electrode is more than three times, preferably more than five times as long as a channel length of the semiconductor device. Further, oxygen is supplied from the gate insulating layer to the oxide semiconductor layer by heat treatment. In addition, an insulating layer is formed after the oxide semiconductor layer is selectively etched. | 2015-02-05 |
20150037935 | ARRAY SUBSTRATE FOR LIQUID CRYSTAL DISPLAY AND METHOD FOR MANUFACTURING THE SAME - An array substrate for a liquid crystal display includes a substrate and first and second subpixels which are positioned on the substrate and are defined by a crossing structure of one gate line, a first data line, a second data line, a first common line, and a second common line. The first subpixel includes a first semiconductor layer, a first source electrode, a first drain electrode, and a first pixel electrode connected to the first drain electrode. The second subpixel includes a second semiconductor layer, a second source electrode, a second drain electrode, and a second pixel electrode connected to the second drain electrode. The first and second subpixels share the one gate line with each other, and the first drain electrode and the second drain electrode are exposed through one contact hole. | 2015-02-05 |
20150037936 | Strength of Micro-Bump Joints - A device includes a work piece including a metal bump; and a dielectric layer having a portion directly over the metal bump. The metal bump and a surface of the portion of the dielectric layer form an interface. A metal finish is formed over and contacting the metal bump. The metal finish extends from over the dielectric layer to below the interface. | 2015-02-05 |
20150037937 | SEMICONDUCTOR DEVICES INCLUDING ELECTROMAGNETIC INTERFERENCE SHIELD - Provided are a semiconductor device including an EMI shield, a method of manufacturing the same, a semiconductor module including the semiconductor device, and an electronic system including the semiconductor device. The semiconductor device includes a lower semiconductor package, an upper semiconductor package, a package bump, and an EMI shield. The lower semiconductor package includes a lower substrate, a lower semiconductor chip mounted on the lower substrate, and a ground wire separated from the lower semiconductor chip. The upper semiconductor package includes an upper substrate stacked on the lower semiconductor package, and an upper semiconductor chip stacked on the upper substrate. The package bump electrically connects the upper semiconductor package and the lower semiconductor package. The EMI shield covers the upper and lower semiconductor packages and is electrically connected to the ground wire. | 2015-02-05 |
20150037938 | PACKAGING A SEMICONDUCTOR DEVICE HAVING WIRES WITH POLYMERIZED INSULATOR SKIN - A chip is attached to a substrate with wires spanning from the chip to the substrate is loaded in a heated cavity of a mold. The wire surfaces are coated with an adsorbed layer of molecules of a heterocyclic compound. A pressure chamber of the mold is loaded with a solid pellet of a packaging material including a polymerizable resin. The chamber is connected to the cavity. The vapor of resin molecules is allowed to spread from the chamber to the assembly inside the cavity during the time interval needed to heat the solid pellet for rendering it semi-liquid and to pressurize it through runners before filling the mold cavity, wherein the resin molecules arriving in the cavity are cross-linked by the adsorbed heterocyclic compound molecules into an electrically insulating at least one monolayer of polymeric structures on the wire surfaces. | 2015-02-05 |
20150037939 | RARE-EARTH OXIDE ISOLATED SEMICONDUCTOR FIN - A dielectric template layer is deposited on a substrate. Line trenches are formed within the dielectric template layer by an anisotropic etch that employs a patterned mask layer. The patterned mask layer can be a patterned photoresist layer, or a patterned hard mask layer that is formed by other image transfer methods. A lower portion of each line trench is filled with an epitaxial rare-earth oxide material by a selective rare-earth oxide epitaxy process. An upper portion of each line trench is filled with an epitaxial semiconductor material by a selective semiconductor epitaxy process. The dielectric template layer is recessed to form a dielectric material layer that provides lateral electrical isolation among fin structures, each of which includes a stack of a rare-earth oxide fin portion and a semiconductor fin portion. | 2015-02-05 |
20150037940 | LIQUID CRYSTAL DISPLAY PANEL AND METHOD OF MANUFACTURING THE SAME - In one embodiment, a liquid crystal display panel includes an array substrate and a counter substrate each having a display region and a peripheral region arranged adjacent to the display region. A resin layer is formed either one of the array substrate and the counter substrate. A protrusion in the shape of a wall is arranged on the resin layer with a gap between the protrusion and the substrate opposing the protrusion. A seal material is formed between the array substrate and the counter substrate, and arranged between a peripheral portion of the display region and the protrusion for attaching the array substrate and the counter substrate. A liquid crystal layer is formed in a surrounded region by the array substrate, the counter substrate and the seal material. | 2015-02-05 |
20150037941 | FINFET CONTACTING A CONDUCTIVE STRAP STRUCTURE OF A DRAM - A conductive strap structure in lateral contact with a top semiconductor layer is formed on an inner electrode of a deep trench capacitor. A cavity overlying the conductive strap structure is filled with a dielectric material to form a dielectric capacitor cap having a top surface that is coplanar with a topmost surface of an upper pad layer. A portion of the upper pad layer is removed to define a line cavity. A fin-defining spacer comprising a material different from the material of the dielectric capacitor cap and the upper pad layer is formed around the line cavity by deposition of a conformal layer and an anisotropic etch. The upper pad layer is removed, and the fin-defining spacer is employed as an etch mask to form a semiconductor fin that laterally contacts the conductive strap structure. An access finFET is formed employing two parallel portions of the semiconductor fin. | 2015-02-05 |
20150037942 | METHODS OF FORMING MEMORY CELLS, MEMORY CELLS, AND SEMICONDUCTOR DEVICES - A memory device and method of making the memory device. Memory device may include a storage transistor at a surface of a substrate. The storage transistor comprises a body portion between first and second source/drain regions, wherein the source/drain regions are regions of a first conductivity type. The storage transistor also comprises a gate structure that wraps at least partially around the body portion in at least two spatial planes. A bit line is connected to the first source/drain region and a word line is connected to the gate structure. | 2015-02-05 |
20150037943 | METHOD OF FABRICATING DISPLAY DEVICE - A method of fabricating a display device includes forming a thin-film transistor including a gate electrode, a source electrode and a drain electrode on a substrate, forming a first insulating layer and a second insulating layer on the thin-film transistor, forming a common electrode on the second insulating layer by depositing a common electrode material on the second insulating layer, plasma-treating a photoresist pattern on the common electrode material, and etching the common electrode material using the plasma-treated photoresist pattern as a mask, defining a contact hole in the second insulating layer which corresponds to the drain electrode using the plasma-treated photoresist pattern and the common electrode as a mask, forming a third insulating layer on the second insulating layer and the common electrode to expose the contact hole and the drain electrode and forming a pixel electrode connected to the drain electrode on the third insulating layer. | 2015-02-05 |
20150037944 | SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD THEREOF - An object is to reduce a capacitance value of parasitic capacitance without decreasing driving capability of a transistor in a semiconductor device such as an active matrix display device. Further, another object is to provide a semiconductor device in which the capacitance value of the parasitic capacitance was reduced, at low cost. An insulating layer other than a gate insulating layer is provided between a wiring which is formed of the same material layer as a gate electrode of the transistor and a wiring which is formed of the same material layer as a source electrode or a drain electrode. | 2015-02-05 |
20150037945 | EPITAXIALLY FORMING A SET OF FINS IN A SEMICONDUCTOR DEVICE - Approaches for enabling epitaxial growth of silicon fins in a device (e.g., a fin field effect transistor device (FinFET)) are provided. Specifically, approaches are provided for forming a set of silicon fins for a FinFET device, the FinFET device comprising: a set of gate structures formed over a substrate, each of the set of gate structures including a capping layer and a set of spacers; an oxide fill formed over the set of gate structures; a set of openings formed in the device by removing the capping layer and the set of spacers from one or more of the set of gate structures; a silicon material epitaxially grown within the set of openings in the device and then planarized; and wherein the oxide fill is etched to expose the silicon material and form the set of fins. | 2015-02-05 |
20150037946 | SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD THEREOF - A method of manufacturing a semiconductor device is provided. The method includes providing a fin protruding upwardly from or through a surface of a substrate, forming a to-be-sacrificed dummy gate enwrapping a first portion of the fin, forming a first insulating material layer so as to at least cover an exposed second portion of the fin, and selectively removing the dummy gate to thereby expose the first portion of the first semiconductor layer portion that was enwrapped by the dummy gate. The method further includes introducing, into the exposed portion of the first semiconductor layer portion, one or more dopants including a conductivity type reversing dopant, so as to form a channel region having a first conductivity type and at least two opposed channel control regions having a second conductivity type, wherein the channel control regions further comprise a portion formed above and adjoining a top of the channel region. | 2015-02-05 |
20150037947 | WRAP-AROUND FIN FOR CONTACTING A CAPACITOR STRAP OF A DRAM - A conductive strap structure in lateral contact with a top semiconductor layer is formed on an inner electrode of a deep trench capacitor. A cavity overlying the conductive strap structure is filled a dielectric material to form a dielectric capacitor cap having a top surface that is coplanar with a topmost surface of an upper pad layer. A semiconductor mandrel in lateral contact with the dielectric capacitor cap is formed. The combination of the dielectric capacitor cap and the semiconductor mandrel is employed as a protruding structure around which a fin-defining spacer is formed. The semiconductor mandrel is removed, and the fin-defining spacer is employed as an etch mask in an etch process that etches a lower pad layer and the top semiconductor layer to form a semiconductor fin that laterally wraps around the conductive strap structure. An access finFET is formed employing two parallel portions of the semiconductor fin. | 2015-02-05 |
20150037948 | METHODS FOR FABRICATING INTEGRATED CIRCUITS WITH A HIGH-VOLTAGE MOSFET - Methods for fabricating integrated circuits are disclosed. In an exemplary embodiment, a method for fabricating an integrated circuit includes forming a silicon material layer over a semiconductor substrate. The method further includes forming a capping layer over the silicon material layer and over the memory gate stack, removing the capping layer from over the memory array region and the high-voltage MOSFET region, forming a second silicon material layer over the capping layer and over the first silicon material layer, and removing the second silicon material layer. The method further includes removing the capping layer from over the first silicon material layer in the logic device region and removing the first and second silicon material layers from the high-voltage MOSFET region. Still further, the method includes forming a photoresist material layer over the memory array region and the logic device region and exposing the semiconductor substrate to an ion implantation process. | 2015-02-05 |
20150037949 | METHODS OF FORMING SEMICONDUCTOR MEMORY DEVICES - Methods of fabricating a semiconductor device are provided. The method includes alternately stacking first material layers and second material layers on a substrate to form a stacked structure, forming a through hole penetrating the stacked structure, forming a data storage layer on a sidewall of the through hole, forming a semiconductor pattern electrically connected to the substrate on an inner sidewall of the data storage layer, etching an upper portion of the data storage layer to form a first recessed region exposing an outer sidewall of the semiconductor pattern, and forming a first conductive layer in the first recessed region. Related devices are also disclosed. | 2015-02-05 |
20150037950 | COMPACT THREE DIMENSIONAL VERTICAL NAND AND METHOD OF MAKING THEREOF - A NAND device has at least a 3×3 array of vertical NAND strings in which the control gate electrodes are continuous in the array and do not have an air gap or a dielectric filled trench in the array. The NAND device is formed by first forming a lower select gate level having separated lower select gates, then forming plural memory device levels containing a plurality of NAND string portions, and then forming an upper select gate level over the memory device levels having separated upper select gates. | 2015-02-05 |
20150037951 | Three-Dimensional Semiconductor Devices and Methods of Fabricating the Same - Three-dimensional semiconductor devices are provided. The three-dimensional semiconductor device includes a substrate, a buffer layer on the substrate. The buffer layer includes a material having an etching selectivity relative to that of the substrate. A multi-layer stack including alternating insulation patterns and conductive patterns is provided on the buffer layer opposite the substrate. One or more active patterns respectively extend through the alternating insulation patterns and conductive patterns of the multi-layer stack and into the buffer layer. Related fabrication methods are also discussed. | 2015-02-05 |
20150037952 | RECESSED CHANNEL INSULATED-GATE FIELD EFFECT TRANSISTOR WITH SELF-ALIGNED GATE AND INCREASED CHANNEL LENGTH - A metal-oxide-semiconductor transistor (MOS) and method of fabricating the same, in which the effective channel length is increased relative to the width of the gate electrode. A dummy gate electrode overlying dummy gate dielectric material is formed at the surface of the structure, with self-aligned source/drain regions, and dielectric spacers on the sidewalls of the dummy gate structure. The dummy gate dielectric underlies the sidewall spacers. Following removal of the dummy gate electrode and the underlying dummy gate dielectric material, including from under the spacers, a silicon etch is performed to form a recess in the underlying substrate. This etch is self-limiting on the undercut sides, due to the crystal orientation, relative to the etch of the bottom of the recess. The gate dielectric and gate electrode material are then deposited into the remaining void, for example to form a high-k metal gate MOS transistor. | 2015-02-05 |
20150037953 | METHOD FOR FABRICATING TRENCH TYPE TRANSISTOR - An epitaxial layer is formed on the semiconductor substrate. A nitride doping region is then formed at a surface of the epitaxial layer. A hard mask layer is formed on the epitaxial layer. The hard mask layer comprises at least an opening. Through the opening, agate trench is etched into the epitaxial layer. A gate is formed within the gate trench. The hard mask layer is removed such that the gate protrudes from the surface of the epitaxial layer. An ion well is formed within the epitaxial layer. A source doping region is formed within the ion well. An upper portion of the gate that protrudes from the surface of the epitaxial layer is selectively oxidized to thereby form an oxide capping layer. Using the oxide capping layer as an etching hard mask, the epitaxial layer is self-aligned etched to thereby form a contact hole. | 2015-02-05 |
20150037954 | SUPER-JUNCTION TRENCH MOSFETS WITH SHORT TERMINATIONS - A super-junction trench MOSFET with a short termination area is disclosed, wherein the short termination area comprising a charge balance region and a channel stop region formed near a top surface of an epitaxial layer with a trenched termination contact penetrating therethrough. | 2015-02-05 |
20150037955 | TRANSISTOR, METHOD OF MANUFACTURING THE TRANSISTOR, AND ELECTRONIC DEVICE INCLUDING THE TRANSISTOR - Example embodiments relate to a transistor, a method of manufacturing a transistor, and/or an electronic device including the transistor. In example embodiments, the transistor includes a first field effect transistor (FET) and a second FET connected in series to each other, wherein a first gate insulating film of the first FET and a second gate insulating film of the second FET have different leakage current characteristics or gate electric field characteristics. | 2015-02-05 |
20150037956 | MANUFACTURING METHOD OF A SEMICONDUCTOR DEVICE - Provided is a manufacturing method of a semiconductor device including providing a substrate including a first region and a second region, forming active fins in the first region and the second region, forming gate electrodes which intersect the active fins and have surfaces facing side surfaces of the active fins, forming an off-set zero (OZ) insulation layer covering the active fins, forming a first residual etch stop layer and a first hard mask pattern which cover the first region, injecting first impurities into the active fins of the second region, removing the first hard mask pattern and the first residual etch stop layer, forming second residual etch stop layer and a second hard mask pattern which cover the second region, injecting a second impurities into the active fins of the first region, and removing the second residual etch stop layer and the second hard mask pattern. | 2015-02-05 |
20150037957 | SEMICONDUCTOR DEVICES HAVING TENSILE AND/OR COMPRESSIVE STRESS AND METHODS OF MANUFACTURING - Semiconductor devices are provided which have a tensile and/or compressive strain applied thereto and methods of manufacturing. A method of forming a semiconductor structure includes forming sidewalls and spacers adjacent to a gate stack structure, and forming a recess in the gate stack structure. The method further includes epitaxially growing a straining material on a polysilicon layer of the gate stack structure, and in the recess in the gate stack structure. The straining material is Si:C and the gate stack structure is a PFET gate stack structure. The straining material is grown above and covering a top surface of the sidewalls and the spacers. | 2015-02-05 |
20150037958 | METHODS OF MAKING MULTI-STATE NON-VOLATILE MEMORY CELLS - A semiconductor device includes a region in a semiconductor substrate having a top surface with a first charge storage layer on the top surface. A first conductive line is on the first charge storage layer. A second charge storage layer is on the top surface. A second conductive line is on the second charge storage layer. A third charge storage layer is on the top surface. A third conductive line is on the third charge storage layer. A fourth charge storage layer has a first side adjoining a first sidewall of the first conductive line and a second side adjoining a first sidewall of the second conductive line. A fifth charge storage layer has a first side adjoining a second sidewall of the second conductive line and a second side adjoining a first sidewall of the third conductive line. Source and drain regions are formed in the substrate on either side of the semiconductor device. | 2015-02-05 |
20150037959 | Bipolar Multistate Nonvolatile Memory - Embodiments generally include a method of forming a nonvolatile memory device that contains a resistive switching memory element that has an improved device switching capacity by using multiple layers of variable resistance layers. In one embodiment, the resistive switching element comprises at least three layers of variable resistance materials to increase the number of logic states. Each variable resistance layer may have an associated high resistance state and an associated low resistance state. As the resistance of each variable resistance layer determines the digital data bit that is stored, the multiple variable resistance layers per memory element allows for additional data storage without the need to further increase the density of nonvolatile memory devices. Typically, resistive switching memory elements may be formed as part of a high-capacity nonvolatile memory integrated circuit, which can be used in various electronic devices, such as digital cameras, mobile telephones, handheld computers, and music players. | 2015-02-05 |
20150037960 | METHOD OF MANUFACTURING A CAPACITOR - A method of forming a device comprises forming a through via extending from a surface of a substrate into the substrate. The method also comprises forming a first insulating layer over the surface of the substrate. The method further comprises forming a first metallization layer in the first insulating layer, the first metallization layer electrically connecting the through via. The method additionally comprises forming a capacitor over the first metallization layer. The capacitor comprises a first capacitor dielectric layer over the first metallization layer and a second capacitor dielectric layer over the first capacitor dielectric layer. The method also comprises forming a second metallization layer over and electrically connecting the capacitor. | 2015-02-05 |
20150037961 | METHOD FOR FABRICATING SEMICONDUCTOR DEVICE - Provided is a method for fabricating a semiconductor device, including the following steps. A substrate having a plurality of pillars is provided, wherein a plurality of trenches are formed around each pillar. A doped region is formed in the substrate and below each pillar. The doped region below each trench is removed to form an opening such that the doped regions below the adjacent pillars are separated from each other. A shielding layer is formed in each opening. | 2015-02-05 |
20150037962 | LAMINATED WAFER PROCESSING METHOD - A method of processing a laminated wafer in which a first wafer is laminated on a second wafer, the method including: a laminated wafer forming step of forming the laminated wafer by laminating the first wafer on the second wafer; a modified layer forming step of forming a modified layer within the first wafer by positioning a focusing point of a laser beam within the first wafer and moving the first wafer in a horizontal direction relative to the focusing point while applying the laser beam, the modified layer forming step being performed before or after the laminated wafer forming step is performed; and a separating step of separating part of the first wafer from the laminated wafer with the modified layer as a boundary, the separating step being performed after the laminated wafer forming step and the modified layer forming step are performed. | 2015-02-05 |
20150037963 | SEMICONDUCTOR SUBSTRATE, SEMICONDUCTOR DEVICE, AND MANUFACTURING METHODS THEREOF - A method of manufacturing a semiconductor substrate includes forming a first semiconductor layer on a substrate, forming a metallic material layer on the first semiconductor layer, forming a first portion of a second semiconductor layer on the first semiconductor layer and the metallic material layer, removing the metallic material layer under the first portion of the second semiconductor layer by dipping the substrate in a solution, forming a second portion of the second semiconductor layer on the first portion of the second semiconductor layer, and forming a cavity in a portion of the first semiconductor layer located under where the metallic material layer was removed. | 2015-02-05 |
20150037964 | Method for Manufacturing a Marked Single-Crystalline Substrate and Semiconductor Device with Marking - A method for manufacturing a marked single-crystalline substrate comprises providing a single-crystalline substrate comprising a first material, the single-crystalline substrate having a surface area; forming a marking structure on the surface area of the single-crystalline substrate, wherein the marking structure comprises a first semiconductor material; and depositing a semiconductor layer on the marking structure and at least partially on the surface area of the single-crystalline substrate, wherein the semiconductor layer comprises the second semiconductor material, and wherein the marking structure is buried under the second semiconductor material. | 2015-02-05 |
20150037965 | Fabrication of III-Nitride Semiconductor Device and Related Structures - A method of fabricating a III-nitride power semiconductor device that includes growing a transition layer over a substrate using at least two distinct and different growth methods. | 2015-02-05 |
20150037966 | METHOD FOR PRODUCING A PATTERN IN AN INTEGRATED CIRCUIT AND CORRESPONDING INTEGRATED CIRCUIT - At least one projecting block is formed in an element. The projecting block is then covered with a first cover layer so as to form a concave ridge self-aligned with the projecting block and having its concavity face towards the projecting block. A first trench is then formed in the ridge in a manner that is self-aligned with both the ridge and the projecting block. The first trench extends to a depth which reaches the projecting block. The projecting block is etched using the ridge and first trench as an etching mask to form a second trench in the projecting block that is self-aligned with the first trench. A pattern is thus produced by the second trench and unetched parts of the projecting block which delimit the second trench. | 2015-02-05 |
20150037967 | CONTROLLING IMPURITIES IN A WAFER FOR AN ELECTRONIC CIRCUIT - Methods of processing a silicon wafer for an electronic circuit, substrates for an electronic circuit, and device manufacturing methods are disclosed. According to an embodiment the method of processing a silicon wafer comprises impregnating the silicon wafer with impurities that form one or more deep energy levels within the band gap of silicon, wherein at least one of said deep energy levels is positioned at least 0.3 eV away from the conduction band if the level is a donor level or at least 0.3 eV away from the valence band if the level is an acceptor level, wherein: said impregnating step is performed in such a way that the ratio between the maximum concentration of said impurities in said silicon wafer and the average concentration of said impurities in said silicon wafer is less than 7:1. | 2015-02-05 |
20150037968 | METHOD FOR FORMING SHIELDED GATE OF MOSFET - A method for forming a shielded gate of a MOSFET includes steps as following: providing a semiconductor substrate having at least one trench, forming a bottom gate oxide region and a shielded gate poly region in the trench of the semiconductor substrate, forming an inter-poly oxide region on the shielded gate poly region through high temperature plasma deposition, poly etching back and oxide etching back; and forming a gate oxide region and a gate poly region on the inter-poly oxide region. By utilizing the etching back processes in replace of traditional chemical mechanical polishing processes, the manufacturing cost of manufacturing a shielded gate structure is reduced, and the total cost of manufacturing a FET is also reduced. Meanwhile, the gate charge is effectively reduced due to the shielded gate structure, so that the performance of a MOSFET is enhanced. | 2015-02-05 |
20150037969 | METHOD FOR MANUFACTURING SEMICONDUCTOR DEVICE - A method for manufacturing a semiconductor device including: preparing a semiconductor substrate with a gate oxide layer on the top thereof; depositing a polycrystalline silicon layer on the top of the semiconductor substrate; depositing a protection layer overlying the top of the polycrystalline silicon layer; etching the protection layer and the polycrystalline silicon layer to form a gate body block; forming an oxide layer overlying the gate body block and the semiconductor substrate; polishing the oxide layer through Chemical Mechanical Polishing (CMP) until the top of the gate body block; removing the protection layer on the top of the gate body block; and forming a metal silicide layer on the gate body block. | 2015-02-05 |
20150037970 | Silicon Film Forming Method, Thin Film Forming Method and Cross-Sectional Shape Control Method - The present disclosure provides a silicon film forming method for forming a silicon film on a workpiece having a processed surface, including: forming a seed layer by supplying a high-order aminosilane-based gas containing two or more silicon atoms in a molecular formula onto the processed surface and by having silicon adsorbed onto the processed surface; and forming a silicon film by supplying a silane-based gas not containing an amino group onto the seed layer and by depositing silicon onto the seed layer, wherein, when forming a seed layer, a process temperature is set within a range of 350 degrees C. or lower and a room temperature or higher. | 2015-02-05 |
20150037971 | CHIP CONNECTION STRUCTURE AND METHOD OF FORMING - Chip connection structures and related methods of forming such structures are disclosed. In one case, an interconnect structure is disclosed, the structure including: a pillar connecting an integrated circuit chip and a substrate, the pillar including a barrier layer, a first copper layer over the barrier layer, and a first solder layer over the first copper layer. | 2015-02-05 |
20150037972 | METHODS AND APPARATUSES FOR ATOMIC LAYER CLEANING OF CONTACTS AND VIAS - Described are cleaning methods for removing contaminants from an electrical contact interface of a partially fabricated semiconductor substrate. The methods may include introducing a halogen-containing species into a processing chamber, and forming an adsorption-limited layer, which includes halogen from the halogen-containing species, atop the electrical contact interface and/or the contaminants thereon. The methods may further include thereafter removing un-adsorbed halogen-containing species from the processing chamber and activating a reaction between the halogen of the adsorption-limited layer and the contaminants present on the electrical contact interface. The reaction may then result in the removal of at least a portion of the contaminants from the electrical contact interface. In some embodiments, the halogen adsorbed onto the surface and reacted may be fluorine. Also described herein are apparatuses having controllers for implementing such electrical contact interface cleaning techniques. | 2015-02-05 |
20150037973 | METHOD FOR CAPPING COPPER INTERCONNECT LINES - A method of forming a capping layer over copper containing contacts in a dielectric layer with a liner comprising a noble metal liner around the copper containing contacts is provided. An electroless deposition is provided to deposit a deposition comprising copper on the noble metal liner and the copper containing contacts. A capping layer is formed over the deposition comprising copper. | 2015-02-05 |
20150037974 | METHOD OF PATTERNING PLATINUM LAYER - A method of patterning a platinum layer includes the following steps. A substrate is provided. A platinum layer is formed on the substrate. An etching process is performed to pattern the platinum layer, wherein an etchant used in the etching process simultaneously includes at least a chloride-containing gas and at least a fluoride-containing gas. | 2015-02-05 |
20150037975 | METHOD AND APPARATUS FOR FORMING SILICON FILM - Provided is a method of forming a silicon film in a groove formed on a surface of an object to be processed, which includes: forming a first silicon layer on the surface of the object to be processed to embed the groove; doping impurities near a surface of the first silicon layer; forming a seed layer on the doped first silicon layer; and forming a second silicon layer containing impurities on the seed layer. | 2015-02-05 |
20150037976 | METHOD OF MAKING A STRUCTURE - A method of making a structure includes forming a first supporting member over a substrate, the first supporting member comprising a first material and having a first width defined along a reference plane. The method further includes forming a second supporting member over the substrate, the second supporting member having a second width defined along the reference plane, and the first supporting member and the second supporting member being separated by a gap region. The first width is at least 10 times the second width, and a gap width of the gap region being from 5 to 30 times the second width. | 2015-02-05 |
20150037977 | MASK AND PATTERN FORMING METHOD - According to one embodiment, a mask includes a line-and-space mask pattern. The mask has a separation portion separating a line pattern in a predetermined region within the line-and-space mask pattern. The mask also includes a connection pattern arranged in a crossing direction crossing the extending direction of the line pattern connecting the separated line patterns. The connection pattern is arranged on a position where the end of the line pattern, which is separated by the separation portion, projects from the connection pattern. | 2015-02-05 |
20150037978 | HARD MASK REMOVAL METHOD - A method of removing a hard mask is provided. Gate stacks are patterned on a substrate, where the gate stacks include a polysilicon layer and the hard mask deposited over the polysilicon layer. A dielectric layer is deposited on the substrate and on the patterned gate stacks. A first portion of the dielectric layer is planarized by chemical mechanical polishing (CMP) to remove a topography of the dielectric layer. The hard mask and a second portion of the dielectric layer are removed by the CMP. | 2015-02-05 |
20150037979 | CONFORMAL SIDEWALL PASSIVATION - A method for etching features into an etch layer in a stack disposed below a patterned mask with mask features is provided. Coating providing molecules are provided. The coating providing molecules are pyrolyzed, which only produces a first set of byproducts and a second set of byproducts, wherein the first set of byproducts have a sticking coefficient between 10 | 2015-02-05 |
20150037980 | SEMICONDUCTOR DEVICES INCLUDING A CAPPING LAYER AND METHODS OF FORMING SEMICONDUCTOR DEVICES INCLUDING A CAPPING LAYER - Methods of forming a semiconductor device are provided. A method of forming a semiconductor device may include forming a capping layer on a metal pattern and on an adjacent portion of an insulating layer, the capping layer comprising a first etch selectivity, with respect to the insulating layer, on the metal pattern and a second etch selectivity, with respect to the insulating layer, on the portion of the insulating layer. Moreover, the method may include forming a recess region adjacent the metal pattern by removing the capping layer from the portion of the insulating layer. At least a portion of the capping layer may remain on an uppermost surface of the metal pattern after removing the capping layer from the portion of the insulating layer. Related semiconductor devices are also provided. | 2015-02-05 |
20150037981 | FAST-GAS SWITCHING FOR ETCHING - A method for etching a layer in a plasma chamber with an inner injection zone gas feed and an outer injection zone gas feed is provided. The layer is placed in the plasma chamber. A pulsed etch gas is provided from the inner injection zone gas feed at a first frequency, wherein flow of pulsed etch gas from the inner injection zone gas feed is ramped down to zero. The pulsed etch gas is provided from the outer injection zone gas feed at the first frequency and simultaneous with and out of phase with the pulsed etch gas from the inner injection zone gas feed. The etch gas is formed into a plasma to etch the layer, simultaneous with the providing the pulsed etch gas from the inner injection zone gas feed and providing the pulsed gas from the outer interjection zone gas feed. | 2015-02-05 |
20150037982 | SEMICONDUCTOR DEVICE MANUFACTURING METHOD - In a semiconductor device manufacturing method, a target object including a multilayer film and a mask formed on the multilayer film is prepared in a processing chamber of a plasma processing apparatus. The multilayer film is formed by alternately stacking a silicon oxide film and a silicon nitride film. The multilayer film is etched by supplying a processing gas containing hydrogen gas, hydrogen bromide gas, nitrogen trifluoride gas and at least one of hydrocarbon gas, fluorohydrocarbon gas and fluorocarbon gas into the processing chamber of the plasma processing apparatus and generating a plasma of the processing gas in the processing chamber. | 2015-02-05 |
20150037983 | OPTICAL HEAT SOURCE WITH RESTRICTED WAVELENGTHS FOR PROCESS HEATING - A semiconductor manufacturing system or process, such as an ion implantation system, apparatus and method, including a component or step for heating a semiconductor workpiece are provided. An optical heat source emits light energy to heat the workpiece. The optical heat source is configured to provide minimal or reduced emission of non-visible wavelengths of light energy and emit light energy at a wavelength in a maximum energy light absorption range of the workpiece. | 2015-02-05 |
20150037984 | Laser Annealing Apparatus and Laser Annealing Method - A laser annealing apparatus includes: a laser beam generator for providing a stable single-pulse laser; a cyclic delay unit ( | 2015-02-05 |
20150037985 | LOW PROFILE ELECTRICAL CONNECTOR - An electrical connector for electrically connecting a package with a printed circuit board (PCB) with a plurality of pads and an alignment feature includes an insulating housing, a plurality of contacts received in the insulating housing and a stiffener insert molding with the insulating housing. When the stiffener is assembled upon the alignment feature correspondingly, the contacts align with the pads of the PCB correspondingly. | 2015-02-05 |
20150037986 | CABLE CONNECTOR ASSEMBLY - A cable connector assembly comprises: a first connector module comprising an insulative housing with a plurality of receiving rooms, a plurality of first connectors respectively received into the receiving rooms, a first PCB electrically connected to the plurality of first connectors and a metallic shell enclosing the insulative housing; and a second connector module comprising a second PCB formed therein; a flat wire electrically connecting to the first connector module and the second connector module. One end of the flat wire is electrically connected to the first PCB, and the other end of the flat wire is electrically connected to the second PCB. | 2015-02-05 |
20150037987 | CONTACT MEMBER BETWEEN A SUBSTRATE AND A DEVICE AND ELECTRICAL CONNECTOR COMPRISING SUCH A CONTACT MEMBER - A contact member establishes an electrical contact between a substrate and a first device. The contact member includes: a base extending substantially along a plane (P) and having a first surface that can be fixed on to the substrate, and a second surface ( | 2015-02-05 |
20150037988 | COVER-FITTED CONNECTOR - A cover-fitted connector includes a connector housing that houses a terminal connected to a terminal of an electric wire, and a cover that covers the electric wire pulled out from the connector housing. The connector housing includes a connector housing body, and a connecting portion connected to the connector housing body. The cover includes a cover body, a connected portion connected with the connecting portion at a time of mating the cover with the connector housing, and a cutout portion having an end portion positioned at a boundary between the connector housing body to cover the connecting portion and configured to expose the connector housing body outside the cover at the time of mating the cover with the connector housing. | 2015-02-05 |
20150037989 | ACCESS-RESTRICTED ELECTRICAL RECEPTACLE - An access-restricted electrical receptacle is configured to permit proper access to energized electrical contacts within the receptacle by a corresponding and properly-aligned plug, and to substantially limit or prevent improper access by foreign objects. The receptacle includes a receptacle body that defines a shutter cavity and a ramped slide surface, a face portion coupled to the receptacle body and defining a plurality of outlet openings to the shutter cavity, and a shutter that is movable in the shutter cavity between an unblocking position and at least one blocking position. The face portion defines a ramped return surface spaced from the ramped slide surface, and the shutter includes contact surfaces that engage the slide surface and the return surface during operation. Optionally, the ramped surfaces may be formed in either or both of a side wall or a base wall of the receptacle body and the face portion. | 2015-02-05 |
20150037990 | SLIDEABLE LOW PROFILE ELECTRICAL CONNECTOR - An electrical connector includes a base with a number of contacts, a cover pivotally mounted to the base, a pair of supporting components for mating with the cover and a pair of rail brackets for mating with the base. Each supporting component is pivotal between an opening status and a closed status relative to the base. The base is slidable relative to the rail brackets along a front-to-back direction. The cover and the pair of supporting components are mateable with each other in condition that one of the cover and the pair of supporting components pivots clockwise while a remaining one of the cover and the pair of supporting components pivots anticlockwise. | 2015-02-05 |
20150037991 | ELECTRIFIED RAIL, PARTICULARLY FOR POWERING METAL SHELVING UNITS, AND METHOD FOR ITS MANUFACTURING - An electrified rail, particularly for the electrification of metal shelving units provided on their front of electronic labels, displays and/or other peripherals, the rail being of the kind comprising a body ( | 2015-02-05 |