| 06th week of 2015 patent applcation highlights part 17 |
| Patent application number | Title | Published |
|---|
| 20150035031 | MAGNETIC RANDOM ACCESS MEMORY DEVICE AND METHOD OF MANUFACTURING THE SAME - In an MRAM device, the MRAM includes a magnetic tunnel junction (MTJ) structure and a protection layer on a sidewall of the MTJ structure. The protection layer includes a fluorinated metal oxide. When an MRAM device in accordance with example embodiments is manufactured, a metal layer may be formed to cover a MTJ structure. The metal layer may be oxidized and fluorinated to form the protection layer. A free layer pattern included in the MTJ structure may not be oxidized and the metal layer may be fully oxidized. Because the free layer pattern is not oxidized, the MTJ structure has a good TMR. Because the metal layer is fully oxidized, the MRAM device may be prevented from electrical short between the free layer pattern and a fixed layer pattern. | 2015-02-05 |
| 20150035032 | NONVOLATILE SEMICONDUCTOR MEMORY DEVICE INCLUDING MEMORY CELL ARRAY WITH PSEUDO SEPARATE SOURCE LINE STRUCTURE - A memory cell array of a nonvolatile semiconductor memory device is provided which includes a first memory cell including a first variable resistance element and a first access transistor connected to each other, and having a first node connected to a first bit line and one end of the first variable resistance element and a second node connected to a second bit line and one end of the first access transistor; and a second memory cell including a second variable resistance element and a second access transistor connected to each other, and having a first node connected to the second bit line and one end of the second variable resistance element and a second node connected to one end of the second access transistor, wherein the first and second access transistors are connected to first and second word lines, respectively. | 2015-02-05 |
| 20150035033 | LIGHT EMITTING DEVICE - A light emitting device is provided which can prevent a change in gate voltage due to leakage or other causes and at the same time can prevent the aperture ratio from lowering. A capacitor storage is formed from a connection wiring line, an insulating film, and a capacitance wiring line. The connection wiring line is formed over a gate electrode and an active layer of a TFT of a pixel, and is connected to the active layer. The insulating film is formed on the connection wiring line. The capacitance wiring line is formed on the insulating film. This structure enables the capacitor storage to overlap the TFT, thereby increasing the capacity of the capacitor storage while keeping the aperture ratio from lowering. Accordingly, a change in gate voltage due to leakage or other causes can be avoided to prevent a change in luminance of an OLED and flickering of screen in analog driving. | 2015-02-05 |
| 20150035034 | SPLIT GATE NON-VOLATILE MEMORY CELL - A method of making a semiconductor structure uses a substrate having a background doping of a first type. A gate structure has a gate dielectric on the substrate and a select gate layer on the gate dielectric. Implanting is performed into a first portion of the substrate adjacent to a first end with dopants of a second type. The implanting is prior to any dopants being implanted into the background doping of the first portion which becomes a first doped region of the second type. An NVM gate structure has a select gate, a storage layer having a first portion over the first doped region, and a control gate over the storage layer. Implanting at a non-vertical angle with dopants of the first type forms a deep doped region under the select gate. Implanting with dopants of the second type forms a source/drain extension. | 2015-02-05 |
| 20150035035 | NON-VOLATILE MEMORY DEVICE - According to one embodiment, a non-volatile memory device includes abase layer, a first stacked unit and a second stacked unit disposed above the base layer and arranged in parallel to each other and spaced apart from each other in a first direction, in a plane parallel to the base layer, a first semiconductor layer penetrating the first stacked unit, a second semiconductor layer penetrating in the second stacked unit, the first memory film disposed between the first semiconductor layer and the first stacked unit, and a connecting portion disposed between the base layer and the first stacked unit and between the base layer and the second stacked unit and electrically connecting the first semiconductor layer and the second semiconductor layer. An end portion of the first semiconductor layer is positioned between the connecting portion and the base layer. | 2015-02-05 |
| 20150035036 | NONVOLATILE SEMICONDUCTOR MEMORY DEVICE AND METHOD OF FABRICATING THE SAME - According to an aspect of the invention, a first insulating layer is buried in a first trench provided in at least one of an interstice between first and second semiconductor pillars, a side surface portion of the first semiconductor pillar opposed to the second semiconductor pillar, and a side surface portion of the second semiconductor pillar opposed to the first semiconductor pillar. A first trench penetrates each stack from an uppermost portion of the stack to a first conductive layer in a lowermost portion of the stack. The first trench is arranged away from a first connection portion. Each of the first conductive layers in contact with the first insulating layer includes a silicide layer. | 2015-02-05 |
| 20150035037 | SEMICONDUCTOR MEMORY DEVICE AND METHOD FOR MANUFACTURING SAME - According to one embodiment, the select transistor is provided between a memory array region and the layer selection portion. The channel body and the charge storage film are provided in the memory array region. The select transistor includes a gate electrode provided on a side wall of one of the line portions between the memory array region and the layer selection portion; and a gate insulator film provided between the gate electrode and the line portions. The gate electrode extends in the stacking direction. | 2015-02-05 |
| 20150035038 | SEMICONDUCTOR STRUCTURE AND METHOD FOR FORMING THE SAME - Various embodiments provide semiconductor structures and methods for forming the same. In an exemplary method, a semiconductor substrate is provided. A first stop layer, a first sacrificial layer, a second stop layer, and a second sacrificial layer are formed sequentially on the semiconductor substrate. The second sacrificial layer, the second stop layer, the first sacrificial layer, the first stop layer, and the semiconductor substrate are etched to form a groove, the groove then being filled to form an isolation structure. The second sacrificial layer is removed to expose sidewalls and a top of an exposed portion of the isolation structure. The second stop layer is removed, and the exposed portion of the isolation structure is etched to reduce a width of the top of the exposed portion of the isolation structure. The first sacrificial layer is removed. A floating gate is formed on the first stop layer. | 2015-02-05 |
| 20150035039 | LOGIC FINFET HIGH-K/CONDUCTIVE GATE EMBEDDED MULTIPLE TIME PROGRAMMABLE FLASH MEMORY - A method for fabricating a multiple time programmable (MTP) device includes forming fins of a first conducting type on a substrate of a second conducting type. The method further includes forming a floating gate dielectric to partially surround the fins. The method also includes forming a floating gate on the floating gate dielectric. The method also includes forming a coupling film on the floating gate and forming a coupling gate on the coupling film. | 2015-02-05 |
| 20150035040 | Split Gate Non-volatile Flash Memory Cell Having A Silicon-Metal Floating Gate And Method Of Making Same - A non-volatile memory cell includes a substrate of a first conductivity type with first and second spaced apart regions of a second conductivity type, forming a channel region therebetween. A select gate is insulated from and disposed over a first portion of the channel region which is adjacent to the first region. A floating gate is insulated from and disposed over a second portion of the channel region which is adjacent the second region. Metal material is formed in contact with the floating gate. A control gate is insulated from and disposed over the floating gate. An erase gate includes a first portion insulated from and disposed over the second region and is insulated from and disposed laterally adjacent to the floating gate, and a second portion insulated from and laterally adjacent to the control gate and partially extends over and vertically overlaps the floating gate. | 2015-02-05 |
| 20150035041 | NON-VOLATILE MEMORY DEVICE - According to one embodiment, a non-volatile memory device includes a first stacked electrode provided above a underlying layer, a second stacked electrode juxtaposed with the first stacked electrode above the underlying layer, a plurality of first semiconductor layers piercing the first stacked electrode in a direction perpendicular to the underlying layer, and a second semiconductor layer piercing the second stacked electrode in a direction perpendicular to the underlying layer. The device further includes a memory film provided between the first stacked electrode and the first semiconductor layers, and between the second stacked electrode and the second semiconductor layer, and a link part provided between the underlying layer and the first stacked electrode, and between the underlying layer and the second stacked electrode. The link part is electrically connected to one end of each of the first semiconductor layers and one end of the second semiconductor layer. | 2015-02-05 |
| 20150035042 | NONVOLATILE MEMORY DEVICE AND METHOD OF MANUFACTURING THE SAME - A nonvolatile memory device includes gate electrodes three dimensionally arranged on a semiconductor substrate, a semiconductor pattern extending from the semiconductor substrate and crossing sidewalls of the gate electrodes, a metal liner pattern formed between the semiconductor pattern and formed on a top surface and a bottom surface of each of the gate electrodes, and a charge storage layer formed between the semiconductor pattern and the metal liner pattern. | 2015-02-05 |
| 20150035043 | CHARGE TRAPPING DIELECTRIC STRUCTURES - A dielectric structure may be arranged having a thin nitrided surface of an insulator with a charge blocking insulator over the nitrided surface. The insulator may be formed of a number of different insulating materials such as a metal oxide, a metal oxycarbide, a semiconductor oxide, or oxycarbide. In an embodiment, the dielectric structure may be formed by nitridation of a surface of an insulator using ammonia and deposition of a blocking insulator having a larger band gap than the insulator. The dielectric structure may form part of a memory device, as well as other devices and systems. | 2015-02-05 |
| 20150035044 | Method to Improve Charge Trap Flash Memory Core Cell Performance and Reliability - A semiconductor processing method to provide a high quality bottom oxide layer and top oxide layer in a charged-trapping NAND and NOR flash memory. Both the bottom oxide layer and the top oxide layer of NAND and NOR flash memory determines array device performance and reliability. The method describes overcomes the corner thinning issue and the poor top oxide quality that results from the traditional oxidation approach of using pre-deposited silicon-rich nitride. | 2015-02-05 |
| 20150035045 | NONVOLATILE SEMICONDUCTOR MEMORY DEVICE AND METHOD OF MANUFACTURING THE SAME - A nonvolatile semiconductor memory device of an embodiment includes: a semiconductor layer; a tunnel insulating film that is formed on the semiconductor layer and includes a first organic molecular film including first organic molecules each having an alkyl molecular chain as the main chain; a charge storage layer formed on the tunnel insulating film, the charge storage layer being made of an inorganic material; a block insulating film formed on the charge storage layer; and a control gate electrode formed on the block insulating film. | 2015-02-05 |
| 20150035046 | SEMICONDUCTOR DEVICE INCLUDING FIELD EFFECT TRANSISTOR - A semiconductor device includes a fin portion protruding from a substrate. The fin portion includes a base part, an intermediate part on the base part, and a channel part on the intermediate part. A width of the intermediate part is less than a width of the base part and greater than a width of the channel part. A gate electrode coves both sidewalls and a top surface of the channel part, and a device isolation pattern covers both sidewalls of the base part and both sidewalls of the intermediate part. | 2015-02-05 |
| 20150035047 | Dual Trench Rectifier and Method for Forming the Same - A structure of dual trench rectifier comprises of the following elements. A plurality of trenches are formed parallel in an n− epitaxial layer on an n+ semiconductor substrate and spaced with each other by a mesa. A plurality of recesses are formed on the mesas. Each the trench has a trench oxide layer formed on the sidewalls and bottom thereof, and a first poly silicon layer is filled therein to form MOS structures. Each the recess has a recess oxide layer formed on the sidewalls and bottom thereof, and a second poly silicon layer is filled therein to form MOS structures. A plurality of p type bodies are formed at two sides of the MOS structures in recesses. A top metal is formed above the semiconductor substrate for serving as an anode. A bottom metal is formed beneath the semiconductor substrate for serving as a cathode. | 2015-02-05 |
| 20150035048 | A SUPPER JUNCTION STRUCTURE INCLUDES A THICKNESS OF FIRST AND SECOND SEMICONDUCTOR REGIONS GRADUALLY CHANGED FROM A TRANSISTOR AREA INTO A TERMINATION AREA - A super junction semiconductor device includes a super junction structure including first and second areas alternately arranged along a first lateral direction and extending in parallel along a second lateral direction. Each one of the first areas includes a first semiconductor region of a first conductivity type. Each one of the second areas includes, along the first lateral direction, an inner area between opposite second semiconductor regions of a second conductivity type opposite to the first conductivity type. A width w | 2015-02-05 |
| 20150035049 | Vertical Semiconductor MOSFET Device with Double Substrate-Side Multiple Electrode Connections and Encapsulation - A semiconductor device with substrate-side exposed device-side electrode (SEDE) is disclosed. The semiconductor device has semiconductor substrate (SCS) with device-side, substrate-side and semiconductor device region (SDR) at device-side. Device-side electrodes (DSE) are formed for device operation. A through substrate trench (TST) is extended through SCS, reaching a DSE turning it into an SEDE. The SEDE can be interconnected via conductive interconnector through TST. A substrate-side electrode (SSE) and a windowed substrate-side passivation (SSPV) atop SSE can be included. The SSPV defines an area of SSE for spreading solder material during device packaging. A device-side passivation (DSPV) beneath thus covering the device-side of SEDE can be included. A DSE can also include an extended support ledge, stacked below an SEDE, for structurally supporting it during post-wafer processing packaging. The projected footprint of extended support ledge onto the major SCS plane can essentially enclose the correspondingly projected footprint of SEDE. | 2015-02-05 |
| 20150035050 | SEMICONDUCTOR DEVICE WITH AIR GAP AND METHOD FOR FABRICATING THE SAME - A semiconductor device includes a plurality of first conductive structures formed over a substrate, second conductive structures each formed between neighboring first conductive structures of the first conductive structures, air gaps each formed between the second conductive structures and the neighboring first conductive structures thereof, third conductive structures each capping a portion of the air gaps, and capping structures each capping the other portion of the air gaps. | 2015-02-05 |
| 20150035051 | CONFIGURATIONS AND METHODS FOR MANUFACTURING CHARGED BALANCED DEVICES - This invention discloses a semiconductor power device disposed in a semiconductor substrate and the semiconductor substrate has a plurality of deep trenches. The deep trenches are filled with an epitaxial layer thus forming a top epitaxial layer covering areas above a top surface of the deep trenches covering over the semiconductor substrate. The semiconductor power device further includes a plurality of transistor cells disposed in the top epitaxial layer whereby a device performance of the semiconductor power device is dependent on a depth of the deep trenches and not dependent on a thickness of the top epitaxial layer. Each of the plurality of transistor cells includes a trench DMOS transistor cell having a trench gate opened through the top epitaxial layer and filled with a gate dielectric material. | 2015-02-05 |
| 20150035052 | CONTACT POWER RAIL - A method for forming CA power rails using a three mask decomposition process and the resulting device are provided. Embodiments include forming a horizontal diffusion CA power rail in an active layer of a semiconductor substrate using a first color mask; forming a plurality of vertical CAs in the active layer using second and third color masks, the vertical CAs connecting the CA power rail to at least one diffusion region on the semiconductor substrate, spaced from the CA power rail, wherein each pair of CAs formed by one of the second and third color masks are separated by at least two pitches. | 2015-02-05 |
| 20150035053 | DEVICE AND METHOD FOR A LDMOS DESIGN FOR A FINFET INTEGRATED CIRCUIT - Semiconductor devices and methods for manufacturing an LDMOS FinFET integrated circuit. The intermediate semiconductor device includes a substrate, a first well in the substrate, a second well in the substrate, and at least two polysilicon gates. The first well overlaps the second well and the at least one first gate is disposed over the first well and at least one second gate is disposed over the second well. The method includes forming a channel region and a drift region in the substrate, wherein the channel region overlaps the drift region, forming a shallow trench isolation region in the drift region, forming at least one first gate over the channel region, forming at least one second gate over the shallow trench isolation region, and applying at least one metal layer over the at least one first gate and the at least one second gate. | 2015-02-05 |
| 20150035054 | SEMICONDUCTOR DEVICE - A device includes a first transistor including a first gate electrode including first and second parallel electrode portions each extending in a first direction, and a first connecting electrode portion extending in a second direction approximately orthogonal to the first direction and connecting one ends of the first and second parallel electrode portions to each other, and first and second diffusion layers separated from each other by a channel region under the first gate electrode, a first output line connected to the first diffusion layer of the first transistor, and a second transistor comprising a second gate electrode extending in the second direction, and the second transistor being configured to use the second diffusion layer of the first transistor as one of two diffusion layers that are separated from each other by a channel region under the second gate electrode. | 2015-02-05 |
| 20150035055 | SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD THEREFOR - A method for manufacturing a semiconductor device includes providing a substrate, forming a pseudo-gate stack and sidewalls on the substrate, forming an S/D region on both sides of the pseudo-gate stack, and forming a stop layer and a first interlayer dielectric layer covering the entire semiconductor device; removing part of the stop layer to expose the pseudo-gate stack, and further removing the pseudo-gate stack to expose the channel region; etching the channel region to form a groove structure; forming a new channel region to flush with the upper surface of the substrate, wherein the new channel region includes a buffer layer, a Ge layer, and a Si cap layer; forming a gate stack. Accordingly, the present application also discloses a semiconductor device. The present application can effectively improve the carrier mobility and the performance of the semiconductor device by replacing Si with Ge to form a new channel region. | 2015-02-05 |
| 20150035056 | SEMICONDUCTOR DEVICE - A semiconductor device includes an N | 2015-02-05 |
| 20150035057 | SEMICONDUCTOR DEVICE INCLUDING METAL SILICIDE LAYER AND METHOD FOR MANUFACTURING THE SAME - A device formed from a method of fabricating a fine metal silicide layer having a uniform thickness regardless of substrate doping. A planar vacancy is created by the separation of an amorphousized surface layer of a silicon substrate from an insulating layer, a metal source enters the vacancy through a contact hole through the insulating later connecting with the vacancy, and a heat treatment converts the metal in the vacancy into metal silicide. The separation is induced by converting the amorphous silicon into crystalline silicon. | 2015-02-05 |
| 20150035058 | SILICON NITRIDE FILM, AND SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING THE SAME - An object of the present invention is to apply an insulating film of cure and high quality that is suitably applicable as gate insulating film and protective film to a technique that the insulating film is formed on the glass substrate under a temperature of strain point or lower, and to a semiconductor device realizing high efficiency and high reliability by using it. In a semiconductor device of the present invention, a gate insulating film of a field effect type transistor with channel length of from 0.35 to 2.5 μm in which a silicon nitride film is formed over a crystalline semiconductor film through a silicon oxide film, wherein the silicon nitride film contains hydrogen with the concentration of 1×10 | 2015-02-05 |
| 20150035059 | METHOD, STRUCTURE AND DESIGN STRUCTURE FOR CUSTOMIZING HISTORY EFFECTS OF SOI CIRCUITS - A design structure is embodied in a machine readable medium for designing, manufacturing, or testing a design. The design structure includes a high-leakage dielectric formed over an active region of a FET and a low-leakage dielectric formed on the active region and adjacent the high-leakage dielectric. The low-leakage dielectric has a lower leakage than the high-leakage dielectric. Also provided is a structure and method of fabricating the structure. | 2015-02-05 |
| 20150035060 | FIELD EFFECT TRANSISTOR (FET) WITH SELF-ALIGNED CONTACTS, INTEGRATED CIRCUIT (IC) CHIP AND METHOD OF MANUFACTURE - Field Effect Transistors (FETs), Integrated Circuit (IC) chips including the FETs, and a method of forming the FETs and IC. FET locations and adjacent source/drain regions are defined on a semiconductor wafer, e.g., a silicon on insulator (SOI) wafer. Source/drains are formed in source/drains regions. A stopping layer is formed on source/drains. Contact spacers are formed above gates. Source/drain contacts are formed to the stopping layer, e.g., after converting the stopping layer to silicide. The contact spacers separate source/drain contacts from each other. | 2015-02-05 |
| 20150035061 | Semiconductor Device and Method for Fabricating the Same - Provided are a multi-gate transistor device and a method for fabricating the same. The method for fabricating the multi-gate transistor device includes forming first and second fins shaped to protrude on a substrate and aligned and extending in a first direction and a trench separating the first and second fins from each other in the first direction between the first and second fins, performing ion implantation of impurities on sidewalls of the trench, forming a field dielectric film filling the trench, forming a recess in the first fin not exposing the field dielectric film, and growing an epitaxial layer in the recess. | 2015-02-05 |
| 20150035062 | INTEGRATED CIRCUITS HAVING FINFETS WITH IMPROVED DOPED CHANNEL REGIONS AND METHODS FOR FABRICATING SAME - Integrated circuits and methods for fabricating integrated circuits are provided. In an embodiment, a method for fabricating an integrated circuit includes forming a channel region of a fin structure with a first side, a second side, an exposed first end surface and an exposed second end surface. A gate is formed overlying the first side and second side of the channel region. The method includes implanting ions into the channel region through the exposed first end surface and the exposed second end surface. Further, the method includes forming source/drain regions of the fin structure adjacent the exposed first end surface and the exposed second end surface of the channel region. | 2015-02-05 |
| 20150035063 | REDUCED SPACER THICKNESS IN SEMICONDUCTOR DEVICE FABRICATION - In aspects of the present disclosure, a reliable encapsulation of a gate dielectric is provided at very early stages during fabrication. In other aspects, a semiconductor device is provided wherein a reliable encapsulation of a gate dielectric material is maintained, the reliable encapsulation being present at early stages during fabrication. In embodiments, a semiconductor device having a plurality of gate structures is provided over a surface of a semiconductor substrate. Sidewall spacers are formed over the surface and adjacent to each of the plurality of gate structures, wherein the sidewall spacers cover sidewall surfaces of each of the plurality of gate structures. After performing an implantation sequence into the sidewall spacers using adjacent gate structures as implantations masks, shadowing lower portions of the sidewall spacers, an etching process is performed for removing implanted portions from the sidewall spacers, leaving lower shadowed portions of the sidewall spacer as shaped sidewall spacers. | 2015-02-05 |
| 20150035064 | INVERSE SIDE-WALL IMAGE TRANSFER - Methods forming structures on a chip. The methods include etching a mandrel layer that is disposed over a bottom layer to be patterned to form gaps between plateaus of mandrel material; forming spacers on sidewalls of the plateaus; forming a hardmask material in gaps between the spacers; removing the spacers to define a pattern around the hardmask material; and etching the bottom layer according to the pattern around the hardmask material. | 2015-02-05 |
| 20150035065 | SEMICONDUCTOR DEVICE AND METHOD FOR FABRICATING THE SAME - A semiconductor device includes a substrate with an active region defined by a device isolation layer. A word line extends over the active region in a first direction, and a plurality of interconnections extends over the word line in a second direction perpendicular to the first direction. A contact pad is disposed between and spaced apart from the word line and the plurality of interconnections, extending in the first direction to overlap the plurality of interconnections and the active region when viewed from a plan view. A lower contact plug electrically connects the contact pad to the active region. An upper contact plug electrically connects the contact pad to one of the plurality of interconnections. | 2015-02-05 |
| 20150035066 | FET CHIP - An FET chip is configured to include an oscillation suppression circuit that has a gate capacitance C formed between a gate electrode 5 | 2015-02-05 |
| 20150035067 | LOW RDSON DEVICE AND METHOD OF MANUFACTURING THE SAME - A device and method of making thereof are disclosed. The device includes a substrate having a device region for a switch transistor. The device includes a switch transistor having a gate disposed on the substrate in the device region and first and second heavily doped regions disposed adjacent to the gate. The first heavily doped region serves as a source region of the switch transistor and the second heavily doped region serves as a drain region of the switch transistor. The drain region includes a lightly doped diffusion (LDD) region adjacent thereto and the source region is devoid of a LDD region. | 2015-02-05 |
| 20150035068 | AIRGAP STRUCTURE AND METHOD OF MANUFACTURING THEREOF - A process for fabricating a gate structure, the gate structure having a plurality of gates defined by a network of spaces. The word line (WL) spaces within a dense WL region having airgaps and those spaces outside of the dense WL being substantially free of airgaps. A gate structure having a silicide layer dispose across the plurality of gates is also provided. | 2015-02-05 |
| 20150035069 | FINFET AND METHOD FOR FABRICATING THE SAME - A method for fabricating fin-shaped field-effect transistor (FinFET) is disclosed. The method includes the steps of: providing a substrate; forming a fin-shaped structure in the substrate; forming a shallow trench isolation (STI) on the substrate and around the bottom portion of the fin-shaped structure; forming a first gate structure on the STI and the fin-shaped structure; and removing a portion of the STI for exposing the sidewalls of the STI underneath the first gate structure. | 2015-02-05 |
| 20150035070 | METHOD AND LAYOUT OF AN INTEGRATED CIRCUIT - An integrated circuit layout includes a first active region, a second active region, a first PODE (poly on OD edge), a second PODE, a first transistor and a second transistor. The first transistor, on the first active region, includes a gate electrode, a source region and a drain region. The second transistor, on the second active region, includes a gate electrode, a source region and a drain region. The first active region and the second active region are adjacent and electrically disconnected with each other. The first PODE and the second PODE are on respective adjacent edges of the first active region and the second active region. The source regions of the first and second transistor are adjacent with the first PODE and the second PODE respectively. The first PODE and the second PODE are sandwiched between source regions of the first transistor and the second transistor. | 2015-02-05 |
| 20150035071 | Semiconductor Device and Fabricating the Same - The present disclosure provides a method for fabricating an integrated circuit device. The method includes providing a precursor including a substrate having first and second metal-oxide-semiconductor (MOS) regions. The first and second MOS regions include first and second gate regions, semiconductor layer stacks, and source/drain regions respectively. The method further includes laterally exposing and oxidizing the semiconductor layer stack in the first gate region to form first outer oxide layer and inner nanowire set, and exposing the first inner nanowire set. A first high-k/metal gate (HK/MG) stack wraps around the first inner nanowire set. The method further includes laterally exposing and oxidizing the semiconductor layer stack in the second gate region to form second outer oxide layer and inner nanowire set, and exposing the second inner nanowire set. A second HK/MG stack wraps around the second inner nanowire set. | 2015-02-05 |
| 20150035072 | METHODS AND APPARATUSES FOR FORMING MULTIPLE RADIO FREQUENCY (RF) COMPONENTS ASSOCIATED WITH DIFFERENT RF BANDS ON A CHIP - A method includes forming a first gate oxide in a first region and in a second region of a wafer. The method further includes performing first processing to form a second gate oxide in the second region. The second gate oxide has a different thickness than the first gate oxide. The method also includes forming first gate material of a first device in the first region and forming second gate material of a second device in the second region. The first device corresponds to a first radio frequency (RF) band and the second device corresponds to a second RF band that is different from the first RF band. | 2015-02-05 |
| 20150035073 | ENABLING ENHANCED RELIABILITY AND MOBILITY FOR REPLACEMENT GATE PLANAR AND FINFET STRUCTURES - A method for semiconductor fabrication includes forming at least one of a diffusion barrier layer and a metal containing layer over a dielectric layer in a gate cavity. A first anneal is performed to diffuse elements from the at least one of the diffusion barrier layer and the metal containing layer into the dielectric layer. The metal containing layer and the diffusion barrier layer are removed. A second anneal is performed to adjust diffusion of the elements in the dielectric layer to provide a gate dielectric region. | 2015-02-05 |
| 20150035074 | FINFET DEVICES INCLUDING RECESSED SOURCE/DRAIN REGIONS HAVING OPTIMIZED DEPTHS AND METHODS OF FORMING THE SAME - A finFET device can include a source/drain contact recess having an optimal depth beyond which an incremental decrease in a spreading resistance value for a horizontal portion of a source/drain contact in the recess provided by increased depth may be less than an incremental increase in total resistance due to the increase in the vertical portion of the source/drain contact at the increased depth. | 2015-02-05 |
| 20150035075 | GATE STRAIN INDUCED WORK FUNCTION ENGINEERING - A stack of a gate dielectric layer and a workfunction material layer are deposited over a plurality of semiconductor material portions, which can be a plurality of semiconductor fins or a plurality of active regions in a semiconductor substrate. A first gate conductor material applying a first stress is formed on a first portion of the workfunction material layer located on a first semiconductor material portion, and a second gate conductor material applying a second stress is formed on a second portion of the workfunction material layer located on a second semiconductor material portion. The first and second stresses are different in at least one of polarity and magnitude, thereby inducing different strains in the first and second portions of the workfunction material layer. The different strains cause the workfunction shift differently in the first and second portions of the workfunction material layer, thereby providing devices having multiple different workfunctions. | 2015-02-05 |
| 20150035076 | Self-Aligned Gate Electrode Diffusion Barriers - A structure that provides a diffusion barrier between two doped regions. The structure includes a diffusion barrier including a semiconductor layer comprising a first doped region and a second doped region; and a diffusion barrier separating the first doped region and the second doped region, wherein the diffusion barrier comprises a doped portion and a notch above the doped portion. | 2015-02-05 |
| 20150035077 | MOS TRANSISTORS INCLUDING A RECESSED METAL PATTERN IN A TRENCH - Methods of manufacturing a MOS transistor are provided. The methods may include forming first and second trenches. The methods may further include forming first metal patterns within portions of the first and second trenches. The methods may additionally include removing the first metal patterns from the second trench while at least portions of the first metal patterns remain within the first trench. The methods may also include forming a second metal layer within the first and second trenches, the second metal layer formed on the first metal patterns within the first trench. | 2015-02-05 |
| 20150035078 | METAL GATE TRANSISTOR AND INTEGRATED CIRCUITS - A transistor includes a gate dielectric structure over a substrate and a work function metallic layer over the gate dielectric structure. The work function metallic layer is configured to adjust a work function value of a gate electrode of the transistor. The transistor also includes a silicide structure over the work function metallic layer. The silicide structure is configured to be independent of the work function value of the gate electrode of the transistor. | 2015-02-05 |
| 20150035079 | METHOD FOR CORE AND IN/OUT-PUT DEVICE RELIABILITY IMPROVE AT HIGH-K LAST PROCESS - A method for fabricating a semiconductor device includes providing a semiconductor substrate, forming on the semiconductor substrate a dummy gate interface layer and a dummy gate of a core device and a gate interface layer and a dummy gate of an IO device, removing the dummy gates of the core and IO devices, removing the dummy gate interface layer of the core device, forming a gate interface layer in the original location of the removed dummy gate interface layer, forming a high-k dielectric layer each on the gate interface layer of the core and IO devices, and submitting the semiconductor substrate to a high-pressure fluorine annealing. The high-pressure fluorine annealing causes the gate interface layer and the high-k dielectric layer of the core and IO devices to be doped with fluoride ions. | 2015-02-05 |
| 20150035080 | Semiconductor Device - Disclosed is a semiconductor device in which a resistance component resulting from wiring is reduced. A plurality of transistor units are arranged side by side in a first direction (Y direction in the view), each of which has a plurality of transistors. The gate electrodes of the transistors extend in the first direction. First source wiring extends between first transistor unit and second transistor unit, and first drain wiring extends between the second transistor unit and third transistor unit. Second drain wiring extends on the side of the first transistor unit opposite to the side where the first source wiring extends, and second source wiring extends on the side of the third transistor unit opposite to the side where the second drain wiring extends. | 2015-02-05 |
| 20150035081 | INVERSE SIDE-WALL IMAGE TRANSFER - Semiconductor devices include a set of fin field effect transistors (FETs), each having a fin structure formed from a monocrystalline substrate. A trench between fin structures of respective fin FETs is formed by a cut in the monocrystalline substrate that has a width smaller than a width of the fin structures and that penetrates less than a full depth of the monocrystalline substrate. The trenches have a width smaller than a minimum pitch of a lithographic technology employed. | 2015-02-05 |
| 20150035082 | SEMICONDUCTOR DEVICE STRUCTURES INCLUDING ENERGY BARRIERS, AND RELATED METHODS - A semiconductor device structure includes a transistor with an energy barrier beneath its transistor channel. The energy barrier prevents leakage of stored charge from the transistor channel into a bulk substrate. Methods for fabricating semiconductor devices that include energy barriers are also disclosed. | 2015-02-05 |
| 20150035083 | MOS TRANSISTORS AND FABRICATION METHOD THEREOF - A method is provided for fabricating an MOS transistor. The method includes providing a semiconductor substrate; forming a metal gate structure; and forming a source region and a drain region. The method also includes forming a contact-etch-stop layer; forming an interlayer dielectric layer on the contact-etch-stop layer and the metal gate structure; and forming a first opening in the interlayer dielectric layer with a portion of the sidewall spacer and the contact-etch-stop layer left on the bottom. Further, forming a first contact hole in the interlayer dielectric layer by removing the portion of the sidewall spacer and the contact-etch-stop layer. Further, the method also includes forming a first conductive via in the first contact hole. | 2015-02-05 |
| 20150035084 | MOS TRANSISTORS AND FABRICATION METHOD THEREOF - A method is provided for fabricating an MOS transistor. The method includes providing a semiconductor substrate; and forming a ploy silicon dummy gate structure having a high-K gate dielectric layer, a high-K gate dielectric protection layer containing nitrogen and a poly silicon dummy gate on the semiconductor substrate. The method also includes forming a source region and a drain region in the semiconductor substrate at both sides of the poly silicon dummy gate structure. Further, the method includes removing the poly silicon dummy gate to form a trench exposing the high-K gate dielectric protection layer containing nitrogen and performing a nitrogen treatment process to repair defects in the high-K gate dielectric protection layer containing nitrogen caused by removing the poly silicon dummy gate. Further, the method also includes forming a metal gate structure in the trench. | 2015-02-05 |
| 20150035085 | Doped High-k Dielectrics and Methods for Forming the Same - Embodiments provided herein describe high-k dielectric layers and methods for forming high-k dielectric layers. A substrate is provided. The substrate includes a semiconductor material. The substrate is exposed to a hafnium precursor. The substrate is exposed to a zirconium precursor. The substrate is exposed to an oxidant only after the exposing of the substrate to the hafnium precursor and the exposing of the substrate to the zirconium precursor. The exposing of the substrate to the hafnium precursor, the exposing of the substrate to the zirconium precursor, and the exposing of the substrate to the oxidant causes a layer to be formed over the substrate. The layer includes hafnium, zirconium, and oxygen. | 2015-02-05 |
| 20150035086 | METHODS OF FORMING CAP LAYERS FOR SEMICONDUCTOR DEVICES WITH SELF-ALIGNED CONTACT ELEMENTS AND THE RESULTING DEVICES - One method disclosed herein includes forming an etch stop layer above recessed sidewall spacers and a recessed replacement gate structure and, with the etch stop layer in position, forming a self-aligned contact that is conductively coupled to the source/drain region after forming the self-aligned contact. A device disclosed herein includes an etch stop layer that is positioned above a recessed replacement gate structure and recessed sidewall spacers, wherein the etch stop layer defines an etch stop recess that contains a layer of insulating material positioned therein. The device further includes a self-aligned contact. | 2015-02-05 |
| 20150035087 | Method for Manufacturing Dummy Gate in Gate-Last Process and Dummy Gate in Gate-Last Process - A method for manufacturing a dummy gate in a gate-last process and a dummy gate in a gate-last process are provided. The method includes: providing a semiconductor substrate; growing a gate oxide layer on the semiconductor substrate; depositing bottom-layer amorphous silicon on the gate oxide layer; depositing an ONO structured hard mask on the bottom-layer amorphous silicon; depositing top-layer amorphous silicon on the ONO structured hard mask; depositing a hard mask layer on the top-layer amorphous silicon; forming photoresist lines on the hard mask layer, and trimming the formed photoresist lines so that the trimmed photoresist lines a width less than or equal to 22 nm; and etching the hard mask layer, the top-layer amorphous silicon, the ONO structured hard mask and the bottom-layer amorphous silicon in accordance with the trimmed photoresist lines, and removing the photoresist lines, the hard mask layer and the top-layer amorphous silicon. | 2015-02-05 |
| 20150035088 | SEMICONDUCTOR STRUCTURES - A method is provided for fabricating a semiconductor structure. The method includes providing a semiconductor substrate having a plurality of first doped regions and second doped regions; and forming a first dielectric layer on the semiconductor substrate. The method also includes forming a first gate dielectric layer and a second gate dielectric layer; and forming a first metal gate and a second metal gate on the first gate dielectric layer and the second gate dielectric layer, respectively. Further, the method includes forming a third dielectric layer on the second metal gate; and forming a second dielectric layer on the first dielectric layer. Further, the method also includes forming at least one opening exposing at least one first metal gate and one first doped region; and forming a contact layer contacting with the first metal gate and the first doped region to be used as a share contact structure. | 2015-02-05 |
| 20150035089 | MEMS DEVICE AND METHOD OF FORMING THE SAME - A method for forming a MEMS device is provided. The method includes the following steps of providing a substrate having a first portion and a second portion; fabricating a membrane type sensor on the first portion of the substrate; and fabricating a bulk silicon sensor on the second portion of the substrate. | 2015-02-05 |
| 20150035090 | STACKED DIE PACKAGE FOR MEMS RESONATOR SYSTEM - In a packaging structure for a microelectromechanical-system (MEMS) resonator system, a resonator-control chip is mounted on a lead frame having a plurality of electrical leads, including electrically coupling a first contact on a first surface of the resonator-control chip to a mounting surface of a first electrical lead of the plurality of electrical leads through a first electrically conductive bump. A MEMS resonator chip is mounted to the first surface of the resonator-control chip, including electrically coupling a contact on a first surface of the MEMS resonator chip to a second contact on the first surface of the resonator-control chip through a second electrically conductive bump. The MEMS resonator chip, resonator-control chip and mounting surface of the first electrical lead are enclosed within a package enclosure that exposes a contact surface of the first electrical lead at an external surface of the packaging structure. | 2015-02-05 |
| 20150035091 | PROCESS FOR MANUFACTURING A PACKAGED DEVICE, IN PARTICULAR A PACKAGED MICRO-ELECTRO-MECHANICAL SENSOR, HAVING AN ACCESSIBLE STRUCTURE, SUCH AS A MEMS MICROPHONE AND PACKAGED DEVICE OBTAINED THEREBY - In order to manufacture a packaged device, a die having a sensitive region is bonded to a support, and a packaging mass of moldable material is molded on the support so as to surround the die. During molding of the packaging mass, a chamber is formed, which faces the sensitive region and is connected to the outside environment. To this end, a sacrificial mass of material that may evaporate/sublimate is dispensed on the sensitive region; the packaging mass is molded on the sacrificial mass; a through hole is formed in the packaging mass to extend as far as the sacrificial mass; the sacrificial mass is evaporated/sublimated through the hole. | 2015-02-05 |
| 20150035092 | SENSORS AND METHOD OF OPERATING SENSOR - Sensors and methods of operating sensors are described herein. One sensor includes a number of III-nitride strain sensitive devices and a number of passive electrical components that connects each of them to one of the III-nitride strain sensitive devices. | 2015-02-05 |
| 20150035093 | INERTIAL AND PRESSURE SENSORS ON SINGLE CHIP - In one embodiment, the process flow for a capacitive pressures sensor is combined with the process flow for an inertial sensor. In this way, an inertial sensor is realized within the membrane layer of the pressure sensor. The device layer is simultaneously used as z-axis electrode for out-of-plane sensing in the inertial sensor, and/or as the wiring layer for the inertial sensor. The membrane layer (or cap layer) of the pressure sensor process flow is used to define the inertial sensor sensing structures. Insulating nitride plugs in the membrane layer are used to electrically decouple the various sensing structures for a multi-axis inertial sensor, allowing for fully differential sensing. | 2015-02-05 |
| 20150035094 | MICROPHONE ASSEMBLY HAVING AT LEAST TWO MEMS MICROPHONE COMPONENTS - A microphone assembly includes two MEMS components each having a micromechanical microphone structure, each microphone structure having: a diaphragm configured to be deflected by sound pressure and provided with at least one diaphragm electrode of a capacitor system; and a stationary acoustically permeable counter-element that acts as bearer for at least one counter-electrode of the capacitor system. The microphone assembly is configured such that under the action of sound the spacing between the diaphragm and the counter-element of the two microphone structures changes in opposite directions. | 2015-02-05 |
| 20150035095 | MAGNETIC MEMORY DEVICES HAVING A PERPENDICULAR MAGNETIC TUNNEL JUNCTION - A magnetic memory device may include a free magnetic structure and a reference magnetic structure that are separated from each other by a tunnel barrier. The free magnetic structure may include an exchange-coupling layer, and first and second free layers that are separated from each other by the exchange-coupling layer. The first free layer may be provided between the second free layer and the tunnel barrier. A thickness of the first free layer may be greater than a first maximum anisotropy thickness, being the thickness at which the first free layer has maximum perpendicular anisotropy. A thickness of the second free layer may be smaller than a second maximum anisotropy thickness, being the thickness at which the second free layer has maximum perpendicular anisotropy. A magnetic tunnel junction having two free layers with different thicknesses can enable a magnetic memory device that has increased MR ratio and reduced switching current. | 2015-02-05 |
| 20150035096 | MAGNETIC MEMORY DEVICE AND METHOD OF FABRICATING THE SAME - Provided are a magnetic memory device and a method of fabricating the same. The device may include a cell selection device, a magnetic tunnel junction (MTJ), and a lower electrode connecting them. The lower electrode may include a vertical portion and a horizontal portion laterally extending from a side surface of the vertical portion. In the lower electrode, the vertical portion has a top surface higher than the horizontal portion and has a top surface including at least two parallel sides and other side at an angle thereto. The MTJ may be provided on the vertical portion of the lower electrode. | 2015-02-05 |
| 20150035097 | SEMICONDUCTOR STORAGE DEVICE - A memory includes a semiconductor substrate. Magnetic tunnel junction elements are provided above the semiconductor substrate. Each of the magnetic tunnel junction elements stores data by a change in a resistance state, and the data is rewritable by a current. Cell transistors are provided on the semiconductor substrate. Each of the cell transistors is in a conductive state when the current is applied to the corresponding magnetic tunnel junction element. Gate electrodes are included in the respective cell transistors. Each of the gate electrodes controls the conductive state of the corresponding cell transistor. In active areas, the cell transistors are provided, and the active areas extend in an extending direction of intersecting the gate electrodes at an angle of (90-atan(⅓)) degrees. | 2015-02-05 |
| 20150035098 | MEMORY CELL WITH SCHOTTKY DIODE - Memory cell comprising two conductors, with a serially connected magnetic storage element and a Schottky diode between the two conductors. The Schottky diode provides a unidirectional conductive path between the two conductors and through the element. The Schottky diode is formed between a metal layer in one of the two conductors and a processed junction layer. Methods for process and for operation of the memory cell are also disclosed. The memory cell using the Schottky diode can be designed for high speed operation and with high density of integration. Advantageously, the junction layer can also be used as a hard mask for defining the individual magnetic storage element in the memory cell. The memory cell is particularly useful for magnetic random access memory (MRAM) circuits. | 2015-02-05 |
| 20150035099 | METHOD AND SYSTEM FOR PROVIDING MAGNETIC JUNCTIONS INCLUDING A PACKAGE STRUCTURE USABLE IN SPIN TRANSFER TORQUE MEMORIES - A method and system for providing a magnetic junction usable in a magnetic device are described. The magnetic includes a pinned layer, a nonmagnetic spacer layer, a free layer, and package structure(s). The pinned layer has a pinned layer perimeter and a top surface. The nonmagnetic spacer layer is on at least part of the top surface and between the pinned and free layers. The free layer has a free layer perimeter. The package structure(s) are ferromagnetic and encircles at least one of the free layer and the pinned layer. The package structure(s) are ferromagnetically coupled with the pinned layer. The magnetic junction is configured such that the free layer is switchable between stable magnetic states when a write current is passed through the magnetic junction. | 2015-02-05 |
| 20150035100 | SOLID STATE IMAGING DEVICE AND METHOD OF MANUFACTURING SOLID STATE IMAGING DEVICE - A solid state imaging device includes a semiconductor layer, and a light shielding portion. The semiconductor layer has multiple photoelectric conversion elements. The light shielding portion is provided in the semiconductor layer, and has a light shielding member whose interface with the semiconductor layer is covered by an insulating film. The light shielding portion includes a light shielding region and an element isolation region. The light shielding region is provided in the semiconductor layer on the side close to the light receiving surface of the photoelectric conversion element for shielding light incident on the photoelectric conversion element from a specific direction. The element isolation region is formed to project in the depth direction of the semiconductor layer from the light shielding region toward a portion between the multiple photoelectric conversion elements in order to electrically and optically isolate the multiple photoelectric conversion elements from one another. | 2015-02-05 |
| 20150035101 | SOLID-STATE IMAGING DEVICE AND METHOD FOR MANUFACTURING THE SOLID-STATE IMAGING DEVICE - According to one embodiment, a solid-state imaging device is provided. The solid-state imaging device includes a photoelectric conversion element, a first anti-reflection film, an intermediate film, and a second anti-reflection film. The photoelectric conversion element is disposed corresponding to each of a plurality of colored lights. The first anti-reflection film is disposed on a photo-receiving surface side of the photoelectric conversion element. The intermediate film is disposed on a photo-receiving surface side of the first anti-reflection film. The second anti-reflection film is disposed on a photo-receiving surface side of the intermediate film. At least one of the first anti-reflection film, the intermediate film, and the second anti-reflection film has different film thicknesses for respective colored lights to be received. | 2015-02-05 |
| 20150035102 | METHOD OF MANUFACTURING SOLID-STATE IMAGING DEVICE AND SOLID-STATE IMAGING DEVICE - According to one embodiment, the method of manufacturing a solid-state imaging device includes: forming a plurality of photoelectric conversion elements by two-dimensionally arranging semiconductor areas of a second conductivity type at a semiconductor layer of a first conductivity type in a matrix pattern; forming the photoelectric conversion elements in a rectangular shape in plan view, the photoelectric conversion elements being formed by forming a grid-like trench in plan view so as to partition the semiconductor layer; forming the photoelectric conversion element formed into the rectangular shape in plan view into a convex polygonal shape in plan view whose number of corners is larger than the number of corners of a rectangular; and forming an element isolation area including a light shielding member at a trench coated with an insulating film after coating an inner peripheral surface of the trench with the insulating film. | 2015-02-05 |
| 20150035103 | SOLID STATE IMAGING DEVICE - According to one embodiment, a solid state imaging device includes a semiconductor substrate comprising a first surface and a second surface opposite the first surface; a circuit at a side of the first surface of the semiconductor substrate; a pixel in the semiconductor substrate and converting light from a side of the second surface into electric charge; and an element at a side of the second surface of the semiconductor substrate. The pixel includes a photo diode in the semiconductor substrate at the side of the first surface, and the photo diode includes a diffusion layer in an impurity region in the semiconductor substrate at the side of the first surface. | 2015-02-05 |
| 20150035104 | SOLID-STATE IMAGING APPARATUS, METHOD OF MANUFACTURING THE SAME, AND ELECTRONIC APPARATUS - A solid-state imaging apparatus includes an imaging region in which pixels are arranged, a connection region that surrounds the imaging region and includes an electrode pad, and an in-layer lens that is formed in the imaging region for each of the pixels. The in-layer lens is formed of a coating-type high-refractive-index material. The connection region includes an opening that is formed such that an upper surface of the electrode pad is exposed from the high-refractive-index material applied to the electrode pad. | 2015-02-05 |
| 20150035105 | IMAGE PICKUP ELEMENT, IMAGING APPARATUS, MANUFACTURING APPARATUS FOR IMAGE PICKUP ELEMENT, AND MANUFACTURING METHOD FOR IMAGE PICKUP ELEMENT - Provided is an image pickup element, including: condenser lenses made of a resin containing fine metal particles; photoelectric conversion elements formed in a silicon substrate and each configured to photoelectrically convert incident light that enter from an outside through corresponding one of the condenser lenses; and a protective film made of a silicon compound, the protective film being formed between the condenser lenses and the silicon substrate. | 2015-02-05 |
| 20150035106 | BACK SIDE ILLUMINATION IMAGE SENSOR WITH LOW DARK CURRENT - An integrated circuit includes a back side illuminated image sensor formed by a substrate supporting at least one pixel, an interconnect part situated above a front side of the substrate and an anti-reflective layer situated above a back side of the substrate. The anti-reflective layer may be formed of a silicon nitride layer. An additional layer is situated above the anti-reflective layer. The additional layer is formed of one of amorphous silicon nitride or hydrogenated amorphous silicon nitride, in which the ratio of the number of silicon atoms per cubic centimeter to the number of nitrogen atoms per cubic centimeter is greater than 0.7. | 2015-02-05 |
| 20150035107 | COLOR IMAGE SAMPLING AND RECONSTRUCTION - An image capture apparatus that includes an array of color filters for green, red, and magenta colors arranged over a semiconductor substrate in the manner of a primary color Bayer pattern except a magenta color replaces the blue color. Light passing through the magenta color filter is integrated separately in a magenta pixel for a shallow photodiode signal and a deep photodiode signal in a first photodiode and a deeper second photodiode in the substrate, respectively. A mezzanine photodiode may be disposed between the first and second photodiodes and held at a fixed voltage level or reset multiple times during charge integration. A red pixel value for the magenta pixel is a function of the deep photodiode signal and an adjacent red pixel's red pixel signal. A minimum exists in its derivative with respect to the former at a value of the former that varies with the latter. | 2015-02-05 |
| 20150035108 | HIGH DENSITY CAPACITOR INTEGRATED INTO FOCAL PLANE ARRAY PROCESSING FLOW - Methods and structures of photodetectors are described. The structure may include a readout integrated circuit substrate having an internally integrated capacitor. The structure may additionally include an external capacitor overlying the readout integrated circuit substrate. The external capacitor may be coupled with the internally integrated capacitor of the readout integrated circuit substrate, and configured to operate in parallel with the internally integrated capacitor of the readout integrated circuit substrate. The structure may also include a detector overlying the external capacitor. | 2015-02-05 |
| 20150035109 | SEMICONDUCTOR DEVICE, MANUFACTURING METHOD OF SEMICONDUCTOR DEVICE, SEMICONDUCTOR WAFER, AND ELECTRONIC EQUIPMENT - The present technology relates to a semiconductor device, a manufacturing method of a semiconductor device, a semiconductor wafer, and electronic equipment, which allow a semiconductor device, in which miniaturization is possible, to be provided. | 2015-02-05 |
| 20150035110 | PYROELECTRIC ALUMINUM NITRIDE MEMS INFRARED SENSOR WITH SELECTIVE WAVELENGTH INFRARED ABSORBER - A MEMS sensor for detecting electromagnetic waves in a particular frequency range is provided. In a preferred embodiment, the MEMS sensor comprises a bottom substrate layer; a first electrode layer over the substrate layer; a pyroelectric layer over the first electrode layer; and a second electrode layer over the pyroelectric layer; wherein a top electrode layer is patterned with a periodic structure that has a periodicity less than or equal to target infrared wavelength. | 2015-02-05 |
| 20150035111 | SEMICONDUCTOR DEVICE - A semiconductor device includes first and second electrodes. First semiconductor regions of a first conductivity type are positioned between the first electrode and the second electrode and contact the first electrode. These semiconductor regions are arranged along a first direction. A second semiconductor region of the first conductivity type also contacts the first electrode and is disposed around the plurality of first semiconductor regions. The second semiconductor region has a dopant concentration that is higher than the first semiconductor regions. A semiconductor layer of a second conductivity type has portions that are between the first semiconductor regions and the second semiconductor region. These portions are in Schottky contact with the first electrode. | 2015-02-05 |
| 20150035112 | SEGMENTED GUARD RING STRUCTURES WITH ELECTRICALLY INSULATED GAP STRUCTURES AND DESIGN STRUCTURES THEREOF - Disclosed are guard ring structures with an electrically insulated gap in a substrate to reduce or eliminate device coupling of integrated circuit chips, methods of manufacture and design structures. The method includes forming a guard ring structure comprising a plurality of metal layers within dielectric layers. The method further includes forming diffusion regions to electrically insulate a gap in a substrate formed by segmented portions of the guard ring structure. | 2015-02-05 |
| 20150035113 | Epitaxial Structures and Methods of Forming the Same - An embodiment is a method. A first III-V compound semiconductor is epitaxially grown in a trench on a substrate, and the epitaxial growth is performed in a chamber. The first III-V compound semiconductor has a first surface comprising a facet. After the epitaxial growth, the first surface of the first III-V compound semiconductor is etched to form an altered surface of the first III-V compound semiconductor. Etching the first surface is performed in the chamber in situ. A second III-V compound semiconductor is epitaxially grown on the altered surface of the first III-V compound semiconductor. The epitaxial growth of the first III-V compound semiconductor may be performed in a MOCVD chamber, and the etch may use an HCl gas. Structures resulting from methods are also disclosed. | 2015-02-05 |
| 20150035114 | INTEGRATED CIRCUIT DEVICE - An integrated circuit device includes a semiconductor substrate, an active element and a passive element. The active element is made of the semiconductor substrate. The passive element includes a functional element filled in a groove or hole provided in the semiconductor substrate along a thickness direction thereof and is electrically connected to the active element. The functional element has a Si—O bond region obtained by reacting Si particles with an organic Si compound. | 2015-02-05 |
| 20150035115 | MODIFIED VIA BOTTOM FOR BEOL VIA EFUSE - An electronic fuse structure including an M | 2015-02-05 |
| 20150035116 | SEMICONDUCTOR DEVICE WITH CIRCUITS CONNECTED TO EACH OTHER IN CONTACTLESS MANNER - In a semiconductor device, a first semiconductor chip includes a first circuit and a first inductor, and a second semiconductor chip includes a second circuit and chip-side connecting terminals. An interconnect substrate is placed over the first semiconductor chip and the second semiconductor chip. The interconnect substrate includes a second inductor and substrate-side connecting terminals. The second inductor is located above the first inductor. The chip-side connecting terminals and the two substrate-side connecting terminals are connected through first solder balls. | 2015-02-05 |
| 20150035117 | METHOD FOR REDUCING LATERAL EXTRUSION FORMED IN SEMICONDUCTOR STRUCTURES AND SEMICONDUCTOR STRUCTURES FORMED THEREOF - Aspects of the present invention relate to method for reducing lateral extrusion formed in semiconductor structures and semiconductor structures formed thereof. Various embodiments include a method for reducing lateral extrusion formed in semiconductor structures. The method can include removing a portion of a first lateral extrusion in an aluminum layer of the semiconductor structure, and determining a post-removal thickness of a dielectric layer positioned adjacent the aluminum layer. The post-removal thickness may be determined subsequent to the removing of the portion of the first lateral extrusion. The method can also include determining a difference between the post-removal thickness of the dielectric layer and a pre-removal thickness of the dielectric layer. | 2015-02-05 |
| 20150035118 | SEMICONDUCTOR DEVICE INCLUDING AN ELECTRODE LOWER LAYER AND AN ELECTRODE UPPER LAYER AND METHOD OF MANUFACTURING SEMICONDUCTOR DEVICE - The semiconductor device according to the present invention includes a ferroelectric film and an electrode stacked on the ferroelectric film. The electrode has a multilayer structure of an electrode lower layer in contact with the ferroelectric film and an electrode upper layer stacked on the electrode lower layer. The electrode upper layer is made of a conductive material having an etching selection ratio with respect to the materials for the ferroelectric film and the electrode lower layer. The upper surface of the electrode upper layer is planarized. | 2015-02-05 |
| 20150035119 | CAPACITORS AND METHODS WITH PRASEODYMIUM OXIDE INSULATORS - Methods of forming and the resulting capacitors formed by these methods are shown. Monolayers that contain praseodymium are deposited onto a substrate and subsequently processed to form praseodymium oxide dielectrics. Monolayers that contain titanium or other metals are deposited onto a substrate and subsequently processed to form metal electrodes. Resulting capacitor structures includes properties such as improved dimensional control. One improved dimensional control includes thickness. Some resulting capacitor structures also include properties such as an amorphous or nanocrystalline microstructure. Selected components of capacitors formed with these methods have better step coverage over substrate topography and more robust film mechanical properties. | 2015-02-05 |
| 20150035120 | Wafer Scale Package for High Power Devices - A semiconductor device package is formed of DBC in which thinned MOSgated and/or diode die are soldered to the bottom of an etched depression in the upper conductive layer. A via in the insulation layer of the DBC is filled with a conductive material to form a resistive shunt. Plural packages may be formed in a DBC card and may be separated individually or in clusters. The individual packages arc mounted in various arrays on a support DBC board and heat sink. Integrated circuits may be mounted on the assembly and connected to the die for control of the die conduction. | 2015-02-05 |
| 20150035121 | BIPOLAR TRANSISTOR, SEMICONDUCTOR DEVICE, AND BIPOLAR TRANSISTOR MANUFACTURING METHOD - Disconnection of a base line is suppressed even when a short-side direction of a collector layer is parallel to crystal orientation [011]. A bipolar transistor includes: a collector layer that has a long-side direction and a short-side direction in a plan view, in which the short-side direction is parallel to crystal orientation [011], a cross-section perpendicular to the short-side direction has an inverted mesa shape, and a cross-section perpendicular to the long-side direction has a forward mesa shape; a base layer that is formed on the collector layer; a base electrode that is formed on the base layer; and a base line that is connected to the base electrode and that is drawn out from an end in the short-side direction of the collector layer to the outside of the collector layer in a plan view. | 2015-02-05 |
| 20150035122 | Micro-Electro-Mechanical System (MEMS) Structures And Design Structures - Micro-Electro-Mechanical System (MEMS) structures, methods of manufacture and design structures are disclosed. The method includes forming at least one fixed electrode on a substrate. The method further includes forming a Micro-Electro-Mechanical System (MEMS) beam with a varying width dimension, as viewed from a top of the MEMS beam, over the at least one fixed electrode. | 2015-02-05 |
| 20150035123 | CURVATURE COMPENSATED SUBSTRATE AND METHOD OF FORMING SAME - A curvature-control-material (CCM) is formed on one side of a substrate prior to forming a Group III nitride material on the other side of the substrate. The CCM possess a thermal expansion coefficient (TEC) that is lower than the TEC of the substrate and is stable at elevated growth temperatures required for formation of a Group III nitride material. In some embodiments, the deposition conditions of the CCM enable a flat-wafer condition for the Group III nitride material maximizing the emission wavelength uniformity of the Group III nitride material. Employment of the CCM also reduces the final structure bowing during cool down leading to reduced convex substrate curvatures. In some embodiments, the final structure curvature can further be engineered to be concave by proper selection of CCM properties, and via controlled selective etching of the CCM, this method enables the final structure to be flat. | 2015-02-05 |
| 20150035124 | PROCESS FOR IMPROVING CRITICAL DIMENSION UNIFORMITY OF INTEGRATED CIRCUIT ARRAYS - Methods for patterning integrated circuit (IC) device arrays employing an additional mask process for improving center-to-edge CD uniformity are disclosed. In one embodiment, a repeating pattern of features is formed in a masking layer over a first region of a substrate. Then, a blocking mask is applied over the features in the masking layer. The blocking mask is configured to differentiate array regions of the first region from peripheral regions of the first region. Subsequently, the pattern of features in the array regions is transferred into the substrate. In the embodiment, an etchant can be uniformly introduced to the masking layer because there is no distinction of center/edge in the masking layer. Thus, CD uniformity can be achieved in arrays which are later defined. | 2015-02-05 |
| 20150035125 | SEMICONDUCTOR DEVICE, SEMICONDUCTOR WAFER AND MANUFACTURING METHOD OF SEMICONDUCTOR DEVICE - A semiconductor device includes wiring layers formed over a semiconductor wafer, a via-layer between the wiring layers, conductive films in the wiring layers, and a via-plug in the via-layer connecting the conductive films of the wiring layers above and below, a scribe region at an outer periphery of a chip region along an edge of the semiconductor substrate and including a pad region in the vicinity of the edge, the pad region overlapping the conductive films of the plurality of wiring layers in the plan view, the plurality of wiring layers including first second wiring layers, the conductive film of the first wiring layer includes a first conductive pattern formed over an entire surface of said pad region in a plan view, and the conductive film of the second wiring layer includes a second conductive pattern formed in a part of the pad region in a plan view. | 2015-02-05 |
| 20150035126 | METHODS AND STRUCTURES FOR PROCESSING SEMICONDUCTOR DEVICES - Methods of forming a semiconductor structure include exposing a carrier substrate to a silane material to form a coating, removing a portion of the coating at least adjacent a periphery of the carrier substrate, adhesively bonding another substrate to the carrier substrate, and separating the another substrate from the carrier substrate. The silane material includes a compound having a structure of (XO) | 2015-02-05 |
| 20150035127 | SEMICONDUCTOR PACKAGE AND METHOD OF FABRICATING THE SAME - The present disclosure relates to a semiconductor package and a method of fabricating the same. The semiconductor package includes a substrate, a grounding layer, a chip, a package body, and a shielding layer. The substrate includes a lateral surface and a bottom surface. The grounding layer is buried in the substrate and extends horizontally in the substrate. The chip is arranged on the substrate. The package body envelops the chip and includes a lateral surface. The shielding layer covers the lateral surface of the package body and the lateral surface of the substrate, and is electrically connected to the grounding layer, where a bottom surface of the shielding layer is separated from a bottom surface of the substrate. | 2015-02-05 |
| 20150035128 | SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING SEMICONDUCTOR DEVICE - According to one embodiment, a semiconductor device includes a metal holder, a semiconductor chip on the holder, and a reinforcing portion. The reinforcing portion is formed by bending a portion of the holder, the reinforcing portion includes a groove depressed from a surface of the holder and a protrusion on a back of the groove. | 2015-02-05 |
| 20150035129 | STACKED MULTI - CHIP PACKAGING STRUCTURE AND MANUFACTURING METHOD THEREOF - A stacked multi-chip packaging structure comprises a lead frame, a first semiconductor chip mounted on the lead frame, a second semiconductor chip flipped-chip mounted on the lead frame, a metal clip mounted on top of the first and second semiconductor chips and a third semiconductor chip stacked on the meal clip; bonding wires electrically connecting electrodes on the third semiconductor chip to the first and second semiconductor chips and the pins of the lead frame; plastic molding encapsulating the lead frame, the chips and the metal clip. | 2015-02-05 |
| 20150035130 | Integrated Circuit with Stress Isolation - A packaged semiconductor device has a semiconductor substrate with circuitry formed thereon. A shield plate is mounted over a designated region of the substrate and separated from the semiconductor substrate by a separator, such that the shield plate is separated from the designated region of the substrate by a distance. Mold compound encapsulates the semiconductor substrate and the shield plate, but is prevented from touching the designated region of the substrate by the shield plate. | 2015-02-05 |
