| 06th week of 2015 patent applcation highlights part 16 |
| Patent application number | Title | Published |
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| 20150034931 | ORGANIC EL MODULE AND POWER SUPPLY STRUCTURE MADE UP OF ORGANIC EL MODULES - The present invention aims at providing a further downsizable organic EL module. Void parts are formed on first and second power supply members. The power supply members are different in shape, so that at least a part of the first power supply member is located in a vertically projected region of the second void part and at least a part of the second power supply member is located in a vertically projected region of the first void part when the power supply members overlap with an insulation layer sandwiched between. An electric wire penetrates the second power supply member to be connected to the first power supply member. The first power supply member is connected to one electrode layer directly or via a conducting member. The second power supply member, to which another electric wire is connected, is connected to another electrode layer directly or via a conducting member. | 2015-02-05 |
| 20150034932 | FLEXIBLE ORGANIC ELECTROLUMINESCENT DEVICE AND METHOD OF FABRICATING THE SAME - A flexible organic electroluminescent device is disclosed which includes: a flexible substrate; a buffer layer entirely formed on the flexible substrate; a thin film transistor formed on the buffer layer and configured to include an active layer; a planarization film formed to cover the thin film transistor; an organic light emitting diode formed on the planarization film and configured to include a first electrode, an organic emission layer and a second electrode; and at least one silicon nitride layer formed above the active layer of the thin film transistor but under the planarization film and patterned into a plurality of island patterns. | 2015-02-05 |
| 20150034933 | ORGANIC LIGHT EMITTING DIODE DISPLAY HAVING THIN FILM TRANSISTOR SUBSTRATE USING OXIDE SEMICONDUCTOR AND METHOD FOR MANUFACTURING THE SAME - Provided is a thin film transistor having an oxide semiconductor material for an organic light emitting diode display and a method for manufacturing the same. The organic light emitting diode display comprises: a gate electrode formed on a substrate; a gate insulating layer formed on the gate electrode; a semiconductor layer formed on the gate insulating layer to overlap with the gate electrode, and including a channel area and source and drain areas which extend from the channel area to both outsides, respectively and are conductorized; an etch stopper formed on the channel area and exposing the source area and the drain area; a source electrode contacting portions of the exposed source electrode; and a drain electrode contacting portions of the exposed drain electrode. | 2015-02-05 |
| 20150034934 | LOCAL SEAL FOR ENCAPSULATION OF ELECTRO-OPTICAL ELEMENT ON A FLEXIBLE SUBSTRATE - An electroluminescent display or lighting product incorporates a panel comprising a collection of distinct light-emitting elements formed on a substrate. A plurality of distinct local seals are formed over respective individual light-emitting elements or groups of light-emitting elements. Each local seal is formed by depositing a low melting temperature glass powder suspension or paste using inkjet technology, and fusing the glass powder using a scanning laser beam having a tailored beam profile. The local seal may be used in conjunction with a continuous thin film encapsulation structure. Optical functions can be provided by each local seal, including refraction, filtering, color shifting, and scattering. | 2015-02-05 |
| 20150034935 | FLEXIBLE DISPLAY DEVICE AND MANUFACTURING METHOD THEREOF - A flexible display device includes: a display substrate which is divided into a first region corresponding to a within-cell region of an integrated devices sheet from which the flexible display device is cut and into a second region corresponding to an outside-the-cell region of the integrated devices sheet, where within the first region there is provided a display unit including a light emitting element layer; a patterned inorganic film layer formed to be substantially continuously present within the first region of the display substrate and to be not present or not substantially continuously present within the second region of the display substrate; and a thin film encapsulation layer formed on the inorganic film layer to encapsulate the substantially continuously present portion of the inorganic film layer that is within the first region and the display unit, wherein an outer boundary of the thin film encapsulation layer is located more inwardly and toward an outer boundary of the display unit than is an outer boundary of the substantially continuously present portion of the inorganic film layer. | 2015-02-05 |
| 20150034936 | LIGHT-EMITTING DEVICE AND METHOD OF MANUFACTURING THE SAME - To provide a bright and highly reliable light-emitting device. An anode ( | 2015-02-05 |
| 20150034937 | Light-Emitting Element and Display Device - There has been a problem that difference in refractive index between an opposite substrate or a moisture barrier layer provided thereover, and air is maintained large, and light extraction efficiency is low. Further, there has been a problem that peeling or cracking due to the moisture barrier layer is easily generated, which leads to deteriorate the reliability and lifetime of a light-emitting element. A light-emitting element comprises a pixel electrode, an electroluminescent layer, a transparent electrode, a passivation film, a stress relieving layer, and a low refractive index layer, all of which are stacked sequentially. The stress relieving layer serves to prevent peeling of the passivation film. The low refractive index layer serves to reduce reflectivity of light generated in the electroluminescent layer in emitting to air. Therefore, a light-emitting element with high reliability and long lifetime and a display device using the light-emitting element can be provided. | 2015-02-05 |
| 20150034938 | COMPOUND FOR ORGANIC OPTOELECTRONIC DEVICE, ORGANIC LIGHT EMITTING DIODE INCLUDING THE SAME AND DISPLAY INCLUDING THE ORGANIC LIGHT EMITTING DIODE - A compound for an organic optoelectronic device, an organic light emitting diode including the same, and a display device including the organic light emitting diode are disclosed and the compound for an organic optoelectronic device represented by the following Chemical Formula 1 or 2 provides an organic light emitting diode having life-span characteristics due to excellent electrochemical and thermal stability, and high luminous efficiency at a low driving voltage. | 2015-02-05 |
| 20150034939 | Display Device and Method for Manufacturing the Same - A structure of an EL display device which has an increased display area is provided. Further, a structure of an EL display device which has a high definition display is provided. An auxiliary electrode is formed over a first partition and side surfaces of the auxiliary electrode are covered with a second partition. A top surface of the auxiliary electrode is in contact with the conductive film which is one electrode of a light-emitting element and has a light-transmitting property, which enables a large-area display. Further, even the distance between the adjacent light-emitting elements is shortened, the auxiliary electrode can be provided between the adjacent light-emitting elements, which enables a high definition display. | 2015-02-05 |
| 20150034940 | ADHESIVE FILM AND PRODUCT FOR ENCAPSULATING ORGANIC ELECTRONIC DEVICE USING SAME - Provided are an adhesive film and an organic electronic device (OED) encapsulation product using the same. As moisture resistance is maintained by preventing traveling of moisture in a matrix resin, moisture or oxygen input to the organic electronic device from an external environment may be effectively prevented, and temporal stability, life span and durability may be enhanced even when a panel of the organic electronic device is formed as a thin film, thereby ensuring long-term reliability. | 2015-02-05 |
| 20150034941 | INTEGRATED CIRCUITS HAVING FINFET SEMICONDUCTOR DEVICES AND METHODS OF FABRICATING THE SAME TO RESIST SUB-FIN CURRENT LEAKAGE - Integrated circuits that have a FinFET and methods of fabricating the integrated circuits are provided herein. In an embodiment, a method of fabricating an integrated circuit having a FinFET includes providing a substrate comprising fins. The fins include semiconductor material. A first metal oxide layer is formed over sidewall surfaces of the fins. The first metal oxide layer includes a first metal oxide. The first metal oxide layer is recessed to a depth below a top surface of the fins to form a recessed first metal oxide layer. The top surface and sidewall surfaces of the fins at a top portion of the fins are free from the first metal oxide layer. A gate electrode structure is formed over the top surface and sidewall surfaces of the fins at the top portion of the fins. The recessed first metal oxide layer is recessed beneath the gate electrode structure. | 2015-02-05 |
| 20150034942 | THIN FILM TRANSISTOR AND METHOD OF MANUFACTURING THE SAME - According to example embodiments, a thin film transistor (TFT) includes a channel layer including zinc, nitrogen, and oxygen; an etch stop layer on the channel layer; source and drain electrodes respectively contacting both ends of the channel layer; a gate electrode corresponding to the channel layer; and a gate insulating layer between the channel layer and the gate electrode. The etch stop layer includes fluorine. The channel layer may be on the gate electrode. | 2015-02-05 |
| 20150034943 | Thin film transistor array substrate - The present invention discloses a thin film transistor array substrate comprising a plurality of thin film transistors, with each one thereof including a gate electrode, a gate insulation layer, an amorphous-oxide semiconductor layer and a pair of a source electrode and a drain electrode. The amorphous-oxide semiconductor layer comprises an amorphous-oxide semiconductor material having a-IGZO. The thin film transistor array substrate further comprises a first insulation layer and a second insulation layer disposed on the thin film transistors. Since the a-IGZO semiconductor layer and the thick insulation layer covered thereon are used in the present invention, a common electrode can overlap the scan lines or data lines to increase the aperture ratio of the pixel structure. Furthermore, the thick insulation layer can be fabricated through a coating process, so as to keep the a-IGZO semiconductor layer from damages during the fabrication processes. | 2015-02-05 |
| 20150034944 | X-RAY DETECTING PANEL AND MANUFACTURING METHOD THEREOF - A panel to detect X-rays includes a plurality of signal lines, a plurality of gate lines, and a plurality of cells in areas adjacent intersections of respective ones of the gate and control lines. A first area includes a first cell having a driving circuit, and a second area includes a second cell which omits a driving circuit. Data lines connected to respective ones of the cells carry signals from which an X-ray image is generated. The second cell may be located in a dummy cell area of the panel. | 2015-02-05 |
| 20150034945 | SEMICONDUCTOR DEVICE - A semiconductor device with a transistor in which current flowing between a source and a drain when the voltage of a gate electrode is 0 V can be reduced is provided. The semiconductor device incorporates a multi-gate transistor having an oxide semiconductor film formed over an insulating surface, a first gate insulating film in contact with a first surface of the oxide semiconductor film, a first gate electrode between the insulating surface and the oxide semiconductor film, a second gate insulating film in contact with a second surface of the oxide semiconductor film, and a second gate electrode in contact with the second gate insulating film. The oxide semiconductor film has a first region overlapping with the first gate electrode and a second region not overlapping with the first gate electrode, and the second gate electrode overlaps with the first region and the second region of the oxide semiconductor film. | 2015-02-05 |
| 20150034946 | DISPLAY PANEL - The present invention provides a display panel including a novel structure that is suitable for preventing a short circuit between terminals. The present invention relates to a display panel including: an active matrix substrate; a counter substrate; and a sealing material, the active matrix substrate including a plurality of terminals outside the display region; and a plurality of insulating films respectively formed from inside to outside the display region, wherein lower portions of the plurality of terminals are formed of a same material as the gate wiring or the source wiring, upper portions of the plurality of terminals are formed of a same material as the pixel electrode, and the plurality of insulating films includes an inorganic insulating film and an organic insulating film thicker than the inorganic insulating film, the inorganic insulating film and the organic insulating film being arranged between the gate wiring or the source wiring and the pixel electrode, the organic insulating film including an end portion arranged on an outer side of a region where the sealing material is provided and at a position distant from a region where the terminals are provided, the inorganic insulating film including an end portion arranged on a boundary between the plurality of wirings and the plurality of terminals. | 2015-02-05 |
| 20150034947 | OXIDE SEMICONDUCTOR FILM AND SEMICONDUCTOR DEVICE - A crystalline oxide semiconductor film which can be used as a semiconductor film of a transistor or the like is provided. In particular, a crystalline oxide semiconductor film with less defects such as grain boundaries is provided. One embodiment of the present invention is a crystalline oxide semiconductor film which is provided over a substrate and has a region including five or less areas where a transmission electron diffraction pattern showing discontinuous points is observed when an observation area is changed one-dimensionally within a range of 700 nm, using a transmission electron diffraction apparatus with an electron beam having a probe diameter of 1 nm. | 2015-02-05 |
| 20150034948 | SEMICONDUCTOR DEVICE - Electric charge is stored, in accordance with a bias voltage, in a gate of a transistor performing switching operation between an input terminal and an output terminal, and the gate is brought into an electrically floating state at the time of completing the storage of electric charge in the gate. One electrode of a capacitor is connected to the gate in an electrically floating state, and the potential of the other electrode of the capacitor is increased, so that the voltage of the gate is increased using capacitive coupling. The potential of the gate of the transistor is increased, and the bias voltage is sampled without being decreased. Each of the transistor performing switching operation and a transistor connected to the gate of the transistor is a transistor with an extremely low off-state current. | 2015-02-05 |
| 20150034949 | SEMICONDUCTOR DEVICE AND METHOD FOR MANUFACTURING SEMICONDUCTOR DEVICE - Provided is a semiconductor device having a structure which can prevent deterioration of the electrical characteristics, which becomes more significant with miniaturization. The semiconductor device includes a first oxide semiconductor film over an insulating surface; a second oxide semiconductor film over the first oxide semiconductor film; a third oxide semiconductor film over the second oxide semiconductor film; a source electrode and a drain electrode each in contact with side surfaces of the first oxide semiconductor film, the second oxide semiconductor film, and the third oxide semiconductor film and a top surface of the third oxide semiconductor film; a gate insulating film over the third oxide semiconductor film, the source electrode, and the drain electrode; and a gate electrode which is on and in contact with the gate insulating film and faces a top surface and a side surface of the second oxide semiconductor film. | 2015-02-05 |
| 20150034950 | THIN FILM TRANSISTOR CIRCUIT AND DISPLAY DEVICE USING IT - If the threshold of a thin film transistor is depleted, a leak-induced voltage drop takes place and the desired voltage cannot be obtained. Depending on the severity of the phenomenon, the thin film transistor may fail to function. This disclosure offers a thin film transistor circuit having a first transistor connected to a low voltage, and a second transistor connected to the gate of the first transistor. When the gate voltage of the second transistor is changed from the high level to the low level, the gate voltage of the first transistor is brought to a voltage level lower than the low voltage. | 2015-02-05 |
| 20150034951 | DISPLAY DEVICE AND MANUFACTURING METHOD THEREOF - Disclosed is a display device including a transistor showing extremely low off current. In order to reduce the off current, a semiconductor material whose band gap is greater than that of a silicon semiconductor is used for forming a transistor, and the concentration of an impurity which serves as a carrier donor of the semiconductor material is reduced. Specifically, an oxide semiconductor whose band gap is greater than or equal to 2 eV, preferably greater than or equal to 2.5 eV, more preferably greater than or equal to 3 eV is used for a semiconductor layer of a transistor, and the concentration of an impurity which serves as a carrier donor included is reduced. Consequently, the off current of the transistor per micrometer in channel width can be reduced to lower than 10 zA/μm at room temperature and lower than 100 zA/μm at 85° C. | 2015-02-05 |
| 20150034952 | SEMICONDUCTOR DEVICE - A semiconductor device includes a plurality of cells in a main region, a plurality of cells in a sensing region, a transistor, and a gate shut-off time for the sensing region. The transistor is configured to drive each of the plurality of cells in the main region and each of the plurality of cells in the sensing region. The gate shut-off time for the sensing region is set according to D=(Cgs/Cgm)*(Rgs/Rgm) to be earlier than a gate shut-off time for the main region. D indicates a CR delay ratio, Rgm indicates a gate resistance value for the main region and Rgs indicates a gate resistance value for the sensing region in the transistor, and Cgm indicates a parasitic capacitance for the main region and Cgs indicates a parasitic capacitance for the sensing region in the transistor. | 2015-02-05 |
| 20150034953 | SEMICONDUCTOR FUSE WITH ENHANCED POST-PROGRAMMING RESISTANCE - Post programming resistance of a semiconductor fuse is enhanced by using an implantation to form an amorphous silicon layer and to break up an underlying high-κ/metal gate. Embodiments include forming a shallow trench isolation (STI) region in a silicon substrate, forming a high-κ dielectric layer on the STI region, forming a metal gate on the high-κ dielectric layer, forming a polysilicon layer over the metal gate, performing an implantation to convert the polysilicon layer into an amorphous silicon layer, wherein the implantation breaks up the metal gate, and forming a silicide on the amorphous silicon layer. By breaking up the metal gate, electrical connection of the fuse contacts through the metal gate is eliminated. | 2015-02-05 |
| 20150034954 | SEMICONDUCTOR DEVICE - Solved is a problem of attenuation of output amplitude due to a threshold value of a TFT when manufacturing a circuit with TFTs of a single polarity. In a capacitor ( | 2015-02-05 |
| 20150034955 | THIN FILM TRANSISTOR ARRAY SUBSTRATE - A pixel electrode is connected to a drain electrode of TFT via a first aperture formed on a second interlayer insulating film, a second aperture, which includes a bottom portion of the first aperture and is formed on a common electrode, and a third aperture, which is included in the bottom portion of the first aperture and is formed on a first interlayer insulating film and a third interlayer insulating film. The common electrode is connected to a common wiring via a fourth aperture formed on the second interlayer insulating film, and a fifth aperture that is included in a bottom portion of the fourth aperture and is formed on the first interlayer insulating film, and a contact electrode that is formed in the fourth aperture and the fifth aperture. | 2015-02-05 |
| 20150034956 | ARRAY SUBSTRATE FOR LIQUID CRYSTAL DISPLAY AND MANUFACTURING METHOD THEREOF - An array substrate for a liquid crystal display (LCD) and manufacturing method thereof are provided. The array substrate for a liquid crystal display (LCD) includes: a substrate, including: a gate electrode, a pixel electrode, and a common electrode, a gate pad formed on the substrate, and connected to the gate electrode, a gate insulating layer formed on the gate pad, a first protective layer formed on the gate insulating layer, a second protective layer formed on the first protective layer, a first metal layer formed on the second protective layer, and connected to the gate pad through a first contact hole which exposes the gate pad, a third protective layer formed on the first metal layer and the second protective layer, and a second metal layer formed on the third protective layer, and connected to the first metal layer through a second contact hole which exposes the first metal layer. | 2015-02-05 |
| 20150034957 | NORMALLY-OFF ENHANCEMENT-MODE MISFET - The present disclosure relates to an enhancement mode MISFET device. In some embodiments, the MISFET device has an electron supply layer located on top of a layer of semiconductor material. A multi-dielectric layer, having two or more stacked dielectric materials sharing an interface having negative fixed charges, is disposed above the electron supply layer. A metal gate structure is disposed above the multi-dielectric layer, such that the metal gate structure is separated from the electron supply layer by the multi-dielectric layer. The multi-dielectric layer provides fixed charges at interfaces between the separate dielectric materials, which cause the transistor device to achieve a normally off disposition. | 2015-02-05 |
| 20150034958 | HEMT-COMPATIBLE LATERAL RECTIFIER STRUCTURE - The present disclosure relates to a high electron mobility transistor compatible power lateral field-effect rectifier device. In some embodiments, the rectifier device has an electron supply layer located over a layer of semiconductor material at a position between an anode terminal and a cathode terminal. A layer of doped III-N semiconductor material is disposed over the electron supply layer. A layer of gate isolation material is located over the layer of doped III-N semiconductor material. A gate structure is disposed over layer of gate isolation material, such that the gate structure is separated from the electron supply layer by the layer of gate isolation material and the layer of doped III-N semiconductor material. The layer of doped III-N semiconductor material modulates the threshold voltage of the rectifier device, while the layer of gate isolation material provides a barrier that gives the rectifier device a low leakage. | 2015-02-05 |
| 20150034959 | PATTERNED SUBSTRATE AND LIGHT EMITTING DIODE STRUCTURE HAVING THE SAME - A light emitting diode structure includes a patterned substrate, an N-type semiconductor layer, a light emitting layer, and a P-type semiconductor layer. Plural protruding portions are formed on a surface of the substrate. A horizontal projection of each of the protruding portions on the surface of the substrate has a projection width W | 2015-02-05 |
| 20150034960 | METHOD OF MANUFACTURING SEMICONDUCTOR DEVICE - A method of manufacturing a semiconductor device is provided as a semiconductor device manufacturing method that permits an opening to be formed in a good shape in a resist film. This manufacturing method is a semiconductor device manufacturing method having: a step of forming an insulating film | 2015-02-05 |
| 20150034961 | AlN SINGLE CRYSTAL SCHOTTKY BARRIER DIODE AND METHOD OF PRODUCING THE SAME - An AlN single crystal Schottky barrier diode including: an AlN single crystal substrate having a defect density of 10 | 2015-02-05 |
| 20150034962 | INTEGRATED CIRCUIT WITH MATCHING THRESHOLD VOLTAGES AND METHOD FOR MAKING SAME - An integrated circuit having a substrate, a buffer layer formed over the substrate, a barrier layer formed over the buffer layer, and an isolation region that isolates an enhancement mode device from a depletion mode device. The integrated circuit further includes a first gate contact for the enhancement mode device that is disposed in one gate contact recess and a second gate contact for the depletion mode device that is disposed in a second gate contact recess. | 2015-02-05 |
| 20150034963 | SEMICONDUCTOR LIGHT EMITTING ELEMENT - A semiconductor light emitting element in which changes in light distribution characteristics due to inclination angle of side surfaces are suppressed. The semiconductor light emitting element includes a semiconductor structure having a light extracting surface as its upper surface; a reflecting layer disposed on side surfaces of the semiconductor structure; and a positive electrode and a negative electrode disposed on a lower surface of the semiconductor structure. Side surfaces of the semiconductor structure are inclined, expanding upward from the lower surface to the upper surface. At least a portion of each side surface includes a plurality of protrusions, a plurality of recesses, or a combination thereof. | 2015-02-05 |
| 20150034964 | GALLIUM NITRIDE-BASED DIODE AND METHOD OF FABRICATING THE SAME - A GaN-based diode may include an intrinsic GaN-based semiconductor layer, GaN-based semiconductor layers configured to have a first conductivity type and bonded to the intrinsic GaN-based semiconductor layer. A first electrode made of metal is placed on a surface opposite a surface bonded to the GaN-based semiconductor layers of the intrinsic GaN-based semiconductor layer; a second electrode is placed on a surface opposite to a surface bonded to the intrinsic GaN-based semiconductor layer of the GaN-based semiconductor layers of the first conductivity type. Voltage-resistant layers configured to have a second conductivity type are formed in regions of the intrinsic GaN-based semiconductor layer that come in contact with edges of the first electrode. | 2015-02-05 |
| 20150034965 | LIGHT EMITTING DIODE AND METHOD FOR MANUFACTURING SAME - An LED includes a substrate and a semiconductor structure mounted on the substrate. A plurality of first holes and a plurality of second holes are defined in the semiconductor structure. The second holes are located above the first holes and communicate with the first holes. A method for manufacturing the LED is also provided. | 2015-02-05 |
| 20150034966 | NITRIDE-BASED FIELD EFFECT TRANSISTOR AND METHOD OF FABRICATING THE SAME - Disclosed herein is a GaN-based transistor. The GaN-based transistor includes source electrodes, first switching semiconductor layers of a first conductivity type formed under the respective source electrodes, second switching semiconductor layers of a second conductivity type formed under the respective first switching semiconductor layers, and third switching semiconductor layers of the first conductivity type surrounding lower parts of the second switching semiconductor layers and sides of the first switching semiconductor layers and the second switching semiconductor layers. Gates are formed each having vertical faces or inclined faces in which a channel is formed on sides of the first switching semiconductor layer and the second switching semiconductor layer. Gate insulating layers are formed under the gates, and a drain electrode electrically is coupled to the source electrodes along a flow of charges in a vertical direction that passes through the channels. | 2015-02-05 |
| 20150034967 | SEMICONDUCTOR DEVICE - A semiconductor device including a high resistance layer formed on a substrate, the high resistance layer being formed with a semiconductor material doped with as impurity element that makes the semiconductor material highly resistant; a multilayer intermediate layer formed on the high resistance layer; an electron transit layer formed with a semiconductor material on the multilayer intermediate layer; and an electron supply layer formed with a semiconductor material on the electron transit layer, wherein the multilayer intermediate layer is formed with a multilayer film in which a GaN layer and an AlN layer are alternately laminated. | 2015-02-05 |
| 20150034968 | PHOTOELECTRIC CONVERSION ELEMENT, PHOTOELECTRIC CONVERSION SYSTEM, AND METHOD FOR PRODUCTION OF PHOTOELECTRIC CONVERSION ELEMENT - A photoelectric conversion element of an embodiment is a photoelectric conversion element which performs photoelectric conversion by receiving illumination light having n light emission peaks having a peak energy Ap (eV) (where 1≦p≦n and 2≦n) of 1.59≦Ap≦3.26 and a full width at half maximum Fp (eV) (where 1≦p≦n and 2≦n), wherein the photoelectric conversion element includes m photoelectric conversion layers having a band gap energy Bq (eV) (where 1≦q≦m and 2≦m≦n), and the m photoelectric conversion layers each satisfy the relationship of Ap−Fp| 2015-02-05 | |
| 20150034969 | METHOD AND SYSTEM FOR A SEMICONDUCTOR DEVICE WITH INTEGRATED TRANSIENT VOLTAGE SUPPRESSION - A power transistor assembly and method of operating the assembly are provided. The power transistor assembly includes integrated transient voltage suppression on a single semiconductor substrate and includes a transistor formed of a wide band gap material, the transistor including a gate terminal, a source terminal, and a drain terminal, the transistor further including a predetermined maximum allowable gate voltage value, and a transient voltage suppression (TVS) device formed of a wide band gap material, the TVS device formed with the transistor as a single semiconductor device, the TVS device electrically coupled to the transistor between at least one of the gate and source terminals and the drain and source terminals, the TVS device including a breakdown voltage limitation selected to be greater than the predetermined maximum allowable gate voltage value. | 2015-02-05 |
| 20150034970 | SEMICONDUCTOR DEVICE AND METHOD FOR PRODUCING SAME - A semiconductor device of the present invention includes a semiconductor layer made of a wide bandgap semiconductor and a Schottky electrode being in contact with a surface of the semiconductor layer. The semiconductor layer includes a drift layer that forms the surface of the semiconductor layer and a high-resistance layer that is formed on a surface layer portion of the drift layer and that has higher resistance than the drift layer. The high-resistance layer is formed by implanting impurity ions from the surface of the semiconductor layer and then undergoing annealing treatment at less than 1500° C. | 2015-02-05 |
| 20150034971 | SEMICONDUCTOR DEVICE AND METHOD FOR MANUFACTURING SAME - [Problem] To provide an SiC semiconductor device, with which stabilization of high-temperature operation can be achieved by decreasing mobile ions in a gate insulating film, and a method for manufacturing the SiC semiconductor device. | 2015-02-05 |
| 20150034972 | SEMICONDUCTOR DEVICE - A semiconductor device according to an embodiment includes, a first conductivity type semiconductor substrate including one of Si and SiC; a second conductivity type semiconductor region at a surface of the semiconductor substrate, a GaN-based semiconductor layer on the semiconductor substrate, and a lateral semiconductor element at the GaN-based semiconductor layer and above the semiconductor region, the lateral semiconductor element having a first electrode and a second electrode electrically connected to the semiconductor region. | 2015-02-05 |
| 20150034973 | SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING THE SAME - A semiconductor device of an embodiment includes: an n-type first SiC epitaxial layer; a p-type second SiC epitaxial layer provided on the first SiC epitaxial layer and contains a p-type impurity and an n-type impurity, the p-type impurity being an element A, the n-type impurity being an element D, the element A and the element D forming a combination of Al, Ga, or In and N, and/or a combination of B and P, the ratio of the concentration of the element D to the concentration of the element A in the combination(s) being higher than 0.33 but lower than 1.0; n-type first and second SiC regions provided in the surface of the second SiC epitaxial layer; a gate insulating film; a gate electrode; a first electrode provided on the second SiC region; and a second electrode provided on the opposite side from the first electrode. | 2015-02-05 |
| 20150034974 | SEMICONDUCTOR DEVICE - A semiconductor device of an embodiment includes: an n-type first SiC epitaxial layer; a p-type second SiC epitaxial layer on the first SiC epitaxial layer containing a p-type impurity and an n-type impurity, the p-type impurity being an element A, the n-type impurity being an element D, the element A and the element D forming a combination of Al, Ga, or In and N, and/or a combination of B and P, the ratio of the concentration of the element D to the element A being higher than 0.33 but lower than 1.0; a surface region at the surface of the second SiC epitaxial layer containing the element A at a lower concentration than in the second SiC epitaxial layer, the ratio being higher than in the second SiC epitaxial layer; n-type first and second SiC regions; a gate insulating film; a gate electrode; a first electrode; and a second electrode. | 2015-02-05 |
| 20150034975 | OPTOELECTRONIC MODULES THAT HAVE SHIELDING TO REDUCE LIGHT LEAKAGE OR STRAY LIGHT, AND FABRICATION METHODS FOR SUCH MODULES - Various optoelectronic modules are described that include an optoelectronic device (e.g., a light emitting or light detecting element) and a transparent cover. Non-transparent material is provided on the sidewalls of the transparent cover, which, in some implementations, can help reduce light leakage from the sides of the transparent cover or can help prevent stray light from entering the module. Fabrication techniques for making the modules also are described. | 2015-02-05 |
| 20150034976 | LED CHIP-ON-BOARD TYPE FLEXIBLE PCB AND FLEXIBLE HEAT SPREADER SHEET PAD AND HEAT-SINK STRUCTURE USING THE SAME - A chip-on-board LED structure having multiple of LED dies, includes a flexible heat spreading pad for spreading heat and having a planar area; a top flexible foil on the flexible heat spreading pad; a dielectric layer on the first flexible foil; a flexible metal film on the dielectric layer; and an LED die array mounted on and covering a first area of the flexible metal film, wherein the planar area of the flexible heat spreading pad is at least four times larger than the first area of the flexible metal film. | 2015-02-05 |
| 20150034977 | Display Device - A display device includes a plurality of pixels in matrix, a substrate on which the plurality of pixels are formed, and a support member under the substrate. The substrate is arranged on a front surface of the support member and a plurality of recesses are formed on a rear surface of the support member. Each of the substrate and the support member is formed in substantially rectangular shape and has a first side, a second side, a third side facing to the first side, and a fourth side facing to the second side. Each of the plurality of recesses extends in a first direction extending substantially in parallel to the first side and the third side. | 2015-02-05 |
| 20150034978 | LIGHT EMITTER DEVICES AND METHODS FOR LIGHT EMITTING DIODE (LED) CHIPS - Light emitter devices and methods are provided herein. In some aspects, emitter devices and methods provided herein are for light emitting diode (LED) chips, and can include providing a substrate and a plurality of LED chips over the substrate. The devices and methods described herein can further include providing a plurality of integral lenses over the LED chips, where at least some of the lenses can be distorted. In some aspects, the distorted lenses can be compressed towards each other along one or more directions. | 2015-02-05 |
| 20150034979 | LIGHT EMITTING DIODE ASSEMBLY - Disclosed is a light emitting diode assembly. The light emitting diode assembly comprised: a red light emitting diode chip; a short-wavelength light emitting diode chip emitting a light having a wavelength relatively shorter than that of a light emitted from the red light emitting diode chip; a first heat-dispersion member for dispersing most of the heat generated in the short wavelength light emitting diode chip; and a second heat-dispersion member for dispersing most of the heat generated in the red light emitting diode chip. Further, the second heat-dispersion member has heat dispersion performance relatively superior to that of the first heat dispersion member. Thus, spectrum movement in the red light emitted from the red light emitting diode chip may be prevented so as to prevent a color-coordinate transformation during the operation time of same. | 2015-02-05 |
| 20150034980 | PHOSPHOR LED - A phosphor LED for emitting light emitting diode light may include an LED designed for emitting blue primary light; and an LED phosphor designed and arranged such that it is excited by the primary light during operation and emits secondary light as a consequence, said secondary light forming at least a portion of the LED light. The LED phosphor may include a green phosphor and a red phosphor. The green phosphor and the red phosphor may be provided in a ratio such that the light emitting diode light in the CIE standard chromaticity system has a color locus in the green which is spaced apart from the Planckian locus, to be precise by at least 0.01 in terms of absolute value. | 2015-02-05 |
| 20150034981 | CHIP COMPONENT - [Problem] There is a need for a chip component which has excellent mountability, which can accommodate multiple types of requested values with a common basic design, and which has improved geometric accuracy and micromachining accuracy. | 2015-02-05 |
| 20150034982 | LIGHT EMITTING DIODE STRUCTURE - A light emitting diode structure is provided. The light emitting diode structure comprises a substrate, a light emitting multi-layer structure, a first current blocking layer, a first current spreading layer, a second current blocking layer and a second current spreading layer. The light emitting multi-layer structure is formed on the substrate by way of stacking. The first current blocking layer is formed on part of the light emitting multi-layer structure. The first current spreading layer covers the first current blocking layer and the light emitting multi-layer structure. The second current blocking layer is formed on part of the first current spreading layer. An orthogonal projection of the second current blocking layer is disposed in an orthogonal projection of the first current blocking layer. The second current spreading layer covers the second current blocking layer and the first current spreading layer. | 2015-02-05 |
| 20150034983 | LIGHT EMITTING DEVICE AND METHOD FOR PRODUCING SAME - There is provided a light emitting device highly resistant to the environment, and having good heat resistance, light resistance and gas barrier property, and a method for producing same. With the light emitting device, a substrate | 2015-02-05 |
| 20150034984 | METHOD AND APPARATUS FOR MOLDING ENCAPSULANT OF LIGHT EMITTING DEVICE - Disclosed is an apparatus for forming an encapsulation material for a light emitting device. The apparatus for forming an encapsulation material comprises: an upper mold on which is mounted a substrate having a plurality of optical semiconductors; a lower mold arranged opposite the upper mold; a resin-capture space for capturing a resin between the upper mold and the lower mold; and an ejector pin for dividing the resin-capture space into a plurality of spaces at the position where the encapsulating material is formed, thereby dividing the encapsulation material into a plurality of parts formed on the substrate. | 2015-02-05 |
| 20150034985 | SEMICONDUCTOR LIGHT EMITTING DEVICE AND METHOD FOR MANUFACTURING SAME - According to one embodiment, the optical layer has a larger planar size than the semiconductor layer. The optical layer is transmissive to emission light of the light emitting layer. The first insulating film is provided on a side surface of the semiconductor layer continued from the first surface. The metal film includes a first reflective part covering the side surface of the semiconductor layer via the first insulating film. The metal film includes a second reflective part opposed to the optical layer in a region around the side surface of the semiconductor layer and extending from the first reflective part toward a side opposite from the side surface of the semiconductor layer. | 2015-02-05 |
| 20150034986 | LED PACKAGE - An LED package includes a chip carrier, an adhesive layer, one high-voltage LED die, and an encapsulating member. The chip carrier defines a receiving space. The adhesive layer is disposed in the receiving space and has a thermal conductivity of larger than or equal to 1 W/mK. The high-voltage LED die is attached to the adhesive layer to be received in the reflective space and has a top surface formed with a trench. The trench of the high-voltage LED die is disposed at an optical center of the receiving space. The encapsulating member encapsulates the high-voltage LED die and includes a plurality of diffusers. The trench is embedded with the encapsulating member and has a width ranging from 1 μm to 10 μm and a depth of less than or equal to 50 μm. | 2015-02-05 |
| 20150034987 | LIGHT EMITTING DEVICE AND METHOD FOR MANUFACTURING LIGHT EMITTING DEVICE - A semiconductor device includes a substrate; a light emitting element flip-chip mounted on the substrate; a phosphor-containing member provided at least above the light emitting element and separated from the light emitting element; and a first reflecting member configured to cover the phosphor-containing member, at least one of a side faces of the light emitting device having an opening for extracting light emitted from the light emitting element and light wavelength-converted by the phosphor-containing member. | 2015-02-05 |
| 20150034988 | LIGHT EMITTING DEVICE AND LIGHT EMITTING DEVICE PACKAGE - Disclosed are a light emitting device and a light emitting device package. The light emitting device includes a first electrode, a light emitting structure including a first semiconductor layer, an active layer, and a second semiconductor layer on the first electrode, a nano-tube layer including a plurality of carbon nano tubes on the light emitting structure, and a second electrode on the light emitting structure. | 2015-02-05 |
| 20150034989 | ANISOTROPIC CONDUCTIVE ADHESIVE AND METHOD FOR MANUFACTURING SAME, LIGHT-EMITTING DEVICE AND METHOD FOR MANUFACTURING SAME - an anisotropic conductive adhesive which uses conductive particles where a silver-based metal is used as a conductive layer, having high light reflectance and excellent migration resistance is provided. The anisotropic conductive adhesive includes light reflective conductive particles in an insulating adhesive resin. The light reflective conductive particle includes a light reflective metal layer made of a metal alloy including silver, gold and hafnium formed on the surface of a resin particle as a core by sputtering method. The light reflective metal layer is preferably formed having a composition ratio of a silver of at least 50% by weight to at most 80% by weight: a gold of at least 10% by weight to at most 45%: a hafnium of at least 10% by weight to at most 40% by weight, and a total ratio does not exceed 100% by weight. | 2015-02-05 |
| 20150034990 | CONTROLLING LED EMISSION PATTERN USING OPTICALLY ACTIVE MATERIALS - A light emission device comprising a light emitting element, a wavelength conversion (e.g. phosphor) element, and a filter that reduces Color over Angle (CoA) effects by at least partially reflecting light from the light emitting element that strike the filter at near-normal angles of incidence. In some embodiments, a combined phosphor and filter layer is formed over the LED die. The filter may comprise a dispersion of self-aligning moieties, such as dielectric platelets in a film that is vacuum laminated to the LED structure. Xirallic® Galaxy Blue pigment, comprising an aluminium oxide core coated on both sides with thin films of SnO | 2015-02-05 |
| 20150034991 | LIGHT EMITTING DEVICE, LIGHT EMITTING DEVICE PACKAGE - Provided are a light emitting device, a light emitting device package, and a lighting system. The light emitting device includes a light emitting structure including a first conductive type semiconductor layer, a second conductive type semiconductor layer, and an active layer between the first conductive type semiconductor layer and the second conductive type semiconductor layer and a light extraction pattern in which a period (a) exceeds λ/n (where, λ is a wavelength of light emitted from the active layer, and n is a refractive index of the light emitting structure) on the light emitting structure. The period (a) may be in the range of 5×(λ/n)| 2015-02-05 | |
| 20150034992 | LIGHT EMITTING DEVICE - A light emitting device includes a substrate, metallization, a light emitting element, conducting wire, light reflective resin, and insulating material. The metallization is provided on a surface of the substrate that is made of insulating substance. The light emitting element is mounted on the substrate. The conducting wire electrically connects the metallization and the light emitting element. The light reflective resin is provided on the substrate to reflect light from the light emitting element. The insulating material covers at least part of metallization surfaces. The insulating material is established to come in contact with a side of the light emitting element. | 2015-02-05 |
| 20150034993 | SEMICONDUCTOR LIGHT-EMITTING DEVICE - A semiconductor light-emitting device includes a substrate, an LED chip mounted on the substrate, and a resin package covering the LED chip. The substrate includes a base and a wiring pattern formed on the base. The resin package includes a lens. The base includes an upper surface, a lower surface and a side surface extending between the upper surface and the lower surface. The LED chip is mounted on the upper surface of the base. The side surface of the base is oriented in a lateral direction. The wiring pattern includes a pair of first mount portions and a pair of second mount portions. The paired first mount portions are formed on the lower surface of the base. The paired second mount portions are oriented in the lateral direction and offset from the side surface of the base in the lateral direction. | 2015-02-05 |
| 20150034994 | LIGHT-EMITING DEVICE, LIGHT-EMITING DEVICE PACKAGE, METHOD OF MANUFACTURING LIGHT-EMITING DEVICE, AND METHOD OF PACKAGING LIGHT-EMITING DEVICE - A light-emitting device including a phosphor layer, a light-emitting device package employing the light-emitting device, a method of manufacturing the light-emitting device, and a method of packaging the light-emitting device. The light-emitting device includes: a light-transmissive substrate having a top surface, a bottom surface, and side surfaces; a light-emitting unit formed on the top surface of the light-transmissive substrate; and a phosphor layer covering all the side surfaces of the light-transmissive substrate. According to the present invention, chromaticity inferiorities of light emitted from side surfaces of a substrate may be reduced. | 2015-02-05 |
| 20150034995 | SEMICONDUCTOR DEVICE WITH COMBINED PASSIVE DEVICE ON CHIP BACK SIDE - Semiconductor chips are described that combine a semiconductor device and a capacitor onto a single substrate such that the semiconductor device and the capacitor are electrically isolated from each other. In one example, a semiconductor chip includes a substrate having a first side and a second side, wherein the second side is opposite the first side. The semiconductor chip further includes a semiconductor device formed on the first side of the substrate and an electrically insulating layer formed on at least a portion of the second side of the substrate. The semiconductor chip further includes a capacitor device formed on at least a portion of the electrically insulating layer on the second side of the substrate, wherein the capacitor device is electrically insulated from the semiconductor device. | 2015-02-05 |
| 20150034996 | LIGHT-EMITTING DEVICE - A light-emitting device comprises a substrate; a first semiconductor stack formed on the substrate; a connecting part formed on the first semiconductor stack; and a plurality of droplets formed near the connecting part, wherein the plurality of droplets comprises a material same as that of the connecting part. | 2015-02-05 |
| 20150034997 | SEMICONDUCTOR LIGHT EMITTING ELEMENT AND LIGHT EMITTING DEVICE - A semiconductor light emitting element includes a first substrate, a stacked body, an electrode, and a conductive layer. The first substrate has a first face and a first side face. The first side face intersects the first face. The first substrate includes a plurality of conductive portions and a plurality of insulating portions arranged alternately. The stacked body is aligned with the first substrate. The stacked body includes first and second semiconductor layers and a light emitting layer. The electrode is electrically connected to the first semiconductor layer. The conductive layer is electrically connected to at least one of the conductive portions and the second semiconductor layer. At least one of the insulating portions is disposed between the first side face and a portion of the conductive layer nearest to the first side face. | 2015-02-05 |
| 20150034998 | LEAD FRAME, LEAD FRAME WITH RESIN ATTACHED THERETO, RESIN PACKAGE, LIGHT EMITTING DEVICE, AND METHOD FOR MANUFACTURING RESIN PACKAGE - A lead frame includes at least one row of a plurality of unit regions arranged in a first direction. Each of the unit regions includes: a first lead; a second lead; and an isolation region configured to isolate the first lead from the second lead, the isolation region including a bent portion that is located at an end part of the second lead. The first lead has an extending portion extending along the end part of the second lead. The plurality of unit regions includes a first unit region, and a second unit region that is adjacent to the first unit region in the first direction. The first lead of the first unit region is connected to the first lead or second lead of the second unit region via the extending portion. | 2015-02-05 |
| 20150034999 | LIGHT EMITTING DEVICE, LIGHT EMITTING DEVICE PACKAGE, AND LIGHTING SYSTEM - Provided is a light emitting device. The light emitting device includes a light emitting structure layer comprising a first conductive type semiconductor layer, an active layer, and a second conductive type semiconductor layer. A first electrode is connected to the first conductive type semiconductor layer and includes first pad, plurality of first bridge portions and plurality of first contact portions. A current spreading layer is on a top surface of the second conductive type semiconductor layer. An insulation layer is on an upper surface of the first conductive type semiconductor layer and a top surface of the current spreading layer. A second electrode is on a top surface of the current spreading layer. The plurality of first bridge portions are extended from the first pad at an acute angle to each other. | 2015-02-05 |
| 20150035000 | LIGHT EMITTING ELEMENT AND LIGHT EMITTING DEVICE USING THE SAME - An object of the present invention is to provide a light emitting element having slight increase in driving voltage with accumulation of light emitting time. Another object of the invention is to provide a light emitting element having slight increase in resistance value with increase in film thickness. A light emitting element of the invention includes a first layer for generating holes, a second layer for generating electrons and a third layer comprising a light emitting substance between first and second electrodes. The first and third layers are in contact with the first and second electrodes, respectively. The second and third layers are connected to each other so as to inject electrons generated in the second layer into the third layer when applying the voltage to the light emitting element such that a potential of the second electrode is higher than that of the first electrode. | 2015-02-05 |
| 20150035001 | LIGHT-EMITTING DEVICE, ELECTRONIC DEVICE, AND LIGHTING DEVICE - A lightweight flexible light-emitting device that is less likely to be broken is provided. The light-emitting device includes a first flexible substrate, a second flexible substrate, an element layer, a first bonding layer, and a second bonding layer. The element layer includes a light-emitting element. The element layer is provided between the first flexible substrate and the second flexible substrate. The first bonding layer is provided between the first flexible substrate and the element layer. The second bonding layer is provided between the second flexible substrate and the element layer. The first and second bonding layers are in contact with each other on the outer side of an end portion of the element layer. The first and second flexible substrates are in contact with each other on the outer side of the end portions of the element layer, the first bonding layer, and the second bonding layer. | 2015-02-05 |
| 20150035002 | Super Junction Semiconductor Device and Manufacturing Method - A method for manufacturing a super junction semiconductor device includes forming a trench in an n-doped semiconductor body and forming a first p-doped semiconductor layer lining sidewalls and a bottom side of the trench. The method further includes removing a part of the first p-doped semiconductor layer at the sidewalls and at the bottom side of the trench by electrochemical etching, and filling the trench. | 2015-02-05 |
| 20150035003 | DUAL TRENCH-GATE IGBT STRUCTURE - Aspects of the present disclosure describe an IGBT device including a substrate including a bottom semiconductor layer of a first conductivity type and an upper semiconductor layer of a second conductivity type, at least one first gate formed in a corresponding first trench disposed over the substrate, and a second gate formed in a second trench disposed over the bottom semiconductor layer. The first and second trenches are provided with gate insulators on each side of the trenches and filled with polysilicon. The second trench extends vertically to depth deeper than the at least one first trench. The IGBT device further includes a body region of the first conductivity type provided between the at least one first gate and/or the second gate, and at least one stacked layer provided between a bottom of the at least one first gate and a top of the upper semiconductor layer. The at least one stacked layer includes a floating body region of the second conductivity type provided on top of a floating body region of the first conductivity type. It is emphasized that this abstract is provided to comply with rules requiring an abstract that will allow a searcher or other reader to quickly ascertain the subject matter of the technical disclosure. It is submitted with the understanding that it will not be used to interpret or limit the scope or meaning of the claims. | 2015-02-05 |
| 20150035004 | SEMICONDUCTOR DEVICES WITH GRADED DOPANT REGIONS - Most semiconductor devices manufactured today, have uniform dopant concentration, either in the lateral or vertical device active (and isolation) regions. By grading the dopant concentration, the performance in various semiconductor devices can be significantly improved. Performance improvements can be obtained in application specific areas like increase in frequency of operation for digital logic, various power MOSFET and IGBT ICS, improvement in refresh time for DRAM's, decrease in programming time for nonvolatile memory, better visual quality including pixel resolution and color sensitivity for imaging ICs, better sensitivity for varactors in tunable filters, higher drive capabilities for JFET's, and a host of other applications. | 2015-02-05 |
| 20150035005 | MONOLITHIC IGBT AND DIODE STRUCTURE FOR QUASI-RESONANT CONVERTERS - This invention discloses a semiconductor power device formed in a semiconductor substrate. The semiconductor power device further includes a channel stop region near a peripheral of the semiconductor substrate wherein the channel stop region further includes a peripheral terminal of a diode corresponding with another terminal of the diode laterally opposite from the peripheral terminal disposed on an active area of the semiconductor power device. In an embodiment of this invention, the semiconductor power device is an insulated gate bipolar transistor (IGBT). | 2015-02-05 |
| 20150035006 | MANUFACTURING METHOD OF SEMICONDUCTOR DEVICE - A semiconductor device includes a first-conductivity-type semiconductor layer including an active region in which a transistor having impurity regions is formed and a marginal region surrounding the active region, a second-conductivity-type channel layer formed between the active region and the marginal region and forming a front surface of the semiconductor layer, at least one gate trench formed in the active region to extend from the front surface of the semiconductor layer through the channel layer, a gate insulation film formed on an inner surface of the gate trench, a gate electrode formed inside the gate insulation film in the gate trench, and at least one isolation trench arranged between the active region and the marginal region to surround the active region and extending from the front surface of the semiconductor layer through the channel layer, the isolation trench having a depth equal to that of the gate trench. | 2015-02-05 |
| 20150035007 | SILICON CONTROLLED RECTIFIER FOR HIGH VOLTAGE APPLICATIONS - In a silicon-controlled rectifier, an anode region includes p-type anode well regions which are laterally surrounded by an n-type well region. A length of a p-type anode well region, as measured in a first direction, is greater than a width of the p-type anode well region, as measured in a second direction perpendicular to the first direction. A p-type well region meets the n-type well region at a junction, wherein the junction extends between the p-type well region and n-type well region in the second direction. A cathode region includes a plurality of n-type cathode well regions which are formed in the p-type well region. A length of an n-type cathode well region, as measured in the first direction, is greater than a width of the n-type cathode well region, as measured in the second direction. | 2015-02-05 |
| 20150035008 | FINFET DEVICES INCLUDING HIGH MOBILITY CHANNEL MATERIALS WITH MATERIALS OF GRADED COMPOSITION IN RECESSED SOURCE/DRAIN REGIONS AND METHODS OF FORMING THE SAME - A finFET device can include a high mobility semiconductor material in a fin structure that can provide a channel region for the finFET device. A source/drain recess can be adjacent to the fin structure and a graded composition epi-grown semiconductor alloy material, that includes a component of the high mobility semiconductor material, can be located in the source/drain recess. | 2015-02-05 |
| 20150035009 | FIN FIELD EFFECT TRANSISTOR, SEMICONDUCTOR DEVICE INCLUDING THE SAME AND METHOD OF FORMING THE SEMICONDUCTOR DEVICE - A fin field effect transistor includes a first fin structure and a second fin structures both protruding from a substrate, first and second gate electrodes on the first and second fin structures, respectively, and a gate dielectric layer between each of the first and second fin structures and the first and second gate electrodes, respectively. Each of the first and second fin structures includes a buffer pattern on the substrate, a channel pattern on the buffer pattern, and an etch stop pattern provided between the channel pattern and the substrate. The etch stop pattern includes a material having an etch resistivity greater than that of the buffer pattern. | 2015-02-05 |
| 20150035010 | SEMICONDUCTOR APPARATUS AND MANUFACTURING METHOD OF THE SEMICONDUCTOR APPARATUS - Provided is a semiconductor apparatus including a channel layer, an upper barrier layer that is provided on the channel layer, a first barrier layer that constitutes a boundary layer on a side of the channel layer in the upper barrier layer, a second barrier layer that is provided in a surface layer of the upper barrier layer, a low-resistance region that is provided in at least a surface layer in the second barrier layer, a source electrode and a drain electrode that are connected to the second barrier layer, at positions across the low-resistance region, a gate insulating film that is provided on the low-resistance region, and a gate electrode that is provided above the low-resistance region via the gate insulating film. | 2015-02-05 |
| 20150035011 | HETEROJUNCTION BIPOLAR TRANSISTORS WITH REDUCED PARASITIC CAPACITANCE - Fabrication methods, device structures, and design structures for a heterojunction bipolar transistor. A trench isolation region and a collector are formed in a semiconductor substrate. The collector is coextensive with the trench isolation region. A first semiconductor layer is formed that includes a of single crystal section disposed on the collector and on the trench isolation region. A second semiconductor layer is formed that includes a single crystal section disposed on the single crystal section of the first semiconductor layer and that has an outer edge that overlies the trench isolation region. The section of the first semiconductor layer has a second width greater than a first width of the collector. The section of the second semiconductor layer has a third width greater than the second width. A cavity extends laterally from the outer edge of section of the second semiconductor layer to the section of the first semiconductor layer. | 2015-02-05 |
| 20150035012 | Methods and Apparatus for Bipolar Junction Transistors and Resistors - Methods and apparatus for bipolar junction transistors (BJTs) are disclosed. A BJT comprises a collector made of p-type semiconductor material, a base made of n-type well on the collector; and an emitter comprising a p+ region on the base and a SiGe layer on the p+ region. The BJT can be formed by providing a semiconductor substrate comprising a collector, a base on the collector, forming a sacrificial layer on the base, patterning a first photoresist on the sacrificial layer to expose an opening surrounded by a STI within the base; implanting a p-type material through the sacrificial layer into an area of the base, forming a p+ region from the p-type implant; forming a SiGe layer on the etched p+ region to form an emitter. The process can be shared with manufacturing a polysilicon transistor up through the step of patterning a first photoresist on the sacrificial layer. | 2015-02-05 |
| 20150035013 | IMAGE PICKUP DEVICE - An image pickup device according to the present invention is an image pickup device in which a plurality of pixel are arranged in a semiconductor substrate. Each of the plurality of pixels includes a photoelectric conversion element, a floating diffusion (FD) region, a transfer gate that transfers charges in the first semiconductor region to the FD region, and an amplification transistor whose gate is electrically connected to the FD region. The photoelectric conversion element has an outer edge which has a recessed portion in plan view, a source region and a drain region of the amplification transistor are located in the recessed portion, and the FD region is surrounded by the photoelectric conversion region or is located in the recessed portion in plan view. | 2015-02-05 |
| 20150035014 | PIN DIODE STRUCTURE HAVING SURFACE CHARGE SUPPRESSION - A semiconductor structure having: a silicon structure; and a plurality of laterally spaced PiN diodes formed in the silicon structure; and a surface of the silicon structure configured to reduce reverse bias leakage current through the PiN diodes. In one embodiment, a gate electrode structures is disposed on a surface of the silicon structure, the gate electrode structure having portions disposed between adjacent pairs of the diodes, the gate structure being biased to prevent leakage current through the diodes. | 2015-02-05 |
| 20150035015 | METHOD OF MANUFACTURING SEMICONDUCTOR DEVICE AND SEMICONDUCTOR DEVICE - To provide a semiconductor device having a vertical JFET excellent in off-state performance without reducing a production yield. A gate region quadrangular in the cross-section along a channel width direction is formed below a source region by impurity ion implantation. By first etching, the source region over the upper surface of the gate region is removed to separate therebetween. Then, the upper surface of the gate region is processed by second etching having an etching rate lower at the side surface than at the center of the gate region. The resulting gate region has a lower surface parallel to the substrate surface and an upper surface below a boundary between the source region and the channel formation region and having, in the cross-section along the channel width direction, a downward slope from the side surface to the center. As a result, a channel length with reduced variations can be obtained. | 2015-02-05 |
| 20150035016 | NITRIDE SPACER FOR PROTECTING A FIN-SHAPED FIELD EFFECT TRANSISTOR (FINFET) DEVICE - Approaches for protecting a semiconductor device (e.g., a fin field effect transistor device (FinFET)) using a nitride spacer are provided. Specifically, a nitride spacer is formed over an oxide and a set of fins of the FinFET device to mitigate damage during subsequent processing. The nitride spacer is deposited before the block layers to protect the oxide on top of a set of gates in an open area of the FinFET device uncovered by a photoresist. The oxide on top of each gate will be preserved throughout all of the block layers to provide hardmask protection during subsequent source/drain epitaxial layering. Furthermore, the fins that are open and uncovered by the photoresist or the set of gates remain protected by the nitride spacer. Accordingly, fin erosion caused by amorphization of the fins exposed to resist strip processes is prevented, resulting in improved device yield. | 2015-02-05 |
| 20150035017 | Contact Structure of Semiconductor Device - The disclosure relates to a semiconductor device. An exemplary structure for a contact structure for a semiconductor device comprises a substrate comprising a major surface; a fin structure extending upward from the substrate major surface, wherein the fin structure comprises a first fin, a second fin, and a third fin between the first fin and second fin; a first germanide over the first fin, wherein a first bottom surface of the first germanide has a first acute angle to the major surface; a second germanide over the second fin on a side of the third fin opposite to first germanide substantially mirror-symmetrical to each other; and a third germanide over the third fin, wherein a third bottom surface of the third germanide has a third acute angle to the major surface less than the first acute angle. | 2015-02-05 |
| 20150035018 | DEVICES AND METHODS OF FORMING BULK FINFETS WITH LATERAL SEG FOR SOURCE AND DRAIN ON DIELECTRICS - Devices and methods for forming semiconductor devices with FinFETs are provided. One intermediate semiconductor device includes, for instance: a substrate with at least one fin with at least one channel; at least one gate over the channel; at least one hard-mask over the gate; and at least one spacer disposed over the gate and hard-mask. One method includes, for instance: obtaining an intermediate semiconductor device; forming at least one recess into the substrate, the recess including a bottom and at least one sidewall exposing a portion of the at least one fin; depositing a dielectric layer into the at least one recess; removing at least a portion of the dielectric layer to form a barrier dielectric layer; and performing selective epitaxial growth in the at least one recess over the barrier dielectric layer. | 2015-02-05 |
| 20150035019 | METHOD OF FORMING FINS FROM DIFFERENT MATERIALS ON A SUBSTRATE - A method of forming fins of different materials includes providing a substrate with a layer of a first material having a top surface, masking a first portion of the substrate leaving a second portion of the substrate exposed, etching a first opening at the second portion, forming a body of a second material in the opening to a level of the top surface of the layer of the first material, removing the mask, and forming fins of the first material at the first portion and forming fins of the second material at the second portion. A finFET device having fins formed of at least two different materials is also disclosed. | 2015-02-05 |
| 20150035020 | Systems and Methods for Fabricating Semiconductor Devices at Different Levels - Systems and methods are provided for fabricating semiconductor device structures on a substrate. For example, a substrate including a first region and a second region is provided. One or more first semiconductor device structures are formed on the first region. One or more semiconductor fins are formed on the second region. One or more second semiconductor device structures are formed on the semiconductor fins. A top surface of the semiconductor fins is higher than a top surface of the first semiconductor device structures. | 2015-02-05 |
| 20150035021 | MISFET Device and Method of Forming the Same - Embodiments of the present disclosure include a method for forming a semiconductor device, a method for forming a MISFET device, and a MISFET device. An embodiment is a method for forming a semiconductor device, the method including forming a source/drain over a substrate, forming a first etch stop layer on the source/drain, and forming a gate dielectric layer on the first etch stop layer and along the substrate. The method further includes forming a gate electrode on the gate dielectric layer, forming a second etch stop layer on the gate electrode, and removing the gate dielectric layer from over the source/drain. | 2015-02-05 |
| 20150035022 | SEMICONDUCTOR DEVICE HAVING PASSING GATE AND METHOD FOR FABRICATING THE SAME - A semiconductor device includes passing gates. In the semiconductor device, a passing gate formed in a device isolation film is vertically positioned at a deeper and lower level than an operation gate formed in an active region defined by the device isolation film such that the passing gate does not overlap with a junction region. A step difference is formed in a storage node junction region, and thus a contact area between a storage node contact and the storage node junction region is increased, resulting in the improvement of operational characteristics of the semiconductor device. | 2015-02-05 |
| 20150035023 | SEMICONDUCTOR DEVICE AND METHOD FOR FABRICATING THE SAME - A semiconductor device may include first and second fins formed side by side on a substrate, a first elevated doped region formed on the first fin and having a first doping concentration of impurities, a second elevated doped region formed on the second fin, and a first bridge connecting the first elevated doped region and the second elevated doped region to each other. Methods of manufacturing such a semiconductor device are also disclosed. | 2015-02-05 |
| 20150035024 | TRANSISTOR AND METHOD OF MANUFACTURING THE SAME - A transistor includes a substrate, a gate structure and impurity regions. The substrate is divided into a field region and an active region by an isolation layer pattern. The field region has the isolation layer pattern thereon, and the active region has no isolation layer pattern thereon. The gate structure includes a central portion and an edge portion. The central portion is on a middle portion of the active region along a first direction and has a first width in a second direction substantially perpendicular to the first direction. The edge portion is on at least one end portion of the active region in the first direction and connected to the central portion and has a second width smaller than the first width in the second direction. The impurity regions are at upper portions of the active region adjacent to both end portions of the gate structure in the second direction. | 2015-02-05 |
| 20150035025 | SEMICONDUCTOR INTEGRATED CIRCUIT DEVICES INCLUDING GATES HAVING CONNECTION LINES THEREON - Provided are semiconductor integrated circuit (IC) devices including gate patterns having a step difference therebetween and a connection line interposed between the gate patterns. The semiconductor IC device includes a semiconductor substrate including a peripheral active region, a cell active region, and a device isolation layer. Cell gate patterns are disposed on the cell active region and the device isolation layer. A peripheral gate pattern is disposed on the peripheral active region. A cell electrical node is disposed on the cell active region adjacent to the cell gate patterns. Peripheral electrical nodes are disposed on the peripheral active region adjacent to the peripheral gate pattern. Connection lines are disposed on the cell gate patterns disposed on the device isolation layer. The connection lines are connected between the cell gate patterns and the peripheral gate pattern. | 2015-02-05 |
| 20150035026 | MIDDLE-OF-LINE BORDERLESS CONTACT STRUCTURE AND METHOD OF FORMING - Various embodiments disclosed include semiconductor structures and methods of forming such structures. In one embodiment, a method includes: providing a semiconductor structure including: a substrate; at least one gate structure overlying the substrate; and an interlayer dielectric overlying the substrate and the at least one gate structure; removing the ILD overlying the substrate to expose the substrate; forming a silicide layer over the substrate; forming a conductor over the silicide layer and the at least one gate structure; forming an opening in the conductor to expose a portion of a gate region of the at least one gate structure; and forming a dielectric in the opening in the conductor. | 2015-02-05 |
| 20150035027 | SEMICONDUCTOR COMPONENT WITH A WINDOW OPENING AS AN INERFACE FOR AMBIENT COUPLING - A window opening in a semiconductor component is produced on the basis of a gate structure which serves as an efficient etch resist layer in order to reliably etch an insulation layer stack without exposing the photosensitive semiconductor area. The polysilicon in the gate structure is then removed on the basis of an established gate etching process, with the gate insulation layer preserving the integrity of the photosensitive semiconductor material. | 2015-02-05 |
| 20150035028 | Image Sensor with Buried Light Shield and Vertical Gate - A pixel in an image sensor can include a photodetector and a storage region disposed in one substrate, or a photodetector disposed in one substrate and a storage region in another substrate. A buried light shield is disposed between the photodetector and the storage region. A sense region, such as a floating diffusion, can be adjacent to the storage region, with the buried light shield disposed between the photodetector and the storage and sense regions. When the photodetector and the storage region are disposed in separate substrates, a vertical gate can be formed through the buried light shield and used to initiate the transfer of charge from the photodetector and the storage region. A transfer channel formed adjacent to, or around the vertical gate provides a channel for the charge to transfer from the photodetector to the storage region. | 2015-02-05 |
| 20150035029 | IMAGING DEVICE, ELECTRONIC APPARATUS, AND METHOD OF MANUFACTURING IMAGING DEVICE - An imaging device includes: a photodiode configured to perform photoelectric conversion and to generate electric charge in accordance with an amount of received light; a floating diffusion section configured to accumulate the electric charge generated in the photodiode; a reading circuit configured to output a pixel signal having a voltage in accordance with a level of the electric charge accumulated in the floating diffusion section, the reading circuit including one or a plurality of transistors each having a gate that is electrically connected to a wiring used for selecting a pixel; and an insulating section extending into part or whole of a bottom surface of the floating diffusion section, part or whole of bottom surfaces of source-drain regions in the one or the plurality of transistors, or both. The photodiode, the floating diffusion section, the reading circuit, and the insulating section are provided in a semiconductor layer. | 2015-02-05 |
| 20150035030 | SOLID-STATE IMAGING APPARATUS FOR CAUSING AN FD CAPACITOR VALUE TO BE VARIABLE WITHOUT INCREASING A NUMBER OF ELEMENTS - A solid-state imaging apparatus wherein an FD capacitor value is variable without increasing the number of elements. There is provided a solid-state imaging apparatus including a plurality of photoelectric conversion elements arranged in a horizontal direction and a vertical direction, for generating an electric charge by photoelectric conversion; a plurality of transfer transistors each connected to each of the photoelectric conversion elements, for transferring the electric charge generated by the plurality of photoelectric conversion elements; a plurality of floating diffusion regions for holding the electric charge transferred by the transfer transistors; a plurality of amplifiers each connected to each of the floating diffusion regions, for amplifying a signal based on the electric charge in the plurality of floating diffusion regions; and a connecting unit for connecting and disconnecting between the plurality of floating diffusion regions. | 2015-02-05 |
