| 06th week of 2009 patent applcation highlights part 45 |
| Patent application number | Title | Published |
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| 20090035866 | Method and device for test sample loading - An automated analyzer is configured to receive and analyze samples provided to the automated analyzer in primary sample containers. The automated analyzer comprises a sample retention unit, at least one transport device, and at least one aspiration device. The sample retention unit is configured to receive and retain a plurality of sample retention vessels. The sample retention unit may comprise a sample storage unit, an analytic unit, or other processing unit within the automated analyzer that retains a sample for some purpose. The transport device is configured to receive a first primary sample container containing a first sample and deliver the first primary sample container to the sample retention unit as one of the plurality of sample retention vessels. The aspiration device is configured to receive a second sample from a second primary sample container and deliver the second sample into one of the plurality of sample retention vessels. | 2009-02-05 |
| 20090035867 | AUTOMATIC ANALYZER AND METHOD FOR USING THE SAME - Disclosed herein is an automatic analyzer that is capable of reducing a user's workload required when a reagent is placed, and thereby facilitating change of the operation mode of the automatic analyzer. | 2009-02-05 |
| 20090035868 | RAPID PROTEIN LABELING AND ANALYSIS - The present invention provides methods and compositions for labeling, separating and analyzing proteins, particularly a specific protein of interest within a cell lysate or in a mixture of proteins. The proteins are labeled with an amine reactive or thiol reactive fluorescent dye, or an amine reactive fluorogenic reagent that becomes fluorescent upon reacting to amine groups located on the protein. Following the labeling step, the proteins within the mixture can be separated and analyzed. In a further embodiment, a tag binding fluorogenic reagent that can bind to a tag on a tagged protein is added to specifically label the protein of interest. | 2009-02-05 |
| 20090035869 | METHOD AND SYSTEM FOR GENETIC PATTERN RECOGNITION - A method and an system for the detection of nucleic acid oligonucleotides is characterized in that said detection corresponds to a capacitive reading of the melting point of complexes obtained by hybridization of said oligonucleotides and suitably modified molecules of oligonucleotide probes. | 2009-02-05 |
| 20090035870 | Particle sensor - A particle sensor is provided having a first temperature sensing device having a sensing surface exposed to particles contained within a fluid. The sensing surface is at least partially coated with a catalyst for promoting an exothermic reaction with at least a portion of the particles. The particle sensor also has a second temperature sensing device positioned at a location substantially thermally isolated from thermal energy generated by the exothermic reaction. | 2009-02-05 |
| 20090035871 | Method for measuring maturity degree of compost and measuring solution - A method for measuring the maturity degree of a compost capable of determining the maturity degree of a compost purportedly of a product in a short period of time (10 to 30 minutes) by compost manufacturers, users and even those with insufficient expertise and experiences such as buyers in the distribution industry on site and also capable of determining it according to the maturity stage in an easy and cost-effective manner, and a measuring solution. A specific measuring solution is added to the compost to flocculate a compost extract containing humic-like substance and decomposed organic matter, and a liquid phase is acquired by precipitating the compost extract by the solid/liquid separation. Based on the correlation in which the absorbency of the liquid phase declines as the compost becomes more mature, the maturity degree of the compost is measured from the color contrasting density of the liquid phase. | 2009-02-05 |
| 20090035872 | FLUIDICS SYSTEM - The present invention provides a fluidics system and a method for selectively drawing fluid from at least one selected reservoir into a channel by providing a negative pressure source downstream of the fluid and channel and selectively back filling the selected reservoir with a gas. | 2009-02-05 |
| 20090035873 | Sample analyzer, sample analyzing method, and computer program product - The present invention is to present a sample analyzer which is automated even when measuring a small amount sample and is capable of improving a measurement precision. The sample analyzer S comprises a sample preparation section for preparing a measurement sample; a detector D | 2009-02-05 |
| 20090035874 | THERAPEUTIC AGENTS AND METHODS FOR CARDIOVASCULAR DISEASE - The present invention provides methods and agents for treating subjects who have or are at risk of developing or having cardiovascular disease. Such agents inhibit binding of myeloperoxidase (MPO) to a molecule comprising the MPO binding site of apolipoprotein A-1 (apoA-1) and include a peptide fragment of apoA-1 comprising at least 4 contiguous amino acids in SEQ ID. NO: 2, a modified form of the apo-1 fragment comprising one or more D amino acids, a retro-inverso form of the apoA-1 peptide fragment, an organo-mimetic of the apoA-1 peptide fragment, a peptide-mimetic of the apoA1 peptide fragment, or a nucleic acid encoding the apo A-1 peptide fragment. The present invention also provides methods of identifying or screening test agents for treating subjects having or at risk of having or developing CVD. The method comprises incubating one or more test agents and MPO with a molecule comprising the MPO binding site of apoA-1 under conditions which permit binding of MPO to the MPO binding site and determining whether one or more of the agents inhibit such binding. | 2009-02-05 |
| 20090035875 | Cytochrome C And Leucine-Rich Alpha-2-Glycoprotein-1 Assays, Methods, And Antibodies - The present invention relates generally to assays and methods involving Cytochrome c (Cyt c) and leucine-rich alpha-2-glycoprotein-1 (LRG), and related antibodies. In an embodiment, the invention includes an isolated antibody produced by a hybridoma cell line having ATCC Accession Number PTA-8131, or antibody fragment thereof that specifically binds to leucine-rich alpha-2-glycoprotein-1. In an embodiment, the invention includes a hybridoma cell line producing such an antibody or antibody fragment. In an embodiment, the invention includes a kit including such an antibody. Other embodiments are included herein. | 2009-02-05 |
| 20090035876 | Electrochemical Assay - A method of determining the presence or amount of analyte in a fluid sample, which comprises: contacting a fluid sample with a binding reagent that comprises a plurality of cleavable species and wherein said species, when cleaved, are detectable using electrochemical means; separating any binding reagent-analyte complex that forms from the unbound binding reagent; cleaving the cleavable species from the immobilized binding reagent-analyte complex; and detecting the cleaved species using electrochemical means. | 2009-02-05 |
| 20090035877 | METHODS OF FORMING A FERROELECTRIC LAYER AND METHODS OF MANUFACTURING A FERROELECTRIC CAPACITOR INCLUDING THE SAME - A method of forming a ferroelectric layer is provided. A metal-organic source gas is provided into a chamber into which an oxidation gas is provided for a first time period to form ferroelectric grains on a substrate. A ferroelectric layer is formed by performing at least twice a step of providing a metal-organic source gas into the chamber during the first time period using a pulse method to grow the ferroelectric grains. | 2009-02-05 |
| 20090035878 | Plasma Doping Method and Apparatus - There are provided a plasma doping method and apparatus which is excellent in a repeatability and a controllability of an implanting depth of an impurity to be introduced into a sample or a depth of an amorphous layer. | 2009-02-05 |
| 20090035879 | LASER DICING DEVICE AND LASER DICING METHOD - An object is to provide a laser dicing apparatus and a laser dicing method capable of speedily performing high-quality dicing without causing any working defect even in a case where wafers varying in thickness are supplied. The laser dicing apparatus is provided with a measuring device which measures thickness of a wafer W, a recording device which stores a database in which modified region forming conditions associated with different thicknesses of the wafer W are described, and a control device which controls the laser dicing apparatus by automatically selecting, from the database, on the basis of the thickness of the wafer measured by the measuring device, the modified region forming conditions corresponding to the measured thickness of the wafer W. The optimum modified region forming conditions are thereby automatically set, so that even in a case where wafers W differing in thickness are supplied, high-quality dicing can be speedily performed without causing a working defect. | 2009-02-05 |
| 20090035880 | Maunfacturing method for exposure mask, generating method for mask substrate information, mask substrate, exposure mask, manufacturing method for semiconductor device and server - There is disclosed a manufacturing method for exposure mask, which comprises acquiring a first information showing surface shape of surface of each of a plurality of mask substrates, and a second information showing the flatness of the surface of each of mask substrates before and after chucked on a mask stage of an exposure apparatus, forming a corresponding relation of each mask substrate, the first information and the second information, selecting the second information showing a desired flatness among the second information of the corresponding relation, and preparing another mask substrate having the same surface shape as the surface shape indicated by the first information in the corresponding relation with the selected second information, and forming a desired pattern on the above-mentioned another mask substrate. | 2009-02-05 |
| 20090035881 | METHOD FOR MANUFACTURING SEMICONDUCTOR DEVICE - A burn-in input signal input to a burn-in circuit is delivered to an internal circuit through a selector. In response to a control signal from the burn-in circuit, the selector selects either the burn-in input signal or an input signal for operating the internal circuit. In the burn-in test process, a portion of an output signal is monitored to determine the degree of degradation of the internal circuit. | 2009-02-05 |
| 20090035882 | METHOD AND APPARATUS FOR AFFECTING SURFACE COMPOSITION OF CIGS ABSORBERS FORMED BY TWO-STAGE PROCESS - A method and system to modify a surface composition of thin film Group IBIIIA VIA solar cell absorbers having non-uniformly distributed Group IIIA materials or graded materials, such as Indium (In), gallium (Ga) and aluminum (Al). The graded materials distribution varies between the surface and the bottom of the absorber layer such that a molar ratio of (Ga+Al)/(Ga+Al+In) is the highest at the bottom of the absorber layer and the lowest at the surface of the absorber. Within the bulk of the absorber, the molar ratio gradually changes between the bottom and the surface of the absorber. In one embodiment, the surface composition of a graded absorber layer may be modified by removing a top portion or slice of the absorber layer, where the molar ratio is low so as to expose the inner portions of the absorber layer having a higher molar ratio of graded materials. | 2009-02-05 |
| 20090035883 | Auto Routing for Optimal Uniformity Control - A method for improving within-wafer uniformity is provided. The method includes forming an electrical component by a first process step and a second process step, wherein the electrical component has a target electrical parameter. The method includes providing a first plurality of production tools for performing the first process step; providing a second plurality of production tools for performing the second process step; providing a wafer; performing the first process step on the wafer using one of the first plurality of production tools; and selecting a first route including a first production tool from the second plurality of production tools. A within-wafer uniformity of the target electrical parameter on the wafer manufactured by the first route is greater than a second route including a second production tool in the second plurality of production tools. | 2009-02-05 |
| 20090035884 | METHOD FOR MANUFACTURING SURFACE-EMITTING LASER - Provided is a method for manufacturing a surface-emitting laser capable of forming a photonic crystal structure inside a semiconductor highly accurately and easily without direct bonding. It is a method by laminating on a substrate a plurality of semiconductor layers including an active layer and a semiconductor layer having a photonic crystal structure formed therein, the method including the steps of forming a second semiconductor layer on a first semiconductor layer to form the photonic crystal structure, forming a plurality of microholes in the second semiconductor layer, forming a low refractive index portion in a part of the first semiconductor layer via the plurality of microholes thereby to provide the first semiconductor layer with the photonic crystal structure having a one-dimensional or two-dimensional refractive index distribution in a direction parallel to the substrate, and forming a third semiconductor layer by crystal regrowth from a surface of the second semiconductor layer. | 2009-02-05 |
| 20090035885 | METHODS OF FORMING LIGHT-EMITTING STRUCTURES - Methods of forming light-emitting structures, as well as related devices and/or systems are described. In some cases, the methods utilize a layer transfer and/or layer separation step(s) used to form such structures. | 2009-02-05 |
| 20090035886 | PREDOPED TRANSFER GATE FOR A CMOS IMAGE SENSOR - A novel CMOS image sensor Active Pixel Sensor (APS) cell structure and method of manufacture. Particularly, a CMOS image sensor APS cell having a predoped transfer gate is formed that avoids the variations of V | 2009-02-05 |
| 20090035887 | SOLID-STATE IMAGE PICKUP ELEMENT, METHOD FOR MANUFACTURING SUCH SOLID-STATE IMAGE PICKUP ELEMENT AND OPTICAL WAVEGUIDE FORMING DEVICE - A solid-state imaging device of the present invention includes a base | 2009-02-05 |
| 20090035888 | TWO EPITAXIAL LAYERS TO REDUCE CROSSTALK IN AN IMAGE SENSOR - An image sensor includes a substrate of a first conductivity type having an image area with a plurality of photosensitive sites, wherein a portion of the charge generated in response to light is collected in the pixel; and a subcollector of a second conductivity spanning the image area that collects another portion of the generated charge that would have otherwise diffused to adjacent photosensitive sites. | 2009-02-05 |
| 20090035889 | CMOS Image Sensor and Method for Manufacturing the Same - Provided is a CMOS image sensor. The CMOS image sensor can include a semiconductor substrate, a blue photodiode region, a red photodiode region, a green photodiode region, an overcoat layer, and microlenses. The substrate can have a first photodiode region, a second photodiode region, and a transistor region. The blue photodiode region is formed having a predetermined depth in the first photodiode region. The red photodiode region is formed in the first photodiode region having a depth greater than that of the blue photodiode region with a gap separating the red photodiode region from the blue photodiode region. The green photodiode region is formed in the second photodiode region having a depth between the depths of the blue and red photodiode regions. The overcoat layer is formed on the semiconductor substrate, and microlenses are formed on the overcoat layer to correspond to the first and second photodiode regions. | 2009-02-05 |
| 20090035890 | TECHNIQUES FOR DIRECT ENCASEMENT OF CIRCUIT BOARD STRUCTURES - A technique for processing an electronic apparatus (e.g., manufacturing an assembled circuit board, treating an assembled circuit board, etc.) involves applying encasement material to an area of the circuit board assembly while leaving at least a portion of the circuit board assembly exposed. The technique further involves causing the applied encasement material to harden (e.g., heating the encasement material in a curing oven, applying radiation, providing a chemical catalyst, etc.). Application and hardening of the encasement material may take place shortly after circuit board assembly (e.g., by automated equipment at a manufacturing facility in order to treat newly assembled boards) or at some later time in the field (e.g., by a technician servicing a legacy board). | 2009-02-05 |
| 20090035891 | METHOD AND APPARATUS FOR FLIP-CHIP BONDING - Provided are a laser flip-chip bonding method having high productivity and excellent bonding reliability and a flip-chip bonder employing the same. The flip-chip bonder includes: a bonding stage on which a substrate rests; a bonding head picking up a semiconductor chip and attaching the semiconductor chip to the substrate; and a semiconductor chip heating unit heating the semiconductor chip to a bonding temperature. The semiconductor chip heating unit includes: a laser light source; and a lens assembly refracting a laser beam emitted by the laser light source to a top surface of the semiconductor chip so that a central position of the laser beam varies across the top surface of the semiconductor chip. | 2009-02-05 |
| 20090035892 | Component Bonding Method, Component Laminating Method And Bonded Component Structure - It is an object of the invention to provide a component bonding method and a component laminating method that can improve productivity in the heat pressing process. | 2009-02-05 |
| 20090035893 | SEMICONDUCTOR ELEMENT AND A PRODUCING METHOD FOR THE SAME, AND A SEMICONDUCTOR DEVICE AND A PRODUCING METHOD FOR THE SAME - A columnar bump formed of copper etc. is formed on a wiring film of a semiconductor chip through an interconnected film and an adhesive film in a wafer unit by electrolytic plating in which package formation is possible. An oxidation prevention film is formed of such as gold on an upper surface or a part of the upper surface and side surface. A wet prevention film of such as an oxide film is formed on the columnar bump side as needed. If this bump is soldered to the pad on a packaging substrate, solder gets wet in the whole region of the columnar bump upper surface and only a part of the side surface. Stabilized and reliable junction form can be thus formed. Moreover, since the columnar bump does not fuse, the distance between a semiconductor board and a packaging board is not be narrowed by solder. | 2009-02-05 |
| 20090035894 | Apparatus and method for bonding silicon wafer to conductive substrate - A system and method is disclosed for bonding a substrate to a semiconductor die that is prone to curling when subjected to an elevated temperature in a solder reflow oven, for example, thereby improving the electrical and mechanical bonding for large dies, wafers, chips, and photovoltaic cells. In one embodiment, the substrate is adapted to curl to the same degree as the die to form a uniform gap between the substrate and die across the boundary there between. In another embodiment, solder used to bond the die and substrate is applied such that the volume deposited varies based on the expected gap between the die and substrate when heated to the melting temperature of the solder. | 2009-02-05 |
| 20090035895 | CHIP PACKAGE AND CHIP PACKAGING PROCESS THEREOF - A chip package comprises a substrate, a chip, a conductive layer and a molding compound. The substrate has a carrying surface and at least a ground pad disposed on the carrying surface. The chip has an active surface and a back surface opposite thereto. The chip is bonded to the substrate with the active surface facing towards the carrying surface of the substrate, wherein the ground pad is disposed outside of the chip. The conductive layer covers the chip and a portion of the carrying surface, and electrically connects to the ground pad. The molding compound is disposed on the carrying surface of the substrate and encapsulates the chip and the conductive layer. | 2009-02-05 |
| 20090035896 | HIGH POWER MCM PACKAGE WITH IMPROVED PLANARITY AND HEAT DISSIPATION - A structure and a manufacturing method providing improved coplanarity accommodation and heat dissipation in a multi-chip module. One of the components in a multi-chip module (MCM) is provided with a recess formed in its respective top surface; and a film is applied so as to cover the top surfaces of the components and so that any excess film can enter into the recess. The recess is preferably a peripheral groove. Then when molding material is injected, it may surround and seal the side surfaces of the components, while not substantially covering the top surfaces that are covered by the film. Since the recess receives any excess film material that may be present, it may prevent such excess film material from covering the respective side surfaces of the corresponding component and creating a void between the component and the molding material. This advantageous effect of the invention is particularly useful when the top component surface in which the recess is formed is higher above the circuit substrate than the respective top surface of another one of the components. | 2009-02-05 |
| 20090035897 | HYBRID ORIENTATION CMOS WITH PARTIAL INSULATION PROCESS - The present invention provides a method of integrated semiconductor devices such that different types of devices are formed upon a specific crystallographic orientation of a hybrid substrate. In accordance with the present invention, junction capacitance of one of the devices is improved in the present invention by forming the source/drain diffusion regions of the device in an epitiaxial semiconductor material such that they are situated on a buried insulating layer that extends partially underneath the body of the second semiconductor device. The second semiconductor device, together with the first semiconductor device, is both located atop the buried insulating layer. Unlike the first semiconductor device in which the body thereof is floating, the second semiconductor device is not floating. Rather, it is in contact with an underlying first semiconducting layer. | 2009-02-05 |
| 20090035898 | METHOD OF FABRICATING A LAYER WITH TINY STRUCTURE AND THIN FILM TRANSISTOR COMPRISING THE SAME - A method of fabricating a layer with a tiny structure and a thin film transistor comprising the same is disclosed. The method of fabricating the layer with a tiny structure comprises providing a substrate, coating a coating composition on the substrate to form a coating layer, wherein the coating composition comprises nano conductive particles or nano semiconductor particles having functional groups bonded on a surface thereof uniformly dispersed in a solvent, and irradiating the coating layer by an additional energy to break the functional groups, resulting in aggregation of nano conductive particles or nano semiconductor particles to form a tiny structure. | 2009-02-05 |
| 20090035899 | Microelectronic device - A thin film transistor is manufactured by a process including forming an oxide semiconductor channel, patterning the oxide semiconductor channel with a photolithographic process, and exposing the patterned oxide semiconductor channel to an oxygen containing plasma. | 2009-02-05 |
| 20090035900 | Method of Forming High Density Trench FET with Integrated Schottky Diode - A method of forming a monolithically integrated trench FET and Schottky diode includes the following steps. Two trenches are formed extending through an upper silicon layer and terminating within a lower silicon layer. The upper and lower silicon layers have a first conductivity type. First and second silicon regions of a second conductivity type are formed in the upper silicon layer between the pair of trenches. A third silicon region of the first conductivity type is formed extending into the first and second silicon regions between the pair of trenches such that remaining lower portions of the first and second silicon regions form two body regions separated by a portion of the upper silicon layer. A silicon etch is performed to form a contact opening extending through the first silicon region such that outer portions of the first silicon region remain, the outer portions forming source regions. An interconnect layer is formed filling the contact opening so as to electrically contact the source regions and the portion of the upper silicon layer. The interconnect layer electrically contacts the second silicon region so as to form a Schottky contact therebetween. | 2009-02-05 |
| 20090035901 | METHOD FOR FABRICATING MEMORY DEVICE WITH RECESS CHANNEL MOS TRANSISTOR - A method for fabricating line type recess channel MOS transistors utilizes a lithography process to form line type gate trenches in the line type recess channel MOS transistors before finishing a STI process. The method can further control the critical dimension variation in a range required in precision semiconductor processes. Therefore, the short problem between the transistors can be avoided. | 2009-02-05 |
| 20090035902 | INTEGRATED METHOD OF FABRICATING A MEMORY DEVICE WITH REDUCED PITCH - Provided is a method of fabricating a memory device. A substrate including an array region and a peripheral region is provided. A first feature and a second feature are formed in the array region. The first feature and the second feature have a first pitch. A plurality of spacers abutting each of the first feature and the second feature are formed. The plurality of spacers have a second pitch. A third feature in the peripheral region and a fourth and fifth feature in the array region are formed concurrently. The forth and fifth feature have the second pitch. | 2009-02-05 |
| 20090035903 | SEMICONDUCTOR DEVICES AND METHODS OF FABRICATING THE SAME - Disclosed is a semiconductor device and method of fabricating the same. The device is disposed on a substrate, including a fin constructed with first and second sidewalls, a first gate line formed in the pattern of spacer on the first sidewall of the fin, and a second gate line formed in the pattern of spacer on the second sidewall of the fin. First and second impurity regions are disposed in the fin. The first and second impurity regions are isolated from each other and define a channel region in the fin between the first and second gate lines. | 2009-02-05 |
| 20090035904 | METHODS OF FORMING NON-VOLATILE MEMORY HAVING TUNNEL INSULATOR OF INCREASING CONDUCTION BAND OFFSET - Methods of forming non-volatile memory cell structures are described that facilitate the use of band-gap engineered gate stacks with asymmetric tunnel barriers in reverse and normal mode floating node memory cells that allow for direct tunnel programming and erase, while maintaining high charge blocking barriers and deep carrier trapping sites for good charge retention. The low voltage direct tunneling program and erase capability reduces damage to the gate stack and the crystal lattice from high energy carriers, reducing write fatigue and enhancing device lifespan. The low voltage direct tunnel program and erase capability also enables size reduction through low voltage design and further device feature scaling. Such memory cells also allow multiple bit storage. These characteristics allow such memory cells to operate within the definition of a universal memory, capable of replacing both DRAM and ROM in a system. | 2009-02-05 |
| 20090035905 | INSITU FORMATION OF INVERSE FLOATING GATE POLY STRUCTURES - Briefly, in accordance with one or more embodiments, a method of making an inverse-t shaped floating gate in a non-volatile memory cell or the like is disclosed. | 2009-02-05 |
| 20090035906 | Method of manufacturing a non-volatile semiconductor device - Example embodiments relate to methods of fabricating a non-volatile memory device. According to example embodiments, a method of fabricating a non-volatile memory device may include forming at least one gate structure on an upper face of a substrate. The at least one gate structure may include a tunnel insulation layer pattern, a charge storing layer pattern, a dielectric layer pattern and a control gate. According to example embodiments, a method of fabricating a non-volatile memory device may also include forming a silicon nitride layer on the upper face of the substrate to cover the at least one gate structure, forming an insulating interlayer on the silicon nitride layer on the upper face of the substrate, and providing an annealing gas toward the upper face of the substrate and a lower face of the substrate to cure defects of the tunnel insulation layer pattern. | 2009-02-05 |
| 20090035907 | METHOD OF FORMING STACKED GATE STRUCTURE FOR SEMICONDUCTOR MEMORY - A method of manufacturing a nonvolatile semiconductor memory comprising: forming a gate insulating film formed on a surface of a semiconductor substrate; forming a source region and a drain region in the semiconductor substrate; forming a floating gate electrode on the gate insulating film; forming a inter-gate insulating film on the floating gate electrode; forming a control gate electrode on the inter-gate insulating film; forming a source contact region wherein the source contact region is electrically contact to said source region, and top part of said source contact region is lower than bottom part of said control gate electrode. | 2009-02-05 |
| 20090035908 | PROCESS FOR FABRICATING A NANOWIRE-BASED VERTICAL TRANSISTOR STRUCTURE - The invention relates to a process for fabricating a vertical transistor structure. On a substrate ( | 2009-02-05 |
| 20090035909 | METHOD OF FABRICATION OF A FINFET ELEMENT - The present disclosure provides a method of fabricating a FinFET element including providing a substrate including a first fin and a second fin. A first layer is formed on the first fin. The first layer comprises a dopant of a first type. A dopant of a second type is provided to the second fin. High temperature processing of the substrate is performed on the substrate including the formed first layer and the dopant of the second type. | 2009-02-05 |
| 20090035910 | Method of Forming The NDMOS Device Body With The Reduced Number of Masks - This disclosure describes an improved process and resulting structure that allows a single masking step to be used to define both the body and the threshold adjustment layer of the body. The method consists of forming a first mask on a surface of a substrate with an opening exposing a first region of the substrate; implanting through the opening a first impurity of a first conductivity type and having a first diffusion coefficient; and implanting through the opening a second impurity of the first conductivity type and having a second diffusion coefficient lower than the first diffusion coefficient. The first and second impurities are then co-diffused to form a body region of a field effect transistor. The remainder of the device is formed. | 2009-02-05 |
| 20090035911 | METHOD FOR FORMING A SEMICONDUCTOR DEVICE HAVING ABRUPT ULTRA SHALLOW EPI-TIP REGIONS - A method for forming a semiconductor device having abrupt ultra shallow epi-tip regions comprises forming a gate stack on a crystalline substrate, performing a first ion implantation process to amorphisize a first pair of regions of the substrate disposed adjacent to and on laterally opposite sides of the gate stack, forming a pair of spacers on the substrate disposed on laterally opposite sides of the gate stack, performing a second ion implantation process to amorphisize a second pair of regions of the substrate that are disposed on laterally opposite sides of the gate stack and adjacent to the spacers, applying a selective wet etch chemistry to remove the amorphisized first and second pair of regions and form a pair of cavities on laterally opposite sides of the gate stack, and depositing a silicon alloy in the pair of cavities to form source and drain regions and source and drain epi-tip regions. | 2009-02-05 |
| 20090035912 | Semiconductor Device and Fabrication Method Thereof - In order to diversify a current control method of a semiconductor device, improve performance (including a current drive performance) of the semiconductor device, and reduce a size of the semiconductor device, a second gate may be formed inside a substrate that forms a channel upon applying a bias voltage thereto. In one aspect, the semiconductor device includes: a well region of a first conductivity; source and drain regions of a second conductivity in the well region; a first gate on an oxide layer above the well region, controlling a first channel region of a second conductivity between the source region and the drain region; and a second gate under the first channel region. | 2009-02-05 |
| 20090035913 | HIGH-CAPACITANCE DENSITY THIN FILM DIELECTRICS HAVING COLUMNAR GRAINS FORMED ON BASE-METAL FOILS - Deposited thin-film dielectrics having columnar grains and high dielectric constants are formed on heat treated and polished metal foil. The sputtered dielectrics are annealed at low oxygen partial pressures. | 2009-02-05 |
| 20090035914 | ISOLATION TRENCH PROCESSING FOR STRAIN CONTROL - A semiconductor fabrication process includes forming a hard mask, e.g., silicon nitride, over an active layer of a silicon on insulator (SOI) wafer, removing a portion of the hard mask and the active layer to form a trench, and forming an isolation dielectric in the trench where the dielectric exerts compressive strain on a channel region of the active layer. Forming the dielectric may include performing a thermal oxidation. Before performing the thermal oxidation, semiconductor structures may be formed, e.g., by epitaxy, on sidewalls of the trench. The structures may be silicon or a silicon compound, e.g., silicon germanium. During the thermal oxidation, the semiconductor structures are consumed. In the case of a silicon germanium, the germanium may diffuse during the thermal oxidation to produce a silicon germanium channel region. | 2009-02-05 |
| 20090035915 | METHOD OF HIGH DENSITY PLASMA GAP-FILLING WITH MINIMIZATION OF GAS PHASE NUCLEATION - A method of high density plasma (HDP) gap-filling with a minimization of gas phase nucleation (GPN) is provided. The method includes providing a substrate having a trench in a reaction chamber. Next, a first deposition step is performed to partially fill a dielectric material in the trench. Then, an etch step is performed to partially remove the dielectric material in the trench. Thereafter, a second deposition step is performed to partially fill the dielectric material in the trench. A reaction gas used in the second deposition step includes a carrier gas, an oxygen-containing gas, a silicon-containing gas, and a hydrogen-containing gas. After the carrier gas and oxygen-containing gas are introduced into the reaction chamber and a radio frequency (RF) power is turned on for a period of time, the silicon-containing gas and hydrogen-containing gas are introduced into the reaction chamber. | 2009-02-05 |
| 20090035916 | METHOD FOR MANUFACTURING SEMICONDUCTOR DEVICE HAVING FIN GATE - When manufacturing a semiconductor device, an isolation layer is formed on a semiconductor substrate to define an active region that includes gate forming area. Portions of the isolation layer that are adjacent to the gate forming area of the active region are etching by a dry cleaning process which utilizes NH | 2009-02-05 |
| 20090035917 | METHOD FOR FORMING DEVICE ISOLATION STRUCTURE OF SEMICONDUCTOR DEVICE USING ANNEALING STEPS TO ANNEAL FLOWABLE INSULATION LAYER - A method for forming a device isolation structure of a semiconductor device using at least three annealing steps to anneal a flowable insulation layer is presented. The method includes the steps of forming a hard mask pattern on a semiconductor substrate having active regions exposing a device isolation region of the semiconductor substrate; etching the device isolation region of the semiconductor substrate exposed through the hard mask pattern, and therein forming a trench; forming a flowable insulation layer to fill a trench; first annealing the flowable insulation layer at least three times; second annealing the first annealed flowable insulation layer; removing the second annealed flowable insulation layer until the hard mask pattern is exposed; and removing the exposed hard mask pattern. | 2009-02-05 |
| 20090035918 | POST DEPOSITION PLASMA TREATMENT TO INCREASE TENSILE STRESS OF HDP-CVD SIO2 - Methods of forming a dielectric layer where the tensile stress of the layer is increased by a plasma treatment at an elevated position are described. In one embodiment, oxide and nitride layers are deposited on a substrate and patterned to form an opening. A trench is etched into the substrate. The substrate is transferred into a chamber suitable for dielectric deposition. A dielectric layer is deposited over the substrate, filling the trench and covering mesa regions adjacent to the trench. The substrate is raised to an elevated position above the substrate support and exposed to a plasma which increases the tensile stress of the substrate. The substrate is removed from the dielectric deposition chamber, and portions of the dielectric layer are removed so that the dielectric layer is even with the topmost portion of the nitride layer. The nitride and pad oxide layers are removed to form the STI structure. | 2009-02-05 |
| 20090035919 | IN-PLACE BONDING OF MICROSTRUCTURES - A method for bonding microstructures to a semiconductor substrate using attractive forces, such as, hydrophobic, van der Waals, and covalent bonding is provided. The microstructures maintain their absolute position with respect to each other and translate vertically onto a wafer surface during the bonding process. The vertical translation of the micro-slabs is also referred to herein as “in-place bonding”. Semiconductor structures which include the attractively bonded microstructures and substrate are also disclosed. | 2009-02-05 |
| 20090035920 | PROCESS FOR FABRICATING A SUBSTRATE OF THE SILICON-ON-INSULATOR TYPE WITH REDUCED ROUGHNESS AND UNIFORM THICKNESS - A process for fabricating a silicon on insulator (SOI) substrate by co-implanting atomic or ionic species into a semiconductor donor substrate to form a weakened zone therein, the weakened zone forming a boundary between a thin silicon active layer and the remainder of the donor substrate. The donor substrate is then bonded to a semiconductor receiver substrate by molecular adhesion, resulting in a layer of buried silicon interposed between the donor substrate and the receiver substrate. The remainder of the donor substrate is detached along the weakened zone to obtain a SOI substrate with the receiver substrate covered with the buried oxide layer and the thin silicon active layer. The silicon active layer is then thermally annealed for at least 10 minutes in a gaseous atmosphere containing hydrogen, argon or both at a temperature of at least 950° C. but not exceeding 1100° C. The annealing step minimizes roughness of the surface of the silicon active layer, prevents reduction in thickness of the buried oxide layer, and achieves uniform thickness of the thin silicon active layer and the buried oxide layer. | 2009-02-05 |
| 20090035921 | FORMATION OF LATTICE-TUNING SEMICONDUCTOR SUBSTRATES - A method of forming a lattice-tuning semiconductor substrate comprises defining a selected area ( | 2009-02-05 |
| 20090035922 | SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD THEREOF - There are provided a structure of a semiconductor device in which low power consumption is realized even in a case where a size of a display region is increased to be a large size screen and a manufacturing method thereof. A gate electrode in a pixel portion is formed as a three layered structure of a material film containing mainly W, a material film containing mainly Al, and a material film containing mainly Ti to reduce a wiring resistance. A wiring is etched using an IPC etching apparatus. The gate electrode has a taper shape and the width of a region which becomes the taper shape is set to be 1 μm or more. | 2009-02-05 |
| 20090035923 | Method for manufacturing a semiconductor device - A process for fabricating a highly stable and reliable semiconductor, comprising: coating the surface of an amorphous silicon film with a solution containing a catalyst element capable of accelerating the crystallization of the amorphous silicon film, and heat treating the amorphous silicon film thereafter to crystallize the film. | 2009-02-05 |
| 20090035924 | METHOD OF FORMING A SEMICONDUCTOR STRUCTURE COMPRISING AN IMPLANTATION OF IONS OF A NON-DOPING ELEMENT - A method of forming a semiconductor structure includes providing a substrate having a first feature and a second feature. A mask is formed over the substrate. The mask covers the first feature. An ion implantation process is performed to introduce ions of a non-doping element into the second feature. The mask is adapted to absorb ions impinging on the first feature. After the ion implantation process, an annealing process is performed. | 2009-02-05 |
| 20090035925 | Gallium Nitride Semiconductor Device - A gallium nitride based semiconductor Schottky diode fabricated from a n+ doped GaN layer having a thickness between one and six microns disposed on a sapphire substrate; an n− doped GaN layer having a thickness greater than one micron disposed on said n+ GaN layer patterned into a plurality of elongated fingers and a metal layer disposed on the n− doped GaN layer and forming a Schottky junction therewith. The layer thicknesses and the length and width of the elongated fingers are optimized to achieve a device with breakdown voltage of greater than 500 volts, current capacity in excess of one ampere, and a forward voltage of less than three volts. | 2009-02-05 |
| 20090035926 | Methods of Fabricating Silicon Carbide Devices Incorporating Multiple Floating Guard Ring Edge Terminations - Edge termination for silicon carbide devices has a plurality of concentric floating guard rings in a silicon carbide layer that are adjacent and spaced apart from a silicon carbide-based semiconductor junction. An insulating layer, such as an oxide, is provided on the floating guard rings and a silicon carbide surface charge compensation region is provided between the floating guard rings and is adjacent the insulating layer. Methods of fabricating such edge termination are also provided. | 2009-02-05 |
| 20090035927 | METHOD OF FORMING DIELECTRIC LAYERS ON A SUBSTRATE AND APPARATUS THEREFOR - Methods of forming dielectric layers on a substrate comprising silicon and oxygen are disclosed herein. In some embodiments, a method of forming a dielectric layer on a substrate includes provide a substrate having an exposed silicon oxide layer; treating an upper surface of the silicon oxide layer with a plasma; and depositing a silicon nitride layer on the treated silicon oxide layer via atomic layer deposition. The silicon nitride layer may be exposed to a plasma nitridation process. The silicon oxide and silicon nitride layers may be subsequently thermally annealed. The dielectric layers may be used as part of a gate structure. | 2009-02-05 |
| 20090035928 | METHOD OF PROCESSING A HIGH-K DIELECTRIC FOR CET SCALING - A method of making a semiconductor device includes making a gate dielectric with an overlying gate electrode. The semiconductor device is made over a semiconductor layer. A high-k dielectric comprising hafnium zirconate is deposited over the semiconductor layer. The high-k dielectric is annealed at a temperature between 650 degrees Celsius and 850 degrees Celsius in an ambient comprising hydrogen and nitrogen. The gate electrode is formed on the high-k dielectric. The high-k dielectric function is for use in the gate dielectric. One affect is to improve the transistor performance while retaining or even improving the level of gate leakage. | 2009-02-05 |
| 20090035929 | Method of manufacturing semiconductor device - A method of manufacturing a semiconductor device includes: (a) forming an insulating layer having a contact hole on a semiconductor section in which an element is formed; (b) forming an electrode pad on the insulating layer so that a depression or a protrusion remains at a position at which the electrode pad overlaps the contact section; (c) forming a passivation film to have an opening on a first section of the electrode pad and to be positioned on a second section of the electrode pad; (d) forming a barrier layer on the electrode pad; and (e) forming a bump to be larger than the opening in the passivation film and to be partially positioned on the passivation film. The contact section is connected with the second section at a position within a range in which the contact section overlaps the bump while avoiding the first section of the electrode pad. | 2009-02-05 |
| 20090035930 | METHOD OF FORMING A WIRE STRUCTURE - In a method of forming a wire structure, first active regions and second active regions are formed on a substrate. Each of the first active regions has a first sidewall of a positive slope and a second sidewall opposed to the first sidewall. The second active regions are arranged along a first direction. An isolation layer is between the first active regions and the second active regions. A first mask is formed on the first active regions, the second active regions and the isolation layer. The first mask has an opening exposing the first sidewall and extending along the first direction. The first active regions, the second active regions and the isolation layer are etched using the first mask to form a groove extending along the first direction and to form a fence having a height substantially higher than a bottom face of the groove. A wire is formed to fill the groove. A contact is formed on the wire. The contact is disposed toward the second active regions from the fence. | 2009-02-05 |
| 20090035931 | METHOD FOR FORMING VIAS IN A SUBSTRATE - The present invention relates to a method for forming vias in a substrate, comprising the following steps: (a) providing a substrate having a first surface and a second surface; (b) forming a photo resist layer on the first surface of the substrate; (c) forming a pattern on the photo resist layer; (d) forming a groove and a pillar in the substrate according to the pattern, wherein the groove surrounds the pillar; (e) forming a polymer in the groove of the substrate; (f) removing the pillar of the substrate to form an accommodating space; (g) forming a conductive metal in the accommodating space; and (h) removing part of the second surface of the substrate to expose the conductive metal and the polymer. As a result, thicker polymer can be formed in the groove, and the thickness of the polymer in the groove is uniform. | 2009-02-05 |
| 20090035932 | METHOD FOR FORMING VIAS IN A SUBSTRATE - The present invention relates to a method for forming vias in a substrate, including the following steps: (a) providing a substrate having a first surface and a second surface; (b) forming a groove on the substrate; (c) filling the groove with a conductive metal; (d) removing part of the substrate which surrounds the conductive metal, wherein the conductive metal is maintained so as to form an accommodating space between the conductive metal and the substrate; (e) forming an insulating material in the accommodating space; and (f) removing part of the second surface of the substrate to expose the conductive metal and the insulating material. In this way, thicker insulating material can be formed in the accommodating space, and the thickness of the insulating material in the accommodating space is even. | 2009-02-05 |
| 20090035933 | DENDRITE GROWTH CONTROL CIRCUIT - A circuit is provided which prevents dendrite formation on interconnects during semiconductor device processing due to a dendrite-forming current. The circuit includes a switch located in at least one of the dendrite-forming current paths. The switch is configured to be open or in the “off” state during processing, and is configured to be closed or in the “on” state after processing to allow proper functioning of the semiconductor device. The switch may include an nFET or pFET, depending on the environment in which it is used to control or prevent dendrite formation. The switch may be configured to change to the “closed” state when an input signal is provided during operation of the fabricated semiconductor device. | 2009-02-05 |
| 20090035934 | Self-Aligned Cross-Point Memory Fabrication - Fabricating a cross-point memory structure using two lithography steps with a top conductor and connector or memory element and a bottom conductor orthogonal to the top connector. A first lithography step followed by a series of depositions and etching steps patterns a first channel having a bottom conductor. A second lithography step followed by a series of depositions and etching steps patterns a second channel orthogonal to the first channel and having a memory element connecting the an upper conductor and the lower conductor at their overlaid intersections. | 2009-02-05 |
| 20090035935 | Method of forming a metal wiring - A method of forming a metal wiring for a semiconductor device includes forming a metal-based layer on a substrate, the substrate including at least one conductive structure, forming a metal seed layer on the metal-based layer, forming a supplementary contact layer on the metal seed layer along peripheral portions of the substrate, the metal seed layer being between the substrate and the supplementary contact layer, and the supplementary contact layer including a supplementary metal having an electrical resistance smaller than or equal to an electrical resistance of the metal seed layer, loading the substrate into a plating apparatus, such that the supplementary contact layer is being in direct contact with the cathode of the plating apparatus, and performing an electroplating process on the metal seed layer to form a metal wiring layer on the metal-based layer. | 2009-02-05 |
| 20090035936 | SEMICONDUCTOR DEVICE HAVING A GRAIN ORIENTATION LAYER - A manufacturing process of a semiconductor device includes generating a less random grain orientation distribution in metal features of a semiconductor device by employing a grain orientation layer. The less random grain orientation, e.g., a grain orientation distribution which has a higher percentage of grains that have a predetermined grain orientation, may lead to improved reliability of the metal features. The grain orientation layer may be deposited on the metal features wherein the desired grain structure of the metal features may be obtained by a subsequent annealing process, during which the metal feature is in contact with the grain orientation layer. | 2009-02-05 |
| 20090035937 | In-Situ Deposition for Cu Hillock Suppression - A semiconductor interconnect structure having reduced hillock formation and a method for forming the same are provided. The semiconductor interconnect structure includes a conductor formed in a dielectric layer. The conductor includes at least three sub-layers, wherein the ratio of the impurity concentrations in neighboring sub-layers is preferably greater than about two. | 2009-02-05 |
| 20090035938 | Methods of Forming CoSi2, Methods of Forming Field Effect Transistors, and Methods of Forming Conductive Contacts - The invention included to methods of forming CoSi | 2009-02-05 |
| 20090035939 | FABRICATION METHOD TO MINIMIZE BALLAST LAYER DEFECTS - A method for minimizing fabrication defects in ballast contact to a conductor in monolithically integrated semiconductor devices includes forming a sloping sidewall ( | 2009-02-05 |
| 20090035940 | COPPER METALLIZATION OF THROUGH SILICON VIA - A method for metallizing a through silicon via feature in a semiconductor integrated circuit device substrate comprising immersing the semiconductor integrated circuit device substrate into an electrolytic copper deposition composition comprising a source of copper ions, an organic sulfonic acid or inorganic acid, or one or more organic compounds selected from among polarizers and/or depolarizers, and chloride ions. | 2009-02-05 |
| 20090035941 | METHODS AND APPARATUS FOR MANUFACTURING A SEMICONDUCTOR DEVICE IN A PROCESSING CHAMBER - An apparatus for manufacturing a semiconductor device includes a process chamber configured to perform a plurality of different processes on a substrate. A gas supply unit is configured to supply at least one process gas to the process chamber. At least one upper electrode unit is positioned at an upper portion of the process chamber. At least one lower electrode unit is opposite the upper electrode unit and configured to support a substrate thereon. A driving member is connected to at least one of the lower electrode unit and the upper electrode unit and is configured to move the lower electrode unit and/or the upper electrode unit to control a distance between the upper and the lower electrode units. A power supply unit is configured to apply a first power to the upper electrode unit and to apply a second power to the lower electrode unit. | 2009-02-05 |
| 20090035942 | Ruthenium CMP compositions and methods - The present invention provides a chemical-mechanical polishing (CMP) composition for polishing a ruthenium-containing substrate in the presence of an oxidizing agent such as hydrogen peroxide without forming a toxic level of ruthenium tetroxide during the polishing process. The composition comprises a particulate abrasive (e.g., silica, alumina, and/or titania) suspended in an aqueous carrier containing a ruthenium-coordinating oxidized nitrogen ligand (N—O ligand), such as a nitroxide (e.g., 4-hydroxy-TEMPO). In the presence of the oxidizing agent, the N—O ligand prevents the deposition of ruthenium species having an oxidation state of IV or higher on the surface of the substrate, and concomitantly forms a soluble Ru(II) N—O coordination complex with oxidized ruthenium formed during CMP of the substrate. CMP methods for polishing ruthenium-containing surfaces with the CMP composition are also provided. | 2009-02-05 |
| 20090035943 | Method of Fabricating for Semiconductor Device Fabrication - A method of fabricating a semiconductor device, includes providing a substrate having at least one first portion and at least one second portion. The first portion includes a semiconductor material and the second portion includes an electrically isolating material. An etching step is performed using an etchant in order to at least partially remove the first and the second portions. The etchant includes a NF | 2009-02-05 |
| 20090035944 | METHODS OF FOR FORMING ULTRA THIN STRUCTURES ON A SUBSTRATE - Methods for forming an ultra thin structure using a method that includes multiple cycles of polymer deposition of photoresist (PDP) process and etching process. The embodiments described herein may be advantageously utilized to fabricate a submicron structure on a substrate having a critical dimension less than 55 nm and beyond. In one embodiment, a method of forming a submicron structure on a substrate may include providing a substrate having a patterned photoresist layer disposed on a film stack into an etch chamber, wherein the film stack includes at least a hardmask layer disposed on a dielectric layer, performing a polymer deposition process to deposit a polymer layer on the pattered photoresist layer, thus reducing a critical dimension of an opening in the patterned photoresist layer, and etching the underlying hardmask layer through the opening having the reduced dimension. | 2009-02-05 |
| 20090035945 | MANUFACTURING METHOD OF SEMICONDUCTOR INTEGRATED CIRCUIT DEVICE - In remote plasma cleaning, it is difficult to locally excite a plasma because the condition is not suitable for plasma excitation different from that at the time of film formation and a method using light has a problem of fogginess of a detection window that cannot be avoided in a CVD process and is not suitable for a mass production process. In order to solve these problems, the outline of the present invention is a manufacturing method of a semiconductor integrated circuit device in which a step of depositing a desired film by exciting a reaction gas using a plasma in a reaction chamber and a step of introducing a cleaning gas excited in a remote plasma excitation chamber into the reaction chamber and performing remote plasma cleaning of the reaction chamber in an atmosphere without plasma excitation are repeated, wherein a local plasma is generated in the reaction chamber or a vacuum system for evacuating the reaction chamber by a plasma excitation system of capacitively coupled type and the end point of the remote plasma cleaning is detected by monitoring the electrical characteristic of the plasma. | 2009-02-05 |
| 20090035946 | IN SITU DEPOSITION OF DIFFERENT METAL-CONTAINING FILMS USING CYCLOPENTADIENYL METAL PRECURSORS - A method is disclosed depositing multiple layers of different materials in a sequential process within a deposition chamber. A substrate is provided in a deposition chamber. A plurality of cycles of a first atomic layer deposition (ALD) process is sequentially conducted to deposit a layer of a first material on the substrate in the deposition chamber. These first cycles include pulsing a cyclopentadienyl metal precursor. A plurality of cycles of a second ALD process is sequentially conducted to deposit a layer of a second material on the layer of the first material in the deposition chamber. The second material comprises a metal different from the metal in the cyclopentadienyl metal precursor. | 2009-02-05 |
| 20090035947 | Manufacturing Method of Semiconductor Device, and Substrate Processing Apparatus - The present invention provides a manufacturing method of a semiconductor device that has a rapid film formation rate and high productivity, and to provide a substrate processing apparatus. | 2009-02-05 |
| 20090035948 | Substrate processing apparatus, heating apparatus for use in the same, method of manufacturing semiconductors with those apparatuses, and heating element supporting structure - A substrate treating device comprising a treatment chamber for storing and treating substrates and a heating device having a heating element and a heat insulator and heating the substrates in the treatment chamber by the heating element. The heating element is so formed that only its one end is held by a holding part, and a projection projected to the treatment chamber side at the intermediate part of the heating element and positioned in proximity to or in contact with the heating element is formed on the heat insulator. A pin with an enlarged part is passed through the heating element and the heat insulator at the intermediate part of the heating element and The enlarged part is positioned in proximity to or in contact with the heating element. The plurality of projections may be formed on the heat insulator and the pins may be disposed between these plurality of projections. | 2009-02-05 |
| 20090035949 | METHOD OF DEPOSITING RARE EARTH OXIDE THIN FILMS - The present invention concerns a process for depositing rare earth oxide thin films, especially yttrium, lanthanum and gadolinium oxide thin films by an ALD process, according to which invention the source chemicals are cyclopentadienyl compounds or rare earth metals, especially those of yttrium, lanthanum and gadolinium. Suitable deposition temperatures for yttrium oxide are between 200 and 400° C. when the deposition pressure is between 1 and 50 mbar. Most suitable deposition temperatures for lanthanum oxide are between 160 and 165° C. when the deposition pressure is between 1 and 50 mbar. | 2009-02-05 |
| 20090035950 | NITRIDING METHOD OF GATE OXIDE FILM - A substrate processing method comprises the step of forming an oxide film on a silicon substrate surface, and introducing nitrogen atoms into the oxide film by exposing the oxide film to nitrogen radicals excited in plasma formed by a microwave introduced via a planar antenna. | 2009-02-05 |
| 20090035951 | MANUFACTURING METHOD OF SEMICONDUCTOR DEVICE - Provided is a manufacturing method of a semiconductor device composed of a step of carrying-in a wafer into a processing chamber; a step of forming an HfO | 2009-02-05 |
| 20090035952 | METHODS FOR LOW TEMPERATURE OXIDATION OF A SEMICONDUCTOR DEVICE - Methods of fabricating an oxide layer on a semiconductor substrate are provided herein. In some embodiments, a method of forming an oxide layer on a semiconductor substrate includes placing a substrate to be oxidized on a substrate support in a vacuum chamber of a plasma reactor, the chamber having an ion generation region remote from the substrate support; introducing a process gas into the chamber, the process gas comprising at least one of hydrogen (H | 2009-02-05 |
| 20090035953 | Power supply apparatus for long slide - An object of the present invention is to provide a smooth and secure sliding operation for a sliding structure for long slide without drooping and bending a wire harness. A power supply apparatus | 2009-02-05 |
| 20090035954 | INTERCONNECT STRUCTURE WITH GRAIN GROWTH PROMOTION LAYER AND METHOD FOR FORMING THE SAME - In general, the present invention provides an interconnect structure and method for forming the same. This present invention discloses an interconnect structure includes a Cu seeding layer embedded between a diffusion barrier layer and a grain growth promotion layer. Specifically, under the present invention, a diffusion barrier layer is formed on a patterned inter-level dielectric layer. A (Cu) seeding layer is then formed on the diffusion barrier layer, and a grain growth promotion layer is formed on the seeding layer. Once the grain growth promotion layer is formed, post-processing steps (e.g., electroplating and chemical-mechanical polishing) are performed. | 2009-02-05 |
| 20090035955 | Electrical connector with divider shields to minimize crosstalk - A wafer for an electrical connector includes a conductive shield plate, a plurality of signal conductors disposed on the shield plate, and a divider shield. Each of the plurality of signal conductors has at least one contact portion. The divider shield is disposed on the shield plate aligned with the at least one contact portion and is made of conductive metal. The divider shield is separate from and coupled to the shield plate. | 2009-02-05 |
| 20090035956 | Circuit board electrical connector - An electrical circuit board connector includes a housing made of an electrical insulating material; a groove formed in the housing for receiving a flat conductive member from a rear side of the housing; a signal terminal arranged at a front side of the housing; a ground terminal disposed at a position closer to the rear side relative to the signal terminal; and a pressing member supported to be movable. The signal terminal includes a contact arm, a first contact section for contacting with a circuit section of the flat conductive member, and a connecting section protruding outside the housing. The ground terminal includes a second contact section for contacting with a ground plate of the flat conductive member. When the pressing member moves, the pressing member presses the flat conductive member to the first contact section and the second contact section. | 2009-02-05 |
| 20090035957 | LEAD FRAME FOR CIRCUIT BOARD - A sub-component circuit board may be electrically and mechanically connected to a higher order circuit board using one or more leads extending from a lead frame embedded in the sub-component circuit board. The sub-component board is produced as a layered assembly with the embedded lead frame at the core. One or more dielectric layers and one or more circuitry layers are provided over the lead frame and then bonded using heat and pressure. Apertures in the dielectric and circuitry layers define a perimeter of the circuit board where the leads of the lead frame are exposed. The lead frame connects to the circuitry layer(s) using plated vias. | 2009-02-05 |
| 20090035958 | ELECTRONIC DEVICE AND ELASTIC SHEET UNIT THEREOF - An electronic device includes a body, a first circuit board, an electronic element set and an elastic sheet unit. The body includes a first surface, a second surface and at least one through hole. The first surface is opposite to the second surface. The through hole passes through the body. The first circuit board includes a first conductive portion. The electronic element set is provided at the first surface. The electronic element set includes a second conductive portion. The elastic sheet unit includes a fixing element and two elastic sheets. The fixing element fixes the elastic sheets on the second surface. Each of the elastic sheets includes a first end and a second end. The first ends abut the first conductive portion, and the second ends pass through the through hole to abut the second conductive portion. | 2009-02-05 |
| 20090035959 | INTERCONNECT ASSEMBLIES AND METHODS - Interconnect assemblies having resilient contact elements and methods for making these assemblies. In one aspect, the interconnect assembly includes a substrate and a resilient electrical contact element disposed on the substrate. A first portion of the resilient contact structure is disposed on the substrate and a second portion extends away from the substrate and is capable of moving from a first position to a second position under the application of a force. A stop structure is disposed on the surface of the substrate and on a surface of the first portion of the resilient contact structure. According to another aspect of the present invention, a beam portion of the resilient contact structure has a substantially triangular shape. | 2009-02-05 |
| 20090035960 | ELECTRICAL CONNECTING APPARATUS - The electrical connecting apparatus disclosed herein includes a frame member having a recess for receiving a device under test provided with a plurality of electrodes, a plurality of contacts provided in correspondence to the electrodes, a plurality of slots formed in the bottom portion of the recess of the frame member and arranged parallel to each other so as to receive the contacts such that the tip of each contact can abut the corresponding electrode, an elastic member disposed across the slots over the bottom portion within the recess to elastically hold the contacts, and a cap member mounted on the frame member and sandwiching the elastic body together with the frame member. | 2009-02-05 |
| 20090035961 | Surface Mount Electrical Connector - A surface mount electrical connector for mounting to a substrate comprising a housing and a contact carried by the housing, the contact comprising a retention section held by the housing and a tine configured for mounting to a surface of the substrate wherein the tine extends from the retention section and wherein the tine lies inside an outer contour line of the housing is disclosed. A method of connecting a surface mount electrical connector to a substrate comprising the steps of providing a housing carrying a contact, the contact having a tine within a projected footprint of the housing on the substrate, attaching the housing to the substrate, inserting a jig into an opening of the housing, and bending the tine toward the substrate is disclosed. | 2009-02-05 |
| 20090035962 | Card-through-connector fastener for reducing connector distortion - A card-through-connector fastener for reducing connector distortion is disclosed. One embodiment provides circuit card coupled with electronics associated with an actuator. A connector assembly is also coupled with the circuit card, the connector assembly for conveying data with respect to the circuit card. In addition, a fastener connectively couples the connector assembly with a portion of the housing, the fastener passing through the circuit card and providing fixed support between the connector assembly and the hard disk drive housing to reduce distortion transfer from the circuit card to the connector. | 2009-02-05 |
| 20090035963 | Semiconductor device socket - A fixed side terminal of a contact terminal having a movable side contact piece and a fixed side contact piece has a contact portion in contact with a group of electrodes of a printed wiring board at a predetermined pressure, and a socket body is fixed to the printed wiring board via locking nibs fastened by a tapping screw. | 2009-02-05 |
| 20090035964 | BOARD-MOUNTED ELECTRICAL CONNECTOR - An electrical connector is provided for mounting on a circuit board and includes a dielectric housing mounting a plurality of first terminals having circuit board press-fit portions projecting therefrom. A plurality of second terminals are mounted on the housing and have circuit board press-fit portions projecting therefrom. A press-fitting block is engageable with the housing and is locked to the first terminals for press-fitting the first terminals into holes in the circuit board. The press-fit portions of the second terminals are exposed exteriorly of the housing and the press-fitting block for locking engagement by an appropriate independent pressfitting jig for press-fitting the second terminals into holes in the circuit board. | 2009-02-05 |
| 20090035965 | Electrical card connector with improved contacts - An electrical card connector ( | 2009-02-05 |
