| 05th week of 2021 patent applcation highlights part 63 |
| Patent application number | Title | Published |
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| 20210036078 | DISPLAY PANEL AND DISPLAY DEVICE - A display panel and a display device are provided, and the display panel includes a substrate and a pixel layer disposed on the substrate. The pixel layer includes a plurality of pixel units arranged in an array. The display panel includes a main light-transmitting region surrounded by the plurality of pixel units, and an orthographic projection of the main light-transmitting region on the substrate is not overlapped with orthographic projections of the plurality of pixel units on the substrate, so that external light is allowed to pass through the main light-transmitting region of the display panel, and then is received by an image acquisition device disposed on a side of the display panel. | 2021-02-04 |
| 20210036079 | DISPLAY DEVICE AND METHOD OF MANUFACTURING THE SAME - A display device includes: a pixel at a display region. The pixel includes: a light-emitting element connected between a first power source and a second power source; and a first transistor connected between the first power source and the light-emitting element, the first transistor to control a driving current of the light-emitting element in response to a voltage of a first node. The first transistor includes a first driving transistor and a second driving transistor that are connected in series with each other between the first power source and the light-emitting element, and the first driving transistor and the second driving transistor have structures that are asymmetric with each other in a cross-sectional view. | 2021-02-04 |
| 20210036080 | DISPLAY DEVICE AND METHOD OF MANUFACTURING THE SAME - A display device includes a pixel disposed in a display region. The pixel includes a light-emitting element connected between a first power source and a second power source; a first transistor connected between the first power source and the light-emitting element to control a driving current flowing in the light-emitting element in response to a voltage of a first node; and at least one switching transistor to transmit a data signal or a voltage of an initialization power source to the first node. The switching transistor includes a first channel region, a first conductive region and a second conductive region which are respectively disposed at opposite sides of the first channel region, and a first wide band-gap region disposed between the first channel region and the second conductive region. | 2021-02-04 |
| 20210036081 | TRANSPARENT DISPLAY SUBSTRATE AND MANUFACTURING METHOD THEREFOR, AND TRANSPARENT DISPLAY PANEL - A transparent display substrate includes a first base and a plurality of sub-pixels disposed on the first base. At least one sub-pixel of the plurality of sub-pixels has a light-emitting region and a transparent region. In the at least one sub-pixel, each sub-pixel includes at least one thin-film transistor, a capacitor and a self-luminescent device that are located in the light-emitting region of the sub-pixel. The self-luminescent device is disposed on a side of the capacitor away from the at least one thin film transistor in a direction perpendicular to the first base. The at least one thin film transistor and the capacitor are electrically connected. | 2021-02-04 |
| 20210036082 | DISPLAY PANEL AND METHOD OF FABRICATING THE SAME - A display panel includes a base layer having a first region and a bent second region. An inorganic layer is disposed on the base layer. A lower groove is formed within the inorganic layer and overlaps the second region. A first thin-film transistor is disposed on the inorganic layer and includes a silicon semiconductor pattern overlapping the first region. A second thin-film transistor is disposed on the inorganic layer and includes an oxide semiconductor pattern overlapping the first region. Insulating layers overlap the first and second regions. An upper groove is formed within the insulating layers. A signal line electrically connects the second thin-film transistor. An organic layer overlaps the first and second regions and is disposed in the lower and upper grooves. A luminescent device is disposed on the organic layer and overlaps the first region. | 2021-02-04 |
| 20210036083 | PIXEL CIRCUIT, DISPLAY PANEL AND DISPLAY DEVICE - The disclosure discloses a pixel circuit, a display panel, and a display device. The display device comprises: a light emitting device with a second terminal coupled to a low voltage signal line; a drive thin film transistor with a second terminal coupled to a first terminal of the light emitting device; a light emitting control thin film transistor with a first terminal coupled to a high voltage signal line, and a second terminal coupled to a first terminal of the drive thin film transistor; a switch thin film transistor, which controls data voltage to be written into a control terminal of the drive thin film transistor; a reset thin film transistor, which resets potential of the control terminal of the drive thin film transistor; and a storage capacitor, coupled to the control terminal and the second terminal of the drive thin film transistor. | 2021-02-04 |
| 20210036084 | DISPLAY PANEL - The present application discloses a display panel, including an electromagnetic shielding structure; an array layer disposed inside the electromagnetic shielding structure; and a touch layer disposed outside the electromagnetic shielding structure and positioned on one side of the electromagnetic shielding structure. | 2021-02-04 |
| 20210036085 | ORGANIC LIGHT-EMITTING DIODE DISPLAY SUBSTRATE, DISPLAY PANEL, DISPLAY DEVICE, MANUFACTURING METHOD THEREOF, AND FINGERPRINT IDENTIFICATION MODULE - An OLED display substrate, a display panel, a display device, a manufacturing method and a fingerprint identification module are provided. The OLED display substrate includes a microporous light-shielding pattern arranged between adjacent pixel regions and including a plurality of pinholes. The microporous light-shielding pattern is arranged at a same layer as, and insulated from, a nontransparent electrode of the OLED display substrate. | 2021-02-04 |
| 20210036086 | THIN FILM TRANSISTOR, DISPLAY PANEL HAVING THE SAME, AND METHOD OF MANUFACTURING THE DISPLAY PANEL - A display panel includes a base layer, a first thin film transistor on the base layer, a second thin film transistor electrically coupled to the first thin film transistor, and a light emitting element electrically coupled to the second thin film transistor. The first thin film transistor includes a first semiconductor pattern on the base layer, a first barrier pattern on the first semiconductor pattern and including a gallium (Ga) oxide and a zinc (Zn) oxide, and a first control electrode on the first barrier pattern and overlapping the first semiconductor pattern. Accordingly, a signal transmission speed of the display panel may be improved, and electrical characteristics and reliability of the thin film transistor included in the display panel may be improved. | 2021-02-04 |
| 20210036087 | DISPLAY APPARATUS - A display apparatus includes: a plurality of pixel circuits at a display area, the display area having a non-quadrangular shape; a first signal line extending on the display area in a first direction, and electrically connected to a first pixel circuit from among the plurality of pixel circuits; a first voltage line extending on the display area in the first direction; a first load compensation capacitor adjacent to an end portion of the first signal line and an end portion of the first voltage line; a test circuit outside the display area; an output line electrically connected to the test circuit; and a connection portion configured to electrically connect the output line, the first signal line, and an electrode of the first load compensation capacitor to each other. | 2021-02-04 |
| 20210036088 | DISPLAY DEVICE - A display device includes: a plurality of pixels arranged in a display area that has a non-quadrangular shape; and a plurality of driving circuits arranged in a peripheral area outside the display area and connected to the plurality of pixels, wherein a plurality of sub-driving circuits included in each of the plurality of driving circuits are distributed in a line in the peripheral area. | 2021-02-04 |
| 20210036089 | OLED DISPLAY PANEL, AND METHOD FOR DETECTING THE OLED DISPLAY PANEL, AND DISPLAY DEVICE - The present disclosure provides an OLED display panel and a method for detecting the OLED display panel, and a display device. The OLED display panel includes a base substrate including a display area and a non-display area surrounding the display area and having a first region adjacent to the display area. The display area includes a drive signal line and a power supply voltage signal line both extending from the display area to the first region. The drive signal line includes, in the first region, a first section of wiring at an anode layer, the power supply voltage signal line includes, in the first region, a second section of wiring at a gate metal layer, and parts of the drive signal line and the power supply voltage signal line in the display area are located at a source-drain metal layer. | 2021-02-04 |
| 20210036090 | DISPLAY DEVICE - A display device includes a substrate including a display area including a plurality of main pixels, and a sensor area including a plurality of auxiliary pixels and a plurality of transmission portions; and a plurality of wirings arranged along edges of the plurality of transmission portions and electrically connecting the plurality of auxiliary pixels to each other. The plurality of wrings includes a first directional wirings extending in a first direction and arranged in a second direction crossing the first direction, and a second directional wirings extending in the second direction and arranged in the first direction, and a wiring adjacent to the transmission portion from among the first directional wirings includes a first extension portion. | 2021-02-04 |
| 20210036091 | DISPLAY DEVICE - A display device including: a substrate including a display area and a peripheral area adjacent to the display area; a plurality of data lines extending in a first direction in the display area; a fan-out unit arranged in the peripheral area and connected to the plurality of data lines; a first signal line arranged in the peripheral area; and a common power supply line arranged in the peripheral area and overlapping the fan-out unit. | 2021-02-04 |
| 20210036092 | DISPLAY DEVICE - A display device includes: a display region; a frame region comprising a folding portion, the frame region being disposed around the display region; an outer terminal comprising a first outer terminal and a second outer terminal in the frame region, the first and second outer terminals being disposed sequentially on an outside in such a manner that the first outer terminal is closer to the display region than the second outer terminal is, the outside being more remote from the display region than the folding portion is; a first routing wire crossing the folding portion to electrically connect together the first outer terminal and an inner wire that is disposed in the display region; at least one inner terminal disposed inside the folding portion in the frame region; and a second routing wire that is flexible, the second routing wire electrically connecting at least the second outer terminal out of the first and second outer terminals to the at least one inner terminal without passing through the folding portion. | 2021-02-04 |
| 20210036093 | DISPLAY DEVICE - A first conductive layer in the same layer as that of a first electrode is coupled to a third conductive layer and a second electrode in the same layer as that of a third metal layer through a slit formed in a flattening film of a non-display area. Second conductive layers in the same layer as that of a second metal layer are provided to overlap with the slit. | 2021-02-04 |
| 20210036094 | ORGANIC LIGHT-EMITTING DISPLAY DEVICE - An organic light-emitting display device includes a plurality of pixels, each of which includes an organic light-emitting device including a pixel electrode, an organic emission layer, and an opposing electrode; a pixel defining layer covering an edge of the pixel electrode and being configured to define a light-emission region by having an opening which exposes a portion of the pixel electrode; and a reference line overlapping the pixel electrode with an insulating layer between the reference line and the pixel electrode and extending in a first direction. The reference line overlaps with a center point of the opening, and the opening is shifted to one side of the pixel electrode in a second direction perpendicular to the first direction. | 2021-02-04 |
| 20210036095 | SUBSTRATE-COMPATIBLE INDUCTORS WITH MAGNETIC LAYERS - An exemplary embodiment of the present invention provides a planar inductor including a substrate, a first magnetic layer, a conductive coil, and a second magnetic layer. The first magnetic layer can be disposed on at least a portion of the substrate. The conductive coil can be disposed on a first portion of the first magnetic layer. The second magnetic layer can be disposed on a second portion of the first magnetic layer and on at least a portion of the conductive coil. | 2021-02-04 |
| 20210036096 | SWITCHABLE METAL INSULATOR METAL CAPACITOR - A switchable metal insulator metal capacitor (MIMcap) and a method for fabricating the MIMcap. In another aspect of the invention operating the MIMcap is also described. A first capacitor plate and a second capacitor plate are separated by a capacitor dielectric and disposed over a substrate. A first via is electrically connected to the first capacitor plate and comprised of phase change material (PCM). The PCM is deposited in an electrically conductive state and convertible by application of heat to an insulating state. A first heater is proximate to and electrically isolated from the PCM in the first via. When the first heater is activated it converts the PCM in the first via to the insulating state. This isolates the first capacitor plate from an integrated circuit. | 2021-02-04 |
| 20210036097 | INTERCONNECT LAYOUT FOR SEMICONDUCTOR DEVICE - A semiconductor device and a method of forming the same are provided. The semiconductor device includes a substrate, a deep trench capacitor (DTC) within the substrate, and an interconnect structure over the DTC and the substrate. The interconnect structure includes a seal ring structure in electrical contact with the substrate, a first conductive via in electrical contact with the DTC, and a first conductive line electrically coupling the seal ring structure to the first conductive via. | 2021-02-04 |
| 20210036098 | Capacitor - A capacitor is made using a wafer, and includes structural elevation portions to allow an electrode layer in the capacitor to be extended along surface profiles of the structural elevation portions to thereby increase its extension length, so as to reduce capacitor area, simplify capacitor manufacturing process and reduce manufacturing cost. | 2021-02-04 |
| 20210036099 | ELECTRONIC PRODUCT COMPRISING A COMPONENT HAVING TRISKELION-PILLARS, AND CORRESPONDING FABRICATION METHOD - An electronic product that includes a component having a first electrode with a first surface and a pillar extending from the first surface in a first direction, the pillar having three protrusions, the three protrusions forming angles of about 120 degrees with each other around a central line of the pillar where the three protrusions meet, and the three protrusions being bent so that the pillar has a triskelion cross-section in a plane perpendicular to the first direction. | 2021-02-04 |
| 20210036100 | CAPACITOR AND MANUFACTURING METHOD THEREFOR - Present disclosure provide a capacitor includes: a semiconductor substrate; a laminated structure including n conductive layers and m dielectric layer(s), the i-th conductive layer being provided with at least one i-th isolation trench, the (i+1)-th conductive layer being provided above the i-th conductive layer and in the i-th isolation trench, isolation trenches in odd-numbered and even-numbered conductive layers having a first and a second overlap region in a vertical direction respectively, and the first overlap region not overlapping the second overlap region, where m, n, and i are positive integers, n≥2, and 1≤i≤n−1; at least one first external electrode electrically connected to all odd-numbered conductive layer(s) through a first conductive via structure in the second overlap region; and at least one second external electrode electrically connected to all even-numbered conductive layer(s) through a second conductive via structure in the first overlap region. | 2021-02-04 |
| 20210036101 | METHODS OF FABRICATING CAPACITOR AND SEMICONDUCTOR DEVICE AND SEMICONDUCTOR DEVICES AND APPARATUS INCLUDING THE SAME - Capacitor forming methods may include sequentially forming a first mold layer, a first support material layer, and a second mold layer on a substrate, forming a mask pattern on the second mold layer, forming a recess in the second mold layer, the first support material layer, and the first mold layer using the mask pattern as a mask, forming a lower electrode in the recess, removing the mask pattern by a dry cleaning process, reducing a width of an upper portion of the lower electrode, removing the first mold layer, forming a dielectric layer on a surface of the lower electrode, and forming an upper electrode on the dielectric layer. | 2021-02-04 |
| 20210036102 | SEMICONDUCTOR DEVICE, INVERTER CIRCUIT, DRIVE DEVICE, VEHICLE, AND ELEVATOR - A semiconductor device of an embodiment includes a SiC layer including a first trench, a second trench having first and second regions, an n-type first SiC region, a p-type second SiC region, an n-type third SiC region, a p-type fourth SiC region between the first trench and the first SiC region, and a p-type fifth SiC region between the second trench and the first SiC region and having a first portion and a second portion, a gate electrode in the first trench, a first electrode in the second trench, and a second electrode. A distance between the first trench and the first region is greater than a distance between the first trench and the second region, the first portion is separated from the fourth SiC region, the second portion contacts the fourth SiC region, the first region contacts the first portion, and the second region contacts the second portion. | 2021-02-04 |
| 20210036103 | FABRICATION OF LATERAL SUPERJUNCTION DEVICES USING SELECTIVE EPITAXY - A lateral superjunction includes a substrate layer, a selective epitaxy layer deposited on the substrate layer, a trench formed into the selective epitaxy layer to expose a portion of the substrate layer, a first layer of semiconductor deposited in the trench, a second layer of semiconductor deposited adjacent to the first layer, and a first end layer of semiconductor deposited adjacent to the first layer of semiconductor and a second end layer of semiconductor deposited adjacent to the second layer of semiconductor. | 2021-02-04 |
| 20210036104 | CHARGE-BALANCE POWER DEVICE, AND PROCESS FOR MANUFACTURING THE CHARGE-BALANCE POWER DEVICE - A charge-balance power device includes a semiconductor body having a first conductivity type. A trench gate extends in the semiconductor body from a first surface toward a second surface. A body region has a second conductivity type that is opposite the first conductivity type, and the body region faces the first surface of the semiconductor body and extends on a first side and a second side of the trench gate. Source regions having the first conductivity type extend in the body region and face the first surface of the semiconductor body. A drain terminal extends on the second surface of the semiconductor body. The device further comprises a first and a second columnar region having the second conductivity, which extend in the semiconductor body adjacent to the first and second sides of the trench gate, and the first and second columnar regions are spaced apart from the body region and from the drain terminal. | 2021-02-04 |
| 20210036105 | VERTICAL COMPOUND SEMICONDUCTOR STRUCTURE AND METHOD FOR PRODUCING THE SAME - The invention relates to a vertical compound semiconductor structure having a substrate with a first main surface and an opposite second main surface, a vertical channel opening extending completely through the substrate between the first main surface and the second main surface and a layer stack arranged within the vertical channel opening. The layer stack includes an electrically conductive layer arranged within the vertical channel opening and a compound semiconductor layer arranged within the vertical channel opening. The compound semiconductor layer includes a compound semiconductor layer arranged on the electrically conductive layer and connected galvanically to the electrically conductive layer. Further, the invention relates to a method for producing such a vertical compound semiconductor structure. | 2021-02-04 |
| 20210036106 | SEMICONDUCTOR DEVICE - A semiconductor device includes a substrate having a first region and a second region, first and second nanowires disposed sequentially on the substrate in the first region, and extending respectively in a first direction, third and fourth nanowires disposed sequentially on the substrate in the second region, and extending respectively in the first direction, a first inner spacer between the first nanowire and the second nanowire, and including hydrogen of a first hydrogen mole fraction, and a second inner spacer between the third nanowire and the fourth nanowire, and including hydrogen of a second hydrogen mole fraction that is greater than the first hydrogen mole fraction. | 2021-02-04 |
| 20210036107 | SEMICONDUCTOR DEVICE - Provided is a technique capable of improving performance of a semiconductor device. A semiconductor device includes a first semiconductor region of a first conductivity type, a second semiconductor region. of a second conductivity type located on the first semiconductor region, third and fourth semiconductor regions of the second conductivity type, a fifth semiconductor region of the first conductivity type, and an electrode. The third semiconductor region is located on the second semiconductor region, and has a higher impurity concentration than the second semiconductor region. The fourth semiconductor region has a higher impurity concentration than the second semiconductor region, is located separately from the third semiconductor region in a planar view, and has contact with the second semiconductor region. The fifth semiconductor region is located on the second semiconductor region, and is located between the third and fourth semiconductor regions in a planar view. The electrode does not have contact with the fourth and fifth semiconductor regions but has contact with the third semiconductor region. | 2021-02-04 |
| 20210036108 | HIGH VOLTAGE TRANSISTOR WITH FIN SOURCE/DRAIN REGIONS AND TRENCH GATE STRUCTURE - An illustrative device includes a transistor including a first set of fins defined above a substrate, a second set of fins defined above the substrate, and a gate structure embedded in the substrate between the first set of fins and the second set of fins, wherein the first set of fins and the second set of fins are doped with a first dopant type and the substrate is doped with a second dopant type different than the first dopant type. | 2021-02-04 |
| 20210036109 | SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD OF SEMICONDUCTOR DEVICE - A semiconductor device includes a source structure, a bit line, a stacked structure between the source structure and the bit line, a source contact structure penetrating the stacked structure and electrically coupled to the source structure, and a protective pattern interposed between the source contact structure and the source structure and having a varying thickness depending on an area of the protective pattern. | 2021-02-04 |
| 20210036110 | QUANTUM WELL STACKS FOR QUANTUM DOT DEVICES - Disclosed herein are quantum dot devices, as well as related computing devices and methods. For example, in some embodiments, a quantum dot device may include: a quantum well stack including a quantum well layer, wherein the quantum well layer includes an isotopically purified material; a gate dielectric above the quantum well stack; and a gate metal above the gate dielectric, wherein the gate dielectric is between the quantum well layer and the gate metal. | 2021-02-04 |
| 20210036111 | METHOD FOR REDUCING SCHOTTKY BARRIER HEIGHT AND SEMICONDUCTOR DEVICE WITH REDUCED SCHOTTKY BARRIER HEIGHT - A method for controlling Schottky barrier height in a semiconductor device includes forming an alloy layer including at least a first element and a second element on a first surface of a semiconductor substrate. The semiconductor substrate is a first element-based semiconductor substrate, and the first element and the second element are Group IV elements. A first thermal anneal of the alloy layer and the first element-based substrate is performed. The first thermal anneal causes the second element in the alloy layer to migrate towards a surface of the alloy layer. A Schottky contact layer is formed on the alloy layer after the first thermal anneal. | 2021-02-04 |
| 20210036112 | LDMOSFET DEVICE AND METHOD FOR MAKING THE SAME - The disclosure discloses an LDMOSFET device. The second side of a polysilicon gate is extended to the surface of a drift region field oxide and forms a first field plate. A second field plate dielectric layer and a second field plate are formed between the second side of the polysilicon gate and the second side of the drift region field oxide. The second field plate is formed by a metal silicide formed on the surface of the self-aligned block dielectric layer. The first field plate and the second field plate are connected together through a metal layer and are connected to a gate formed by the metal layer. The disclosure further discloses a method for making the LDMOSFET device. The disclosure can optimize the relationship between BV and Rsp of the device. | 2021-02-04 |
| 20210036113 | SEMICONDUCTOR DEVICE, SEMICONDUCTOR MODULE, AND PACKAGED SEMICONDUCTOR DEVICE - A semiconductor device includes a semiconductor substrate including a first conductivity-type impurity, a low-concentration impurity layer including a first conductivity-type impurity having a concentration lower than a concentration of the first conductivity-type impurity in the semiconductor substrate, a backside electrode including a metal material, and first and second transistors in the low-concentration impurity layer. The first transistor includes a first source electrode and a first gate electrode on a surface of the low-concentration impurity layer, the second transistor includes a second source electrode and a second gate electrode on the surface of the low-concentration impurity layer. The semiconductor substrate serves as a common drain region of the transistors. The thickness of the backside electrode ranges from 25 to 35 μm, and the ratio of the thickness of the backside electrode to the thickness of a semiconductor layer including the semiconductor substrate and the low-concentration impurity layer is 0.32 or more. | 2021-02-04 |
| 20210036114 | SEMICONDUCTOR DEVICE, SEMICONDUCTOR MODULE, AND PACKAGED SEMICONDUCTOR DEVICE - A semiconductor device includes a semiconductor substrate including a first conductivity-type impurity, a low-concentration impurity layer including a first conductivity-type impurity having a concentration lower than a concentration of the first conductivity-type impurity in the semiconductor substrate, a backside electrode including a metal material, and first and second transistors in the low-concentration impurity layer. The first transistor includes a first source electrode and a first gate electrode on a surface of the low-concentration impurity layer, the second transistor includes a second source electrode and a second gate electrode on the surface of the low-concentration impurity layer. The semiconductor substrate serves as a common drain region of the transistors. The thickness of the backside electrode ranges from 25 to 35 μm, and the ratio of the thickness of the backside electrode to the thickness of a semiconductor layer including the semiconductor substrate and the low-concentration impurity layer is 0.32 or more. | 2021-02-04 |
| 20210036115 | FIELD-EFFECT TRANSISTOR - A field effect transistor according to the present invention includes a semiconductor substrate, a plurality of drain electrodes provided on a first surface of the semiconductor substrate and extending in a first direction, an input terminal, an output terminal, and a plurality of metal layers provided in the semiconductor substrate apart from the first surface and extending in a second direction crossing the first direction, in which the plurality of metal layers include a first metal layer and a second metal layer which is longer than the first metal layer and which crosses more drain electrodes than the first metal layer when seen from a direction perpendicular to the first surface, and among the plurality of drain electrodes, those having a smaller length of line from the input terminal to the output terminal are provided with more metal layers directly thereunder. | 2021-02-04 |
| 20210036116 | SEMICONDUCTOR DEVICE, INVERTER CIRCUIT, DRIVE DEVICE, VEHICLE, AND ELEVATOR - A semiconductor device of an embodiment includes a first electrode, a second electrode, a silicon carbide layer between the first electrode and the second electrode, and the silicon carbide layer having a first plane and a second plane, the silicon carbide layer including a first trench, p-type first silicon carbide regions and n-type second silicon carbide regions alternately disposed, a p-type third silicon carbide region between the second silicon carbide region and the first plane, and an n-type fourth silicon carbide region between the third silicon carbide region and the first plane, and a p-type fifth silicon carbide region between the first silicon carbide region and the first trench, a gate electrode in the first trench, and a gate insulating layer. The length of the first silicon carbide region perpendicular to the first plane is longer than a depth of the first trench. | 2021-02-04 |
| 20210036117 | Memory And Method For Forming The Same - The present disclosure provides a memory and a method for forming the memory. The method includes: providing a base with a first fin and a second fin formed thereon, wherein the first fin comprises an erasing region and a floating gate region on both sides of the erasing region, and a sacrificial layer is disposed on a surface of the erasing region and a surface of the second fin; forming a floating gate structure across the floating gate region on the base; forming a first sidewall film on a top surface and sidewall surfaces of the floating gate structure on the base; removing the sacrificial layer, and forming an opening in the floating gate structure and the first sidewall film; and forming an erasing gate structure in the opening. The memory formed by the method has good performance. | 2021-02-04 |
| 20210036118 | MEMORY DEVICE AND MANUFACTURING METHOD THEREOF - A memory device includes a floating gate, a control gate, a spacer structure, a dielectric layer, and an erase gate. The floating gate is above a substrate. The floating gate has a curved sidewall. The control gate is above the floating gate. The spacer structure is in contact with the control gate and the floating gate. The spacer structure is spaced apart from the curved sidewall of the floating gate. The dielectric layer is in contact with the spacer structure and the curved sidewall of the floating gate. The erase gate is above the dielectric layer. | 2021-02-04 |
| 20210036119 | GATE-ALL-AROUND STRUCTURE AND MANUFACTURING METHOD FOR THE SAME - A gate-all-around structure is provided. The gate-all-around structure includes a plurality of nanostructures stacked over a substrate in a vertically direction, and the nanostructures extends from a gate region to a source/drain (S/D) region. The gate-all-around structure includes a gate structure formed in the gate region around the first nanostructures, and a S/D structure formed in the S/D region. The S/D structure is in direct contact with a top surface of one of the nanostructures | 2021-02-04 |
| 20210036120 | FINFET SEMICONDUCTOR DEVICE - A semiconductor device is disclosed that includes a plurality of fins on a substrate. A long channel gate is disposed over a first portion of the plurality of fins. A gate contact is provided having an extended portion that extends into an active area from a gate contact base outside the active area. | 2021-02-04 |
| 20210036121 | SEMICONDUCTOR DEVICES INCLUDING A GATE ISOLATION STRUCTURE AND A GATE CAPPING LAYER INCLUDING DIFFERENT MATERIALS FROM EACH OTHER - A semiconductor device is provided including an active region on a substrate A plurality of channel layers is spaced apart on the active region. Gate structures are provided. The gate structures intersect the active region and the plurality of channel layers. The gate structures surround the plurality of channel layers. Source/drain regions are disposed on the active region on at least one side of the gate structures. The source/drain regions contact with the plurality of channel layers. A lower insulating layer is disposed between side surfaces of the gate structures on the source/drain regions. Contact plugs penetrate through the lower insulating layer. The contact plugs contact the source/drain regions. An isolation structure intersects the active region on the substrate and is disposed between the source/drain regions adjacent to each other. Each of the gate structures includes a gate electrode and a gate capping layer including materials different from each other. | 2021-02-04 |
| 20210036122 | Methods of Reducing Parasitic Capacitance in Multi-Gate Field-Effect Transistors - A semiconductor structure includes a stack of semiconductor layers disposed over a substrate, a first metal gate stack disposed over the stack of semiconductor layers, a second metal gate stack interleaved between the stack of semiconductor layers, a source/drain (S/D) feature disposed in the stack of semiconductor layers, and an S/D contact disposed over the S/D feature. In many examples, the S/D feature is separated from a sidewall of the second metal gate stack by a first air gap and the S/D contact is separated from a sidewall of the first metal gate stack by a second air gap. | 2021-02-04 |
| 20210036123 | METHOD OF MANUFACTURING A SEMICONDUCTOR DEVICE - A method of making a semiconductor device includes forming first and second dummy gates over a substrate. The method includes removing the first and second dummy gates to define first and second openings. The method includes depositing a continuous gate dielectric layer in the first opening and the second opening. The method includes depositing a continuous capping layer on the gate dielectric layer, wherein the capping layer includes TaC. The method further includes depositing a continuous barrier layer on the capping layer, wherein the barrier layer includes TaC and a second material. The method includes depositing a first work function layer over the barrier layer in the first opening. The method includes depositing a second work function layer over the barrier layer in the second opening. The method includes depositing a continuous metal layer over each of the first work function layer and the second work function layer. | 2021-02-04 |
| 20210036124 | PROCESS FOR PRODUCING PREPARING A THIN LAYER OF FERROELECTRIC MATERIAL - A process for preparing a thin layer made of ferroelectric material based on alkali metal, exhibiting a determined Curie temperature, transferred from a donor substrate to a carrier substrate by using a transfer technique including implanting light species into the donor substrate in order to produce an embrittlement plane, the thin layer having a first, free face and a second face that is arranged on the carrier substrate. The process comprises a first heat treatment of the transferred thin layer at a temperature higher than the Curie temperature, the thin layer exhibiting a multi-domain character upon completion of the first heat treatment, and introducing, after the first heat treatment, protons into the thin layer, followed by applying a second heat treatment of the thin layer at a temperature lower than the Curie temperature to generate an internal electric field that results in the thin layer being made single domain. | 2021-02-04 |
| 20210036125 | MEMORY MODULES AND MEMORY PACKAGES INCLUDING GRAPHENE LAYERS FOR THERMAL MANAGEMENT - Systems, apparatuses, and methods relating to memory devices and packaging are described. A device, such as a dual inline memory module (DIMM) or other electronic device package, may include a substrate with a layer of graphene configured to conduct thermal energy (e.g., heat) away from components mounted or affixed to the substrate. In some examples, a DIMM includes an uppermost or top layer of graphene that is exposed to the air and configured to allow connection of memory devices (e.g., DRAMs) to be soldered to the conducting pads of the substrate. The graphene may be in contact with parts of the memory device other than the electrical connections with the conducting pads and may thus be configured as a heat sink for the device. Other thin, conductive layers of may be used in addition to or as an alternative to graphene. Graphene may be complementary to other heat sink mechanisms. | 2021-02-04 |
| 20210036126 | FABRICATION PROCESS COMPRISING AN OPERATION OF DEFINING AN EFFECTIVE CHANNEL LENGTH FOR MOSFET TRANSISTORS - In fabricating metal-oxide-semiconductor field-effect transistors (MOSFETs), the implanting of lightly doped drain regions is performed before forming gate regions with a physical gate length that is associated with a reference channel length. The step of implanting lightly doped drain regions includes forming an implantation mask defining the lightly doped drain regions and an effective channel length of each MOSFET. The forming of the implantation mask is configured to define an effective channel length of at least one MOSFET that is different from the respective reference channel length. | 2021-02-04 |
| 20210036127 | DEVICE PERFORMANCE BY FLUORINE TREATMENT - A method for forming a semiconductor structure is provided. The method includes patterning a semiconductor substrate to form a semiconductor fin, forming a source/drain structure on the semiconductor fin, forming an interfacial layer on the semiconductor fin, treating the interfacial layer with fluorine, forming a ferroelectric gate dielectric layer on the interfacial layer, treating the ferroelectric gate dielectric layer with fluorine, and forming a gate electrode layer on the ferroelectric gate dielectric layer. | 2021-02-04 |
| 20210036128 | Structure and Formation Method of Semiconductor Device Structure with Gate Stack - Structures and formation methods of a semiconductor device structure are provided. The semiconductor device structure includes a semiconductor substrate and a gate electrode over the semiconductor substrate. The semiconductor device structure also includes a source/drain structure adjacent to the gate electrode. The semiconductor device structure further includes a spacer element over a sidewall of the gate electrode, and the spacer element has an upper portion having a first exterior surface and a lower portion having a second exterior surface. Lateral distances between the first exterior surface and the sidewall of the gate electrode are substantially the same. Lateral distances between the second exterior surface and the sidewall of the gate electrode increase along a direction from a top of the lower portion towards the semiconductor substrate. | 2021-02-04 |
| 20210036129 | Semiconductor Device, Method, and Tool of Manufacture - In an embodiment, a method includes: performing a self-limiting process to modify a top surface of a wafer; after the self-limiting process completes, removing the modified top surface from the wafer; and repeating the performing the self-limiting process and the removing the modified top surface from the wafer until a thickness of the wafer is decreased to a predetermined thickness. | 2021-02-04 |
| 20210036130 | Controlling Fin-Thinning Through Feedback - A method includes forming isolation regions extending into a semiconductor substrate. A semiconductor strip is between the isolation regions. The method further includes recessing the isolation regions so that a top portion of the semiconductor strip protrudes higher than top surfaces of the isolation regions to form a semiconductor fin, measuring a fin width of the semiconductor fin, generating an etch recipe based on the fin width, and performing a thinning process on the semiconductor fin using the etching recipe. | 2021-02-04 |
| 20210036131 | FINFET Device Having a Channel Defined in a Diamond-Like Shape Semiconductor Structure - The present disclosure provides a FinFET device. The FinFET device comprises a semiconductor substrate of a first semiconductor material; a fin structure of the first semiconductor material overlying the semiconductor substrate, wherein the fin structure has a top surface of a first crystal plane orientation; a diamond-like shape structure of a second semiconductor material disposed over the top surface of the fin structure, wherein the diamond-like shape structure has at least one surface of a second crystal plane orientation; a gate structure disposed over the diamond-like shape structure, wherein the gate structure separates a source region and a drain region; and a channel region defined in the diamond-like shape structure between the source and drain regions. | 2021-02-04 |
| 20210036132 | METHOD OF MANUFACTURING SEMICONDUCTOR DEVICE - A trench is formed by removing a portion of each of the charge accumulation film and the insulating film located between the control gate electrode and the memory gate electrode. The insulating film is formed in the trench so that the upper surface of each of the insulating film and the charge accumulation film is covered with the insulating film. When exposing the upper surface of the control gate electrode and the memory gate electrode, the upper surface of each of the insulating film and the charge accumulation film is not exposed. | 2021-02-04 |
| 20210036133 | Graphene Spin Transistor and Graphene Rashba Spin Logic Gate for All-Electrical Operation at Room Temperature - The present disclosure relates to a graphene spin transistor for all-electrical operation at room temperature and a logic gate using the graphene Rashba spin transistor. A graphene spin transistor of the present disclosure provides a graphene spin FET (Field Effect Transistor) for all-electrical operation at room temperature without a magnetic field or a ferromagnetic electrode by utilizing the Rashba-Edelstein effect in the graphene or the spin Hall effect of a TMDC (Transition Metal Dichalcogenide) material in order to replace CMOS transistors and extend Moore's Law, and further provides a logic gate using the graphene Rashba spin transistor. | 2021-02-04 |
| 20210036134 | Bipolar Transistor and Production Method Therefor - An element portion is formed on a heat dissipation substrate, and the element portion includes a collector layer, a base layer, an emitter layer, an emitter cap layer, an emitter electrode, and a base electrode. A metallic emitter heat dissipation via that connects an emitter wiring to an emitter heat dissipation pad is provided, and a metallic base heat dissipation via that connects a base wiring to a base heat dissipation pad is also provided. | 2021-02-04 |
| 20210036135 | IGBT POWER DEVICE AND FABRICATION METHOD THEREFOR - Provided is an IGBT power device. The device includes: a p-type collector region; an n-type drift region located above the p-type collector region; multiple first grooves, where a second groove is provided below each of the multiple first grooves; a gate structure located in the first groove and the second groove; a p-type body region located between two adjacent first grooves; an n-type emitter region located in the p-type body region; and an n-type hole charge blocking region located between two adjacent second grooves. | 2021-02-04 |
| 20210036136 | SHORT-CIRCUIT SEMICONDUCTOR COMPONENT AND METHOD FOR OPERATING IT - A short-circuit semiconductor component comprises a semiconductor body, in which a rear-side base region of a first conduction type, an inner region of a second complementary conduction type, and a front-side base region of the first conduction type are disposed. The rear-side base region is electrically connected to a rear-side electrode, and the front-side base region is electrically connected to a front-side electrode. A turn-on structure, which is an emitter structure of the second conduction type, is embedded into the front-side base region and/or rear-side base region and is covered by the respective electrode and is electrically contacted with the electrode placed on the base region respectively embedding it. It can be turned on by a trigger structure which can be activated by an electrical turn-on signal. In the activated state, the trigger structure injects an electrical current surge into the semiconductor body, which irreversibly destroys a semiconductor junction. | 2021-02-04 |
| 20210036137 | NANOWIRE STRUCTURES HAVING WRAP-AROUND CONTACTS - Nanowire structures having wrap-around contacts are described. For example, a nanowire semiconductor device includes a nanowire disposed above a substrate. A channel region is disposed in the nanowire. The channel region has a length and a perimeter orthogonal to the length. A gate electrode stack surrounds the entire perimeter of the channel region. A pair of source and drain regions is disposed in the nanowire, on either side of the channel region. Each of the source and drain regions has a perimeter orthogonal to the length of the channel region. A first contact completely surrounds the perimeter of the source region. A second contact completely surrounds the perimeter of the drain region. | 2021-02-04 |
| 20210036138 | HIGH ELECTRON MOBILITY TRANSISTOR - A high electron mobility transistor (HEMT) includes a substrate; a buffer layer over the substrate, a GaN layer over the buffer layer, a first AlGaN layer over the GaN layer, a first AlN layer over the AlGaN layer, and a p-GaN layer over the first AlN layer. | 2021-02-04 |
| 20210036139 | COMPOUND SEMICONDUCTOR DEVICE, METHOD FOR MANUFACTURING THE SAME AND AMPLIFIER - A compound semiconductor device includes: a semiconductor laminate structure including an electron transit layer and an electron supply layer that are formed from a compound semiconductor; a gate electrode, a source electrode, and a drain electrode that are provided above the electron supply layer; and an insulating layer that is provided between the source electrode and the drain electrode, over the semiconductor laminate structure, and with a gate recess formed therein, wherein the gate electrode includes: a first portion in the gate recess; and a second portion that is coupled to the first portion and is provided over the insulating layer at a position further on the drain electrode side than the gate recess, wherein the insulating layer includes an aluminum oxide film in direct contact with the semiconductor laminate structure. | 2021-02-04 |
| 20210036140 | SEMICONDUCTOR DEVICE HAVING DOPED SEED LAYER AND METHOD OF MANUFACTURING THE SAME - A semiconductor device includes a doped substrate and a seed layer in direct contact with the substrate. The seed layer includes a first seed sublayer having a first lattice structure. The first seed layer is doped with carbon. The seed layer further includes a second seed sublayer over the first see layer, wherein the second seed layer has a second lattice structure. The semiconductor device further includes a graded layer in direct contact with the seed layer. The graded layer includes a first graded sublayer including AlGaN having a first Al:Ga ratio; a second graded sublayer including AlGaN having a second Al:Ga ratio different from the first Al:Ga ratio; and a third graded sublayer over including AlGaN having a third Al:Ga ratio different from the second Al:Ga ratio. The semiconductor device includes a channel layer over the graded layer. The semiconductor device includes an active layer over the channel layer. | 2021-02-04 |
| 20210036141 | SEMICONDUCTOR DEVICE AND POWER CONVERSION DEVICE - Even when a stress is applied due to energization or switching operation, a connection state of electrode layers can be appropriately maintained. A semiconductor device includes a semiconductor layer of first conductivity type, an upper surface structure formed on a surface layer of the semiconductor layer, and an upper surface electrode formed over the upper surface structure. The upper surface electrode includes a first electrode formed on an upper surface of the semiconductor layer, and a second electrode formed over an upper surface of the first electrode. The first concave portion is formed on the upper surface of the first electrode. A side surface of the first concave portion has a tapered shape. The second electrode is formed over the upper surface of the first electrode including an inside of the first concave portion. | 2021-02-04 |
| 20210036142 | GENERATING MILLED STRUCTURAL ELEMENTS WITH A FLAT UPPER SURFACE - A miller, a non-transitory computer-readable medium, and a method for milling a multi-layered object. The method may include milling each structural element of an array of structural elements that are spaced apart from each other by gaps to provide the milled structural elements, wherein each milled structural element has a flat upper surface, wherein prior the milling each one of the structural elements of the array has a flat upper surface of a certain width, wherein the certain width is of a nanometric scale. The milling of each structural element of the array may include scanning a defocused ion beam of the certain width along a longitudinal axis of the structural element. A current intensity of the defocused ion beam decreases with a distance from a middle of the defocused ion beam. | 2021-02-04 |
| 20210036143 | FIELD EFFECT TRANSISTOR WITH A HYBRID GATE SPACER INCLUDING A LOW-K DIELECTRIC MATERIAL - A FET including a hybrid gate spacer separating a gate electrode from at least one of a source, a drain, or source/drain contact metallization. The hybrid spacer may include a low-k dielectric material for a reduction in parasitic capacitance. The hybrid spacer may further include one or more other dielectric materials of greater relative permittivity that may protect one or more surfaces of the low-k dielectric material from damage by subsequent transistor fabrication operations. The hybrid spacer may include a low-k dielectric material separating a lower portion of a gate electrode sidewall from the source/drain terminal, and a dielectric spacer cap separating to an upper portion of the gate electrode sidewall from the source/drain terminal. The hybrid spacer may have a lower total capacitance than conventional spacers while still remaining robust to downstream fabrication processes. Other embodiments may be described and/or claimed. | 2021-02-04 |
| 20210036144 | Inner Spacers for Gate-All-Around Semiconductor Devices - Semiconductor devices and methods are provided. A semiconductor device according to the present disclosure includes a first gate-all-around (GAA) transistor that includes a first plurality of channel members, and a second GAA transistor that includes a second plurality of channel members. The first plurality of channel members has a first pitch (P | 2021-02-04 |
| 20210036145 | FIN FIELD-EFFECT TRANSISTOR DEVICE AND METHOD OF FORMING THE SAME - A semiconductor device includes a first fin, a second fin, and a third fin protruding above a substrate, where the third fin is between the first fin and the second fin; a gate dielectric layer over the first fin, the second fin, and the third fin; a first work function layer over and contacting the gate dielectric layer, where the first work function layer extends along first sidewalls and a first upper surface of the first fin; a second work function layer over and contacting the gate dielectric layer, where the second work function layer extends along second sidewalls and a second upper surface of the second fin, where the first work function layer and the second work function layer comprise different materials; and a first gate electrode over the first fin, a second gate electrode over the second fin, and a third gate electrode over the third fin. | 2021-02-04 |
| 20210036146 | SEMICONDUCTOR STRUCTURE AND METHOD FOR FORMING THE SAME - A semiconductor structure and a method for forming the same are provided. One form of the method includes: providing a base, where a channel stack and a tear-off structure span the channel stack being formed on the base, and the channel stack including a sacrificial layer and a channel layer; forming a groove in channel stacks on both sides of a gate structure; laterally etching the sacrificial layer exposed from the groove to form a remaining sacrificial layer; forming a source/drain doped region in the channel layer exposed from the remaining sacrificial layer; forming an interlayer dielectric layer on the base; etching the interlayer dielectric layer on one side of the source region to expose a surface of the channel layer corresponding to the source region; etching the interlayer dielectric layer on one side of the drain region to expose the surface of the channel layer corresponding to the drain region; forming a first metal silicide layer on a surface of the channel layer corresponding to the source region; forming a second metal silicide layer on a surface of the channel layer corresponding to the drain region; forming a first conductive plug covering the first metal silicide layer and a second conductive plug covering the second metal silicide layer. In the present disclosure, contact resistance of the first conductive plug, the second conductive plug, and the source/drain doped region is reduced. | 2021-02-04 |
| 20210036147 | GATE STRUCTURE, METHOD OF FORMING THE SAME, AND SEMICONDUCTOR DEVICE HAVING THE SAME - Provided are a gate structure and a method of forming the same. The gate structure includes a gate dielectric layer, a metal layer, and a cluster layer. The metal layer is disposed over the gate dielectric layer. The cluster layer is sandwiched between the metal layer and the gate dielectric layer, wherein the cluster layer at least includes an amorphous silicon layer, an amorphous carbon layer, or an amorphous germanium layer. In addition, a semiconductor device including the gate structure is provided. | 2021-02-04 |
| 20210036148 | FinFET Device and Method of Forming and Monitoring Quality of the Same - A FinFET structure with a gate structure having two notch features therein and a method of forming the same is disclosed. The FinFET notch features ensure that sufficient spacing is provided between the gate structure and source/drain regions of the FinFET to avoid inadvertent shorting of the gate structure to the source/drain regions. Gate structures of different sizes (e.g., different gate widths) and of different pattern densities can be provided on a same substrate and avoid inadvertent of shorting the gate to the source/drain regions through application of the notched features. | 2021-02-04 |
| 20210036149 | SEMICONDUCTOR DEVICE, INVERTER CIRCUIT, DRIVING DEVICE, VEHICLE, AND ELEVATOR - A semiconductor device of an embodiment includes a silicon carbide layer having a first plane and a second plane and includes a trench located on a first plane side and has a first region and a second region, a first silicon carbide region of an n-type, a second silicon carbide region of a p-type between the first silicon carbide region and the first plane, a third silicon carbide region of the n-type between the second silicon carbide region and the first plane, and a fourth silicon carbide region of the p-type between the second region and the first silicon carbide region; a gate electrode in the first region; a first electrode on the first plane side of the silicon carbide layer, a part of the first electrode is located in the second region and is in contact with the third and the fourth silicon carbide region; and a second electrode. | 2021-02-04 |
| 20210036150 | LATERAL DOUBLE-DIFFUSED METAL OXIDE SEMICONDUCTOR COMPONENT AND MANUFACTURING METHOD THEREFOR - A lateral double-diffused metal oxide semiconductor component and a manufacturing method therefor. The lateral double-diffused metal oxide semiconductor component comprises: a semiconductor substrate, the semiconductor substrate being provided thereon with a drift area; the drift area being provided therein with a trap area and a drain area, the trap area being provided therein with an active area and a channel; the drift area being provided therein with a deep trench isolation structure arranged between the trap area and the drain area, and the deep trench isolation structure being provided at the bottom thereof with alternately arranged first p-type injection areas and first n-type injection areas. | 2021-02-04 |
| 20210036151 | FOLDED CHANNEL VERTICAL TRANSISTOR AND METHOD OF FABRICATING SAME - A semiconductor structure includes a substrate having a top surface, pillar structures formed on top of the substrate, a gate conductor, a drain/source region and a source/drain region. Each pillar structure of the pillar structures includes a first end and a second end, and the first end is closer to the substrate than the second end. The gate conductor surrounds each of the pillar structures disposed between the first end and the second end. The drain/source region is at the top surface of the substrate and in contact with the first end of a first pillar structure of the pillar structures, and the source/drain region is at the top surface of the substrate and in contact with the first end of a second pillar structure of the pillar structures. | 2021-02-04 |
| 20210036152 | Method for Fabricating a Semiconductor Device - A new method for fabricating a semiconductor device with high selection phosphoric acid solution and eliminating the step of oxide removal and thus reducing oxide loss to improve yield gain and cost saving. | 2021-02-04 |
| 20210036153 | Semiconductor Device and Method for Manufacturing the Same - The present disclosure discloses a semiconductor device, which comprises: an embedded gate structure with a bottom embedded in a semiconductor substrate; a channel region formed below the bottom surface of the embedded gate structure; a source region and a drain region formed on the two sides of the embedded gate structure; an embedded epitaxial layer formed in the source region or the drain region, the bottom surface of the embedded gate structure being in flush with the maximum stress position of the embedded epitaxial layer. The present disclosure further discloses a method for manufacturing a semiconductor device. The present disclosure can enable the channel region to be located in the maximum stress region of the embedded epitaxial layer, thereby improving the mobility of channel carriers to the utmost extent and improving the conduction current of the device. | 2021-02-04 |
| 20210036154 | SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD THEREOF - A fin field effect transistor (Fin FET) device includes a fin structure extending in a first direction and protruding from an isolation insulating layer disposed over a substrate. The fin structure includes a well layer, an oxide layer disposed over the well layer and a channel layer disposed over the oxide layer. The Fin FET device includes a gate structure covering a portion of the fin structure and extending in a second direction perpendicular to the first direction. The Fin FET device includes a source and a drain. Each of the source and drain includes a stressor layer disposed in recessed portions formed in the fin structure. The stressor layer extends above the recessed portions and applies a stress to a channel layer of the fin structure under the gate structure. The Fin FET device includes a dielectric layer formed in contact with the oxide layer and the stressor layer in the recessed portions. | 2021-02-04 |
| 20210036155 | EMBEDDED SOURCE OR DRAIN REGION OF TRANSISTOR WITH DOWNWARD TAPERED REGION UNDER FACET REGION - In some embodiments, a field effect transistor (FET) structure comprises a body structure, dielectric structures, a gate structure and a source or drain region. The gate structure is formed over the body structure. The source or drain region is embedded in the body structure beside the gate structure, and abuts and is extended beyond the dielectric structure. The source or drain region contains stressor material with a lattice constant different from that of the body structure. The source or drain region comprises a first region formed above a first level at a top of the dielectric structures and a second region that comprises downward tapered side walls formed under the first level and abutting the corresponding dielectric structures. | 2021-02-04 |
| 20210036156 | METHOD TO INDUCE STRAIN IN 3-D MICROFABRICATED STRUCTURES - Methods and structures for forming strained-channel finFETs are described. Fin structures for finFETs may be formed in two epitaxial layers that are grown over a bulk substrate. A first thin epitaxial layer may be cut and used to impart strain to an adjacent channel region of the finFET via elastic relaxation. The structures exhibit a preferred design range for increasing induced strain and uniformity of the strain over the fin height. | 2021-02-04 |
| 20210036157 | SEMICONDUCTOR DEVICE WITH GATE STACK - A semiconductor device is provided. The semiconductor device includes a gate stack over a semiconductor substrate. The gate stack has a conductive structure and a gate dielectric layer, and a top of the gate dielectric layer is higher than a top of the conductive structure. The semiconductor device also includes a protection element over the gate stack. The semiconductor device further includes a spacer extending along a side surface of the protection element and a sidewall of the gate stack. | 2021-02-04 |
| 20210036158 | SEMICONDUCTOR DEVICE AND METHOD FOR PRODUCING SAME - A semiconductor device ( | 2021-02-04 |
| 20210036159 | SEMICONDUCTOR DEVICE - A transistor includes oxide semiconductor stacked layers between a first gate electrode layer and a second gate electrode layer through an insulating layer interposed between the first gate electrode layer and the oxide semiconductor stacked layers and an insulating layer interposed between the second gate electrode layer and the oxide semiconductor stacked layers. The thickness of a channel formation region is smaller than the other regions in the oxide semiconductor stacked layers. Further in this transistor, one of the gate electrode layers is provided as what is called a back gate for controlling the threshold voltage. Controlling the potential applied to the back gate enables control of the threshold voltage of the transistor, which makes it easy to maintain the normally-off characteristics of the transistor. | 2021-02-04 |
| 20210036160 | SEMICONDUCTOR DEVICE AND METHOD FOR MANUFACTURING THE SAME - Many of the physical properties of a silicon semiconductor have already been understood, whereas many of the physical properties of an oxide semiconductor have been still unclear. In particular, an adverse effect of an impurity on an oxide semiconductor has been still unclear. In view of the above, a structure is disclosed in which an impurity that influences electrical characteristics of a semiconductor device including an oxide semiconductor layer is prevented or is eliminated. A semiconductor device which includes a gate electrode, an oxide semiconductor layer, and a gate insulating layer provided between the gate electrode and the oxide semiconductor layer and in which the nitrogen concentration in the oxide semiconductor layer is 1×10 | 2021-02-04 |
| 20210036161 | DISPLAY SUBSTRATE, MANUFACTURING METHOD THEREOF, AND DISPLAY DEVICE - The present disclosure provides a display substrate, a manufacturing method thereof, and a display device. The display substrate includes a base substrate and thin-film transistors disposed on the base substrate, where the thin-film transistors each comprises a gate, an active layer insulated from the gate, and two ohmic contact parts in direct contact with the active layer, leaving a gap region between the two ohmic contact parts; and each of the ohmic contact parts comprises a lightly doped region and a heavily doped region, and an orthographic projection of the lightly doped region on the base substrate and an orthographic projection of the heavily doped region on the base substrate do not overlap each other. | 2021-02-04 |
| 20210036162 | Integrated Transistors Having Gate Material Passing Through a Pillar of Semiconductor Material, and Methods of Forming Integrated Transistors - Some embodiments include an integrated assembly having a pillar of semiconductor material. The pillar has a base region, and bifurcates into two segments which extend upwardly from the base region. The two segments are horizontally spaced from one another by an intervening region. A conductive gate is within the intervening region. A first source/drain region is within the base region, a second source/drain region is within the segments, and a channel region is within the segments. The channel region is adjacent to the conductive gate and is vertically disposed between the first and second source/drain regions. Some embodiments include methods of forming integrated assemblies. | 2021-02-04 |
| 20210036163 | THIN FILM TRANSISTOR AND PRODUCTION METHOD THEREFOR - A thin film transistor ( | 2021-02-04 |
| 20210036164 | SCHOTTKY BARRIER DIODE - Disclosed is a Schottky barrier diode which may be applied to an application that requires a low off current (Ioff), such as a mobile integrated circuit. The Schottky barrier diode can improve a blocking characteristic for a backward current flow while maintaining an advantage of a turn-on current, by improving the structure of a contact surface that is pinched off by depletion. | 2021-02-04 |
| 20210036165 | MERGED PiN SCHOTTKY (MPS) DIODE WITH ENHANCED SURGE CURRENT CAPACITY - In one aspect, a merged PiN Schottky (MPS) diode may include a silicon carbide substrate having a first conductivity type. The epitaxial layer with a first conductivity type was formed on the substrate, which has doping concentration lower than the substrate. A plurality of regions having the second conductivity type different from the first conductivity type are formed under the surface of the epitaxial layer. The Ohmic contact metal is formed on the region of the second conductivity type. The Schottky contact metal is placed on top of the entire epitaxial layer to form a Schottky junction. The Ohmic contact was formed by a cathode electrode on the back side of the substrate. | 2021-02-04 |
| 20210036166 | MERGED PiN SCHOTTKY (MPS) DIODE WITH MULTIPLE CELL DESIGN AND MANUFACTURING METHOD THEREOF - A method for manufacturing a merged PiN Schottky (MPS) diode may include steps of providing a substrate having a first conductivity type; forming an epitaxial layer with the first conductivity type on top of the substrate; forming a plurality of regions with a second conductivity type under a top surface of the epitaxial layer; depositing and patterning a first Ohmic contact metal on the regions with the second conductivity type; depositing a Schottky contact metal on top of the entire epitaxial layer; and forming a second Ohmic contact metal on a backside of the substrate. In another embodiment, the step of forming a plurality of regions with a second conductivity type under a top surface of the epitaxial layer may include steps of depositing and patterning a mask layer on the epitaxial layer, implanting P-type dopant into the epitaxial layer, and removing the mask layer. | 2021-02-04 |
| 20210036167 | MERGED PiN SCHOTTKY (MPS) DIODE WITH PLASMA SPREADING LAYER AND MANUFACTURING METHOD THEREOF - A method for manufacturing a merged PiN Schottky (MPS) diode may include steps of providing a substrate having a first conductivity type; forming an epitaxial layer with the first conductivity type on top of the substrate; forming a plurality of regions with a second conductivity type under a top surface of the epitaxial layer; forming a plasma spreading layer; depositing and patterning a first Ohmic contact metal on the regions with the second conductivity type; depositing a Schottky contact metal on top of the entire epitaxial layer; and forming a second Ohmic contact metal on a backside of the substrate. In another embodiment, the step of forming a plurality of regions with a second conductivity type may include steps of depositing and patterning a mask layer on the epitaxial layer, implanting P-type dopant into the epitaxial layer, and removing the mask layer. | 2021-02-04 |
| 20210036168 | COMPLEMENTARY METAL-OXIDE-SEMICONDUCTOR (MOS) CAPACITOR - Aspects generally relate to a complimentary MOS capacitor with improved linearity. A complimentary MOS capacitor includes an n-type MOS capacitor and a p-type MOS capacitor coupled in parallel. The p-type MOS capacitor biased to an opposite voltage polarity of the n-type MOS capacitor. | 2021-02-04 |
| 20210036169 | LOW DRAIN-SOURCE ON RESISTANCE SEMICONDUCTOR COMPONENT AND METHOD OF FABRICATION - A device wafer is provided that includes a substrate having major and minor surfaces, and a plurality of active devices located at the major surface. A eutectic alloy composition having a first thickness is formed at the minor surface of the substrate. The eutectic alloy composition is partially removed from the minor surface of the substrate such that a second thickness of the eutectic alloy composition remains on the minor surface, the second thickness being less than the first thickness. A bonding layer is deposited over the eutectic alloy composition. The bonding layer is utilized for joining semiconductor components of the device wafer to secondary structures. | 2021-02-04 |
| 20210036170 | PHOTODIODE WITH ANTIREFLECTIVE AND HIGH CONDUCTIVE METAL-SEMICONDUCTOR STRUCTURE, METHOD FOR MANUFACTURING THE SAME, AND SOLAR CELL COMPRISING THE SAME - The present disclosure provides a photodiode which maintains a photodiode characteristic even after the metal-assisted chemical etching and uses a metal-semiconductor structure having low reflectance and high conductance, a manufacturing method thereof, and a solar cell using the same. The photodiode of the present disclosure includes a semiconductor substrate with a low reflective and high conductive surface which has a selectively etched electrode formation area and a high conductive electrode formed by placing a metal catalyst used for a metal-assisted chemical etching process for forming an antireflection semiconductor substrate in an etching area of the antireflection semiconductor substrate. | 2021-02-04 |
| 20210036171 | SOLAR CELL EMITTER REGION FABRICATION WITH DIFFERENTIATED P-TYPE AND N-TYPE ARCHITECTURES AND INCORPORATING DOTTED DIFFUSION - Methods of fabricating solar cell emitter regions with differentiated P-type and N-type architectures and incorporating dotted diffusion, and resulting solar cells, are described. In an example, a solar cell includes a substrate having a light-receiving surface and a back surface. A first polycrystalline silicon emitter region of a first conductivity type is disposed on a first thin dielectric layer disposed on the back surface of the substrate. A second polycrystalline silicon emitter region of a second, different, conductivity type is disposed on a second thin dielectric layer disposed in a plurality of non-continuous trenches in the back surface of the substrate. | 2021-02-04 |
| 20210036172 | PHOTOVOLTAIC POWER GENERATION MODULE - Disclosed is a photovoltaic power generation module having a single layer structure in which a pattern glass and a solar cell module are integrated. The disclosed photovoltaic power generation module comprises: a pattern glass comprising a base member, and a pattern member provided thereon in which an optical pattern is formed; a solar cell module provided with a solar cell; a plurality of supportive adhering parts in a pillar shape adhered to the pattern member; and a filler filled between the supportive adhering part and the solar cell module, wherein the pattern glass and the solar cell module are integrated through the supportive adhering parts and the filler, and the height of the supportive adhering parts are configured to be greater than the height of the pattern member so that a gap for forming an air layer between the pattern member and the filler can be provided. | 2021-02-04 |
| 20210036173 | STABILIZED SHINGLED SOLAR CELL STRINGS AND METHODS FOR THEIR PRODUCTION - The present invention is directed to solar cell strings comprising (i) a string of solar cells shingled in string direction, resulting in positive and negative electrode overlap, (ii) an interconnect for electrically connecting the positive and negative electrodes of the shingled solar cells, and (iii) an adhesive foil spanning at least part of the string and positioned on (a) the top (sun facing) sides of the at least two shingled solar cells, and/or (b) the bottom (far) sides of the at least two shingled solar cells, or on (c) the top side of one solar cell and on the bottom side of the overlapping solar cell, in which case the adhesive foil comprises the interconnect and connects the overlap in order to mechanically connect and position the shingled solar cells. In addition, the present invention relates to a method for producing such solar cell strings. | 2021-02-04 |
| 20210036174 | DURABLE SOLAR PANELS - Embodiments provide solar panels and methods of assembly thereof, permitting operation of a photovoltaic material with reduced degradation. As one example, a solar panel comprises one or more solar cells that include perovskite, the one or more solar cells encapsulated by a film and housed in a glass exterior that is hermetically sealed to maintain a vacuum in an interior of the solar panel of 10 | 2021-02-04 |
| 20210036175 | LASER LIGHT COLLECTING ASSEMBLY - A laser light collecting assembly for a wireless power receiver. The assembly includes a compound parabolic concentrator (CPC) mirror and an optical to electrical converter. The CPC minor has curved internal walls that define an inlet aperture and connect the inlet aperture to an outlet aperture. The inlet aperture may be larger than the outlet aperture. The internal walls may focus a majority of the laser light entering the inlet aperture to the outlet aperture. The optical to electrical converter may be positioned adjacent to the outlet aperture and configured to receive the laser light exiting the outlet aperture so as to convert optical power in the laser light to electrical power. | 2021-02-04 |
| 20210036176 | OPTICAL SEMICONDUCTOR ELEMENT - An optical semiconductor element having a mesa portion includes a substrate and semiconductor layers on the substrate. The optical semiconductor element further includes a first contact electrode, a second contact electrode on the semiconductor layer, first and second lead-out wires connected to the first and second contact electrodes, respectively, and an insulating film covering at least an upper surface of the semiconductor layer and the second contact electrode. The second lead-out wire is connected to the second contact electrode in an opening of the insulating film. An outer peripheral end of the second contact electrode in at least a portion where the second contact electrode and the second lead-out wire are connected is above and outside an outer peripheral end of a connection portion with the semiconductor layer, and an inner peripheral end is above and inside an inner peripheral end of the connection portion with the semiconductor layer. | 2021-02-04 |
| 20210036177 | Method for Preparing Avalanche Photodiode - A method for preparing an avalanche photodiode includes preparing a mesa on a wafer, growing a sacrificial layer on an upper surface of the wafer and a side surface of the mesa, removing the sacrificial layer in an ohmic contact electrode region of the wafer, preparing an ohmic contact electrode in the ohmic contact electrode region of the wafer, removing the sacrificial layer in a non-mesa region of the wafer, growing a passivation layer on the upper surface of the wafer and the side surface of the mesa, removing the passivation layer on the upper surface of the mesa of the wafer and the passivation layer in the non-mesa region of the wafer corresponding to the ohmic contact electrode region, and removing the sacrificial layer on the upper surface of the mesa of the wafer. | 2021-02-04 |
