| 05th week of 2021 patent applcation highlights part 62 |
| Patent application number | Title | Published |
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| 20210035977 | SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING THE SAME - A semiconductor device is provided in the disclosure, including a substrate, multiple parallel fins protruding from the substrate and isolated by trenches, and a device insulating layer on the trenches between two fins, wherein the trench is provided with a central first trench and two second trenches at both sides of the first trench, and a depth of the first trench is deeper than a depth of the second trench, and the device insulating layer is provided with a top plane, a first trench and a second trench, and the fins protrude from the top plane, and the bottom surface of the second trench is lower than the bottom surface of the first trench. | 2021-02-04 |
| 20210035978 | SEMICONDUCTOR DEVICE AND METHOD FOR FABRICATING THE SAME - The present application discloses a method for fabricating a semiconductor device including providing a substrate, forming a growing base film above the substrate, forming a plurality of doped segments and a plurality of undoped segments in the growing base film, selectively forming a plurality of insulating segments on the plurality of undoped segments, removing the plurality of doped segments, and forming a plurality of capacitor structures above the substrate. | 2021-02-04 |
| 20210035979 | GATE NOBLE METAL NANOPARTICLES - An example apparatus includes a first source/drain region and a second source/drain region formed in a substrate. The first source/drain region and the second source/drain region are separated by a channel. The apparatus includes a gate opposing the channel. The gate includes noble metal nanoparticles. A sense line is coupled to the first source/drain region and a storage node is coupled to the second source/drain region. | 2021-02-04 |
| 20210035980 | MEMORY STRUCTURE - Provided is a memory structure including first and second transistors, an isolation structure, a conductive layer and a capacitor. Each of the first and second transistors includes a gate disposed on the substrate and source/drain regions disposed in the substrate. The isolation structure is disposed in the substrate between the first and second transistors. The conductive layer is disposed above the first and second transistors and includes a circuit portion electrically connected to the first and second transistors and a dummy portion located above the isolation structure. The capacitor is disposed between the first and second transistors. The capacitor includes a body portion and first and second extension portions. The first and second extension portions extend from the body portion to the source/drain regions of the first and the second transistors, respectively. The first and second extension portions are disposed between the circuit portion and the dummy portion, respectively. | 2021-02-04 |
| 20210035981 | Method and Process for Forming Memory Hole Patterns - A self-aligned multiple patterning (SAMP) process is disclosed for formation of structures on substrates. The process provides improved local critical dimension uniformity by using a first (lower) multicolor array pattern and second (upper) multicolor array pattern. The dimensions of finally formed structures are defined by the overlap of a first spacer that is formed as part of the first multicolor array pattern and a second spacer that is formed as part of the second multicolor array pattern. The spacer widths which control the critical dimension of the formed structure may be highly uniform due to the nature of spacer formation and the use of an atomic layer deposition process for forming the spacer layers of the both first (lower) multicolor array pattern and second (upper) multicolor array pattern. In one embodiment, the structure formed by a memory hole pattern for a dynamic random access memory (DRAM). | 2021-02-04 |
| 20210035982 | METHOD OF PROCESSING DRAM - Methods of forming a DRAM bit line to improve line edge roughness (LER) and lower resistance are described. The method comprises implanting an inert species into a bit line metal layer having a first grain size on a substrate to form an amorphized bit line metal layer having a second grain size smaller than the first grain size. A film stack is then deposited on the amorphized bit line metal layer. The film stack and amorphized bit line metal layer are etched to form a patterned film stack on the substrate. The patterned film stack on the substrate is thermally annealed. | 2021-02-04 |
| 20210035983 | SEMICONDUCTOR MEMORY DEVICE AND METHOD OF MANUFACTURING THE SAME - A method of manufacturing a semiconductor memory device includes forming bit line structures extending in a first horizontal direction on a substrate, and insulating spacer structures covering opposite sidewalls of each bit line structure, forming a preliminary buried contact material layer and a mold layer to respectively fill lower and upper portions of a space between a pair of insulating spacer structures, patterning the mold layer and the preliminary buried contact material layer into mold patterns spaced apart from each other in a second horizontal direction and buried contacts spaced apart from each other in the second horizontal direction, forming insulating fences among the mold patterns separated from each other and among the buried contacts separated from each other, removing the mold patterns to expose the buried contacts, and forming landing pads on the exposed buried contacts, each landing pad connected to a corresponding one of the exposed buried contacts. | 2021-02-04 |
| 20210035985 | APPARATUSES INCLUDING CONDUCTIVE STRUCTURES AND LAYOUTS THEREOF - Embodiments of the disclosure are drawn to arrangements of one or more conductive structures to provide connections to circuits or portions thereof located in different regions of a device. One or more of the conductive structures may include extensions and recesses. The extensions and recesses of different conductive structures may be complementary. That is, the extensions of one conductive structure may extend into a recess of another conductive structure. | 2021-02-04 |
| 20210035986 | Dual-Port SRAM Cell Structure - A dual-port SRAM includes a substrate, first and second active regions over the substrate and oriented lengthwise generally along a first direction; first and second gate electrodes oriented lengthwise generally along a second direction perpendicular to the first direction. The first and second gate electrodes engage the first and second active regions to form first and second pass gate transistors, respectively. The dual-port SRAM further includes a first gate contact disposed over the first gate electrode and electrically connected to the first gate electrode and a first source/drain contact oriented lengthwise generally along the second direction. The first source/drain contact directly contacts source/drain features of the first and second pass gate transistors. A portion of the first gate contact and a portion of the first source/drain contact are at a same vertical level from a top surface of the substrate and are aligned along the first direction. | 2021-02-04 |
| 20210035987 | SEMICONDUCTOR DEVICE - A semiconductor device includes a first stack group having first interlayer insulating layers and first gate layers, alternately and repeatedly stacked on a substrate and a second stack group comprising second interlayer insulating layers and second gate layers, alternately and repeatedly stacked on the first stack group. Separation structures pass through the first and second stack groups and include a first separation region and a second separation region. A vertical structure passes through the first and second stack groups and includes a first vertical region and a second vertical region. A conductive line is electrically connected to the vertical structure on the second stack group. A distance between an upper end of the first vertical region and an upper surface of the substrate is greater than a distance between an upper end of the first separation region and an upper surface of the substrate. | 2021-02-04 |
| 20210035988 | SUBSTRATE PROCESSING METHOD AND DEVICE MANUFACTURED BY THE SAME - Provided is a substrate processing method that may prevent the non-uniformity of the thickness of landing pads deposited on each step in a vertical NAND device having a stepped structure. The substrate processing method includes stacking, a plurality of times, a stack structure including an insulating layer and a sacrificial layer and etching the stack structure to form a stepped structure having an upper surface, a lower surface, and a side surface connecting the upper surface and the lower surface. The method also includes forming a barrier layer on the stepped structure, forming a mask layer on the barrier layer and exposing at least a portion of the barrier layer by etching at least a portion of the mask layer with a first etching solution The method further includes etching the exposed barrier layer with a second etching solution and etching the mask layer with a third etching solution, | 2021-02-04 |
| 20210035989 | SEMICONDUCTOR SWITCHING DEVICES HAVING FERROELECTRIC LAYERS THEREIN AND METHODS OF FABRICATING SAME - A semiconductor device includes a substrate, a channel on or in the substrate, a source/drain pair respectively on opposite ends of the channel, and a gate structure on the channel between the source/drain pair, wherein the gate structure includes an interfacial layer, a ferroelectric layer, a stabilization layer, an oxygen diffusion barrier layer, and a threshold voltage control layer that are sequentially stacked on the channel. | 2021-02-04 |
| 20210035990 | NONVOLATILE MEMORY DEVICE INCLUDING FERROELECTRIC LAYER HAVING NEGATIVE CAPACITANCE - A nonvolatile memory device according to an aspect of the present disclosure includes a substrate having a channel layer, a gate dielectric layer structure disposed on the channel layer, a ferroelectric layer disposed on the gate dielectric layer structure, and a gate electrode layer disposed on the ferroelectric layer. The gate dielectric layer structure has a positive capacitance. The ferroelectric layer has a negative capacitance. The gate dielectric layer structure includes a charge tunneling layer, a charge trap layer and a charge barrier layer disposed on the channel layer. | 2021-02-04 |
| 20210035991 | SEMICONDUCTOR DEVICE - A semiconductor device includes a substrate having a conductive region and an insulating region; gate electrodes including sub-gate electrodes spaced apart from each other and stacked in a first direction perpendicular to an upper surface of the substrate and extending in a second direction perpendicular to the first direction and gate connectors connecting the sub-gate electrodes disposed on the same level; channel structures penetrating through the gate electrodes and extending in the conductive region of the substrate; and a first dummy channel structure penetrating through the gate electrodes and extending in the insulating region of the substrate and disposed adjacent to at least one side of the gate connectors in a third direction perpendicular to the first and second directions. | 2021-02-04 |
| 20210035992 | INTEGRATION METHOD FOR MEMORY CELL - The present disclosure, in some embodiments, relates to an integrated chip. The integrated chip includes a plurality of lower interconnect layers disposed within a lower dielectric structure over a substrate. A lower insulating structure is over the lower dielectric structure and has sidewalls extending through the lower insulating structure. A bottom electrode is arranged along the sidewalls and an upper surface of the lower insulating structure. The upper surface of the lower insulating structure extends past outermost sidewalls of the bottom electrode. A data storage structure is disposed on the bottom electrode and is configured to store a data state. A top electrode is disposed on the data storage structure. The bottom electrode has interior sidewalls coupled to a horizontally extending surface to define a recess within an upper surface of the bottom electrode. The horizontally extending surface is below the upper surface of the lower insulating structure. | 2021-02-04 |
| 20210035993 | FeRAM Decoupling Capacitor - In an embodiment, a structure includes one or more first transistors in a first region of a device, the one or more first transistors supporting a memory access function of the device. The structure includes one or more ferroelectric random access memory (FeRAM) capacitors in a first inter-metal dielectric (IMD) layer over the one or more first transistors in the first region. The structure also includes one or more metal-ferroelectric insulator-metal (MFM) decoupling capacitors in the first IMD layer in a second region of the device. The MFM capacitors may include two or more capacitors coupled in series to act as a voltage divider. | 2021-02-04 |
| 20210035994 | METHODS FOR FORMING FERROELECTRIC MEMORY DEVICES - Embodiments of ferroelectric memory devices and methods for forming the ferroelectric memory devices are disclosed. In an example, a method of forming a ferroelectric memory cell is disclosed. A first electrode is formed. A doped ferroelectric layer is formed in contact with the first electrode. The doped ferroelectric layer includes oxygen and one or more ferroelectric metals. The doped ferroelectric layer further includes a plurality of dopants including at least one dopant from one of Group II elements, Group III elements, or Lanthanide elements. The plurality of dopants are different from the one or more ferroelectric metals. A second electrode is formed in contact with the doped ferroelectric layer. | 2021-02-04 |
| 20210035995 | MEMORY DEVICE INCLUDING PASS TRANSISTORS IN MEMORY TIERS - Some embodiments include apparatuses and methods of using such apparatuses. One of the apparatuses includes a semiconductor material, a pillar extending through the semiconductor material, a select gate located along a first portion of the pillar, memory cells located along a second portion of the pillar, and transistors coupled to the select gate through a portion of the semiconductor material. The transistors include sources and drains formed from portions of the semiconductor material. The transistors include gates that are electrically uncoupled to each other. | 2021-02-04 |
| 20210035996 | PROCESS FOR FABRICATING MEDIUM-VOLTAGE TRANSISTORS AND CORRESPONDING INTEGRATED CIRCUIT - A process for fabricating an integrated circuit includes the fabrication of a first transistor and a floating-gate transistor. The fabrication process for the first transistor and the floating-gate transistor utilizes a common step of forming a dielectric layer. This dielectric layer is configured to form a tunnel-dielectric layer of the floating-gate transistor (which allows transfer of charge via the Fowler-Nordheim effect) and to form a gate-dielectric layer of the first transistor. | 2021-02-04 |
| 20210035997 | ISOLATION STRUCTURES FOR INTEGRATED CIRCUIT DEVICES - Integrated circuits, and integrated circuit devices, might include is semiconductor, a first active area in the semiconductor, a second active area in the semiconductor, and an isolation structure in the semiconductor between the first active area and the second active area. The isolation structure might include a first edge portion extending below a surface of the semiconductor to a first depth, a second edge portion extending below the surface of the semiconductor to the first depth, and an interior portion between the first edge portion and the second edge portion, and extending below the surface of the semiconductor to a second depth, less than the first depth. | 2021-02-04 |
| 20210035998 | THREE-DIMENSIONAL MEMORY DEVICE HAVING ENHANCED CONTACT BETWEEN POLYCRYSTALLINE CHANNEL AND EPITAXIAL PEDESTAL STRUCTURE AND METHOD OF MAKING THE SAME - An alternating stack of insulating layers and sacrificial material layers is formed over a substrate. A memory opening is formed through the alternating stack. An amorphous semiconductor material portion is formed at a bottom region of the memory opening. A memory film is formed in the memory opening. The memory film includes an opening at a bottom portion thereof, and a surface of the amorphous semiconductor material portion is physically exposed at a bottom of the opening in the memory film. An amorphous semiconductor channel material layer is formed on the exposed surface of the amorphous semiconductor material portion and over the memory film. A vertical semiconductor channel is formed by annealing the amorphous semiconductor material portion and the amorphous semiconductor channel material layer. The vertical semiconductor channel and contacts an entire top surface of an underlying semiconductor material portion. | 2021-02-04 |
| 20210035999 | THREE-DIMENSIONAL MEMORY DEVICE HAVING ENHANCED CONTACT BETWEEN POLYCRYSTALLINE CHANNEL AND EPITAXIAL PEDESTAL STRUCTURE AND METHOD OF MAKING THE SAME - An alternating stack of insulating layers and sacrificial material layers is formed over a substrate. A memory opening is formed through the alternating stack. An amorphous semiconductor material portion is formed at a bottom region of the memory opening. A memory film is formed in the memory opening. The memory film includes an opening at a bottom portion thereof, and a surface of the amorphous semiconductor material portion is physically exposed at a bottom of the opening in the memory film. An amorphous semiconductor channel material layer is formed on the exposed surface of the amorphous semiconductor material portion and over the memory film. A vertical semiconductor channel is formed by annealing the amorphous semiconductor material portion and the amorphous semiconductor channel material layer. The vertical semiconductor channel and contacts an entire top surface of an underlying semiconductor material portion. | 2021-02-04 |
| 20210036000 | SEMICONDUCTOR MEMORY DEVICE AND METHOD OF MANUFACTURING SEMICONDUCTOR MEMORY DEVICE - A semiconductor memory device includes a first pillar. The first pillar includes a first portion and a second portion. The first portion includes a first semiconductor layer and a first insulating film on a side surface of the first semiconductor layer. The first pillar includes a first region that faces the first portion and a second region other than the first region. The second portion includes a first conductive film that is in contact with the first insulating film and a second insulating film. The second insulating film has a first thickness in a fourth direction within the second region and a second thickness in the second direction within the first region. The first thickness is greater than the second thickness. | 2021-02-04 |
| 20210036001 | VERTICAL MEMORY DEVICES - A vertical memory device includes lower circuit patterns, a second substrate, a capacitor, gate electrodes, and a channel. The lower circuit patterns are formed on a first substrate including first, second and third regions. Contact plugs are formed in the second region. Through vias are formed in the third region. The second substrate is formed on the lower circuit patterns. The capacitor is formed on the lower circuit patterns, and includes a first conductor, a dielectric layer structure, and a second conductor. The first conductor is spaced apart from the second substrate at the same height as the second substrate. The dielectric layer structure is formed on the first conductor. The second conductor is formed on the dielectric layer structure. The gate electrodes are spaced apart from each other on the second substrate in a vertical direction. The channel extends through the gate electrodes in the vertical direction. | 2021-02-04 |
| 20210036002 | SEMICONDUCTOR MEMORY DEVICE AND MANUFACTURING METHOD OF THE SEMICONDUCTOR MEMORY DEVICE - There is provided a semiconductor memory device including: a substrate having a Complementary Metal Oxide Semiconductor (CMOS) circuit; a gate stack structure including interlayer insulating layers and conductive patterns, which are alternately stacked in a vertical direction on the substrate; a channel structure having a first part penetrating the gate stack structure and a second part extending from one end of the first part, the second part extending beyond the gate stack structure; a common source line extending to overlap with the gate stack structure, the common source line surrounding the second part of the channel structure; a memory layer disposed between the first part of the channel structure and the gate stack structure; and a bit line connected to the other end of the first part of the channel structure, the bit line being disposed between the substrate and the gate stack structure. | 2021-02-04 |
| 20210036003 | THREE-DIMENSIONAL MEMORY DEVICE CONTAINING A VERTICAL SEMICONDUCTOR CHANNEL CONTAINING A CONNECTION STRAP AND METHOD OF MAKING THE SAME - An alternating stack of insulating layers and sacrificial material layers is formed over a substrate. A memory opening is formed through the alternating stack. A memory film is formed in the memory opening. The memory film includes an opening at a bottom portion. A connection strap is formed by performing a selective semiconductor deposition process that grows a strap semiconductor material from a physically exposed surface of an underlying semiconductor material portion through the opening. A vertical semiconductor channel is formed on an inner sidewall of the memory film by non-selectively depositing a semiconductor channel material. The connection strap provides an electrical connection between the underlying semiconductor material portion and the vertical semiconductor channel through the opening in the memory film. The sacrificial material layers are then replaced with electrically conductive layers. | 2021-02-04 |
| 20210036004 | THREE-DIMENSIONAL MEMORY DEVICE CONTAINING A SILICON NITRIDE RING IN AN OPENING IN A MEMORY FILM AND METHOD OF MAKING THE SAME - An alternating stack of insulating layers and sacrificial material layers is formed over a substrate. A memory opening is formed through the alternating stack. A memory film including a silicon nitride layer and a tunneling dielectric layer is formed in the memory opening, and an opening is formed through the memory film. A chemical oxide layer is formed on a physically exposed surface of an underlying semiconductor material portion. A silicon nitride ring can be formed by selectively growing a silicon nitride material from an annular silicon nitride layer portion of the silicon nitride layer while suppressing deposition of the silicon nitride material on the tunneling dielectric layer and on the chemical oxide layer. A vertical semiconductor channel can be formed by depositing a continuous semiconductor material layer on the underlying semiconductor material portion and the tunneling dielectric layer and on the silicon nitride ring. | 2021-02-04 |
| 20210036005 | SEMICONDUCTOR MEMORY DEVICE - A semiconductor memory device includes an electrode structure including a plurality of electrode layers and a plurality of interlayer dielectric layers which are alternately stacked on a source plate defined with a cell area and a connection area in a first direction; a vertical channel passing through the electrode structure in the cell area; a hard mask pattern disposed on the electrode structure in the connection area, and having a plurality of opening holes; a plurality of contact holes defined in the electrode structure under the opening holes, and exposing pad areas of the electrode layers; and a slit dividing the hard mask pattern into units smaller than the electrode structure in the connection area. | 2021-02-04 |
| 20210036006 | THREE-DIMENSIONAL MEMORY DEVICES AND FABRICATING METHODS THEREOF - A method for forming a gate structure of a 3D memory device is provided. The method comprises forming an array wafer including a periphery region and a staircase and array region. A process of forming an array wafer comprises forming an alternating dielectric etch stop structure on a first substrate in the periphery region, forming an array device on the first substrate in the staircase and array region, and forming at least one first vertical through contact in the periphery region and in contact with the alternating dielectric etch stop structure. The method further comprises forming a CMOS wafer and bonding the array wafer and the CMOS wafer. The method further comprises forming at least one through substrate contact penetrating the first substrate and the alternating dielectric etch stop structure, and in contact with the at least one first vertical through contact. | 2021-02-04 |
| 20210036007 | SEMICONDUCTOR MEMORY DEVICE HAVING THREE-DIMENSIONAL STRUCTURE AND METHOD FOR MANUFACTURING THE SAME - A semiconductor memory device includes an electrode structure including a plurality of electrode layers and a plurality of interlayer dielectric layers which are alternately stacked on a substrate defined with a plurality of cell areas and a plurality of coupling areas in a first direction; a hard mask pattern disposed on the electrode structure, and having a plurality of opening holes in the coupling areas; and a plurality of contact holes defined in the electrode structure under the plurality of opening holes, and exposing pad areas of the electrode layers, respectively. The plurality of opening holes are disposed by being distributed in a plurality of rows arranged in a second direction intersecting with the first direction. | 2021-02-04 |
| 20210036008 | VERTICAL MEMORY DEVICES - A vertical memory device is provided. The vertical memory device includes gate electrodes formed on a substrate and spaced apart from each other in a first direction substantially perpendicular to an upper surface of the substrate, the gate electrodes including a first gate electrode and a second gate electrode that is interposed between the first gate electrode and the substrate; a channel extending through the gate electrodes in the first direction; an insulating isolation pattern extending through the first gate electrode in the first direction, and spaced apart from the first gate electrode in a second direction substantially parallel to the upper surface of the substrate; and a blocking pattern disposed on an upper surface, a lower surface and a sidewall of each of the gate electrodes, the sidewall of the gate electrodes facing the channel. The insulating isolation pattern directly contacts the first gate electrode. | 2021-02-04 |
| 20210036009 | NONVOLATILE MEMORY DEVICE AND METHOD FOR FABRICATING THE SAME - A nonvolatile memory device with improved operation performance and reliability, and a method for fabricating the same are provided. The nonvolatile memory device includes a substrate, a peripheral circuit structure on the substrate, a mold structure including a plurality of insulating patterns and a plurality of gate electrodes stacked alternately on the peripheral circuit structure, a channel structure penetrating the mold structure, a first impurity pattern in contact with first portions of the channel structure and having a first conductivity type, on the mold structure, and a second impurity pattern in contact with second portions of the channel structure and having a second conductivity type different from the first conductivity type, on the mold structure. | 2021-02-04 |
| 20210036010 | THREE-DIMENSIONAL SEMICONDUCTOR MEMORY DEVICE - A semiconductor memory device includes horizontal patterns disposed on a peripheral circuit structure and spaced apart from each other in a first direction. Memory structures are disposed on the horizontal patterns. The memory structures include source structures and electrode structures. A division structure is disposed between adjacent horizontal patterns in the first direction and is configured to separate the source structures of adjacent memory structures from each other. An etch stop pattern is disposed between the horizontal patterns at a level lower than a level of the source structures. The etch stop pattern is connected to a lower portion of the division structure. | 2021-02-04 |
| 20210036011 | SEMICONDUCTOR DEVICES AND METHODS OF OPERATING THE SAME - A semiconductor device is disclosed. The semiconductor device includes a channel structure on a substrate and extending in a first direction perpendicular to a top surface of the substrate; a plurality of gate electrodes on the substrate and spaced apart from one another in the first direction on a sidewall of the channel structure; and a gate insulating layer between each of the plurality of gate electrodes and the channel structure, wherein the channel structure includes a body gate layer extending in the first direction; a charge storage structure surrounding a sidewall of the body gate layer; and a channel layer surrounding sidewall of the charge storage structure. | 2021-02-04 |
| 20210036012 | VERTICAL MEMORY DEVICES AND METHODS OF MANUFACTURING THE SAME - A vertical memory device includes a channel extending in a vertical direction on a substrate, a charge storage structure on an outer sidewall of the channel and including a tunnel insulation pattern, a charge trapping pattern, and a first blocking pattern sequentially stacked in a horizontal direction, and gate electrodes spaced apart from each other in the vertical direction, each of which surrounds the charge storage structure. The charge storage structure includes charge trapping patterns, each of which faces one of the gate electrodes in the horizontal direction. A length in the vertical direction of an inner sidewall of each of the charge trapping patterns facing the tunnel insulation pattern is less than a length in the vertical direction of an outer sidewall thereof facing the first blocking pattern. | 2021-02-04 |
| 20210036013 | SEMICONDUCTOR MEMORY DEVICE - A semiconductor memory device includes a peripheral logic structure including peripheral circuits on a substrate, a horizontal semiconductor layer extending along a top surface of the peripheral logic structure, a plurality of stack structures arranged on the horizontal semiconductor layer along a first direction, and a plurality of electrode separation regions in each of the plurality of stack structures to extend in a second direction, which is different from the first direction, wherein each of the plurality of stack structures includes a first electrode pad and a second electrode pad on the first electrode pad, the first electrode pad protruding in the first direction beyond the second electrode pad by a first width, and the first electrode pad protrudes in the second direction beyond the second electrode pad by a second width, which is different from the first width. | 2021-02-04 |
| 20210036014 | THREE-DIMENSIONAL SEMICONDUCTOR DEVICE - A three-dimensional semiconductor device includes: a peripheral circuit structure disposed on a lower substrate, and including an internal peripheral pad portion; an upper substrate disposed on the peripheral circuit structure; a stack structure disposed on the upper substrate, and including gate horizontal patterns; a vertical channel structure passing through the stack structure in a first region on the upper substrate; a first vertical support structure passing through the stack structure in a second region on the upper substrate; and an internal peripheral contact structure passing through the stack structure and the upper substrate, and electrically connected to the internal peripheral pad portion, wherein an upper surface of the first vertical support structure is disposed on a different level from an upper surface of the vertical channel structure, and is coplanar with an upper surface of the internal peripheral contact structure. | 2021-02-04 |
| 20210036015 | NONVOLATILE MEMORY DEVICE HAVING A VERTICAL STRUCTURE AND A MEMORY SYSTEM INCLUDING THE SAME - A nonvolatile memory device including: a first semiconductor layer comprising a plurality of first word lines extending in a first direction, a first upper substrate and a first memory cell array, a second semiconductor layer including a plurality of second word lines extending in the first direction, second and third upper substrates adjacent to each other in the first direction and a second memory cell army, wherein the second memory cell array includes a first vertical structure on the first upper substrate and a second vertical structure on the second upper substrate, wherein the first semiconductor layer and the second semiconductor layer share a plurality of bit lines extending in a second direction, and a third semiconductor layer under the second semiconductor layer in a third direction perpendicular to the first and second directions, wherein the third semiconductor layer includes a lower substrate that includes a plurality of row decoder circuits and a plurality of page buffer circuits, wherein the first vertical structure includes a first via area in which a first through-hole via is provided, wherein the first through-hole via passes through the first vertical structure and connects a first bit line and a first page buffer circuit, and the second vertical structure includes a first partial block, wherein the first partial block overlaps the first via area in the first direction. | 2021-02-04 |
| 20210036016 | MANUFACTURING METHOD OF A SEMICONDUCTOR DEVICE - A method of manufacturing a semiconductor device includes forming a first etch stop pattern on a lower structure including a first region and a second region to expose the second region, stacking a plurality of stack structures on the lower structure to overlap the second region and the first etch stop pattern, forming a stepped stack structure by etching the plurality of stack structures to expose an end portion of the first etch stop pattern, forming a slit passing through the stepped stack structure and the first etch stop pattern, and replacing sacrificial layers of the plurality of stack structures and the first etch stop pattern with conductive patterns through the slit. | 2021-02-04 |
| 20210036017 | NON-VOLATILE FERROELECTRIC MEMORY AND METHOD OF PREPARING THE SAME - The present disclosure relates to a non-volatile ferroelectric memory and a method of preparing the same. The ferroelectric memory includes a ferroelectric storage layer, a first electrode and a second electrode; the first electrode and the second electrode each include a buried conductive layer formed by patterning in a surface of the ferroelectric storage layer and an electrode layer formed on the buried conductive layer; and when a write signal in a certain direction is applied between the first electrode and the second electrode, the electric domains of a part of the ferroelectric storage layer between a pair of the buried conductive layers are enabled to be reversed, so that a domain wall conductive passage that electrically connects the first electrode and the second electrode can be established. | 2021-02-04 |
| 20210036018 | THREE-DIMENSIONAL MEMORY DEVICE CONTAINING EPITAXIAL FERROELECTRIC MEMORY ELEMENTS AND METHODS FOR FORMING THE SAME - A three-dimensional memory device includes an alternating stack of insulating layers and electrically conductive layers located over a substrate, and memory stack structures extending through the alternating stack. Each of the memory stack structures includes a vertical stack of single crystalline ferroelectric dielectric layers and a respective vertical semiconductor channel. | 2021-02-04 |
| 20210036019 | THREE-DIMENSIONAL MEMORY DEVICE CONTAINING EPITAXIAL FERROELECTRIC MEMORY ELEMENTS AND METHODS FOR FORMING THE SAME - A three-dimensional memory device includes an alternating stack of insulating layers and electrically conductive layers located over a substrate, and a memory stack structure extending through the alternating stack. The memory stack structure includes a vertical semiconductor channel, a vertical stack of majority germanium layers each containing at least 51 atomic percent germanium, and a vertical stack of ferroelectric dielectric layers. | 2021-02-04 |
| 20210036020 | SEMICONDUCTOR DEVICE - A semiconductor device is provided. The semiconductor device includes a first stacked structure including a plurality of first insulating patterns and a plurality of first semiconductor patterns alternately stacked on a substrate, the first stacked structure extending in a first direction parallel to an upper surface of the substrate, a first conductive pattern on one side surface of the first stacked structure, the first conductive pattern extending in a second direction crossing the upper surface of the substrate, and a first ferroelectric layer between the first stacked structure and the first conductive pattern, the first ferroelectric layer extending in the second direction, wherein each of the first semiconductor patterns includes a first impurity region, a first channel region and a second impurity region which are sequentially arranged along the first direction. | 2021-02-04 |
| 20210036021 | DISPLAY DEVICE - A display device is provided. A display device includes a substrate; a gate electrode disposed on the substrate; a semiconductor pattern disposed to overlap the gate electrode; a source electrode disposed on the semiconductor pattern; a drain electrode disposed on the semiconductor pattern and facing the source electrode; and a pixel electrode connected to the drain electrode, wherein the drain electrode comprises a bar-shaped portion disposed on the semiconductor pattern and extending in one direction, a compensation portion connected to one distal end portion of the bar-shaped portion, a connecting portion connected to the other distal end portion of the bar-shaped portion, and an pad portion connected to the connecting portion and overlapping the pixel electrode, wherein the bar-shaped portion has a first width and at least portions of the compensation portion and the connecting portion have a second width that is greater than the first width. | 2021-02-04 |
| 20210036022 | Display Device with Through Hole - Disclosed is a display device including a panel including an active area in which a plurality of subpixels is disposed, a through hole formed through the active area of the panel, a hole bezel zone disposed between the through hole and the active area so as to surround the through hole, and a plurality of data lines extending from a first active area of the active area to a second active area of the active area via the hole bezel zone, the plurality of data lines having a smaller wire pitch in the hole bezel zone than in the first active area and the second active area, wherein a first arrangement sequence of the plurality of data lines disposed in the first active area and a second arrangement sequence of the plurality of data lines disposed in the hole bezel zone are different from each other. | 2021-02-04 |
| 20210036023 | THIN FILM TRANSISTOR STRUCTURES WITH REGROWN SOURCE & DRAIN - Thin film transistor structures may include a regrown source or drain material between a channel material and source or drain contact metallization. The source or drain material may be selectively deposited at low temperatures to backfill recesses formed in the channel material. Electrically active dopant impurities may be introduced in-situ during deposition of the source or drain material. The source or drain material may overlap a portion of a gate electrode undercut by the recesses. With channel material of a first composition and source or drain material of a second composition, thin film transistor structures may display low external resistance and high channel mobility. | 2021-02-04 |
| 20210036024 | SEMICONDUCTOR DEVICE INCLUDING FERROELECTRIC MATERIAL, NEUROMORPHIC CIRCUIT INCLUDING THE SEMICONDUCTOR DEVICE, AND NEUROMORPHIC COMPUTING APPARATUS INCLUDING THE NEUROMORPHIC CIRCUIT - A semiconductor device includes a first transistor including a first channel layer of a first conductivity type, a second transistor provided in parallel with the first transistor and including a second channel layer of a second conductivity type, and a third transistor stacked on the first and second transistors. The third transistor may include a gate insulating film including a ferroelectric material. The third transistor may include third channel layer and a gate electrode that are spaced apart from each other in a thickness direction with the gate insulating film therebetween. | 2021-02-04 |
| 20210036025 | SEMICONDUCTOR MATERIAL AND SEMICONDUCTOR DEVICE - A semiconductor device in which an electrification phenomenon that leads to characteristic fluctuations, element deterioration, or dielectric breakdown is inhibited is provided. A first transistor, a second transistor, a third transistor, and a fourth transistor are included over a substrate; the fourth transistor includes a first conductor, a second conductor, a third conductor, and an oxide semiconductor; the first conductor is electrically connected to the semiconductor substrate through the first transistor; the second conductor is electrically connected to the semiconductor substrate through the first transistor; the third conductor is electrically connected to the semiconductor substrate through the first transistor; and the fourth conductor is electrically connected to the semiconductor substrate through the first transistor. | 2021-02-04 |
| 20210036026 | HIGH VOLTAGE THREE-DIMENSIONAL DEVICES HAVING DIELECTRIC LINERS - High voltage three-dimensional devices having dielectric liners and methods of forming high voltage three-dimensional devices having dielectric liners are described. For example, a semiconductor structure includes a first fin active region and a second fin active region disposed above a substrate. A first gate structure is disposed above a top surface of, and along sidewalls of, the first fin active region. The first gate structure includes a first gate dielectric, a first gate electrode, and first spacers. The first gate dielectric is composed of a first dielectric layer disposed on the first fin active region and along sidewalls of the first spacers, and a second, different, dielectric layer disposed on the first dielectric layer and along sidewalls of the first spacers. The semiconductor structure also includes a second gate structure disposed above a top surface of, and along sidewalls of, the second fin active region. The second gate structure includes a second gate dielectric, a second gate electrode, and second spacers. The second gate dielectric is composed of the second dielectric layer disposed on the second fin active region and along sidewalls of the second spacers. | 2021-02-04 |
| 20210036027 | THIN FILM TRANSISTOR, DISPLAY DEVICE, ELECTRONIC APPARATUS AND METHOD OF MANUFACTURING THIN FILM TRANSISTOR - Provided is a thin film transistor, including: a base that includes, on an upper surface, a first region and a second region; a gate electrode that is provided on the first region of the base; a gate insulating film that is provided on a surface of the gate electrode and the second region of the base; and a semiconductor layer that is provided on a surface of the gate insulating film, wherein the semiconductor layer includes a third region and a fourth region, in the third region, the semiconductor layer and the gate electrode face with a minimum interval, in the fourth region, a distance from the semiconductor layer to the gate electrode is larger than the minimum interval, and at a boundary position between the third region and the fourth region, the semiconductor layer forms a linear shape or a substantially linear shape. | 2021-02-04 |
| 20210036028 | DISPLAY DEVICE - A display device includes a pixel connected to a scan line, and a data line crossing the scan line, wherein the pixel includes a light-emitting element, a driving transistor configured to control a driving current supplied to the light-emitting element according to a data voltage applied from the data line, and a first switching transistor configured to apply the data voltage of the data line to the driving transistor according to a scan signal that is applied to the scan line. The driving transistor includes a first active layer including an oxide semiconductor, and a first oxide layer disposed on the first active layer and including an oxide semiconductor. The first switching transistor includes a second active layer including an oxide semiconductor, and the first oxide layer is not disposed on the second active layer. | 2021-02-04 |
| 20210036029 | DISPLAY DEVICE - A display device includes a substrate, a buffer layer disposed on the substrate, a first semiconductor layer disposed on the buffer layer and including an oxide semiconductor and a first active layer, a first gate insulating layer disposed on the first semiconductor layer and the buffer layer, a second semiconductor layer disposed on the first gate insulating layer and including an oxide semiconductor, a second active layer, and a first oxide layer on the first active layer, a second gate insulating layer disposed on the second semiconductor layer, a first conductive layer disposed on the second gate insulating layer, an insulating layer disposed on the first conductive layer, a second conductive layer disposed on the insulating layer, a passivation layer disposed on the second conductive layer, and a third conductive layer disposed on the first passivation layer. | 2021-02-04 |
| 20210036030 | ARRAY SUBSTRATE FABRICATION METHOD, ARRAY SUBSTRATE, AND DISPLAY PANEL - Disclosed is an array substrate. The array substrate includes a display area and a terminal area defined at an edge of the display area; a plurality of thin film transistors are arranged in the display area, and a plurality of driving terminals are arranged at intervals in the terminal area; the driving terminals are electrically connected to the thin film transistors; an insulated film is arranged above an interval area of the driving terminals, to shield the interval area. | 2021-02-04 |
| 20210036031 | DISPLAY DEVICE - The purpose of the present invention is to prevent an overhang in a through hole in the display area when through holes in the organic passivation film in the display area and in the terminal area are simultaneously formed. The structure to realize this purpose is as follows: the terminal area having a lead wire, formed from a first metal, and extending to the display area, a first insulating film covering the lead wire, a second metal formed on the first insulating film, and a third metal formed on the surface of the second metal, wherein the first insulating film has a first through hole and a second through hole, the second metal has a first portion that connects with the lead wire via the first through hole, the second metal has a second portion that overlaps the second through hole, the second portion is separated from the first portion. | 2021-02-04 |
| 20210036032 | DISPLAY DEVICE - A display device includes pixel circuits disposed in a display area and a driving circuit disposed in the peripheral area. The driving circuit includes a first transistor and each pixel circuit includes a second transistor. The first transistor includes a first active pattern disposed on the substrate, a first gate insulation layer having a first outer portion disposed on the first active pattern, and a first gate electrode disposed on the first gate insulation layer. The second transistor includes a second active pattern disposed on the substrate, a second gate insulation layer having a second outer portion disposed on the second active pattern, and a second gate electrode disposed on the second gate insulation layer. The first outer portion doesn't overlap the first gate electrode and has a first width. The second outer portion doesn't overlap the second gate electrode and has a second width smaller than the first width. | 2021-02-04 |
| 20210036033 | ELECTRONIC MODULATING DEVICE - An electronic modulating device is provided. The electronic modulating device includes a first modulating unit. The first modulating unit includes a first transistor including a channel arranged in an extending direction. The first modulating unit also includes a first modulating electrode electrically connected to the first transistor and arranged in a first longitudinal direction. The electronic modulating device also includes a second modulating unit. The second modulating unit includes a second transistor including a channel arranged in the extending direction. The second modulating unit also includes a second modulating electrode electrically connected to the second transistor and arranged in a second longitudinal direction that is different from the first longitudinal direction. The first included angle between the extending direction and the first longitudinal direction is different from a second included angle between the extending direction and the second longitudinal direction. | 2021-02-04 |
| 20210036034 | INTEGRATED CIRCUIT ON FLEXIBLE SUBSTRATE MANUFACTURING PROCESS - The present invention provides processes for manufacturing a plurality of discrete integrated circuits (ICs) on a carrier, the process comprising the steps of: providing a carrier for a flexible substrate; depositing a flexible substrate of uniform thickness on said carrier; removing at least a portion of the thickness of the flexible substrate from at least a portion of the IC connecting areas to form channels in the flexible substrate and a plurality of IC substrate units spaced apart from one another on the carrier by said channels; forming an integrated circuit on at least one of the IC substrate units. | 2021-02-04 |
| 20210036035 | IMAGE SENSOR PANEL AND METHOD FOR FABRICATING THE SAME - The present disclosure provides an image sensor panel (ISP) and a method for fabricating the image sensor panel (ISP). In one aspect, the method includes forming a well in an assembly, forming a bottom electrode in the well, forming a photosensitive layer in the well, and forming a top electrode over the photosensitive layer. | 2021-02-04 |
| 20210036036 | IMAGING DEVICE AND IMAGING SYSTEM - An imaging device comprises pixels. The pixel includes first semiconductor regions of a first conductivity type provided in a surface part of a semiconductor substrate and a second semiconductor region of a second conductivity type provided in the surface part of the semiconductor substrate between the first semiconductor regions. The pixel includes: a light-receiving unit in which photodiodes each configured between the second semiconductor region and one of the first semiconductor regions; quenching circuits, each connected to a corresponding one of the first semiconductor regions; and a counter unit connected to each of connection nodes between the first semiconductor regions and the quenching circuits and counts a pulse generated in response to a photon being incident on the light-receiving unit. The second semiconductor region is provided across a deeper part of the semiconductor substrate than the first semiconductor regions. | 2021-02-04 |
| 20210036037 | PHOTOELECTRIC CONVERSION DEVICE, IMAGE READING DEVICE AND IMAGE FORMING APPARATUS - A photoelectric conversion device includes: a photoelectric conversion block including two-dimensionally arranged photoelectric converters, each photoelectric converter including a color filter and a photoelectric conversion element configured to perform photoelectric conversion in response to incident light; a signal processing block configured to process data output from the photoelectric conversion block; and a plurality of electrode pads disposed in the signal processing block. The electrode pads are configured to supply power to the photoelectric conversion block and the signal processing block. | 2021-02-04 |
| 20210036038 | PIXEL ARRAY FOR A CAMERA, CAMERA AND LIGHT PROPAGATION TIME CAMERA SYSTEM HAVING A CAMERA OF THIS KIND - The disclosure relates to a pixel array for a camera, in particular for a light propagation time camera, having: a plurality of pixel elements arranged in a matrix arrangement, wherein each individual pixel element has a photoelectric region and at least one other region which is non-sensitive to light; and a plurality of routing paths which are arranged in a grid-like manner and which divide the pixel array into fields. A group of first fields and a group of second fields are created, in which each of the first fields is provided by a photoelectric region of one of the pixel elements and each of the second fields is provided by the other regions, wherein the first fields and the second fields are arranged in an alternating manner similar to a chessboard. The disclosure further relates to a corresponding camera, in particular a light propagation time camera for a light propagation time camera system, and to a corresponding light propagation time camera system. | 2021-02-04 |
| 20210036039 | IMAGE SENSING DEVICE - An image sensing device includes a photoelectric conversion element, a floating diffusion (FD) region, and a transfer gate. The photoelectric conversion element is disposed in a substrate, and generates photocharges in response to incident light. The floating diffusion (FD) region is disposed over the photoelectric conversion element, and stores the photocharges generated by the photoelectric conversion element. The transfer gate transfer the photocharges generated by the photoelectric conversion element to the floating diffusion (FD) region in response to a transmission signal. The transfer gate includes a horizontal gate disposed over the photoelectric conversion element, and a vertical gate coupled to the horizontal gate. The vertical gate is positioned at a side of the photoelectric conversion element, and surrounds the photoelectric conversion element. | 2021-02-04 |
| 20210036040 | SOLID-STATE IMAGING APPARATUS AND METHOD FOR MANUFACTURING THE SOLID-STATE IMAGING APPARATUS HAVING SEALING PORTION DISPOSED IN BONDED MEMBERS - A solid-state imaging apparatus includes a first substrate that includes a plurality of photoelectric conversion units, a second substrate that includes at least a part of a readout circuit configured to read signals based on electric charges of the plurality of photoelectric conversion units and a peripheral circuit including a control circuit, and a wiring structure that is disposed between the first substrate and the second substrate and includes a pad portion electrically connected to the peripheral circuit via a draw-out wiring and an insulating layer. The wiring structure has, at least at a part thereof, a seal ring disposed in such a way as to surround the photoelectric conversion units and the peripheral circuit. | 2021-02-04 |
| 20210036041 | CIRCUIT BOARD, SEMICONDUCTOR DEVICE, AND ELECTRONIC APPARATUS - The present technology relates to a circuit board, a semiconductor device, and an electronic apparatus that reduce the generation of noise signals. A circuit board includes: a first conductor layer that has a first conductor portion including a conductor having a planar or mesh-like first basic pattern repeatedly disposed in the same plane; and a second conductor layer that has a second conductor portion including a conductor having a planar or mesh-like second basic pattern repeatedly disposed in the same plane, and a third conductor portion including a conductor having a planar, linear, or mesh-shaped third basic pattern repeatedly disposed in the same plane. The repeating cycles of the first and second basic patterns are substantially the same cycles, and the third basic pattern is different than the second basic pattern. The present technology can be applied to a circuit board of a semiconductor device and the like, for example. | 2021-02-04 |
| 20210036042 | IMAGE SENSOR, MANUFACTURING METHOD AND HAND-HELD DEVICE OF THE SAME - The present disclosure discloses an image sensor, method of manufacturing the same, a chip and a hand-held device adopting the chip. The image sensor includes a semiconductor substrate and a plurality of pixels, wherein each pixel of the plurality of pixels includes: a photosensitive sensor, disposed on the semiconductor substrate; a polarizing layer, disposed over the semiconductor substrate; and a microlens, disposed over the polarizing layer, so that the polarizing layer is disposed between the microlens and the semiconductor substrate The present disclosure further discloses a chip, a hand-held device, and a method of manufacturing the image sensor. | 2021-02-04 |
| 20210036043 | CONCAVE REFLECTOR FOR COMPLEMENTARY METAL OXIDE SEMICONDUCTOR IMAGE SENSOR (CIS) - In some embodiments, the present disclosure relates to an integrated chip having an inter-layer dielectric (ILD) structure along a first surface of a substrate having a photodetector. An etch stop layer is over the ILD structure, and a reflector is surrounded by the etch stop layer and the ILD structure. The reflector has a curved surface facing the substrate at a location directly over the photodetector. The curved surface is coupled between a first sidewall and a second sidewall of the reflector. The reflector has larger thicknesses along the first sidewall and the second sidewall than at a center of the reflector between the first sidewall and the second sidewall. | 2021-02-04 |
| 20210036044 | IMAGE CAPTURING UNIT AND METHOD FOR MANUFACTURING THE SAME - An image capturing unit includes a plurality of input wiring lines for controlling the semiconductor chip, a plurality of first electrodes connecting to the input wiring lines, and an input connector connecting to the input wiring lines. The substrate includes a first area for mounting an electronic component in an opposite surface on which the semiconductor chip is mounted and a second area for use in mounting the semiconductor chip. The connector is disposed in the first area. At least one or more of the first electrodes are disposed in the second area. | 2021-02-04 |
| 20210036045 | SEMICONDUCTOR STRUCTURE AND THE MANUFACTURING METHOD THEREOF - The present invention provides a semiconductor structure for forming a CMOS image sensor. The semiconductor structure includes at least a photodiode formed in the substrate for collecting photoelectrons, and the photodiode has a pinning layer, a first doped region and a second doped region in order from top to bottom in a height direction of the substrate. The semiconductor structure further includes a third doped region located in the substrate corresponding to a laterally extending region of the second doped region. The first doped region has an ion doping concentration greater than the ion doping concentration of the second doped region, the ion doping concentration of the second doped region is greater than the ion doping concentration of the third doped region, and the third doped region is in contact with the second doped region after diffusion. The present invention also provides a method of manufacturing the above-described semiconductor structure. | 2021-02-04 |
| 20210036046 | DISPLAY, ELECTRONIC DEVICE HAVING THE DISPLAY, AND METHOD OF ESTIMATING BIO-INFORMATION USING THE ELECTRONIC DEVICE - A display includes a display portion formed of an array of unit pixels that each respectively include a light source pixel and a detector pixel. The display includes a control driver including a light source driver and a data driver which are respectively connected to each light source pixel, and a detector driver which is connected to each detector pixel. The display includes a controller configured to control the control driver to operate the display portion in a first mode, a second mode, and a third mode that are each different from each other. | 2021-02-04 |
| 20210036047 | DISPLAY HAVING INFRARED ELEMENT ARRANGED SUCH THAT AT LEAST ONE PORTION THEREOF OVERLAPS PIXEL, AND ELECTRONIC DEVICE INCLUDING SAME - Various embodiments of the present document relate to a display and, particularly, relate to a display including infrared elements, and an electronic device including the same. The display according to various embodiments of the present document includes a substrate; a first element for outputting light of a first visible light band and a second element for outputting light of an infrared band, the elements being formed on the substrate; and a third element for outputting light of a second visible light band, wherein at least a portion of the third element is arranged to overlaps the second element. | 2021-02-04 |
| 20210036048 | IMAGE SENSOR AND METHOD FOR MANUFACTURING DEEP TRENCH AND THROUGH-SILICON VIA OF THE IMAGE SENSOR - The present disclosure provides an image sensor and a method for manufacturing deep trench and through-silicon via of the image sensor, wherein: providing a pixel silicon wafer, performing a silicon wafer thinning on a second side of the pixel silicon wafer; forming a deep trench on the the second side of the pixel silicon wafer; filling the deep trench with organic material; coating photoresist on the second side of the pixel silicon wafer; etching the second side of the pixel silicon wafer to form a through-silicon via according to the through-silicon via pattern; depositing a dielectric protective layer on the surface of the deep trench and the surface of the through-silicon via; filling the deep trench with organic material; coating the photoresist on the second side of the pixel silicon wafer; etching the second side of the pixel silicon wafer to form a contact hole according to the contact hole pattern, depositing a barrier layer on the surface of the deep trench and the surface of the through-silicon via, filling the deep trench with a first metal, and form a seed layer on the surface of the through-silicon via; filling the through-silicon via with the first metal. The present disclosure reduces production steps of the image sensor. | 2021-02-04 |
| 20210036049 | LIGHT EMITTING DEVICE AND MANUFACTURING METHOD THEREOF - A light-emitting diode, includes a substrate; a semiconductor stack formed on the substrate; a first current blocking patterned structure and a second current blocking patterned structure formed on the semiconductor stack and separated from each other; and a plurality of electrodes formed on the semiconductor stack and electrically connected to the semiconductor stack; wherein the first current blocking patterned structure is overlapped with one of the plurality of electrodes and the second current blocking patterned structure is not overlapped with the plurality of electrodes. | 2021-02-04 |
| 20210036050 | LIGHT EMISSION DEVICE - A light emission device includes: a wiring board; a plurality of light-emitting elements being disposed on the wiring board and electrically connected to a wiring layer of the wiring board; a first light diffusing member being disposed on the wiring board, the first light diffusing member having a plurality of throughholes and containing a light-diffusive material, each of the plurality of light-emitting elements being disposed in a corresponding one of the plurality of throughholes; a plurality of second light diffusing members covering the plurality of light-emitting elements and being disposed in the plurality of throughholes, each second light diffusing member containing a light-diffusive material, such that a content ratio of the light-diffusive material in each second light diffusing member is higher than a content ratio of the light-diffusive material in the first light diffusing member; and a wavelength converting member. | 2021-02-04 |
| 20210036051 | CHIP-SCALE LINEAR LIGHT-EMITTING DEVICE - A chip-scale linear light-emitting device includes a submount substrate, light-emitting diode (LED) semiconductor chips, a chip-scale packaging structure and a reflective structure. The LED semiconductor chips, the packaging structure and the reflective structure are disposed on the submount substrate, wherein the packaging structure partially covers the chip-upper surface and/or the chip-edge surfaces of the LED semiconductor chips, and the reflective structure partially covers the package-top surface and/or the package-side surfaces of the packaging structure. If one of the chip-edge surfaces and the package-side surface of the packaging structure are exposed from the reflective structure as a primary light-emitting side surface, a side-view type linear light-emitting device is formed. If the package-top surface of the packaging structure is exposed from the reflective structure as a primary light-emitting top surface, a top-view type linear light-emitting device is formed. A substantially transparent light-transmitting material and/or a photoluminescent material can be configured to be included inside the packaging structure. In this configuration, a primary light emitted from the LED semiconductor chips is directed to pass through the packaging structure and radiated outward from the primary light-emitting surface. Therefore, a monochromatic light or a white light with a uniformly distributed linear radiation pattern can be generated using the chip-scale linear light-emitting device. | 2021-02-04 |
| 20210036052 | SOLID STATE TRANSDUCER DEVICES WITH SEPARATELY CONTROLLED REGIONS, AND ASSOCIATED SYSTEMS AND METHODS - Solid state transducer devices with independently controlled regions, and associated systems and methods are disclosed. A solid state transducer device in accordance with a particular embodiment includes a transducer structure having a first semiconductor material, a second semiconductor material and an active region between the first and second semiconductor materials, the active region including a continuous portion having a first region and a second region. A first contact is electrically connected to the first semiconductor material to direct a first electrical input to the first region along a first path, and a second contact electrically spaced apart from the first contact and connected to the first semiconductor material to direct a second electrical input to the second region along a second path different than the first path. A third electrical contact is electrically connected to the second semiconductor material. | 2021-02-04 |
| 20210036053 | SEMICONDUCTOR MEMORY DEVICE - The disclosure provides a semiconductor memory device including a substrate having a memory cell region and an alignment mark region; a dielectric layer covering the memory cell region and the alignment mark region; conductive vias in the dielectric layer within the memory cell region; an alignment mark trench in the dielectric layer within the alignment mark region; and storage structures disposed on the conductive vias, respectively. Each of the storage structures includes a bottom electrode defined from a bottom electrode metal layer, a magnetic tunnel junction (MTJ) structure defined from an MTJ layer, and a top electrode. A residual metal stack is left in the alignment mark trench. The residual metal stack includes a portion of the bottom electrode metal layer and a portion of the MTJ layer. | 2021-02-04 |
| 20210036054 | MRAM DEVICE HAVING SELF-ALIGNED SHUNTING LAYER - Various embodiments of the present disclosure are directed towards a memory device including a shunting layer overlying a spin orbit torque (SOT) layer. A magnetic tunnel junction (MTJ) structure overlies a semiconductor substrate. The MTJ structure includes a free layer, a reference layer, and a tunnel barrier layer disposed between the free and reference layers. A bottom electrode via (BEVA) underlies the MTJ structure, where the BEVA is laterally offset from the MTJ structure by a lateral distance. The SOT layer is disposed vertically between the BEVA and the MTJ structure, where the SOT layer continuously extends along the lateral distance. The shunting layer extends across an upper surface of the SOT layer and extends across at least a portion of the lateral distance. | 2021-02-04 |
| 20210036055 | MEMORY DEVICE AND SEMICONDUCTOR DIE, AND METHOD OF FABRICATING MEMORY DEVICE - A memory device including bit lines, auxiliary lines, selectors, and memory cells is provided. The word lines are intersected with the bit lines. The auxiliary lines are disposed between the word lines and the of bit lines. The selectors are inserted between the bit lines and the auxiliary lines. The memory cells are inserted between the word lines and the auxiliary lines. | 2021-02-04 |
| 20210036056 | MEMORY DEVICE - A memory device is provided. A memory device includes a memory cell array having variable resistance memory cells that are coupled to and disposed between first conductive lines extending in a first direction and second conductive lines crossing the first conductive lines, and a selection circuit configured to select the first conductive lines. The second conductive lines include straight conductive lines extending in a second direction that crosses the first direction, and first bending conductive lines spaced apart from the selection circuit by the straight conductive lines, the first bending conductive lines extending parallel with each other, and having an L shape. | 2021-02-04 |
| 20210036057 | 3D RRAM CELL STRUCTURE FOR REDUCING FORMING AND SET VOLTAGES - An RRAM cell stack is formed over an opening in a dielectric layer. The dielectric layer is sufficiently thick and the opening is sufficiently deep that an RRAM cell can be formed by a planarization process. The resulting RRAM cells may have a U-shaped profile. The RRAM cell area includes contributions from a bottom portion in which the RRAM cell layers are stacked parallel to the substrate and a side portion in which RRAM cell layers are stacked roughly perpendicular to the substrate. The combined side and bottom portions of the curved RRAM cell provide an increased area in comparison to a planar cell stack. The increased area lowers forming and set voltages for the RRAM cell. | 2021-02-04 |
| 20210036058 | VERTICAL JFET DEVICE FOR MEMRISTOR ARRAY INTERFACE - Devices and methods are provided, In one aspect, a device for driving a memristor array includes a substrate including a well having a bottom layer, a first wall and a second wall. The substrate is formed of a strained layer of a first semiconductor material. A vertical JFET is formed in the well. The vertical JFET includes a vertical gate region formed in a middle portion of the well with a gate region height less than a depth of the well. A channel region is formed of an epitaxial layer of a second semiconductor wrapped around the vertical gate region. Vertical source regions are formed on both sides of a first end of the vertical gate region, and vertical drain regions are formed on both sides of a second end of the vertical gate region. | 2021-02-04 |
| 20210036059 | INTEGRATED CIRCUIT (IC) PACKAGE WITH INTEGRATED INDUCTOR HAVING CORE MAGNETIC FIELD (B FIELD) EXTENDING PARALLEL TO DIE SUBSTRATE - An integrated circuit (IC) package product, e.g., system-on-chip (SoC) or system-in-package (SiP) product, may include at least one integrated inductor having a core magnetic field (B field) that extends parallel to the substrate major plane of at least one die or chiplet included in or mounted to the product, which may reduce the eddy currents within each die/chiplet substrate, and thereby reduce energy loss of the indictor. The IC package product may include a horizontally-extending IC package substrate, a horizontally-extending die mount base arranged on the IC package substrate, at least one die mounted to the die mount base in a vertical orientation, and an integrated inductor having a B field extending in a vertical direction parallel to the silicon substrate of each vertically-mounted die, thereby providing a reduced substrate loss in the integrated inductor, which provides an increased quality factor (Q) of the inductor. | 2021-02-04 |
| 20210036060 | DISPLAY DEVICE - A display device includes a display substrate, a light emitting element layer disposed on a surface of the display substrate and including display pixels, a sensing substrate having a surface attached to another surface of the display substrate, a sensing element layer disposed on another surface of the sensing substrate and including sending pixels that each sense light of a color, and a photorefractive layer disposed on the sensing element layer and including micro lenses. | 2021-02-04 |
| 20210036061 | SENSORS AND ELECTRONIC DEVICES - A sensor includes an anode and a cathode, and a near-infrared photoelectric conversion layer between the anode and the cathode. The near-infrared photoelectric conversion layer is configured to absorb light of at least a portion of a near-infrared wavelength spectrum and convert the absorbed light into an electrical signal. The near-infrared photoelectric conversion layer includes a first material having a maximum absorption wavelength in the near-infrared wavelength spectrum and a second material forming a pn junction with the first material and having a wider energy bandgap than an energy bandgap of the first material. The first material is included in the near-infrared photoelectric conversion layer in a smaller amount than the second material. | 2021-02-04 |
| 20210036062 | DISPLAY DEVICE - A display device including: a lower substrate having a display area and a peripheral area; a plurality of lower electrodes disposed in the display area and on the lower substrate; a pixel defining layer covering a portion of each of the lower electrodes; a light emitting layer disposed on the lower electrodes and the pixel defining layer; an upper electrode disposed on the light emitting layer; a plurality of optical filters disposed on the upper electrode and spaced apart from each other; a lower light blocking layer disposed between the optical filters, and having a plurality of openings; an upper substrate disposed on the lower light blocking layer to oppose the lower substrate; and an alignment structure disposed in the peripheral area of the lower substrate and the upper substrate, and including a material identical to a material of the pixel defining layer and the lower light blocking layer. | 2021-02-04 |
| 20210036063 | COLOR CONVERSION PANEL AND DISPLAY DEVICE INCLUDING THE SAME - In a color conversion panel including pixel areas emitting a light having a same color and a non-pixel area between the pixel areas, the color conversion panel may include a substrate, a light shielding pattern disposed on the substrate in the non-pixel area, a color conversion layer disposed on the substrate, covering the light shielding pattern, and configured to convert an incident light, a height of a first portion of the color conversion layer corresponding to the non-pixel area from the substrate being less than each of heights of second portions of the color conversion layer respectively corresponding to the pixel areas from the substrate, and a light shielding partition wall disposed on the color conversion layer in the non-pixel area. | 2021-02-04 |
| 20210036064 | DISPLAY DEVIVCE - A display device includes: a light-emitting substrate including a base substrate having a non-display area and a display area that surrounds the non-display area; an input sensing unit disposed on the light-emitting substrate; and a hole penetrating front and rear surfaces of each of the light-emitting substrate and the input sensing unit, wherein the light-emitting substrate includes a plurality of recesses, the non-display area includes a hole area which overlaps with the hole, a recess area in which the plurality of recesses are disposed and surrounds the hole area, and a peripheral area which surrounds the recess area, and the input sensing unit includes a plurality of first sensor members overlapping the display area and a first connector connecting the first sensor members and overlapping the groove area. | 2021-02-04 |
| 20210036065 | Color stable multicolor OLED device structures - The present invention relates to OLED devices and stacks for OLED devices that include a symmetric emissive-layer architecture. In one embodiment, the present invention relates to an emissive stack having three layers, wherein the top and bottom layers emit light in the same or similar color region while the middle layer emits light in a different color region than the other two layers. In such an embodiment, the three layers are in contact with each other with no other layers in between. The symmetric emissive-layer architecture of the present invention can be used to improve the color stability of OLED devices. | 2021-02-04 |
| 20210036066 | METHOD AND APPARATUS FOR DETERMINING SUBPIXEL ARRANGEMENT OF ORGANIC LIGHT EMITTING DISPLAY PANEL, AND COMPUTER READABLE STORAGE MEDIUM - The present disclosure relates to a method and an apparatus for determining a subpixel arrangement of an organic light emitting display panel, and a computer readable storage medium. The subpixel arrangement determining method includes: determining arrangement parameters of the first subpixel, the second subpixel, and the third subpixel, according to a side length of the virtual square, a spacing between the third subpixel and an adjacent first subpixel, a spacing between the third subpixel and an adjacent second subpixel, a ratio of aperture ratios of the first subpixel, the second subpixel and the third subpixel, and arrangement constraint conditions of the first subpixel, the second subpixel, and the third subpixel, so that the aperture ratio of the first subpixel is not less than a target aperture ratio. | 2021-02-04 |
| 20210036067 | DISPLAY PANEL HAVING AN ARRANGEMENT BY UNIT PIXEL PAIRS - A display panel includes a first unit pixel including a first pixel electrode for emitting red light, a first pixel electrode for emitting blue light, and a first pixel electrode for emitting green light. A second unit pixel neighbors the first unit pixel and includes a second pixel electrode for emitting red light, a second pixel electrode for emitting blue light, and a second pixel electrode for emitting green light. The first unit pixel further includes a first red emission layer disposed on the first pixel electrode for emitting red light. The second unit pixel further includes a second red emission layer disposed on the second pixel electrode for emitting red light. The first red emission layer is spaced apart from the second red emission layer in the first direction. | 2021-02-04 |
| 20210036068 | DISPLAY PANEL AND MANUFACTURING METHOD THEREOF, AND DISPLAY DEVICE - A display panel and a method of manufacturing the display panel, and a display device are disclosed. The display panel includes a display area and a non-display area. The display area includes a first display area and a second display area both bendable in relation to each other. The display panel includes a base substrate, a thin-film transistor layer, and a sensor. One or a plurality of through holes or grooves are disposed on the thin-film transistor layer, and the second is disposed facing the through hole or the groove. | 2021-02-04 |
| 20210036069 | DISPLAY DEVICE - A display device includes a display module. An impact absorption layer is disposed under the display module and includes a first opening exposing a lower surface of the display module. A rigid plate is disposed under the impact absorption layer. A sensor is disposed between the display module and the rigid plate within the first opening and is coupled to a lower surface of the rigid plate. A support member is disposed between the impact absorption layer and the sensor within the first opening, and contacts the display module and the rigid plate. | 2021-02-04 |
| 20210036070 | DISPLAY DEVICE - A display device includes: a substrate including a display area including a plurality of first pixels and a sensor area including a plurality of second pixels and a plurality of transmission portions, a plurality of first counter electrodes disposed corresponding to the plurality of first pixels, respectively, a plurality of second counter electrodes disposed corresponding to the plurality of second pixels, respectively, and a spacer disposed to overlap at least a portion of a boundary region between a transmission portion of the plurality of transmission portions and a second counter electrode of the plurality of second counter electrodes, which are adjacent to each other. | 2021-02-04 |
| 20210036071 | DISPLAY PANEL, METHOD FOR FABRICATING SAME, AND DISPLAY DEVICE COMPRISING SAME - The present disclosure provides a display panel, a method for fabricating the same, and a display device including the same. The display panel includes a display area. The display area includes a camera sub-area and a normal display sub-area. The display panel includes a substrate, a thin film transistor layer, an organic light emitting layer, and an encapsulation layer. A thickness of a region of the substrate corresponding to the camera sub-area is less than a thickness of a region of the substrate corresponding to the display sub-area. The thin film transistor layer is disposed on the substrate. The organic light emitting layer is disposed on the thin film transistor layer. The encapsulation layer is disposed on the organic light emitting layer. A via hole is disposed in regions of the thin film transistor layer and the organic light emitting layer corresponding to the camera sub-area. | 2021-02-04 |
| 20210036072 | ORGANIC LIGHT EMITTING DIODE DISPLAY PANEL AND MANUFACTURING METHOD THEREOF, AND DISPLAY DEVICE - The present disclosure discloses an organic light emitting diode display panel, a method of manufacturing an organic light emitting diode display panel, and a display device. By forming a film layer having super-hydrophobic properties of the outer water oxygen barrier layer of the thin film encapsulation layer, that is, constructing a rough surface, the surface of the hydrophobic film layer has an extremely thin air layer to reduce direct contact of moisture with the thin film encapsulation layer, thereby reducing the penetration of water and oxygen effectively, improving the water-blocking ability of the film encapsulation layer, and extending the lifetime of the display panel. | 2021-02-04 |
| 20210036073 | DISPLAY DEVICE AND METHOD OF MANUFACTURING THE SAME - A display device includes a first base, a pixel electrode on the first base, a pixel defining layer having an opening that at least partially exposes the pixel electrode, a light emitting layer on the pixel electrode, an auxiliary electrode on the same layer as the pixel electrode, a partition wall on the auxiliary electrode that at least partially exposes a side surface of the auxiliary electrode, an organic layer on the partition wall, and a common electrode continuously arranged on the light emitting layer and the organic layer, wherein a side surface of the partition wall has a reverse-tapered shape, and the common electrode contacts the side surface of the auxiliary electrode. | 2021-02-04 |
| 20210036074 | DISPLAY PANEL AND DISPLAY DEVICE - Embodiments of the present disclosure provided a display panel and a display device. The display panel includes a plurality of pixel defining units, each of the plurality of pixel defining units has a pixel hole for arranging a sub-pixel, and a first guide groove section connecting to the pixel hole, and the first guide groove sections corresponding to two adjacent pixel defining units are connected to each other to form a first guide groove. | 2021-02-04 |
| 20210036075 | DISPLAY SUBSTRATE, METHOD FOR MANUFACTURING THE SAME, AND DISPLAY DEVICE - A display substrate, a method for manufacturing the same, and a display device are provided. The method includes: forming a thin film transistor (TFT) array layer on a base substrate; forming a planarization layer covering the TFT array layer; forming a transition layer on the planarization layer, an adhesion between the transition layer and a photoresist is weaker than an adhesion between the planarization layer and the photoresist; forming the photoresist on the transition layer, exposing and developing the photoresist to form a first photoresist pattern; by using the first photoresist pattern as a mask, etching the transition layer to form a first via hole, and etching the planarization layer through the first via hole to form a second via hole, an orthographic projection of the first via hole onto the base substrate overlaps with an orthographic projection of the second via hole onto the base substrate. | 2021-02-04 |
| 20210036076 | DISPLAY DEVICE AND METHOD OF FABRICATING THE SAME - A display device includes a substrate having a display area and a pad area. A gate conductive layer disposed on the substrate includes a gate conductive metal layer and a gate capping layer. The gate conductive layer forms a gate electrode in the display area and a wire pad in the pad area that is exposed by a pad opening. An interlayer insulating film disposed on the gate conductive layer covers the gate electrode. A data conductive layer disposed on the interlayer insulating film in the display area includes source and drain electrodes. A passivation layer disposed on the data conductive layer covers the source and drain electrodes. A via layer is disposed on the passivation layer. A pixel electrode is disposed on the via layer. The pixel electrode is connected to the source electrode through a contact hole penetrating the via layer and the passivation layer. | 2021-02-04 |
| 20210036077 | DISPLAY SUBSTRATE, METHOD FOR FABRICATING THE SAME, AND DISPLAY DEVICE - The disclosure provides a display substrate, a fabrication method thereof and a display device. The display substrate includes a base, and has a display area and a frame area. The method includes: forming an active region of a thin film transistor in the display area; forming a first lead in the frame area; forming a buffer layer directly covering the first lead; forming a connection via hole communicating with the active region; forming a protective layer directly covering the buffer layer in the frame area; cleaning the active region exposed by the connection via hole after forming the protective layer; removing the protective layer in the frame area after cleaning; and forming a second lead in the frame area after removing the protective layer, an orthographic projection of the second lead on the base and an orthographic projection of the first lead on the base at least partially overlap. | 2021-02-04 |
