05th week of 2021 patent applcation highlights part 61 |
Patent application number | Title | Published |
20210035877 | Warpage Control of Packages Using Embedded Core Frame - A method includes placing a package component over a carrier. The package component includes a device die. A core frame is placed over the carrier. The core frame forms a ring encircling the package component. The method further includes encapsulating the core frame and the package component in an encapsulant, forming redistribution lines over the core frame and the package component, and forming electrical connectors over and electrically coupling to the package component through the redistribution lines. | 2021-02-04 |
20210035878 | SEMICONDUCTOR PACKAGE - A semiconductor package includes a semiconductor chip including a chip pad; a lower redistribution structure on the semiconductor chip, the lower redistribution structure including a lower redistribution insulating layer and a lower redistribution pattern electrically connected to the chip pad of the semiconductor chip; a molding layer on at least a portion of the semiconductor chip; and a conductive post in the molding layer, the conductive post having a bottom surface and a top surface, the bottom surface of the conductive post being in contact with the lower redistribution pattern of the lower redistribution structure and the top surface of the conductive post having a concave shape. | 2021-02-04 |
20210035879 | ENCAPSULATED PACKAGE WITH CARRIER, LAMINATE BODY AND COMPONENT IN BETWEEN - A package and method of manufacturing a package is disclosed. In one example, the method comprises mounting at least one electronic component on a carrier, attaching a laminate body to the mounted at least one electronic component, and filling at least part of spaces between the laminate body and the carrier with mounted at least one electronic component with an encapsulant. | 2021-02-04 |
20210035880 | ELECTRONIC DEVICE PACKAGE ON PACKAGE (POP) - Electronic device package on package (POP) technology is disclosed. A POP can comprise a first electronic device package including a heat source. The POP can also comprise a second electronic device package disposed on the first electronic device package. The second electronic device package can include a substrate having a heat transfer portion proximate the heat source that facilitates heat transfer from the heat source through a thickness of the substrate. The substrate can also have an electronic component portion at least partially about the heat transfer portion that facilitates electrical communication. In addition, the POP can comprise an electronic component operably coupled to the electronic component portion. | 2021-02-04 |
20210035881 | IC PACKAGE INCLUDING MULTI-CHIP UNIT WITH BONDED INTEGRATED HEAT SPREADER - A multi-chip unit suitable for chip-level packaging may include multiple IC chips that are interconnected through a metal redistribution structure, and that are directly bonded to an integrated heat spreader. Bonding of the integrated heat spreader to the multiple IC chips may be direct so that no thermal interface material (TIM) is needed, resulting in a reduced bond line thickness (BLT) and lower thermal resistance. The integrated heat spreader may further serve as a structural member of the multi-chip unit, allowing a second side of the redistribution structure to be further interconnected to a host by solder interconnects. The redistribution structure may be fabricated on a sacrificial interposer that may facilitate planarizing IC chips of differing thickness prior to bonding the heat spreader. The sacrificial interposer may be removed to expose the RDL for further interconnection to a substrate without the use of through-substrate vias. | 2021-02-04 |
20210035882 | Power Semiconductor Device and Method - A power semiconductor device includes: a semiconductor body having a front side and a backside and configured to conduct a load current between the front side and the backside; and a plurality of control cells configured to control the load current. Each control cell is at least partially included in the semiconductor body at the front side and includes a gate electrode that is electrically insulated from the semiconductor body by a gate insulation layer. The gate insulation layer is or includes a first boron nitride layer. | 2021-02-04 |
20210035883 | Board Assembly with Chemical Vapor Deposition Diamond (CVDD) Windows for Thermal Transport - A method and apparatus for conducting heat away from a semiconductor die are disclosed. A board assembly is disclosed that includes a first circuit board having an opening extending through the first circuit board. A Chemical Vapor Deposition Diamond (CVDD) window extends within the opening. A layer of thermally conductive paste extends over the CVDD window. A semiconductor die extends over the layer of thermally conductive paste such that a hot-spot on the semiconductor die overlies the CVDD window. | 2021-02-04 |
20210035884 | SEMICONDUCTOR PACKAGE AND MANUFACTURING METHOD THEREOF - A semiconductor package includes a redistribution structure, at least one semiconductor device and a plurality of heat dissipation films. The at least one semiconductor device is mounted on the redistribution structure. The plurality of heat dissipation films are disposed on the at least one semiconductor device in a side by side manner and jointly cover an upper surface of the at least one semiconductor device. A manufacturing method of the semiconductor package is also provided. | 2021-02-04 |
20210035885 | HIGH THERMAL CONDUCTIVITY BORON ARSENIDE FOR THERMAL MANAGEMENT, ELECTRONICS, OPTOELECTRONICS, AND PHOTONICS APPLICATIONS - A device includes: (1) a boron arsenide substrate; and (2) an integrated circuit disposed in or over the boron arsenide substrate. | 2021-02-04 |
20210035886 | MULTI-CHIP PACKAGE WITH PARTIAL INTEGRATED HEAT SPREADER - A multi-chip package includes multiple IC die interconnected to a package substrate. An integrated heat spreader (IHS) is located over one or more primary IC die, but is absent from over one or more secondary IC die. Thermal cross-talk between IC dies and/or thermal performance of individual IC dies may be improved by constraining the dimensions of the IHS to be over less than all IC die of the package. A first thermal interface material (TIM) may be between the IHS and the primary IC die, but absent from over the secondary IC die. A second TIM may be between a heat sink and the IHS and also between the heat sink and the secondary IC die. The heat sink may be segmented, or have a non-planarity to accommodate differences in z-height across the IC die and/or as a result of constraining the dimensions of the IHS to be over less than all IC die. | 2021-02-04 |
20210035887 | THREE-DIMENSIONAL MEMORY DEVICES AND FABRICATING METHODS THEREOF - A method for forming a gate structure of a 3D memory device is provided. The method comprises forming an array wafer including a periphery region and a staircase and array region. A process of forming the array wafer comprises forming an etch stop layer on a first substrate in the periphery region, forming an array device on the first substrate in the staircase and array region, and forming at least one first vertical through in the periphery region and in contact with the etch stop layer. The method further comprises forming a CMOS wafer, and bonding the array wafer and the CMOS wafer. The method further comprises forming at least one through substrate contact penetrating the first substrate and the etch stop layer, and in contact with the at least one first vertical through contact. | 2021-02-04 |
20210035888 | THREE-DIMENSIONAL MEMORY DEVICES AND FABRICATING METHODS THEREOF - A method for forming a gate structure of a 3D memory device is provided. The method comprises forming an array wafer including a periphery region and a staircase and array region. A process of forming the array wafer comprises forming an array well structure in a first substrate in the periphery region, forming an array device on the first substrate in the staircase and array region, and forming at least one vertical through contact in the periphery region and in contact with the array well structure. The method further comprises forming a CMOS wafer, and bonding the array wafer and the CMOS wafer. The method further comprises forming at least one through substrate contact penetrating the first substrate and the array well structure, and in contact with the at least one vertical through contact. | 2021-02-04 |
20210035889 | SEMICONDUCTOR DEVICE - There is provided a semiconductor device that includes a wiring layer having a main surface and a rear surface which face opposite sides in a thickness direction, a first insulating layer covering an entirety of the rear surface, a second insulating layer which is in contact with the main surface, a semiconductor element which faces the second insulating layer and is mounted on the wiring layer, and a sealing resin which is in contact with the second insulating layer and covers the semiconductor element, wherein surface roughness of the main surface is larger than surface roughness of the rear surface. | 2021-02-04 |
20210035890 | SEMICONDUCTOR PACKAGE AND MANUFACTURING METHOD THEREOF - A semiconductor package includes a chip, a redistribution structure, and first under-ball metallurgies patterns. The chip includes conductive posts exposed at an active surface. The redistribution structure is disposed on the active surface. The redistribution structure includes a first dielectric layer, a topmost metallization layer, and a second dielectric layer. The first dielectric layer includes first openings exposing the conductive posts of the chip. The topmost metallization layer is disposed over the first dielectric layer and is electrically connected to the conductive posts. The topmost metallization layer comprises first contact pads and routing traces connected to the first contact pads. The second dielectric layer is disposed on the topmost metallization layer and includes second openings exposing the first contact pads. The first under-ball metallurgies patterns are disposed on the first contact pads, extending on and contacting sidewalls and top surfaces of the first contact pads. | 2021-02-04 |
20210035891 | SEMICONDUCTOR PACKAGES AND METHODS OF PACKAGING SEMICONDUCTOR DEVICES - An embodiment related to a stacked package is disclosed. The stacked package includes a conductive gang with gang legs electrically coupling a second component stacked over a first die to a package substrate. The first die is mounted over a die attach region of the package substrate and electrically coupled to the package substrate. | 2021-02-04 |
20210035892 | LOW STRESS ASYMMETRIC DUAL SIDE MODULE - Implementations of semiconductor packages may include a first substrate having two or more die coupled to a first side, a clip coupled to each of the two or more die on the first substrate and a second substrate having two or more die coupled to a first side of the second substrate. A clip may be coupled to each of the two or more die on the second substrate. The package may include a lead frame between the first substrate and the second substrate and a molding compound. A second side of each of the first substrate and the second substrate may be exposed through the molding compound. A perimeter of the first substrate and a perimeter of the second substrate may not fully overlap when coupled through the lead frame. | 2021-02-04 |
20210035893 | SEMICONDUCTOR DEVICE - A semiconductor device according to embodiments includes a first base material having a first side surface, a first semiconductor chip provided above the first base material, a first insulating plate provided between the first base material and the first semiconductor chip, a first metal plate provided between the first insulating plate and the first semiconductor chip, a first bonding material provided between the first metal plate and the first semiconductor chip, the first bonding material bonding the first metal plate and the first semiconductor chip, a second bonding material provided between the first base material and the first insulating material, the second bonding material bonding the first base material and the first insulating plate, a second base material having a second side surface, a second semiconductor chip provided above the second base material, a second insulating plate provided between the second base material and the second semiconductor chip, a second metal plate provided between the second insulating plate and the second semiconductor chip, a third bonding material provided between the second metal plate and the second semiconductor chip, the third bonding material bonding the second metal plate and the second semiconductor chip, a fourth bonding material provided between the second base material and the second insulating plate, the fourth bonding material bonding the second base material and the second insulating plate, and a first base bonding portion provided between the second side surface and the first side surface and bonded to the first side surface and the second side surface. | 2021-02-04 |
20210035894 | LEAD FRAME FOR A PACKAGE FOR A SEMICONDUCTOR DEVICE, SEMICONDUCTOR DEVICE AND PROCESS FOR MANUFACTURING A SEMICONDUCTOR DEVICE - A lead frame for an integrated electronic device includes a die pad made of a first metallic material. A top coating layer formed by a second metallic material is arranged on a top surface of the die pad. The second metallic material has an oxidation rate lower than the first metallic material. The top coating layer leaves exposed a number of corner portions of the top surface of the die pad. A subsequent heating operation, for example occurring in connection with wirebonding, causes an oxidized layer to form on the corner portions of the top surface of the die pad at a position in contact with the top coating layer. | 2021-02-04 |
20210035895 | SEMICONDUCTOR PACKAGE - A semiconductor package may include a substrate having an upper surface on which a plurality of first pads are disposed and a lower surface on which a plurality of second pads are disposed. The semiconductor package may further include a semiconductor chip disposed on the upper surface of the substrate on which connection electrodes connected to a first set of the plurality of first pads are disposed. The semiconductor package may include an interposer having an upper surface on which a plurality of first connection pads, connected to a second set of the plurality of first pads, and a plurality of second connection pads are disposed. The semiconductor package may further include a plurality of connection terminals disposed on a set of the plurality of second connection pads of the interposer, and a molding material disposed on the upper surface of the substrate. | 2021-02-04 |
20210035896 | WIRING STRUCTURE - A wiring structure includes an upper conductive structure, a lower conductive structure and an intermediate layer. The upper conductive structure includes at least one dielectric layer and at least one circuit layer in contact with the dielectric layer. The lower conductive structure includes at least one dielectric layer and at least one circuit layer in contact with the dielectric layer. The intermediate layer is disposed between the upper conductive structure and the lower conductive structure and bonds the upper conductive structure and the lower conductive structure together. The upper conductive structure is electrically connected to the lower conductive structure. The intermediate layer includes a plurality of sub-layers. Each of the sub-layers is formed from a polymeric material. A boundary is formed between two adjacent sub-layers. | 2021-02-04 |
20210035897 | WIRING STRUCTURE AND METHOD FOR MANUFACTURING THE SAME - A wiring structure includes an upper conductive structure, a lower conductive structure, a plurality of metallic structures and an intermediate layer. The upper conductive structure includes at least one dielectric layer and at least one circuit layer in contact with the dielectric layer. The lower conductive structure includes at least one dielectric layer and at least one circuit layer in contact with the dielectric layer. The metallic structures are disposed between the upper conductive structure and the lower conductive structure, and electrically connecting the upper conductive structure and the lower conductive structure. The intermediate layer is disposed between the upper conductive structure and the lower conductive structure, and covers the metallic structures. | 2021-02-04 |
20210035898 | PACKAGE STRUCTURE AND MANUFACTURING METHOD THEREOF - A package structure and a manufacturing method thereof are provided. The package structure includes a substrate having a first surface and a second surface opposite to each other, a die electrically coupled to the substrate, an encapsulant disposed over the first surface of the substrate to encapsulate the die, at least one first conductive terminal and at least one second conductive terminal. The at least one first conductive terminal and the at least one second conductive terminal are disposed on the second surface of the substrate. The at least one second conductive terminal is electrically connected to the die through the substrate. The at least one first conductive terminal is overlapped with the die in a direction perpendicular to the second surface of the substrate. A first area of the at least one first conductive terminal is larger than a second area of the at least one second conductive terminal. | 2021-02-04 |
20210035899 | SEMICONDUCTOR DEVICE PACKAGE AND METHOD FOR MANUFACTURING THE SAME - A semiconductor device package includes a conductive layer, a first conductive pillar, a circuit layer and a second conductive pillar. The conductive layer has a first surface. The first conductive pillar is disposed on the first surface of the conductive layer. The circuit layer is disposed over the conductive layer. The circuit layer has a first surface facing the conductive layer. The second conductive pillar is disposed on the first surface of the circuit layer. The first conductive pillar is physically spaced apart from the second conductive pillar and electrically connected to the second conductive pillar. | 2021-02-04 |
20210035900 | ELECTRONIC COMPONENT MODULE - According to one embodiment, the electrode pads are provided at a surface of the substrate. The metal pad is provided at the surface of the substrate. The electronic component is mounted to the surface of the substrate. The electronic component includes a plurality of opposing electrodes. The opposing electrodes oppose the electrode pads in a direction toward the surface direction and are electrically connected to the electrode pads. The positioning component is fixed to the metal pad. A gap between the positioning component and the electronic component in an in-plane direction of the surface of the substrate is shorter than a minimum distance of the electrode pads. | 2021-02-04 |
20210035901 | ELECTROMIGRATION RESISTANT AND PROFILE CONSISTENT CONTACT ARRAYS - A package assembly includes a substrate and at least a first die having a first contact array and a second contact array. First and second via assemblies are respectively coupled with the first and second contact arrays. Each of the first and second via assemblies includes a base pad, a cap assembly, and a via therebetween. One or more of the cap assembly or the via includes an electromigration resistant material to isolate each of the base pad and the cap assembly. Each first cap assembly and via of the first via assemblies has a first assembly profile less than a second assembly profile of each second cap assembly and via of the second via assemblies. The first and second cap assemblies have a common applied thickness in an application configuration. The first and second cap assemblies have a thickness variation of ten microns or less in a reflowed configuration. | 2021-02-04 |
20210035902 | SEMICONDUCTOR DEVICE - A semiconductor device includes a first gate electrode disposed on a substrate and extending in a first horizontal direction, a first gate contact and a dummy gate contact, which are spaced apart from each other in the first horizontal direction and are in contact with a top surface of the first gate electrode, a first interconnect line extending in a second horizontal direction and overlapping the first gate contact in a vertical direction with respect to the upper surface of the substrate, and a voltage generator configured to generate a first voltage and apply the first voltage to the first gate electrode via the first interconnect line and the first gate contact. The first gate electrode receives the first voltage via the first interconnect line and the first gate contact from the voltage generator. The dummy gate contact receives the first voltage via the first gate electrode. | 2021-02-04 |
20210035903 | SEMICONDUCTOR STRUCTURE AND MANUFACTURING METHOD THEREOF - A method of manufacturing a semiconductor structure includes providing a substrate and an interlayer dielectric (ILD) over the substrate; disposing a first dielectric layer over the ILD and the substrate; forming a conductive member surrounded by the first dielectric layer; disposing a second dielectric layer over the first dielectric layer and the conductive member; forming a capacitor over the second dielectric layer; disposing a third dielectric layer over the capacitor and the second dielectric layer; forming a conductive via extending through the second dielectric layer, the capacitor and the third dielectric layer; forming a conductive pad over the conductive via; and forming a conductive bump over the conductive pad, wherein the disposing of the third dielectric layer includes disposing an oxide layer over the capacitor and disposing a nitride layer over the capacitor. | 2021-02-04 |
20210035904 | Adjustable Via Dimension and Chamfer Angle - Chamfer-less via interconnects and techniques for fabrication thereof with a protective dielectric arch are provided. In one aspect, a method of forming an interconnect includes: forming metal lines in a first dielectric; depositing an etch stop liner onto the first dielectric; depositing a second dielectric on the etch stop liner; patterning vias and a trench in the second dielectric, wherein the vias are present over at least one of the metal lines, and wherein the patterning forms patterned portions of the second dielectric/etch stop liner over at least another one of the metal lines; forming a protective dielectric arch over the at least another one of the metal lines; and filling the vias/trench with a metal(s) to form the interconnect which, due to the protective dielectric arch, is in a non-contact position with the at least another one of the metal lines. An interconnect structure is also provided. | 2021-02-04 |
20210035905 | SEMICONDUCTOR STRUCTURE AND MANUFACTURING METHOD THEREOF - The semiconductor structure includes a first die, a second die, a connecting portion, and a through-substrate via. The first die includes a first dielectric layer and a first helical conductor embedded therein. The second die includes a second dielectric layer and a second helical conductor embedded therein, wherein the second dielectric layer is bonded with the first dielectric layer, thereby forming an interface. The connecting portion extends from the first dielectric layer through the interface to the second dielectric layer and interconnects the first helical conductor with the second helical conductor. The through-substrate via extends from the first die to the second die through the interface, wherein the through-substrate via is surrounded by the first and the second helical conductors. | 2021-02-04 |
20210035906 | Semiconductor Device Structure Having a Multi-Layer Conductive Feature and Method Making the Same - The present disclosure provides a method of forming a semiconductor device structure. The method includes forming a trench in a dielectric layer on a semiconductor substrate; forming a bottom metal feature of a first metal in a lower portion of the trench by a selective deposition; depositing a barrier layer in an upper portion of the trench, the barrier layer directly contacting both a top surface of the bottom metal feature and sidewalls of the dielectric layer; and forming a top metal feature of a second metal on the barrier layer, filling in the upper portion of the trench, wherein the second metal is different from the first metal in composition. | 2021-02-04 |
20210035907 | INTEGRATED CIRCUIT DEVICE WITH THROUGH INTERCONNECT VIA AND METHODS OF MANUFACTURING THE SAME - Integrated circuit devices and method of manufacturing the same are disclosed. An integrated circuit device includes an interconnect structure on a substrate, a passivation layer on the interconnect structure, a plurality of conductive pads on the passivation layer and a through interconnect via (TIV). The interconnect structure includes a plurality of dielectric layers and an interconnect in the plurality of dielectric layers. The plurality of conductive pads includes a first conductive pad electrically connecting the interconnect. The through interconnect via extends through the plurality of dielectric layers and electrically connecting a first conductive layer of the interconnect. | 2021-02-04 |
20210035908 | SEMICONDUCTOR DEVICE PACKAGE AND METHOD FOR MANUFACTURING THE SAME - A semiconductor device package includes a first circuit layer, a second circuit layer, a first semiconductor die and a second semiconductor die. The first circuit layer includes a first surface and a second surface opposite to the first surface. The second circuit layer is disposed on the first surface of the first circuit layer. The first semiconductor die is disposed on the first circuit layer and the second circuit layer, and electrically connected to the first circuit layer and the second circuit layer. The second semiconductor die is disposed on the second circuit layer, and electrically connected to the second circuit layer. | 2021-02-04 |
20210035909 | ELECTRONIC APPARATUS AND MANUFACTURING METHOD THEREOF - The disclosure provides an electronic apparatus and a manufacturing method thereof. The electronic apparatus includes a first insulating layer, a first metal layer, a second metal layer, and an electronic assembly. The first insulating layer includes a first surface and a second surface opposite to the first surface. The first metal layer has an opening and is formed on the first surface. The second metal layer is formed on the second surface and a projection of the opening on the second surface is overlapped with a projection of the second metal layer on the second surface. The electronic assembly is electrically connected with the first metal layer and the second metal layer. | 2021-02-04 |
20210035910 | SEMICONDUCTOR MEMORY DEVICE AND METHOD OF FABRICATING THE SAME - A semiconductor memory includes electrode structures that each includes horizontal electrodes stacked on each other a substrate, vertical electrodes between the electrode structures and extending along the horizontal electrodes, first contacts connected to the horizontal electrodes at end portions of the electrode structures, second contacts connected to upper portions of the vertical electrodes, and a first interconnection structure connected to top surfaces of the second contacts. The first interconnection structure includes first and second sub-interconnection lines. The sub-interconnection lines extend in a first direction and contact the top surfaces of the second contacts. The second sub-interconnection lines extended in a second direction crossing the first direction and contact the first sub-interconnection lines. | 2021-02-04 |
20210035911 | MULTI-DIE ULTRAFINE PITCH PATCH ARCHITECTURE AND METHOD OF MAKING - Embodiments include semiconductor packages and methods to form the semiconductor packages. A semiconductor package includes a bridge over a glass patch. The bridge is coupled to the glass patch with an adhesive layer. The semiconductor package also includes a high-density packaging (HDP) substrate over the bridge and the glass patch. The HDP substrate is conductively coupled to the glass patch with a plurality of through mold vias (TMVs). The semiconductor package further includes a plurality of dies over the HDP substrate, and a first encapsulation layer over the TMVs, the bridge, the adhesive layer, and the glass patch. The HDP substrate includes a plurality of conductive interconnects that conductively couple the dies to the bridge and glass patch. The bridge may be an embedded multi-die interconnect bridge (EMIB), where the EMIB is communicatively coupled to the dies, and the glass patch includes a plurality of through glass vias (TGVs). | 2021-02-04 |
20210035912 | SEMICONDUCTOR DEVICE PACKAGE AND METHOD OF MANUFACTURING THE SAME - A semiconductor device package includes a magnetically permeable layer having a top surface and a bottom surface opposite to the top surface. The semiconductor device package further includes a first conductive element in the magnetically permeable layer. The semiconductor device package further includes a first conductive via extending from the top surface of the magnetically permeable layer into the magnetically permeable layer to be electrically connected to the first conductive element. The first conductive via is separated from the magnetically permeable layer. A method of manufacturing a semiconductor device package is also disclosed. | 2021-02-04 |
20210035913 | SEMICONDUCTOR PACKAGE AND A METHOD OF FABRICATING THE SAME - A semiconductor package including: a first package; a second package on the first package, the second package including a second package substrate, first and second semiconductor chips on the second package substrate, and a second molding part on the second package substrate and covering the first and second semiconductor chips; and a fill part between the first package and the second package, a first through hole that penetrates the second package substrate, the first through hole being between the first and second semiconductor chips, a second through hole that penetrates the second molding part, the second through hole being connected to the first through hole, and wherein the fill part has an extension disposed in the first through hole and the second through hole. | 2021-02-04 |
20210035914 | CHIP PACKAGE STRUCTURE - A chip package structure including first and second insulating layers, first and second circuit structures, a chip on the first circuit structure, an encapsulant, a conductive through via, and first and second heat dissipation layers is provided. The first circuit structure is disposed at the first surface of the first insulating layer. The bottom electrode of the chip is electrically connected to the first circuit structure. The second circuit structure is disposed on the chip and electrically connected to the top electrode of the chip. The encapsulant encapsulates the first and second circuit structures and the chip. The conductive through via is disposed in the encapsulant and connects the first and second circuit structures. The second insulating layer is disposed on the second circuit structure. The first heat dissipation layer is disposed on the first insulating layer. The second heat dissipation layer is disposed on the second insulating layer. | 2021-02-04 |
20210035915 | SEMICONDUCTOR DEVICE STRUCTURE WITH COMPOUND SEMICONDUCTOR AND METHOD FOR PRODUCING THE SAME - The invention relates to a semiconductor structure including a substrate with a first main surface located on a first substrate side and a second main surface located on an opposite second substrate side as well as a vertical via extending completely through the substrate between the first main surface and the second main surface. On the first substrate side, a metallization layer that is connected galvanically to the via is arranged in the region of the via. A compound semiconductor layer connected galvanically to the metallization layer is arranged on the metallization layer. Further, the invention relates to a method for producing such a semiconductor device structure. | 2021-02-04 |
20210035916 | SEMICONDUCTOR PACKAGE - A semiconductor package includes a substrate, a semiconductor die, a dummy die, a conductive layer, at least one first conductive wire, and at least one second conductive wire. The semiconductor die is disposed on the substrate. The dummy die is disposed on the semiconductor die. The conductive layer is disposed on the dummy die. The first conductive wire electrically connects the semiconductor die to a signal source. The second conductive wire electrically connects the conductive layer to a ground reference. | 2021-02-04 |
20210035917 | SEMICONDUCTOR PACKAGES AND ASSOCIATED METHODS WITH ANTENNAS AND EMI ISOLATION SHIELDS - Semiconductor devices with antennas and electromagnetic interference (EMI) shielding, and associated systems and methods, are described herein. In one embodiment, a semiconductor device includes a semiconductor die coupled to a package substrate. An antenna structure is disposed over and/or adjacent the semiconductor die. An electromagnetic interference (EMI) shield is disposed between the semiconductor die and the antenna structure to shield at least the semiconductor die from electromagnetic radiation generated by the antenna structure and/or to shield the antenna structure from interference generated by the semiconductor die. A first dielectric material and/or a thermal interface material can be positioned between the semiconductor die and the EMI shield, and a second dielectric material can be positioned between the EMI shield and the antenna structure. In some embodiments, the semiconductor device includes a package molding over at least a portion of the antenna, the EMI shield, and/or the second dielectric material. | 2021-02-04 |
20210035918 | SEMICONDUCTOR STRUCTURE AND FABRICATION METHOD THEREOF - A semiconductor structure includes a semiconductor substrate, a shielding structure, a ground terminal, and a through silicon via. The shielding structure is disposed over the semiconductor substrate and includes a first metal layer, a second metal layer, and a third metal layer. The first metal layer is disposed over the semiconductor substrate. The second metal layer is disposed over the first metal layer. The third metal layer is disposed over the second metal layer. The ground terminal is electrically connected to the third metal layer. The through silicon via is disposed over the semiconductor substrate and adjacent to the shielding structure. | 2021-02-04 |
20210035919 | SEMICONDUCTOR PACKAGE WITH EMI SHIELDING STRUCTURE - A semiconductor package includes a carrier substrate having a top surface; a semiconductor die mounted on the top surface; a plurality of first bonding wires connecting the semiconductor die to the carrier substrate; an insulating material encapsulating the plurality of first bonding wires; a component having a metal layer mounted on the insulating material; a plurality of second bonding wires connecting the metal layer of the component to the carrier substrate; and a molding compound covering the top surface of the carrier substrate and encapsulating the semiconductor die, the component, the plurality of first bonding wires, the plurality of second bonding wires, and the insulating material. The metal layer and the plurality of second bonding wires constitute an electromagnetic interference (EMI) shielding structure. | 2021-02-04 |
20210035920 | MAGNETIC SHIELDING MATERIAL WITH INSULATOR-COATED FERROMAGNETIC PARTICLES - A non-conductive magnetic shield material is provided for use in magnetic shields of semiconductor packaging. The material is made magnetic by the incorporation of ferromagnetic particles into a polymer matrix, and is made non-conductive by the provision of an insulating coating on the ferromagnetic particles. | 2021-02-04 |
20210035921 | SOLDERED METALLIC RESERVOIRS FOR ENHANCED TRANSIENT AND STEADY-STATE THERMAL PERFORMANCE - Embodiments disclosed herein include electronic packages with thermal solutions. In an embodiment, an electronic package comprises a package substrate, a first die electrically coupled to the package substrate, and an integrated heat spreader (IHS) that is thermally coupled to a surface of the first die. In an embodiment, the IHS comprises a main body having an outer perimeter, and one or more legs attached to the outer perimeter of the main body, wherein the one or more legs are supported by the package substrate. In an embodiment, the electronic package further comprises a thermal block between the package substrate and the main body of the IHS, wherein the thermal block is within the outer perimeter of the main body. | 2021-02-04 |
20210035922 | SEMICONDUCTOR DEVICE AND HIGH-FREQUENCY MODULE - At least one unit transistor is arranged over a substrate. A first wiring as a path of current that flows to each unit transistor is arranged over the at least one unit transistor. An inorganic insulation film is arranged over the first wiring. At least one first opening overlapping a partial region of the first wiring in a plan view is provided in the inorganic insulation film. An organic insulation film is arranged over the inorganic insulation film. A second wiring coupled to the first wiring through the first opening is arranged over the organic insulation film and the inorganic insulation film. In a plan view, a region in which the organic insulation film is not arranged is provided outside a region in which the first wiring is arranged. The second wiring is in contact with the inorganic insulation film outside the region in which the first wiring is arranged. | 2021-02-04 |
20210035923 | Preventing and Detecting Integrated Circuit Theft and Counterfeiting - A mechanism is provided to secure integrated circuit devices that combines a high degree of security with a low overhead, both in area and cost, thereby making it appropriate for smaller, cheaper integrated circuits. A determination is made whether a device die is on a wafer or if the device die is incorporated into a package. Only if the device die is incorporated in a package can the functional logic of device die be activated, and then only if a challenge-response query is satisfied. In some embodiments, a random number generator is used during wafer testing to form a pair of numbers, along with a die identifier, that is unique for each device die. A final test is then performed in which the device die can be activated if the device die is incorporated in a package, and the die identifier—random number pair is authenticated. | 2021-02-04 |
20210035924 | PACKAGING TECHNIQUES FOR BACKSIDE MESH CONNECTIVITY - The embodiments herein are directed to technologies for backside security meshes of semiconductor packages. One package includes a substrate having a first interconnect terminal of a first type and a second interconnect terminal of a second type. The package also includes a first security mesh structure disposed on a first side of an integrated circuit die and a conductive path coupled between the first interconnect terminal and the second interconnect terminal. The first security mesh structure is coupled to the first interconnect terminal and the second interconnect terminal being coupled to a terminal on a second side of the integrated circuit die. | 2021-02-04 |
20210035925 | DEVICE HAVING PHYSICALLY UNCLONABLE FUNCTION, METHOD FOR MANUFACTURING SAME, AND CHIP USING SAME - The present application relates to a technical field of semiconductors, and discloses a device having a physically unclonable function, a method for manufacturing same, and a chip using same. The may method include: providing a substrate structure that comprises: a substrate comprising encryption device areas and reference device areas; at least one first gate structure on the encryption device areas and used in an encryption device and a first spacer layer on a side wall of the first gate structure; a first interconnection layer on the encryption device areas and the first spacer layer; at least one second gate structure on the reference device areas and used in a reference device and a second spacer layer on a side wall of the second gate structure; and a second interconnection layer on the reference device area and the second spacer layer; performing first ion injection, so as to introduce first impurities into the first interconnection layer; performing second ion injection, so as to introduce second impurities into the first and second interconnection layers, where a password of the device having a physically unclonable function is determined according to a drain current of each encryption device and a drain current of a reference device corresponding to the encryption device. | 2021-02-04 |
20210035926 | SEMICONDUCTOR DEVICES, SEMICONDUCTOR WAFERS, AND METHODS OF MANUFACTURING THE SAME - The present disclosure provides a semiconductor device. The semiconductor device includes a semiconductor substrate and a first deep trench isolation (DTI) structure filled with a dielectric material formed on the semiconductor substrate. The first DTI structure is disposed in the first seal ring region and is extended into the semiconductor substrate. The semiconductor substrate has a pixel array region and a first seal ring region. The first seal ring region is proximate to an edge of the semiconductor substrate and surrounds the pixel array region. The first DTI structure is formed in the first seal ring region and surrounds the pixel array region. | 2021-02-04 |
20210035927 | Method, System, and Apparatus for Forming Three-Dimensional Semiconductor Device Package with Waveguide - A semiconductor device package that incorporates a waveguide usable for high frequency applications, such as radar and millimeter wave is provided. Embodiments employ a rigid-flex printed circuit board structure that can be folded to form the waveguide while, at the same time, mounting one or more semiconductor device die or packages. Embodiments reduce both the area of the mounted package and the distance signals need to travel between the semiconductor device die and antennas associated with the waveguide. | 2021-02-04 |
20210035928 | MANUFACTURING METHOD OF PACKAGE STRUCTURE - A method including the following steps is provided. A seed layer is formed. Conductive patterns are formed on the seed layer. An etching process with an etchant is performed to remove a portion of the seed layer exposed by the conductive patterns, wherein the etchant includes: 0.1 wt % to 10 wt % of phosphoric acid (H | 2021-02-04 |
20210035929 | SEMICONDUCTOR PACKAGE - A semiconductor package includes a main substrate, a resonator device disposed above the main substrate, a wiring portion connected to the resonator device, an electrical connection structure connected to the wiring portion and the main substrate, an encapsulant encapsulating the resonator device and the electrical connection structure, and a heat dissipation member bonded to and mounted on the resonator device. A cavity is provided in the resonator device, and is formed between the resonance portion and a resonator device substrate provided in the resonator device. | 2021-02-04 |
20210035930 | SEMICONDUCTOR PACKAGE STRUCTURE INCLUDING ANTENNA - A semiconductor package structure is provided. The semiconductor package structure includes an antenna device and semiconductor package. The antenna device includes a conductive pattern layer including a first antenna element, formed in an insulating substrate and adjacent to a first surface of the insulating substrate. The antenna device also includes a second antenna element formed on a second surface of the insulating substrate opposite the first surface. The semiconductor package includes a redistribution layer (RDL) structure bonded and electrically connected to the conductive pattern layer. The semiconductor package also includes a first semiconductor die electrically connected to the RDL structure, and an encapsulating layer formed on the RDL structure and surrounding the first semiconductor die. | 2021-02-04 |
20210035931 | SEMICONDUCTOR DEVICE - Disclosed is a semiconductor device including a semiconductor die, a base member, a side wall, first and second conductive films, and first and second conductive leads. The base member has a conductive main surface including a region that mounts the semiconductor die. The side wall surrounds the region and is made of a dielectric. The side wall includes first and second portions. The first and second conductive films are provided on the first and second portions, respectively and are electrically connected to the semiconductor die. The first and second conductive leads are conductively bonded to the first and second conductive films, respectively. At least one of the first and second portions includes a recess on its back surface facing the base member, and the recess defines a gap between the at least one of the first and second portions below the corresponding conductive film and the base member. | 2021-02-04 |
20210035932 | INTEGRATED CIRCUIT BACKSIDE METALLIZATION - A method for backside metallization includes inkjet printing a pattern of nanosilver conductive ink on a first surface of a silicon wafer. The silicon wafer includes a plurality of dies. The pattern includes a clearance area along a scribe line between the dies. A laser is focused, through a second surface of the wafer, at a point between the first surface of the silicon wafer and the second surface of the silicon wafer. The second surface is opposite the first surface. The dies are separated along the scribe line. | 2021-02-04 |
20210035933 | SEMICONDUCTOR STRUCTURE AND METHOD OF MANUFACTURING THE SAME - A semiconductor structure and a method of manufacturing the same are provided. The semiconductor structure includes a first semiconductor element and a first bonding structure. The first semiconductor element has a first element top surface and a first element bottom surface opposite to the element top surface. The first bonding structure is disposed adjacent to the element top surface of the first semiconductor element and includes a first electrical connector, a first insulation layer surrounding the first electrical connector, and a first metal layer surrounding the first insulation layer. | 2021-02-04 |
20210035934 | Method for Producing a Connection Between Component Parts - In an embodiment a method includes providing the first component part with a partially exposed first insulating layer, a plurality of first through-vias and an exposed first contact layer structured in places and planarized in places, wherein the first through-vias are each laterally enclosed by the first insulating layer, and wherein the first contact layer partially covers the first insulating layer and completely covers the first through-vias; providing the second component part with a partially exposed second insulating layer, a plurality of second through-vias and an exposed second contact layer structured in places and planarized in places, wherein the second through-vias are each laterally enclosed by the second insulating layer, and wherein the second contact layer partially covers the second insulating layer and completely covers the second through-vias and joining the component parts such that the contact layers overlap each other thereby mechanically and electrically connecting the component parts to each other by a direct bonding process at the contact layers. | 2021-02-04 |
20210035935 | SEMICONDUCTOR STRUCTURE AND METHOD FOR MANUFACTURING THE SAME - A semiconductor structure includes a first substrate, a first dielectric layer disposed over the first substrate, a plurality of first bonding pads disposed in the first dielectric layer, a plurality of second bonding pads disposed in the first dielectric layer, a second substrate, and a second dielectric layer disposed over the second substrate. The first bonding pads have a first width. The second bonding pads have a second width greater than the first width. The second bonding pads are arranged to form a frame pattern surrounding the first bonding pads. A portion of the second dielectric layer is in physical contact with the second bonding pads. The first bonding pads and the second bonding pads are arranged to form a plurality of columns and a plurality of rows. Two of the second bonding pads are disposed at two opposite ends of each column and two opposite ends of each row. | 2021-02-04 |
20210035936 | PACKAGE STRUCTURE AND METHOD OF MANUFACTURING THE SAME - A package structure and a method of manufacturing the same are provided. The package structure includes a substrate, a redistribution layer (RDL) structure, a first die, an encapsulant and a plurality of conductive terminals. The RDL structure is disposed on and electrically connected to the substrate. A width of the RDL structure is less than a width of the substrate. The first die is disposed on the substrate and the RDL structure. The first connectors of the first die are electrically connected to the RDL structure. The second connectors of the first die are electrically connected to the substrate. A first pitch of two adjacent first connectors is less than a second pitch of two adjacent second connectors. The encapsulant is on the substrate to encapsulate the RDL structure and the first die. The conductive terminals are electrically connected to the first die through the substrate and the RDL structure. | 2021-02-04 |
20210035937 | METHOD FOR FORMING PACKAGE STRUCTURE WITH A BARRIER LAYER - A method for forming a package structure includes forming an under bump metallization (UBM) layer over a metal pad and forming a photoresist layer over the UBM layer. The method further includes patterning the photoresist layer to form an opening in the photoresist layer. The method also includes forming a first bump structure over the first portion of the UBM layer. The first bump structure includes a first barrier layer over a first pillar layer. The method includes placing a second bump structure over the first bump structure. The second bump structure includes a second barrier layer over a second pillar layer. The method further includes reflowing the first bump structure and the second bump structure to form a solder joint between a first inter intermetallic compound (IMC) and a second IMC. | 2021-02-04 |
20210035938 | BUMP STRUCTURE HAVING A SIDE RECESS AND SEMICONDUCTOR STRUCTURE INCLUDING THE SAME - The present disclosure relates to an integrated chip structure having a first copper pillar disposed over a metal pad of an interposer substrate. The first copper pillar has a sidewall defining a recess. A nickel layer is disposed over the first copper pillar and a solder layer is disposed over the first copper pillar and the nickel layer. The solder layer continuously extends from directly over the first copper pillar to within the recess. A second copper layer is disposed between the solder layer and a second substrate. | 2021-02-04 |
20210035939 | PACKAGE STRUCTURE - A package structure includes a redistribution layer having an upper surface and a lower surface opposite to each other, in which the redistribution layer has at least one recess on its lower surface, an electronic element disposed on the upper surface of the redistribution layer, at least one first conductive ball disposed on the at least one recess of the redistribution layer, in which a portion of the at least one first conductive ball is filled into the at least one recess, and a plurality of second conductive balls disposed on the lower surface of the redistribution layer. The height of the first conductive ball is larger than the height of each of the second conductive balls in a direction perpendicular to the lower surface of the redistribution layer. | 2021-02-04 |
20210035940 | CHIP STRUCTURE AND MANUFACTURING METHOD THEREOF - A chip structure includes a first substrate, a second substrate, a conductive via, and a redistribution layer. The first substrate has a first inclined sidewall. The second substrate is located on a bottom surface of the first substrate, and has an upper portion and a lower portion. The lower portion extends from the upper portion. The upper portion is between the first substrate and the lower portion. The upper portion has a second inclined sidewall, and a slope of the first inclined sidewall is substantially equal to a slope of the second inclined sidewall. The conductive via is in the lower portion. The redistribution layer extends from a top surface of the first substrate to a top surface of the lower portion of the second substrate sequentially along the first inclined sidewall and the second inclined sidewall, and is electrically connected to the conductive via. | 2021-02-04 |
20210035941 | HYBRID BONDING USING DUMMY BONDING CONTACTS - Embodiments of bonded semiconductor structures and fabrication methods thereof are disclosed. In an example, a method for forming a semiconductor device is disclosed. A first interconnect layer including first interconnects is formed above a first substrate. A first bonding layer including first bonding contacts is formed above the first interconnect layer, such that each first interconnect is in contact with a respective first bonding contact. A second interconnect layer including second interconnects is formed above a second substrate. A second bonding layer including second bonding contacts is formed above the second interconnect layer, such that at least one second bonding contact is in contact with a respective second interconnect, and at least another second bonding contact is separated from the second interconnects. The first and second substrates are bonded in a face-to-face manner, such that each first bonding contact is in contact with one second bonding contact at a bonding interface. | 2021-02-04 |
20210035942 | BOND WIRE ARRAY FOR PACKAGED SEMICONDUCTOR DEVICE - A packaged radio frequency (RF) amplifier device includes a flange and a transistor die mounted to the flange. The transistor die includes an output terminal. The packaged RF amplifier device includes a first bond wire array including a first plurality of bond wires. Each bond wire in the first plurality of bond wires is electrically coupled to the output terminal of the transistor die. A first ground loop area of a first bond wire in the first plurality of bond wires is greater than a second ground loop area of a second bond wire in the first plurality of bond wires. | 2021-02-04 |
20210035943 | METHOD FOR MANUFACTURING AN ELECTRONIC CIRCUIT COMPONENT AND ELECTRONIC CIRCUIT COMPONENT - A method for manufacturing an electronic circuit component includes: providing a first electronic component with one or several electrically conductive first contacts and with one or several insulating first supporting elements; providing a second electronic component with one or several electrically conductive second contacts and with one or several insulating second supporting elements; configuring a connecting structure with an interposer substrate, with electrically conductive third contacts, with one or several electrically conductive fourth contacts, with one or several insulating third supporting elements, with one or several electrically conductive fifth contacts, and with one or several insulating fourth supporting elements; connecting the first electronic component and the second electronic component to the connecting structure, wherein the first contacts are electrically connected to the fourth contacts, wherein the first supporting elements are mechanically connected to the third supporting elements, wherein the second contacts are electrically connected to the fifth contacts, and wherein the second supporting elements are mechanically connected to the fourth supporting elements, so that the first electronic component, the second electronic component, and the connecting structure are connected electrically and mechanically; removing a part of the interposer substrate so that the third contacts are exposed. | 2021-02-04 |
20210035944 | CHIP PACKAGE FABRICATION KIT AND CHIP PACKAGE FABRICATING METHOD THEREOF - A chip package fabricating kit includes a metal cover, at least one screw, and at least one screw cap. The metal cover includes a cap portion and at least one leg. The cap portion substantially presses against the BGA package. The leg substantially presses a PCB board that loads the BGA package. The leg forms a concave space with the metal cover for substantially encompassing the BGA package. Each the screw screws through a corresponding leg from top to bottom. Each the screw screws the PCB board at a first side. The screw cap respectively corresponds to the screw and one leg. The screw cap caps and fixes a tail of its corresponding screw for affixing the PCB board. A height of the concave space is dynamically adjusted by adjusting a degree that the screw screws with the screw cap. Such that the concave space substantially clamps the BGA package. | 2021-02-04 |
20210035945 | SOLDERING A CONDUCTOR TO AN ALUMINUM LAYER - An arrangement is disclosed. In one example, the arrangement of a conductor and an aluminum layer soldered together comprises a substrate and the aluminum layer disposed over the substrate. The aluminum forms a first bond metal. An intermetallic compound layer is disposed over the aluminum layer. A solder layer is disposed over the intermetallic compound layer, wherein the solder comprises a low melting majority component. The conductor is disposed over the solder layer, wherein the conductor has a soldering surface which comprises a second bond metal. The intermetallic compound comprises aluminum and the second bond metal and is predominantly free of the low melting majority component. | 2021-02-04 |
20210035946 | ADHESIVE BONDING COMPOSITION AND ELECTRONIC COMPONENTS PREPARED FROM THE SAME - A polymerizable composition includes at least one monomer, a photoinitiator capable of initiating polymerization of the monomer when exposed to light, and a phosphor capable of producing light when exposed to radiation (typically X-rays). The material is particularly suitable for bonding components at ambient temperature in situations where the bond joint is not accessible to an external light source. An associated method includes: placing a polymerizable adhesive composition, including a photoinitiator and energy converting material, such as a down-converting phosphor, in contact with at least two components to be bonded to form an assembly; and, irradiating the assembly with radiation at a first wavelength, capable of conversion (down-conversion by the phosphor) to a second wavelength capable of activating the photoinitiator, to prepare items such as inkjet cartridges, wafer-to-wafer assemblies, semiconductors, integrated circuits, and the like. | 2021-02-04 |
20210035947 | METHOD AND DEVICE FOR COMPRESSION BONDING CHIP TO SUBSTRATE - Method and device for compression bonding are disclosed. During compression bonding a chip to a substrate, an anti-adhesion layer on a stage is provided to contact with a solder resist layer on the substrate. The solder resist layer will not stick to the anti-adhesion layer such that the reduction of bonding precision due to the solder resist layer remains residues on the compression bonding device is preventable. | 2021-02-04 |
20210035948 | Package-on-package Assembly With Wire Bond Vias - A microelectronic package includes a substrate having a first surface. A microelectronic element overlies the first surface. Electrically conductive elements are exposed at the first surface of the substrate, at least some of which are electrically connected to the microelectronic element. The package includes wire bonds having bases bonded to respective ones of the conductive elements and ends remote from the substrate and remote from the bases. The ends of the wire bonds are defined on tips of the wire bonds, and the wire bonds define respective first diameters between the bases and the tips thereof. The tips have at least one dimension that is smaller than the respective first diameters of the wire bonds. A dielectric encapsulation layer covers portions of the wire bonds, and unencapsulated portions of the wire bonds are defined by portions of the wire bonds, including the ends, are uncovered by the encapsulation layer. | 2021-02-04 |
20210035949 | PACKAGE STRUCTURE, ASSEMBLY STRUCTURE AND METHOD FOR MANUFACTURING THE SAME - A package structure includes a plurality of lower elements, a reinforcement structure and an encapsulant. The lower elements are disposed side by side. The reinforcement structure surrounds the lower elements. The encapsulant covers the lower elements and the reinforcement structure. The electrical connectors of the lower elements are exposed from the encapsulant. | 2021-02-04 |
20210035950 | MICROELECTRONIC PACKAGES WITH HIGH INTEGRATION MICROELECTRONIC DICE STACK - A microelectronic package may include stacked microelectronic dice, wherein a first microelectronic die is attached to a microelectronic substrate, and a second microelectronic die is stacked over at least a portion of the first microelectronic die, wherein the microelectronic substrate includes a plurality of pillars extending therefrom, wherein the second microelectronic die includes a plurality of pillars extending therefrom in a mirror-image configuration to the plurality of microelectronic substrate pillars, and wherein the second microelectronic die pillars are attached to microelectronic substrate pillars with an attachment material. | 2021-02-04 |
20210035951 | DOUBLE-SIDED SUBSTRATE WITH CAVITIES FOR DIRECT DIE-TO-DIE INTERCONNECT - Embodiments include a package substrate and semiconductor packages. A package substrate includes a first cavity in a top surface, first conductive pads on a first surface of the first cavity, a second cavity in a bottom surface, second conductive pads on a second surface of the second cavity, where the first surface is above the second surface, and a third cavity in the first and second cavities, where the third cavity vertically extends from the top surface to the bottom surface. The third cavity overlaps a first portion of the first cavity and a second portion of the second cavity. The package substrate may include conductive lines coupled to the first and second conductive pads, a first die in the first cavity, a second die in the second cavity, and interconnects in the third cavity that directly couple first die to the second die. | 2021-02-04 |
20210035952 | MULTI-CHIP PACKAGE - A multi-chip package including a first integrated circuit and a second integrated circuit. The first integrated circuit includes a first side having a first conductive layer, a second side having a second conductive layer, and an edge, the first conductive layer coupled to the second conductive layer at a location adjacent to the edge. The second integrated circuit is coupled to the second conductive layer of the first integrated circuit. | 2021-02-04 |
20210035953 | DEVICES EMPLOYING THERMAL AND MECHANICAL ENHANCED LAYERS AND METHODS OF FORMING SAME - A method includes attaching a first-level device die to a dummy die, encapsulating the first-level device die in a first encapsulating material, forming through-vias over and electrically coupled to the first-level device die, attaching a second-level device die over the first-level device die, and encapsulating the through-vias and the second-level device die in a second encapsulating material. Redistribution lines are formed over and electrically coupled to the through-vias and the second-level device die. The dummy die, the first-level device die, the first encapsulating material, the second-level device die, and the second encapsulating material form parts of a composite wafer. | 2021-02-04 |
20210035954 | CAPACITIVE COUPLING IN A DIRECT-BONDED INTERFACE FOR MICROELECTRONIC DEVICES - Capacitive couplings in a direct-bonded interface for microelectronic devices are provided. In an implementation, a microelectronic device includes a first die and a second die direct-bonded together at a bonding interface, a conductive interconnect between the first die and the second die formed at the bonding interface by a metal-to-metal direct bond, and a capacitive interconnect between the first die and the second die formed at the bonding interface. A direct bonding process creates a direct bond between dielectric surfaces of two dies, a direct bond between respective conductive interconnects of the two dies, and a capacitive coupling between the two dies at the bonding interface. In an implementation, a capacitive coupling of each signal line at the bonding interface comprises a dielectric material forming a capacitor at the bonding interface for each signal line. The capacitive couplings result from the same direct bonding process that creates the conductive interconnects direct-bonded together at the same bonding interface. | 2021-02-04 |
20210035955 | STACKING INTEGRATED CIRCUITS CONTAINING SERIALIZER AND DESERIALIZER BLOCKS USING THROUGH VIA - Methods and systems for stacking multiple chips with high speed serializer/deserializer blocks are presented. These methods make use of Through Via (TV) to connect the dice to each other, and to the external pads. The methods enable efficient multilayer stacking that simplifies design and manufacturing, and at the same time, ensure high speed operation of serializer/deserializer blocks, using the TVs. | 2021-02-04 |
20210035956 | LOW STRESS ASYMMETRIC DUAL SIDE MODULE - Implementations of semiconductor packages may include: a first substrate having two or more die coupled to a first side, a clip coupled to each of the two or more die on the first substrate and a second substrate having two or more die coupled to a first side of the second substrate. A clip may be coupled to each of the two or more die on the second substrate. The package may include two or more spacers coupled to the first side of the first substrate and a lead frame between the first substrate and the second substrate and a molding compound. A second side of each of the first substrate and the second substrate may be exposed through the molding compound. A perimeter of the first substrate and a perimeter of the second substrate may not fully overlap when coupled through the two or more spacers. | 2021-02-04 |
20210035957 | MULTIMEDIA DEVICE HAVING A PIXEL ARRAY AND METHOD FOR MANUFACTURING THE MULTIMEDIA DEVICE - A multimedia device has a multimedia substrate, a magnetic substrate and a pixel array. The multimedia substrate has a magnetic induction portion and a cavity portion. The magnetic substrate is disposed under the cavity portion of the multimedia substrate. The pixel array is disposed on the multimedia substrate. At least an active switching element of the pixel array is electrically connected to the magnetic induction portion of the multimedia substrate and at least a display medium module of the pixel array. The magnetic induction portion changes its current to generate a force of attraction and repulsion so as to vibrate the multimedia substrate and/or the magnetic substrate to generate sound. | 2021-02-04 |
20210035958 | MICRO LIGHT-EMITTING DIODE TRANSPARENT DISPLAY - A micro light-emitting diode transparent display including a transparent substrate is provided. N pixels are defined on the transparent substrate. N sets of micro light-emitting diodes are on the transparent substrate and respectively located in the N pixels. A wall portion is on the transparent substrate and surrounding one of the N sets of the micro light-emitting diodes to form an enclosed region on the transparent substrate. A length of a periphery of the enclosed region is equal to or smaller than 85% of a length of an outer periphery of one of the N pixels in which said one of the N sets of the micro light-emitting diodes is located. An area of said one of the N pixels outside the enclosed region allows light to directly pass through the micro light-emitting diode transparent display. | 2021-02-04 |
20210035959 | DISPLAY PANEL AND DISPLAY DEVICE - The present invention provides a display panel and a display device. Multiple florescence film units are placed on a diffusion plate and arranged spaced apart in an array corresponding to light-emitting-diode (LED) chips. Accordingly, a portion of blue light emitted by the LED chips does not pass through the florescence film units and compensates for a yellowish color of partial light. Therefore, a “yellow edge” problem at boundaries of different areas is improved, color distortion is avoided, and high color reproduction and high contrast displays are achieved. Moreover, a thickness of the fluorescent film unit is thinner than that of a conventional fluorescent film, which is conducive to thinning of the display panel. | 2021-02-04 |
20210035960 | LIGHT-EMITTING DEVICE ARRAY WITH INDIVIDUAL CELLS - A light-emitting device and a method for manufacturing the light-emitting device is disclosed. Such a light-emitting device comprises a substrate, a plurality of cells disposed on the substrate, and a plurality of semiconductor dice, wherein each of the plurality of cells accommodates at least one of the plurality of dice. Each of the plurality of cells may be filled with an encapsulant, phosphor or a mixture of an encapsulant with phosphor to control light characteristics of the light-emitting device. In an alternative aspect, cells may be filled with an encapsulant, and comprise a transparent cover coated with or filled with phosphors to control light characteristics of the light-emitting device. | 2021-02-04 |
20210035961 | SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING SEMICONDUCTOR DEVICE - In one example, a semiconductor structure comprises a redistribution structure comprising a conductive structure, a cavity substrate on a top side of the redistribution structure and having a cavity and a pillar contacting the redistribution structure, an electronic component on the top surface of the redistribution structure and in the cavity, wherein the electronic component is electrically coupled with the conductive structure, and an encapsulant in the cavity and on the top side of the redistribution structure, contacting a lateral side of the electronic component, a lateral side of the cavity, and a lateral side of the pillar. Other examples and related methods are also disclosed herein. | 2021-02-04 |
20210035962 | LIGHT EMITTING ELEMENT AND DISPLAY DEVICE INCLUDING THE SAME AND METHOD FOR MANUFACTURING DISPLAY DEVICE - Provided is a light emitting element according to embodiments which includes a body including a semiconductor layer and an active layer, and a ligand including a head portion bonded to a surface of the body, an end portion spaced apart from the body, and having a positive or a negative charge, and a chain portion connecting the head portion and the end portion. | 2021-02-04 |
20210035963 | METHOD AND APPARATUS FOR MANUFACTURING FLEXIBLE LIGHT-EMITTING DEVICE - According to a flexible light-emitting device production method of the present disclosure, after an intermediate region ( | 2021-02-04 |
20210035964 | DYNAMIC RANDOM ACCESS MEMORY DEVICE - A dynamic random access memory (DRAM) device is provided. The DRAM device includes a circuit substrate, a light emitting element, a first light-permeable thermal dissipation element, and a first light blocking element. At least one DRAM chip is disposed on the circuit substrate. The light emitting element is disposed on the circuit substrate and coupled to the circuit substrate. The first light-permeable thermal dissipation element is disposed on the circuit substrate. The first light blocking element is disposed between the first light-permeable thermal dissipation element and the circuit substrate, and the first light blocking element is disposed on the first light-permeable thermal dissipation element. | 2021-02-04 |
20210035965 | BONDED THREE-DIMENSIONAL MEMORY DEVICES AND METHODS OF MAKING THE SAME BY REPLACING CARRIER SUBSTRATE WITH SOURCE LAYER - A three-dimensional memory device includes an alternating stack of insulating layers and electrically conductive layers located over a carrier substrate. Memory stack structures vertically extend through the alternating stack. Each memory stack structure includes a respective vertical semiconductor channel and a respective memory film. The memory die can be bonded to a logic die containing peripheral circuitry for supporting operations of memory cells within the memory die. A distal end of each of the vertical semiconductor channels is physically exposed by removing the carrier substrate. A source layer is formed directly on the distal end each of the vertical semiconductor channels. A source power supply network can be formed on the backside of the source layer. | 2021-02-04 |
20210035966 | Fan-Out Package with Cavity Substrate - Structures and methods of forming fan-out packages are provided. The packages described herein may include a cavity substrate, one or more semiconductor devices located in a cavity of the cavity substrate, and one or more redistribution structures. Embodiments include a cavity preformed in a cavity substrate. Various devices, such as integrated circuit dies, packages, or the like, may be placed in the cavity. Redistribution structures may also be formed. | 2021-02-04 |
20210035967 | HIGHLY REGULAR LOGIC DESIGN FOR EFFICIENT 3D INTEGRATION - An integrated circuit includes an array of unit cells, each unit cell of which including field effect transistors arranged in a stack. Local interconnect structures form select conductive paths between select terminals of the field effect transistors to define cell circuitry that is confined within each unit cell. An array of contacts is disposed on an accessible surface of the unit cell, where each contact is electrically coupled to a corresponding electrical node of the cell circuitry. | 2021-02-04 |
20210035968 | APPARATUS WITH A CURRENT-GAIN LAYOUT - An apparatus including separate first and second active regions that are physically separate, with each region including one or more sets of doped regions that each define a current channel. The current channels on the first and second active regions are activated by a common gate signal. | 2021-02-04 |
20210035969 | HIGH-VOLTAGE CIRCUITRY DEVICE AND RING CIRCUITRY LAYOUT THEREOF - A high-voltage circuitry device is provided. The high-voltage circuitry device includes a high-voltage transistor, a protection component and a feedback component. The high-voltage transistor has a gate, a drain and a source. The protection component is coupled between the source of the high-voltage transistor and the ground. When a current corresponding to an electrostatic discharge (ESD) event flows through the drain of the high-voltage transistor, the current flows from the drain of the high-voltage transistor to the ground through the high-voltage transistor and the protection component. The feedback component is coupled between the protection component, the ground and the gate of the high-voltage transistor. When the ESD event occurs, the feedback component enables the high-voltage transistor to stay on a turned-on state to pass the current. | 2021-02-04 |
20210035970 | SEMICONDUCTOR DISCHARGE PROTECTION DEVICE WITH DIODE AND SILICON CONTROLLED RECTIFIER ARRANGEMENTS - Aspects of the present disclosure include one or more semiconductor electrostatic discharge protection devices. At least one embodiment includes a semiconductor electrostatic discharge device with one or more fingers divided into two segments with alternating p-diffusion and n-diffusion regions, with each region being associated with at least one of a portion of a diode and/or silicon-controlled rectifier (SCR). | 2021-02-04 |
20210035971 | SEMICONDUCTOR DEVICE AND METHOD OF FABRICATING THE SAME - Disclosed are a semiconductor device and a method of fabricating the same. The semiconductor device includes first and second gate patterns that are spaced apart from each other in a first direction on a substrate and extend in the first direction, a separation pattern that is disposed between and being in direct contact with the first and second gate patterns and extends in a second direction intersecting the first direction, a third gate pattern that is spaced apart in the second direction from the first gate pattern and extends in the first direction, and an interlayer dielectric layer disposed between the first gate pattern and the third gate pattern. The separation pattern includes a material different from a material of the interlayer dielectric layer. A bottom surface of the separation pattern has an uneven structure. | 2021-02-04 |
20210035972 | FIN END PLUG STRUCTURES FOR ADVANCED INTEGRATED CIRCUIT STRUCTURE FABRICATION - Embodiments of the disclosure are in the field of advanced integrated circuit structure fabrication and, in particular, 10 nanometer node and smaller integrated circuit structure fabrication and the resulting structures. In an example, an integrated circuit structure includes a first isolation structure over a first end of a fin. A gate structure is over the fin and is spaced apart from the first isolation structure along the direction. A second isolation structure is over a second end of the fin, the second end opposite the first end. The second isolation structure is spaced apart from the gate structure. The first isolation structure and the second isolation structure both comprise a first dielectric material laterally surrounding a recessed second dielectric material distinct from the first dielectric material. The recessed second dielectric material laterally surrounds at least a portion of a third dielectric material different from the first and second dielectric materials. | 2021-02-04 |
20210035973 | S-Contact for SOI - Systems, methods, and apparatus for an improved protection from charge injection into layers of a device using resistive structures are described. Such resistive structures, named s-contacts, can be made using simpler fabrication methods and less fabrication steps. In a case of metal-oxide-semiconductor (MOS) field effect transistors (FETs), s-contacts can be made with direct connection, or resistive connection, to all regions of the transistors, including the source region, the drain region and the gate. | 2021-02-04 |
20210035974 | HVMOS Reliability Evaluation using Bulk Resistances as Indices - A method of determining the reliability of a high-voltage PMOS (HVPMOS) device includes determining a bulk resistance of the HVPMOS device, and evaluating the reliability of the HVPMOS device based on the bulk resistance. | 2021-02-04 |
20210035975 | SEMICONDUCTOR DEVICES - A semiconductor device includes a first transistor, a division pattern, and a second transistor sequentially stacked on a substrate. The first transistor includes a first gate structure, a first source/drain layer at each of opposite sides of the first gate structure, and first semiconductor patterns spaced apart from each other in a vertical direction. Each of the first semiconductor patterns extends through the first gate structure and contacts the first source/drain layer. The division pattern includes an insulating material. The second transistor includes a second gate structure, a second source/drain layer at each of opposite sides of the second gate structure, and second semiconductor patterns spaced apart from each other in the vertical direction. Each of the second semiconductor patterns extends through the second gate structure and contacts the second source/drain layer. The first source/drain layer does not directly contact the second source/drain layer. | 2021-02-04 |
20210035976 | SEMICONDUCTOR DEVICE - A semiconductor device includes a substrate, a first lower pattern and a second lower pattern on the substrate and arranged in a line in a first direction, a first active pattern stack disposed on and spaced apart from the first lower pattern, a second active pattern stack disposed on and spaced apart from the first lower pattern, a fin-cut gate structure disposed on the first lower pattern and overlapping a portion of the first lower pattern, a first gate structure surrounding the first active pattern stack and extending in a second direction crossing the first direction, a second gate structure surrounding the second active pattern stack and extending in the second direction, and a device isolation layer between the first gate structure and the second gate structure and separating the first lower pattern and the second lower pattern. | 2021-02-04 |