| 05th week of 2016 patent applcation highlights part 64 |
| Patent application number | Title | Published |
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| 20160035857 | EXTENDED CONTACT AREA USING UNDERCUT SILICIDE EXTENSIONS - The present invention relates generally to semiconductor devices and more particularly, to a structure and method of forming a contact silicide on a source-drain (S-D) region of a field effect transistor (FET) having extensions by using an undercut etch and a salicide process. A method of forming a contact silicide extension is disclosed. The method may include: forming an undercut region below a dielectric layer and above a source-drain region, the undercut region located directly below a bottom of a contact trench and extending below the dielectric layer to a gate spacer formed on a sidewall of a gate stack; and forming a contact silicide in the undercut region, the contact silicide in direct contact with the source-drain region. | 2016-02-04 |
| 20160035858 | FINFET HAVING HIGHLY DOPED SOURCE AND DRAIN REGIONS - A method of forming a semiconductor device that includes forming an in-situ doped semiconductor material on a semiconductor substrate, and forming fin structures from the in-situ doped semiconductor material. A sacrificial channel portion of the fin structures may be removed, wherein a source region and a drain region portion of the fin structures of the in-situ doped semiconductor material remain. The sacrificial channel portion of the fin structure may then be replaced with a functional channel region. | 2016-02-04 |
| 20160035859 | IGBT AND METHOD OF MANUFACTURING THE SAME - An IGBT has an emitter region, a top body region that is formed below the emitter region, a floating region that is formed below the top body region, a bottom body region that is formed below the floating region, a trench, a gate insulating film that covers an inner face of the trench, and a gate electrode that is arranged inside the trench. When a distribution of a concentration of p-type impurities in the top body region and the floating region, which are located below the emitter region, is viewed along a thickness direction of a semiconductor substrate, the concentration of the p-type impurities decreases as a downward distance increases from an upper end of the top body region that is located below the emitter region, and assumes a local minimum value at a predetermined depth in the floating region. | 2016-02-04 |
| 20160035860 | CONTACT TECHNIQUES AND CONFIGURATIONS FOR REDUCING PARASITIC RESISTANCE IN NANOWIRE TRANSISTORS - Embodiments of the present disclosure provide contact techniques and configurations for reducing parasitic resistance in nanowire transistors. In one embodiment, an apparatus includes a semiconductor substrate, an isolation layer formed on the semiconductor substrate, a channel layer including nano-wire material formed on the isolation layer to provide a channel for a transistor, and a contact coupled with the channel layer, the contact being configured to surround, in at least one planar dimension, nanowire material of the channel layer and to provide a source terminal or drain terminal for the transistor. | 2016-02-04 |
| 20160035861 | METHODS OF MANUFACTURING SEMICONDUCTOR DEVICES - In a method of manufacturing a semiconductor device, a dummy gate structure is formed on a substrate. A first spacer layer is formed on the substrate to cover the dummy gate structure. A nitridation process is performed on the first spacer layer. An upper portion of the substrate adjacent to the dummy gate structure is removed to form a trench. An inner wall of the trench is cleaned. An epitaxial layer is formed to fill the trench. The dummy gate structure is replaced with a gate structure. | 2016-02-04 |
| 20160035862 | FIELD PLATE TRENCH TRANSISTOR AND METHOD FOR PRODUCING IT - A field plate trench transistor having a semiconductor body. In one embodiment the semiconductor has a trench structure and an electrode structure embedded in the trench structure. The electrode structure being electrically insulated from the semiconductor body by an insulation structure and having a gate electrode structure and a field electrode structure. The field plate trench transistor has a voltage divider configured such that the field electrode structure is set to a potential lying between source and drain potentials. | 2016-02-04 |
| 20160035863 | METHODS OF FORMING STRESSED CHANNEL REGIONS FOR A FINFET SEMICONDUCTOR DEVICE AND THE RESULTING DEVICE - An illustrative method includes forming a FinFET device above structure comprising a semiconductor substrate, a first epi semiconductor material and a second epi semiconductor material that includes forming an initial fin structure that comprises portions of the semiconductor substrate, the first epi material and the second epi material, recessing a layer of insulating material such that a portion, but not all, of the second epi material portion of the initial fin structure is exposed so as to define a final fin structure, forming a gate structure above and around the final fin structure, removing the first epi material of the initial fin structure and thereby define an under-fin cavity under the final fin structure and substantially filling the under-fin cavity with a stressed material. | 2016-02-04 |
| 20160035864 | FIN END SPACER FOR PREVENTING MERGER OF RAISED ACTIVE REGIONS - After formation of gate structures over semiconductor fins and prior to formation of raised active regions, a directional ion beam is employed to form a dielectric material portion on end walls of semiconductor fins that are perpendicular to the lengthwise direction of the semiconductor fins. The angle of the directional ion beam is selected to be with a vertical plane including the lengthwise direction of the semiconductor fins, thereby avoiding formation of the dielectric material portion on lengthwise sidewalls of the semiconductor fins. Selective epitaxy of semiconductor material is performed to grow raised active regions from sidewall surfaces of the semiconductor fins. Optionally, horizontal portions of the dielectric material portion may be removed prior to the selective epitaxy process. Further, the dielectric material portion may optionally be removed after the selective epitaxy process. | 2016-02-04 |
| 20160035865 | METHOD OF MANUFACTURING SEMICONDUCTOR DEVICE - A first conductor is formed over a substrate. A first insulator is formed over the first conductor. A second insulator including aluminum oxide is formed over the first insulator. A third insulator is formed in contact with a top surface of the second insulator. A first opening portion reaching the first conductor is provided in the first to third insulators. A second conductor is formed over the third insulator and in the first opening portion. A third conductor is formed in the first opening portion by removing part of the second conductor over the third insulator so that a surface of the third conductor is parallel to a bottom surface of the substrate. A first transistor including an oxide semiconductor is formed over the third insulator. | 2016-02-04 |
| 20160035866 | SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD THEREOF - An object is to provide a thin film transistor using an oxide semiconductor layer, in which contact resistance between the oxide semiconductor layer and source and drain electrode layers is reduced and electric characteristics are stabilized. Another object is to provide a method for manufacturing the thin film transistor. A thin film transistor using an oxide semiconductor layer is formed in such a manner that buffer layers having higher conductivity than the oxide semiconductor layer are formed over the oxide semiconductor layer, source and drain electrode layers are formed over the buffer layers, and the oxide semiconductor layer is electrically connected to the source and drain electrode layers with the buffer layers interposed therebetween. In addition, the buffer layers are subjected to reverse sputtering treatment and heat treatment in a nitrogen atmosphere, whereby the buffer layers having higher conductivity than the oxide semiconductor layer are obtained. | 2016-02-04 |
| 20160035867 | Reverse-Conducting IGBT - A reverse-conducting IGBT includes a semiconductor body having a drift region arranged between first and second surfaces. The semiconductor body further includes first collector regions arranged at the second surface and in Ohmic contact with a second electrode, backside emitter regions and in Ohmic contact with the second electrode. In a horizontal direction substantially parallel to the first surface, the first collector regions and backside emitter regions define an rc-IGBT area. The semiconductor body further includes a second collector region of the second conductivity type arranged at the second surface and in Ohmic contact with the second electrode. The second collector region defines in the horizontal direction a pilot-IGBT area. The rc-IGBT area includes first semiconductor regions in Ohmic contact with the first electrode and arranged between the drift region and first electrode. The pilot-IGBT area includes second semiconductor regions of the same conductivity type as the first semiconductor regions. | 2016-02-04 |
| 20160035868 | SEMICONDUCTOR DEVICE AND SEMICONDUCTOR DEVICE MANUFACTURING METHOD - A semiconductor device and manufacturing method achieve miniaturization, prevent rise in threshold voltage and on-state voltage, and prevent decrease in breakdown resistance. N | 2016-02-04 |
| 20160035869 | SEMICONDUCTOR DEVICE - A semiconductor device formed on a substrate of a first conductivity type, including a base layer of a second conductivity disposed on a first face of the substrate, an anode layer with a higher dopant amount in a portion of the base layer, an IGBT region formed on the base layer, a diode region formed on the anode layer, a trench extending from the top of the IGBT and diode regions in to the substrate. The area occupied by the diode region is different from the area occupied by the IGBT region, but they share collector and emitter electrodes. The contact area between the diode anode layer and the emitter electrode may be adjusted by the arrangement of trenches. | 2016-02-04 |
| 20160035870 | HIGH VOLTAGE GAN TRANSISTOR - A multiple field plate transistor includes an active region, with a source, a drain, and a gate. A first spacer layer is over the active region between the source and the gate and a second spacer layer over the active region between the drain and the gate. A first field plate on the first spacer layer is connected to the gate. A second field plate on the second spacer layer is connected to the gate. A third spacer layer is on the first spacer layer, the second spacer layer, the first field plate, the gate, and the second field plate, with a third field plate on the third spacer layer and connected to the source. The transistor exhibits a blocking voltage of at least 600 Volts while supporting a current of at least 2 Amps with an on resistance of no more than 5.0 mΩ-cm | 2016-02-04 |
| 20160035871 | Lateral/Vertical Semiconductor Device - A lateral semiconductor device and/or design including a space-charge generating layer and a set of electrodes located on an opposite side of a device channel as contacts to the device channel is provided. The space-charge generating layer is configured to form a space-charge region to at least partially deplete the device channel in response to an operating voltage being applied to the contacts to the device channel. | 2016-02-04 |
| 20160035872 | METHOD FOR THE FORMATION OF SILICON AND SILICON-GERMANIUM FIN STRUCTURES FOR FINFET DEVICES - A substrate layer formed of a first semiconductor material includes adjacent first and second regions. Fin structures are formed from the substrate layer in both the first and second regions. At least the side walls of the fin structures in the second region are covered with an epitaxially grown layer of second semiconductor material. A drive in process is performed to convert the fin structures in the second region from the first semiconductor material to the second semiconductor material. The first semiconductor material is, for example, silicon, and the second semiconductor material is, for example, silicon germanium or silicon carbide. The fin structures in the first region are provided for a FinFET of a first (for example, n-channel) conductivity type while the fin structures in the second region are provided for a FinFET of a second (for example, p-channel) conductivity type. | 2016-02-04 |
| 20160035873 | FINFET WITH STRESSORS - A fin type transistor includes a dielectric layer on a substrate surface which serves to isolate the gate of the transistor from the substrate. The dielectric layer includes a non-selectively etched surface to produce top portions of fin structures which have reduced height variations across the wafer. The fin type transistor may also include a buried stressor and/or raised or embedded raised S/D stressors to cause a strain in the channel to improve carrier mobility. | 2016-02-04 |
| 20160035874 | FINFET DEVICE - A fin-type field-effect transistor (FinFET) device includes a plurality of fins formed over a substrate. The semiconductor device further includes a dielectric layer filled in a space between each fin and over a first portion of the plurality of fins and a dielectric trench formed in the dielectric layer. The dielectric trench has a vertical profile. The semiconductor device further includes a second portion of the plurality of fins recessed and exposed in the dielectric trench. The second portion of the plurality of fins have a rounded-convex-shape top profile. | 2016-02-04 |
| 20160035875 | FIN END SPACER FOR PREVENTING MERGER OF RAISED ACTIVE REGIONS - After formation of gate structures over semiconductor fins and prior to formation of raised active regions, a directional ion beam is employed to form a dielectric material portion on end walls of semiconductor fins that are perpendicular to the lengthwise direction of the semiconductor fins. The angle of the directional ion beam is selected to be with a vertical plane including the lengthwise direction of the semiconductor fins, thereby avoiding formation of the dielectric material portion on lengthwise sidewalls of the semiconductor fins. Selective epitaxy of semiconductor material is performed to grow raised active regions from sidewall surfaces of the semiconductor fins. Optionally, horizontal portions of the dielectric material portion may be removed prior to the selective epitaxy process. Further, the dielectric material portion may optionally be removed after the selective epitaxy process. | 2016-02-04 |
| 20160035876 | FIN END SPACER FOR PREVENTING MERGER OF RAISED ACTIVE REGIONS - After formation of gate structures over semiconductor fins and prior to formation of raised active regions, a directional ion beam is employed to form a dielectric material portion on end walls of semiconductor fins that are perpendicular to the lengthwise direction of the semiconductor fins. The angle of the directional ion beam is selected to be with a vertical plane including the lengthwise direction of the semiconductor fins, thereby avoiding formation of the dielectric material portion on lengthwise sidewalls of the semiconductor fins. Selective epitaxy of semiconductor material is performed to grow raised active regions from sidewall surfaces of the semiconductor fins. Optionally, horizontal portions of the dielectric material portion may be removed prior to the selective epitaxy process. Further, the dielectric material portion may optionally be removed after the selective epitaxy process. | 2016-02-04 |
| 20160035877 | FINFET HAVING HIGHLY DOPED SOURCE AND DRAIN REGIONS - A method of forming a semiconductor device that includes forming an in-situ doped semiconductor material on a semiconductor substrate, and forming fin structures from the in-situ doped semiconductor material. A sacrificial channel portion of the fin structures may be removed, wherein a source region and a drain region portion of the fin structures of the in-situ doped semiconductor material remain. The sacrificial channel portion of the fin structure may then be replaced with a functional channel region. | 2016-02-04 |
| 20160035878 | FINFET WITH DIELECTRIC ISOLATION AFTER GATE MODULE FOR IMPROVED SOURCE AND DRAIN REGION EPITAXIAL GROWTH - A method forming a semiconductor device that in one embodiment includes forming a gate structure on a channel region of fin structures, and forming a flowable dielectric material on a source region portion and a drain region portion of the fin structures. The flowable dielectric material is present at least between adjacent fin structures of the plurality of fin structures filling a space between the adjacent fin structures. An upper surface of the source region portion and the drain region portion of fin structures is exposed. An epitaxial semiconductor material is formed on the upper surface of the source region portion and the drain region portion of the fin structures. | 2016-02-04 |
| 20160035879 | SEMICONDUCTOR DEVICE - In general, according to one embodiment, a semiconductor device includes, a first semiconductor region, a plurality of second semiconductor regions, a plurality of third semiconductor regions, a fourth semiconductor region, a fifth semiconductor region, and a gate electrode. The third semiconductor region includes a first portion and a second portion. The first portion is provided between the second semiconductor regions adjacent to each other. An amount of impurity of the second conductivity type in the first portion is greater than an amount of impurity of the first conductivity type in the second semiconductor region contiguous to the first portion. The second portion is arranged with a part of the first semiconductor region. An amount of impurity of the second conductivity type in the second portion is smaller than an amount of impurity of the first conductivity type in the part of the first semiconductor region. | 2016-02-04 |
| 20160035880 | POWER MOSFET, AN IGBT, AND A POWER DIODE - Super-junction MOSFETs by trench fill system requires void-free filling epitaxial growth. This may require alignment of plane orientations of trenches in a given direction. Particularly, when column layout at chip corner part is bilaterally asymmetrical with a diagonal line between chip corners, equipotential lines in a blocking state are curved at corner parts due to column asymmetry at chip corner. This tends to cause points where equipotential lines become dense, which may cause breakdown voltage reduction. In the present invention, in power type semiconductor active elements such as power MOSFETs, a ring-shaped field plate is disposed in chip peripheral regions around an active cell region, etc., assuming a nearly rectangular shape. The field plate has an ohmic-contact part in at least a part of the portion along the side of the rectangle. However, in the portion corresponding to the corner part of the rectangle, an ohmic-contact part is not disposed. | 2016-02-04 |
| 20160035881 | SEMICONDUCTOR DEVICE AND METHOD FOR MANUFACTURING THE SAME - A super junction MOSFET includes a parallel pn layer including a plurality of pn junctions and in which an n-type drift region and a p-type partition region interposed between the pn junctions are alternately arranged and contact each other, a MOS gate structure on the surface of the parallel pn layer, and an n-type buffer layer in contact with an opposite main surface. The impurity concentration of the buffer layer is equal to or less than that of the n-type drift region. At least one of the p-type partition regions in the parallel pn layer is replaced with an n | 2016-02-04 |
| 20160035882 | MULTIPLE SEMICONDUCTOR DEVICE TRENCHES PER CELL PITCH - A semiconductor device includes a plurality of field plate trenches formed in a semiconductor substrate, a plurality of gate trenches formed in the semiconductor substrate and spaced apart from the field plate trenches, and a plurality of device cells having a cell pitch defined by a distance from one side of a field plate trench to the same side of an adjacent field plate trench. Each device cell includes a first doped region of a first conductivity type and a second doped region of a second conductivity type adjacent the first doped region in a part of the semiconductor substrate disposed between the adjacent field plate trenches that define the cell pitch. At least some of the device cells have more than one gate trench per cell pitch. | 2016-02-04 |
| 20160035883 | REDUCTION OF DEGRADATION DUE TO HOT CARRIER INJECTION - In a general aspect, a high-voltage metal-oxide-semiconductor (HVMOS) device can include comprising a first gate dielectric layer disposed on a channel region of the HVMOS device and a second gate dielectric layer disposed on at least a portion of a drift region of the HVMOS device. The drift region can be disposed laterally adjacent to the channel region. The second gate dielectric layer can have a thickness that is greater than a thickness of the first gate dielectric layer. | 2016-02-04 |
| 20160035884 | SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING THE SAME - A semiconductor device includes a semiconductor substrate, and a P-well and an N-type drift region disposed in the semiconductor substrate. The P-well includes a lower well region and an upper well region disposed above the lower well region. The lower well region includes a first surface that is near the N-type drift region, and the upper well region includes a second surface that is near the N-type drift region. A distance from the first surface of the lower well region to the N-type drift region is greater than a distance from the second surface of the upper well region to the N-type drift region. | 2016-02-04 |
| 20160035885 | N-CHANNEL DOUBLE DIFFUSION MOS TRANSISTOR, AND SEMICONDUCTOR COMPOSITE DEVICE - A MOS transistor includes a p-type semiconductor substrate, a p-type epitaxial layer, and an n-type buried layer provided in a boundary between the semiconductor substrate and the epitaxial layer. In a p-type body layer provided in a surface portion of the epitaxial layer, an n-type source layer is provided to define a double diffusion structure together with the p-type body layer. An n-type drift layer is provided in a surface portion of the epitaxial layer in spaced relation from the body layer. An n-type drain layer is provided in a surface portion of the epitaxial layer in contact with the n-type drift layer. A p-type buried layer having a lower impurity concentration than the n-type buried layer is buried in the epitaxial layer between the drift layer and the n-type buried layer in contact with an upper surface of the n-type buried layer. | 2016-02-04 |
| 20160035886 | SEMICONDUCTOR DEVICE AND FORMATION THEREOF - A semiconductor device and method of formation are provided. The semiconductor device includes a first active region adjacent a channel, the channel, and a second active region adjacent the channel. The channel has a channel doping profile. The channel includes a central channel portion having a first dopant concentration of a first dopant and a radial channel portion surrounding the central channel portion. The radial channel portion has a second dopant concentration of a second dopant greater than the first dopant concentration. The channel comprising the central channel portion and the radial channel portion has increased voltage threshold tuning as compared to a channel that lacks a central channel portion and a radial channel portion. | 2016-02-04 |
| 20160035887 | SEMICONDUCTOR DEVICE AND MULTIPLE GATE FIELD EFFECT TRANSISTOR - The present invention provides a semiconductor device, which includes a substrate, a first gate electrode, a second gate electrode, a source region and a drain region, wherein the first gate electrode and the second gate electrode are embedded in the substrate respectively; the source region is formed in the substrate, and at least a portion of the source region is disposed between the first gate electrode and the second gate electrode; and the drain region is formed in the substrate, and at least a portion of the drain region is disposed between the first gate electrode and the second gate electrode. | 2016-02-04 |
| 20160035888 | JUNCTION FET SEMICONDUCTOR DEVICE WITH DUMMY MASK STRUCTURES FOR IMPROVED DIMENSION CONTROL AND METHOD FOR FORMING THE SAME - A method for semiconductor devices on a substrate includes using gate structures which serve as active gate structures in a MOSFET region, as dummy gate structures in a JFET region of the device. The dummy gate electrodes are used as masks and determine the spacing between gate regions and source/drain regions, the width of the gate regions, and the spacing between adjacent gate regions according to some embodiments, thereby forming an accurately dimensioned transistor channel. | 2016-02-04 |
| 20160035889 | STRIP-SHAPED GATE TUNNELING FIELD EFFECT TRANSISTOR USING COMPOSITE MECHANISM AND FABRICATION METHOD THEREOF - The present invention discloses a strip-shaped gate tunneling field effect transistor using composite mechanism and a fabrication method thereof, which belongs to a field of field effect transistor logic devices and circuits in the CMOS ultra large scale integrated circuit (ULSI). According to the tunneling field effect transistor, the energy band of the channel underneath the gate is elevated by means of a change of the gate morphology and the PN junction depletion effect occurred at both sides of the strip-shaped gate, so that the sub-threshold characteristics of the transistor are improved. Meanwhile, the on-state current of the transistor is effectively increased by means of the composite mechanism introduced by the two parts of the doped source region. Moreover, the bulk leakage current, including a source-to-drain direct tunneling current and a punching through current, which comes from the two parts of the doped source region to the doped drain region can be greatly suppressed through the design of the ‘ | 2016-02-04 |
| 20160035890 | LOW COST DEMOS TRANSISTOR WITH IMPROVED CHC IMMUNITY - An integrated circuit and method includes a DEMOS transistor with improved CHC reliability that has a lower resistance surface channel under the DEMOS gate that transitions to a lower resistance subsurface channel under the drain edge of the DEMOS transistor gate. | 2016-02-04 |
| 20160035891 | STRESS IN N-CHANNEL FIELD EFFECT TRANSISTORS - A fin field-effect transistor (FinFET) includes a gate stack on a surface of a semiconductor fin. The semiconductor fin may include a capping material and a stressor material. The stressor material is confined by the capping material to a region proximate the gate stack. The stressor material provides stress on the semiconductor fin proximate the gate stack. | 2016-02-04 |
| 20160035892 | DISLOCATION STRESS MEMORIZATION TECHNIQUE (DSMT) ON EPITAXIAL CHANNEL DEVICES - The present disclosure relates to method of forming a transistor device having epitaxial source and drain regions with dislocation stress memorization (DSM) regions that provide stress to an epitaxial channel region, and an associated device. The method forms a first dislocation stress memorization (DSM) region and a second DSM region having stressed lattices within a substrate. The substrate is selectively etched to form a source cavity and a drain cavity extending from an upper surface of the substrate to positions contacting the first DSM region and the second DSM region. An epitaxial source is formed within the source cavity and an epitaxial drain region is formed within the drain cavity. A gate structure is formed over the substrate at a location laterally between the epitaxial source region and the epitaxial drain region. | 2016-02-04 |
| 20160035893 | PIXEL STRUCTURE AND MANUFACTURING METHOD THEREOF - A manufacturing method of a pixel structure is provided, which includes following steps. A gate and a gate insulating layer are formed on a substrate. A source and a drain are formed on the gate insulating layer. A first and a second semiconductor pattern are formed on the gate insulating layer. The first semiconductor pattern is located above the gate, wherein the first semiconductor pattern contacts the source and the drain. The second semiconductor pattern contacts the drain. A mask which exposes both sides of the first semiconductor pattern is formed on the first semiconductor pattern. A treatment procedure is performed, so that a first and a second conductive region are formed at both sides of the exposed first semiconductor pattern, and the second semiconductor pattern is formed into a pixel electrode pattern. The first semiconductor pattern which is covered by the mask is formed into a channel region. | 2016-02-04 |
| 20160035894 | OXIDE THIN FILM TRANSISTOR, ARRAY SUBSTRATE, METHODS OF MANUFACTURING THE SAME AND DISPLAY DEVICE - An oxide thin film transistor, an array substrate, methods of manufacturing the same and a display device are disclosed. The oxide thin film transistor includes: a base substrate; and a gate electrode, a gate insulating layer, an oxide active layer, drain/source electrodes sequentially disposed on the base substrate. The oxide TFT transistor further includes an ultraviolet barrier layer disposed on the oxide active layer, the ultraviolet barrier layer is made of a resin material contains an ultraviolet absorbent. The stability of the oxide TFT is enhanced by disposing the ultraviolet barrier layer over the oxide active layer of the oxide TFT, since the ultraviolet barrier layer blocks the impact of UV light on the oxide TFT. | 2016-02-04 |
| 20160035895 | OXIDE SEMICONDUCTOR TARGET, OXIDE SEMICONDUCTOR FILM AND METHOD FOR PRODUCING SAME, AND THIN FILM TRANSISTOR - The invention provides an oxide semiconductor target including an oxide sintered body including zinc, tin, oxygen, and aluminum in a content ratio of from 0.005% by mass to 0.2% by mass with respect to the total mass of the oxide sintered body, in which the content ratio of silicon to the total mass of the oxide sintered body is less than 0.03% by mass. | 2016-02-04 |
| 20160035896 | SEMICONDUCTOR DEVICE, MANUFACTURING METHOD THEREOF, AND ELECTRONIC DEVICE - A gate insulating film is formed over an oxide semiconductor film. A gate electrode is formed over the gate insulating film. An interlayer insulating film is formed over the oxide semiconductor film and the gate electrode. Planarization treatment is performed on the interlayer insulating film. An opening is formed in the interlayer insulating film subjected to the planarization treatment. A conductive film is formed in the opening and over the interlayer insulating film subjected to the planarization treatment. A pair of conductive films is formed by performing planarization treatment on the conductive film. A first region and a second region are formed in the oxide semiconductor film by adding an impurity to the pair of conductive films. The second region and the opening overlap with each other. The second region is formed by an impact caused by addition of the impurity to the pair of conductive films. | 2016-02-04 |
| 20160035897 | SEMICONDUCTOR DEVICE - A transistor whose channel is formed in a semiconductor having dielectric anisotropy is provided. A transistor having a small subthreshold swing value is provided. A transistor having normally-off electrical characteristics is provided. A transistor having a low leakage current in an off state is provided. A semiconductor device includes an insulator, a semiconductor, and a conductor. In the semiconductor device, the semiconductor includes a region overlapping with the conductor with the insulator positioned therebetween, and a dielectric constant of the region in a direction perpendicular to a top surface of the region is higher than a dielectric constant of the region in a direction parallel to the top surface. | 2016-02-04 |
| 20160035898 | SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD OF SEMICONDUCTOR DEVICE USING METAL OXIDE - A method of manufacturing a semiconductor device using a metal oxide includes forming a metal oxide layer on a substrate, forming an amorphous semiconductor layer on the metal oxide layer, and forming a polycrystalline semiconductor layer by crystallizing the amorphous semiconductor layer using the metal oxide layer. | 2016-02-04 |
| 20160035899 | BIASING A SILICON-ON-INSULATOR (SOI) SUBSTRATE TO ENHANCE A DEPLETION REGION - A device includes a silicon-on-insulator (SOI) substrate comprising a bulk silicon (Si) substrate, a buried oxide layer over the bulk Si substrate and a silicon device layer over the buried oxide layer, a first substrate tap and a second substrate tap located in the buried oxide layer and the silicon device layer, the first and second substrate taps in contact with the bulk Si substrate, and an initial depletion region located in the bulk Si substrate below the buried oxide layer and associated with at least one of the first substrate tap and the second substrate tap, the first substrate tap and the second substrate tap configured to increase the initial depletion region based on an applied bias voltage. | 2016-02-04 |
| 20160035900 | THIN FILM TRANSISTOR SUBSTRATE AND DISPLAY PANEL USING THE SAME - A thin film transistor includes a gate electrode, a semiconductor layer, a source electrode, a drain electrode, a first protective layer, and a second protective layer. The gate electrode is disposed on a substrate. The metal oxide semiconductor layer is disposed on a gate insulating layer and electrically connects the source electrode and the drain electrode. The first protective layer disposed on the metal oxide semiconductor layer has a first oxygen vacancy concentration. The second protective layer disposed on the first protective layer has a second oxygen vacancy concentration. A boundary area located between the first and second protective layers has a third oxygen vacancy concentration. The third oxygen vacancy concentration is respectively greater than the first oxygen vacancy concentration and the second oxygen vacancy concentration. | 2016-02-04 |
| 20160035901 | FABRICATING METHOD OF THIN FILM TRANSISTOR, THIN FILM TRANSISTOR AND DISPLAY PANEL - Embodiments of the invention provide a fabricating method a thin film transistor, a thin film transistor and a display panel, so as to improve carrier mobility in the polycrystalline silicon. The fabricating method a thin film transistor comprises following M | 2016-02-04 |
| 20160035902 | TRANSISTOR AND DISPLAY DEVICE - It is an object to manufacture a highly reliable display device using a thin film transistor having favorable electric characteristics and high reliability as a switching element. In a bottom gate thin film transistor including an amorphous oxide semiconductor, an oxide conductive layer having a crystal region is formed between an oxide semiconductor layer which has been dehydrated or dehydrogenated by heat treatment and each of a source electrode layer and a drain electrode layer which are formed using a metal material. Accordingly, contact resistance between the oxide semiconductor layer and each of the source electrode layer and the drain electrode layer can be reduced; thus, a thin film transistor having favorable electric characteristics and a highly reliable display device using the thin film transistor can be provided. | 2016-02-04 |
| 20160035903 | THIN-FILM TRANSISTOR - Thin-film transistor includes column-shaped protrusion portion having a side surface and protruding from a main surface of the substrate, a gate insulating layer including a first layer and a second layer, at least part of the gate insulating layer being in a channel region extending along the side surface, a gate electrode in contact with the gate insulating layer, a source electrode and a drain electrode isolated from one another, at least part of one of the source electrode and the drain electrode overlap the protrusion portion and the other being in a region that does not overlap the protrusion portion or the one electrode, and a semiconductor layer in contact with at least part of the source electrode, at least part of the drain electrode, and at least part of the gate insulating layer in the channel region directly or with a functional layer interposed. | 2016-02-04 |
| 20160035904 | VERTICAL-CHANNEL TYPE JUNCTION SIC POWER FET AND METHOD OF MANUFACTURING SAME - In order to secure the performance of a SiC-based JFET having an impurity diffusion rate lower than silicon-based one, a gate depth is secured while precisely controlling a distance between gate regions, instead of forming gate regions by ion implantation into the side wall of a trench. This means that a channel region defined by a gate distance and a gate depth should have a high aspect ratio. Further, due to limitations of process, a gate region is formed within a source region. Formation of a highly doped PN junction between source and gate regions causes various problems such as inevitable increase in junction current. In addition, a markedly high energy ion implantation becomes necessary for the formation of a termination structure. In the invention, provided is a vertical channel type SiC power JFET having a floating gate region below and separated from a source region and between gate regions. | 2016-02-04 |
| 20160035905 | SEMICONDUCTOR DEVICES - Provided are semiconductor devices. A semiconductor device includes a first well formed in a substrate; an element isolation layer formed on the first well; a second well formed in the first well on a first side of the element isolation layer; a third well formed in the second well, the third well has a higher concentration of impurities than the second well; a first electrode electrically connected to the third well; a fourth well formed in the first well on a second side of the element isolation layer; a fifth well formed in the fourth well, the fifth well has a different conductivity type from the fourth well; a second electrode electrically connected to the fifth well; and a sixth well overlapping the fourth well, the sixth well has a lower concentration of impurities than the fourth well. | 2016-02-04 |
| 20160035906 | PLANAR SEMICONDUCTOR ESD DEVICE AND METHOD OF MAKING SAME - An ESD device is provided for protecting a circuit from electrostatic discharge, and includes a planar diode having an anode and a cathode. The anode is electrically coupled to a signal path of the circuit, and the cathode is electrically coupled to a ground of the circuit. The ESD device is configured to be off during normal operation of the circuit and to turn on in response to an electrostatic discharge on the signal path. Two depletion regions in the device are separated by an isolation well. In response to the electrostatic discharge, the depletion regions modulate (e.g., widen and merge), providing a path for the discharge to the ground of the circuit. | 2016-02-04 |
| 20160035907 | SOLAR CELL MODULE - A solar cell module includes a plurality of solar cells each including a semiconductor substrate and first and second electrode parts each having a different polarity, a plurality of interconnectors for electrically connecting the plurality of solar cells, a conductive adhesive for electrically connecting each of the plurality of interconnectors to the corresponding electrode part of each of the plurality of solar cells, and at least one insulating adhesive portion for temporarily fixing the plurality of interconnectors to the corresponding electrode part. The at least one insulating adhesive portion includes an adhesive having adhesiveness to attach the interconnector to the corresponding electrode part at the room temperature. | 2016-02-04 |
| 20160035908 | FORMED PHOTOVOLTAIC MODULE BUSBARS - A method and apparatus directed to busbar components for photovoltaic modules. | 2016-02-04 |
| 20160035909 | Photovoltaic Module and Method for Producing a Photovoltaic Module - A photovoltaic module has at least one solar cell having an irradiation surface for receiving light. The photovoltaic module is configured to provide a voltage. The photovoltaic module also includes a carrier unit which is arranged laterally offset from the solar cell at least on one side. A first surface of the carrier unit is oriented flush with the irradiation surface of the solar cell within a predefined tolerance range. The photovoltaic module also includes at least one electrical conductor, which contacts a carrier contact connection on a second surface of the carrier unit opposite the first surface via a cell contact connection of an electronic component on the solar cell or the solar cell in an electrically conductive manner. The cell contact connection is arranged on a contacting side of the solar cell opposite the irradiation surface. | 2016-02-04 |
| 20160035910 | ELECTRICALLY CONDUCTIVE INKS - The present invention relates to compositions that are suitable for use as electrically conductive inks in the fabrication of electronic devices, such as c-Si solar modules. The electrically conductive ink comprises a) one or more aromatic resins; b) electrically conductive silver particles having an average particle size of 1 μm to 40 μM, and a tap density of 1.5 g/cm | 2016-02-04 |
| 20160035911 | PHOTOVOLTAIC STRUCTURE FOR A ROADWAY - A photovoltaic structure, or a photovoltaic structure for a roadway suitable for circulation of pedestrians and vehicles, including: at least one photovoltaic cell; and a non-opaque coating covering at least a front face of the photovoltaic cell and having an outer surface which is macrotextured and microtextured irregularly, with a mean texture depth MTD, measured according to the norm NF EN 13036-1, of between 0.2 mm and 3 mm, and a polishing resistance value PRV, according to the norm NF EN 13043, of at least PRV | 2016-02-04 |
| 20160035912 | ANTI-REFLECTIVE AND ANTI-SOILING COATINGS WITH SELF-CLEANING PROPERTIES - Disclosed herein is a coated glass element including a glass component and a coating adhered to the glass component through siloxane linkages, the coating having at least one of an anti-reflective property, a high abrasion resistance property and a hydrophobic property, wherein the coating comprises a dried gel formed from at least one hydrolyzed alkoxysilane-based sol and at least one hydrolyzed organosilane-based sol. | 2016-02-04 |
| 20160035913 | Solid State Detection Devices, Methods of Making and Methods of Using - The present application is directed to a solid state device for detecting neutrons. The device includes a semiconductor substrate having pores. The device also includes a p- or n-type doping layer formed on a surface of the pores. Moreover, a layer of fill material is formed on the p- or n-type doping layer. The present application also is directed to a method of making a solid state device. Further, the present application is directed to a method of detecting efficiency of solid state detector devices. | 2016-02-04 |
| 20160035914 | FILTER COATING DESIGN FOR OPTICAL SENSORS - A silicon-based sensor with an integrated multilayer metal-dielectric filter coating for providing a UV transmission curve of interest is disclosed. The sensor includes a silicon-based photodiode and a filter coating integrated with the silicon-based photodiode and comprising a plurality of filter pairs stacked over the silicon-based photodiode. Each filter pair comprises a dielectric layer and a metal layer. The dielectric layers and the metal layers of the plurality of filter pairs are stacked in an alternating fashion. A thickness of the metal layer in at least one filter pair is different from a thickness of the metal layer in at least one other filter pair. A thickness of the dielectric layer in at least one filter pair is different from a thickness of the dielectric layer in at least one other filter pair. | 2016-02-04 |
| 20160035915 | SEMICONDUCTOR SUBSTRATE AND METHOD FOR PRODUCING THE SAME, PHOTOVOLTAIC CELL ELEMENT, AND PHOTOVOLTAIC CELL - The semiconductor substrate of the present invention contains a semiconductor layer and an impurity diffusion layer containing at least one impurity atom selected from the group consisting of an n-type imparity atom and a p-type impurity atom and at least one metallic atom selected from the group consisting of K, Na, Li, Ba, St, Ca, Mg, Be, Zn, Pb, Cd, V, Sn, Zr, Mo, La, Nb, Ta, Y, Ti, Ge, Te, and Lu. | 2016-02-04 |
| 20160035916 | Multifunctional Nanostructured Metal-Rich Metal Oxides - A transparent conductive oxide (TCO) material includes a metal-rich metal oxide having an average formula (M1, M2 . . . Mn) | 2016-02-04 |
| 20160035917 | Techniques for Perovskite Layer Crystallization - Vacuum annealing-based techniques for forming perovskite materials are provided. In one aspect, a method of forming a perovskite material is provided. The method includes the steps of: depositing a metal halide layer on a sample substrate; and vacuum annealing the metal halide layer and methylammonium halide under conditions sufficient to form methylammonium halide vapor which reacts with the metal halide layer and forms the perovskite material on the sample substrate. A perovskite-based photovoltaic device and method of formation thereof are also provided. | 2016-02-04 |
| 20160035918 | THREE-DIMENSIONAL THIN-FILM SOLAR CELLS - A three-dimensional thin-film solar cell | 2016-02-04 |
| 20160035919 | QUANTUM DOT SOLAR CELL PERFORMANCE WITH A METAL SALT TREATMENT - The performance of lead sulfide quantum dot (QD) photovoltaic cells is improved by exposing a QD layer to a solution containing metal salts after the synthesis of the QDs is completed. The halide ions from the salt solution passivate surface lead (Pb) sites and alkali metal ions mend Pb vacancies. Metal cations and halide anions with small ionic radius have high probability of reaching QD surfaces to eliminate surface recombination sites. Compared to control devices fabricated using only a ligand exchange procedure without salt exposure, devices with metal salt treatment show increases in both the form factor and short circuit current of the PV cell. Some embodiments comprise a method for treatment of QDs with a salt solution and ligand exchange. Other embodiments comprise a photovoltaic cell having a QD layer treated with a salt solution and ligand exchange. | 2016-02-04 |
| 20160035920 | PHOTOELECTRIC CONVERSION DEVICE AND IMAGING SYSTEM - A photoelectric conversion device according to an exemplary embodiment includes a pixel which includes a photoelectric conversion unit and an amplifier transistor configured to output a signal generated by the photoelectric conversion unit. The photoelectric conversion unit includes a first electrode, a second electrode electrically connected to the amplifier transistor, a photoelectric conversion layer, and an insulating layer disposed between the photoelectric conversion layer and the second electrode. The photoelectric conversion layer includes quantum dots. | 2016-02-04 |
| 20160035921 | PHOTOELECTRIC CONVERSION APPARATUS AND IMAGE PICKUP SYSTEM - A photoelectric conversion apparatus includes a photoelectric conversion unit having a light incident surface and including: a first electrode; a second electrode disposed further toward the light incident surface; and a photoelectric conversion layer disposed between the first and second electrodes. The photoelectric conversion apparatus includes a member in contact with the photoelectric conversion layer and constituting a light guide together with the layer. An area of a first surface parallel to the light incident surface at a portion of the photoelectric conversion layer surrounded by the member is smaller than an area of a second surface disposed between the first surface and the second electrode at a portion of the photoelectric conversion layer surrounded by the member, and an area of orthogonal projection to the light incident surface of the first electrode is smaller than an area of orthogonal projection to the light incident surface of the second surface. | 2016-02-04 |
| 20160035922 | SOLAR CELL MODULE - A solar cell module is discussed. The solar cell module includes a plurality of solar cells, a light transmission protection part positioned at first surfaces of the plurality of solar cells, a front protection part positioned between the light transmission protection part and the plurality of solar cells, a back sheet positioned at second surfaces of the plurality of solar cells, and a back protection part positioned between the back sheet and the plurality of solar cells. The back sheet includes a first sheet layer including a first area, which overlaps the plurality of solar cells and has a first transmittance, and a second area, which is a remaining portion except the first area and has a second transmittance different from the first transmittance. | 2016-02-04 |
| 20160035923 | COVER GLASS FOR SOLAR CELL, SOLAR CELL MODULE PROVIDED WITH COVER GLASS FOR SOLAR CELL, COATING LIQUID FOR FORMING TRANSPARENT FILM, AND METHOD FOR FORMING TRANSPARENT PROTECTIVE FILM - A provided cover glass for a solar cell panel has excellent transparency, and minimal incidence so-called “glass surface turbidity” due to reactions with components contained in a glass substrate. The cover glass for the solar cell panel comprises: the glass substrate including a surface; and a transparent protective film containing zinc telluride for coating the surface. Particularly, in the cover glass for the solar cell panel, the transparent protective film is preferably formed by bonding the zinc telluride with silica binders. Such a transparent protective film has excellent transparency, and reactions of the contained zinc telluride inhibit the surface of the glass substrate, which is a base of the solar cell, from becoming turbid. | 2016-02-04 |
| 20160035924 | CONFIGURABLE BACKPLANE INTERCONNECTING LED TILES - Relatively small, electrically isolated LED tiles or PV tiles are fabricated having an anode electrode and a cathode electrode. The LED tiles contain microscopic printed LEDs that are connected in parallel by two conductive layers sandwiching the LEDs. The top conductive layer is transparent. Separately formed from the tiles is a large area backplane having a single layer or multiple layers of metal traces connected to backplane electrodes corresponding to the tile electrodes. Multiple tiles are laminated over the backplane's metal pattern to connect the tile electrodes to the backplane electrodes, such as by a conductive adhesive. The backplane metal pattern may connect the tiles in series and/or parallel, or form an addressable circuit for a display. Groups of tiles may be physically connected to each other prior to the lamination to ease handling and alignment. The backplane has power terminals electrically coupled to the metal traces for receiving power. | 2016-02-04 |
| 20160035925 | CONNECTED STRUCTURE AND METHOD FOR MANUFACTURE THEREOF - A method for electrically connecting a surface electrode of a solar battery cell and a wiring member via a conductive adhesive film, wherein the conductive adhesive film contains an insulating adhesive and conductive particles, and wherein when the ten point height of roughness profile and maximum height of the surface of the surface electrode in contact with the conductive adhesive film are Rz (μm) and Ry (μm) respectively, the average particle diameter r (μm) of the conductive particles is equal to or greater than the ten point height of roughness profile Rz, and the thickness t (μm) of the conductive adhesive film is equal to or greater than the maximum height Ry. | 2016-02-04 |
| 20160035926 | SOLAR CELL PANEL - A solar cell panel is discussed, which includes a plurality of solar cells, each solar cell including a substrate having a first surface and a second surface opposite the first surface, and a plurality of first electrodes extending in a first direction; an interconnector that is positioned in a second direction crossing the plurality of first electrodes and electrically connects adjacent ones of the plurality of solar cells to one another; and a conductive adhesive film including a resin and a plurality of conductive particles dispersed in the resin, the conductive adhesive film being positioned between the plurality of first electrodes and the interconnector in the second direction crossing the plurality of first electrodes to electrically connect the plurality of first electrodes to the interconnector. | 2016-02-04 |
| 20160035927 | Tandem Kesterite-Perovskite Photovoltaic Device - Tandem Kesterite-perovskite photovoltaic devices and techniques for formation thereof are provided. In one aspect, a tandem photovoltaic device is provided. The tandem photovoltaic device includes a bottom cell having a first absorber layer comprising copper, zinc, tin, and at least one of sulfur and selenium and a top cell connected in series with the bottom cell, the top cell having a second absorber layer comprising a perovskite material. A method of forming a tandem photovoltaic device is also provided. | 2016-02-04 |
| 20160035928 | PHOTODIODE - According to one embodiment, a photodiode includes a first semiconductor layer of a first conductivity type, a second semiconductor layer of a second conductivity type, a third semiconductor layer of the first conductivity type, and a film. The second semiconductor layer is provided in the first semiconductor layer. The third semiconductor layer is provided in the first semiconductor layer so as to surround the second semiconductor layer. Each of one ends of the second and third semiconductor layers is located at an upper surface of the first semiconductor layer. The first to third semiconductor layers include first to third impurity concentrations respectively. The second and third impurity concentrations are higher than the first impurity concentration. The film is provided above the third semiconductor layer, and blocks light to enter into a neighborhood of the third semiconductor layer. | 2016-02-04 |
| 20160035929 | LATERAL SINGLE-PHOTON AVALANCHE DIODE AND METHOD OF PRODUCING A LATERAL SINGLE-PHOTON AVALANCHE DIODE - The lateral single-photon avalanche diode comprises a semiconductor body comprising a semiconductor material of a first type of electric conductivity, a trench in the semiconductor body, and anode and cathode terminals. A junction region of the first type of electric conductivity is located near the sidewall of the trench, and the electric conductivity is higher in the junction region than at a farther distance from the sidewall. A semiconductor layer of an opposite second type of electric conductivity is arranged at the sidewall of the trench adjacent to the junction region. The anode and cathode terminals are electrically connected with the semiconductor layer and with the junction region, respectively. The junction region may be formed by a sidewall implantation. | 2016-02-04 |
| 20160035930 | GRAIN GROWTH FOR SOLAR CELLS - A solar cell can include a silicon layer formed over a silicon substrate. The silicon layer can have a P-type doped region and an N-type doped region. Portions of the silicon layer can have a grain size larger than other portions of the silicon layer. For example, larger grains of the silicon layer formed within a depletion region between P-type and N-type doped regions can minimize recombination loss at the P-type and N-type doped region boundaries and improve solar cell efficiency. | 2016-02-04 |
| 20160035931 | GALNASSB SOLID SOLUTION-BASED HETEROSTRUCTURE, METHOD FOR PRODUCING SAME AND LIGHT EMITTING DIODE BASED ON SAID HETEROSTRUCTURE - The provided heterostructure includes a substrate containing GaSb, a buffer layer which contains a GaInAsSb solid solution, the buffer layer being disposed over the substrate; an active layer which contains a GaInAsSb solid solution, the active layer being disposed over the buffer layer; a confining layer for localizing major carriers, the confining layer containing a AlGaAsSb solid solution and being disposed over the active layer; a contact layer containing GaSb, the contact layer being disposed over the confining layer, wherein the buffer layer contains less indium (In) than the active layer. The provided heterostructure is characterized by increased quantum efficiency. Also a method of producing the heterostructure and a light emitting diode based on the heterostructure are provided. Light emitting diodes on the basis of the provided heterostructure emit in a mid-infrared spectral range of 1.8-2.4 μm. | 2016-02-04 |
| 20160035932 | NANO-STRUCTURED LIGHT-EMITTING DEVICE AND METHODS FOR MANUFACTURING THE SAME - A nano-structured light-emitting device including a first semiconductor layer; a nano structure formed on the first semiconductor layer. The nano structure includes a nanocore, and an active layer and a second semiconductor layer that are formed on a surface of the nanocore, and of which the surface is planarized. A conductive layer surrounds sides of the nano structure, a first electrode is electrically connected to the first semiconductor layer and a second electrode is electrically connected to the conductive layer. | 2016-02-04 |
| 20160035933 | THICK WINDOW LAYER LED MANUFACTURE - A LED die and method for bonding, dicing, and forming the LED die are disclosed. In an example, the method includes forming a LED wafer, wherein the LED wafer includes a substrate and a plurality of epitaxial layers disposed over the substrate, wherein the plurality of epitaxial layers are configured to form a LED; bonding the LED wafer to a base-board to form a LED pair; and after bonding, dicing the LED pair, wherein the dicing includes simultaneously dicing the LED wafer and the base-board, thereby forming LED dies. | 2016-02-04 |
| 20160035934 | NITRIDE SEMICONDUCTOR STRUCTURE AND SEMICONDUCTOR LIGHT EMITTING DEVICE INCLUDING THE SAME - A nitride semiconductor structure and a semiconductor light emitting device are revealed. The semiconductor light emitting device includes a substrate disposed with a first type doped semiconductor layer and a second type doped semiconductor layer. A light emitting layer is disposed between the first type doped semiconductor layer and the second type doped semiconductor layer. The second type doped semiconductor layer is doped with a second type dopant at a concentration larger than 5×10 | 2016-02-04 |
| 20160035935 | ULTRAVIOLET LIGHT EMITTING DEVICE SEPARATED FROM GROWTH SUBSTRATE AND METHOD OF FABRICATING THE SAME - A UV light emitting device and a method for fabricating the same are disclosed. The method includes forming a first super-lattice layer including Al | 2016-02-04 |
| 20160035936 | Patterned Layer Design for Group III Nitride Layer Growth - A method of fabricating a device using a layer with a patterned surface for improving the growth of semiconductor layers, such as group III nitride-based semiconductor layers with a high concentration of aluminum, is provided. The patterned surface can include a substantially flat top surface and a plurality of stress reducing regions, such as openings. The substantially flat top surface can have a root mean square roughness less than approximately 0.5 nanometers, and the stress reducing regions can have a characteristic size between approximately 0.1 microns and approximately five microns and a depth of at least 0.2 microns. A layer of group-III nitride material can be grown on the first layer and have a thickness at least twice the characteristic size of the stress reducing regions. A device including one or more of these features also is provided. | 2016-02-04 |
| 20160035937 | OXYGEN CONTROLLED PVD ALN BUFFER FOR GAN-BASED OPTOELECTRONIC AND ELECTRONIC DEVICES - Oxygen controlled PVD AlN buffers for GaN-based optoelectronic and electronic devices is described. Methods of forming a PVD AlN buffer for GaN-based optoelectronic and electronic devices in an oxygen controlled manner are also described. In an example, a method of forming an aluminum nitride (AlN) buffer layer for GaN-based optoelectronic or electronic devices involves reactive sputtering an AlN layer above a substrate, the reactive sputtering involving reacting an aluminum-containing target housed in a physical vapor deposition (PVD) chamber with a nitrogen-containing gas or a plasma based on a nitrogen-containing gas. The method further involves incorporating oxygen into the AlN layer. | 2016-02-04 |
| 20160035938 | SEMICONDUCTOR LIGHT EMITTING DEVICE, NITRIDE SEMICONDUCTOR LAYER, AND METHOD FOR FORMING NITRIDE SEMICONDUCTOR LAYER - According to an embodiment, a semiconductor light emitting device includes a foundation layer, a first semiconductor layer, a light emitting layer, and a second semiconductor layer. The foundation layer has an unevenness having recesses, side portions, and protrusions. A first major surface of the foundation layer has an overlay-region. The foundation layer has a plurality of dislocations including first dislocations whose one ends reaching the recess and second dislocations whose one ends reaching the protrusion. A proportion of a number of the second dislocations reaching the first major surface to a number of all of the second dislocations is smaller than a proportion of a number of the first dislocations reaching the first major surface to a number of all of the first dislocations. A number of the dislocations reaching the overlay-region of the first major surface is smaller than a number of all of the first dislocations. | 2016-02-04 |
| 20160035939 | SEMICONDUCTOR LIGHT EMITTING ELEMENT, LIGHT EMITTING DEVICE, AND METHOD FOR MANUFACTURING SEMICONDUCTOR LIGHT EMITTING ELEMENT - A semiconductor light emitting element includes a stacked body, a first metal layer, and a second metal layer. The stacked body includes a first semiconductor layer, a second semiconductor layer, and a light emitting layer. The second semiconductor layer is separated from the first semiconductor layer in a first direction. The light emitting layer is provided between the first semiconductor layer and the second semiconductor layer. The first metal layer is stacked with the stacked body in the first direction to be electrically connected to one selected from the first semiconductor layer and the second semiconductor layer. The first metal layer has a side surface extending in the first direction. The second metal layer covers at least a portion of the side surface of the first metal layer. A reflectance of the second metal layer is higher than a reflectance of the first metal layer. | 2016-02-04 |
| 20160035940 | LIGHT EMITTING APPARATUS, MANUFACTURING METHOD OF LIGHT EMITTING APPARATUS, LIGHT RECEIVING AND EMITTING APPARATUS, AND ELECTRONIC EQUIPMENT - A manufacturing method is a method for manufacturing a light emitting apparatus including a translucent substrate, and a light emitting section and an optical filer section that are arranged in a first region of the substrate when viewed in a normal direction of a first surface of the substrate. The manufacturing method includes: forming a dielectric multilayer film over the first region of the substrate; forming a first electrode on the dielectric multilayer film included in the light emitting section; forming a functional layer with a light emitting layer over the first electrode and the dielectric multilayer film included in the optical filter section; and forming a second electrode having semi-transmissive reflectivity on the functional layer over the first region of the substrate. | 2016-02-04 |
| 20160035941 | HIGH INDEX DIELECTRIC FILM TO INCREASE EXTRACTION EFFICIENCY OF NANOWIRE LEDS - Various embodiments include semiconductor devices, such as nanowire LEDs, that include a plurality of first conductivity type semiconductor nanowire cores located over a support, a plurality of second conductivity type semiconductor shells extending over and around the respective nanowire cores, and a layer of a high index of refraction material over at least a portion of a surface of at least one of the nanowire cores and the shells, wherein the high index of refraction material has an index of refraction that is between about 1.4 and about 4.5. Light extraction efficiency may be improved. | 2016-02-04 |
| 20160035942 | LIGHT-EMITTING APPARATUS HAVING LIGHT-PERVIOUS PLATE - The present invention provides a light-emitting apparatus having light-pervious plate. A circuit layer is disposed on a substrate. The circuit layer is adjacent to the LEDs, so that the LEDs can be connected electrically to the circuit layer. In addition, a frame is disposed on the circuit layer. A light-pervious plate is disposed on the frame and located in a light-emitting direction of the LEDs. Moreover, there is a gap between the light-pervious plate and the LEDs. | 2016-02-04 |
| 20160035943 | FLUORESCENT COMPOSITE RESIN SUBSTRATE WHITE LIGHT LIGHT EMITTING DIODE - A fluorescent composite resin substrate white light LED includes a fluorescent composite resin substrate, two conductive brackets, a light emitting unit, two conductive lines and a package material. The fluorescent composite resin substrate is formed from a mixture through a curing reaction. Each of the conductive brackets is partially connected to the substrate. The light emitting unit is disposed on the substrate. The conductive lines are connected to the light emitting unit and respectively connected to the conductive brackets. The package material is formed from a mixture through a curing reaction. By fixing the light emitting unit at the fluorescent composite resin substrate, when applied to white light LED operations, the present invention achieves effects of emitting light through six planes, having high light flux and good heat dissipation, and significantly increasing production yield rate and speed without incurring different color temperatures at front and reverse sides. | 2016-02-04 |
| 20160035944 | METHODS OF TUNING LIGHT EMITTING DEVICES AND TUNED LIGHT EMITTING DEVICES - Methods of treating an emission spectrum of visible light emitted from a light emitting source, and resulting apparatus, are disclosed. The methods include obtaining the visible light emission spectrum emitted from the light emitting source and a desired visible light emission spectrum. The methods may also include determining at least one wavelength of the emission spectrum of the source with an irradiance or intensity that is less than that of the desired emission spectrum. The methods may include selecting at least one pigment that is effective in tuning the emission spectrum of the source by increasing the intensity or irradiance of the at least one wavelength. The methods may include applying the at least one pigment to the light emitting source to treat the emission spectrum emitted therefrom. | 2016-02-04 |
| 20160035945 | WHITE LED CHIP AND METHOD OF MANUFACTURE - The present invention discloses a white LED chip and method of manufacturing the same. The white LED chip includes a flip blue LED chip and a preformed conversion layer for light conversion, the method of manufacturing the white LED chip includes the steps of preparing for a preformed conversion layer for light conversion, setting up at least one cavity on the conversion layer, for receiving a blue LED chip(s), attaching the blue LED chip into the cavity; and cutting the conversion layer into a single white LED chip based on each cavity that received a blue LED chip. The invention not only enhance the luminous efficiency of the white LED chip, but also avoid the pollution to bottom electrode of the LED chip, making easier manufacture and higher binning yield. | 2016-02-04 |
| 20160035946 | LIGHT EMITTING DIODE PACKAGE STRUCTURE, BACKLIGHT MODULE AND DISPLAY DEVICE - The present disclosure provides a light emitting diode (LED) package structure, a backlight module and a display device, and relates to the field of display technologies. The LED package structure includes an encapsulation housing and an LED chip encapsulated in the encapsulation housing. The encapsulation housing is a polyhedron which includes at least one inclined plane. One inclined plane of the encapsulation housing is a light exiting surface of the LED package structure. | 2016-02-04 |
| 20160035947 | PACKAGE STRUCTURE OF LIGHT-EMITTING DIODE MODULE AND METHOD FOR MANUFACTURING THE SAME - The present invention provides a package structure of LED module and the method for manufacturing the same. The method comprises steps of providing a light-emitting module; disposing a light-pervious member on the light-emitting path of the light-emitting module; and dripping a colloid member on the light-pervious member. The light-pervious member is a transparent structure; and the colloid member forms a transparent structure with a thick center and a thin periphery using the surface tension of colloid material. In the above structure, the light-pervious member and colloid member are used for reducing the total reflection effect in the package. | 2016-02-04 |
| 20160035948 | ELECTRONIC COMPONENT AND ELECTRONIC UNIT - According to one embodiment, an electronic component includes a metal portion, a mold resin covering at least a part of the metal portion, and a molecular adhesion layer provided between a surface of the metal portion and the mold resin. | 2016-02-04 |
| 20160035949 | Color Tuning of Light-Emitting Devices - A variety of light-emitting devices for general illumination utilizing solid state light sources (e.g., light-emitting diodes) are disclosed. A light-emitting device can include a first light-emitting element (LEE) for emitting light having a first spectral composition, a second LEE for emitting light having a second spectral composition, and a scattering element surrounding at least in part the first and second LEEs to scatter light emitted from the first and second LEEs. The light-emitting device can also include electrical connections for connecting the first and second LEEs to a power source, where the electrical connections are arranged such that power to the first LEE is separately adjustable relative to power to the second LEE. | 2016-02-04 |
| 20160035950 | LED ARRAY PACKAGE - Various aspects of a light emitting apparatus includes a substrate. Various aspects of the light emitting apparatus include a light emitting die arranged on the substrate. The light emitting die includes one or more side walls. Various aspects of the light emitting apparatus include a reflective die attach material extending along the one or more side walls of the light emitting die. | 2016-02-04 |
| 20160035951 | OPTICAL SEMICONDUCTOR ELEMENT MOUNTING PACKAGE, AND OPTICAL SEMICONDUCTOR DEVICE USING THE SAME - An optical semiconductor element mounting package that has good adhesion between the resin molding and the lead electrodes and has excellent reliability is provided, as well as an optical semiconductor device using the package is also provided. The optical semiconductor element mounting package having a recessed part that serves as an optical semiconductor element mounting region, wherein the package is formed by integrating: a resin molding composed of a thermosetting light-reflecting resin composition, which forms at least the side faces of the recessed part; and at least a pair of positive and negative lead electrodes disposed opposite each other so as to form part of the bottom face of the recessed part, and there is no gap at a joint face between the resin molding and the lead electrodes. | 2016-02-04 |
| 20160035952 | LIGHT EMITTING DEVICE AND METHOD FOR MANUFACTURING LIGHT EMITTING DEVICE - A light emitting device ( | 2016-02-04 |
| 20160035953 | LIGHT EMITTING DEVICE AND METHOD OF MANUFACTURING THE SAME - Disclosed is a light emitting device and a method of manufacturing the same. The light emitting device includes a body, a first electrode installed in the body and a second electrode separated from the first electrode, a light emitting chip formed on one of the first and second electrodes, and electrically connected to the first and second electrodes, and a protective cap projecting between the first and second electrodes. | 2016-02-04 |
| 20160035954 | THERMOELECTRIC PERFORMANCE OF CALCIUM AND CALCIUM-CERIUM FILLED N-TYPE SKUTTERUDITES - A method is disclosed for inserting elemental calcium and cerium as low cost fillers in n-type Co | 2016-02-04 |
| 20160035955 | System and Method for Using Pre-Equilibrium Ballistic Charge Carrier Refraction - A method and system for using a method of pre-equilibrium ballistic charge carrier refraction comprises fabricating one or more solid-state electric generators. The solid-state electric generators include one or more of a chemically energized solid-state electric generator and a thermionic solid-state electric generator. A first material having a first charge carrier effective mass is used in a solid-state junction. A second material having a second charge carrier effective mass greater than the first charge carrier effective mass is used in the solid-state junction. A charge carrier effective mass ratio between the second effective mass and the first effective mass is greater than or equal to two. | 2016-02-04 |
| 20160035956 | THERMOELECTRIC APPARATUS AND ARTICLES AND APPLICATIONS THEREOF - In one aspect, thermoelectric apparatus and articles and various applications of thermoelectric apparatus and articles are described herein. In some embodiments, a thermoelectric apparatus described herein comprises at least one p-type layer coupled to at least one n-type layer to provide a pn junction, and an insulating layer at least partially disposed between the p-type layer and the n-type layer, the p-type layer comprising carbon nanoparticles and the n-type layer comprising n-doped carbon nanoparticles. In some embodiments, the nanoparticles of the p-type layer and/or the nanoparticles of the n-type layer are disposed in a polymeric matrix comprising electrically poled polymer. In some embodiments, a thermoelectric article comprises a thermally insulating support and thermoelectric modules formed of a structure passing around or through the thermally insulating support to provide faces of the thermoelectric modules on opposing sides of the thermally insulating support. | 2016-02-04 |
