05th week of 2016 patent applcation highlights part 62 |
Patent application number | Title | Published |
20160035657 | SEMICONDUCTOR DEVICE AND SEMICONDUCTOR MODULE - According to one embodiment, a semiconductor device includes a first base portion, a second base portion, a third base portion, and a semiconductor element. A first end portion of the first base portion is positioned closer to a side on which the semiconductor element is provided than a second end portion of the first base portion. A third end portion of the second base portion is positioned closer to the side on which the semiconductor element is provided than a fourth end portion of the second base portion. A fifth end portion of the third base portion is positioned closer to the side on which the semiconductor element is provided than a sixth end portion of the third base portion in the third direction. | 2016-02-04 |
20160035658 | Encapsulated electronic chip device with mounting provision and externally accessible electric connection structure - An electronic device comprising a carrier having a mounting surface, at least one electronic chip mounted on the mounting surface, at least one electric connection structure mounted on the mounting surface, an encapsulant at least partially encapsulating the carrier and the at least one electronic chip, and partially encapsulating the at least one electric connection structure so that part of a surface of the at least one electric connection structure is exposed to an environment, and a mounting provision configured for mounting the electronic device at a periphery device. | 2016-02-04 |
20160035659 | BALL GRID ARRAY AND LAND GRID ARRAY ASSEMBLIES FABRICATED USING TEMPORARY RESIST - Ball grid assembly (BGA) bumping solder is formed on the back side of a laminate panel within a patterned temporary resist. Processes such as singulation and flip chip module assembly are conducted following BGA bumping with the temporary resist in place. The resist is removed from the back side of the singulated laminate panel prior to card assembly. Stand-off elements having relatively high melting points can be incorporated on the BGA side of the laminate panel to ensure a minimum assembly solder collapse height. Alignment assemblies are formed on the socket-facing side of an LGA module using elements having relatively high melting points and injected solder. | 2016-02-04 |
20160035660 | BONDING BODY, POWER MODULE SUBSTRATE, AND HEAT-SINK-ATTACHED POWER MODULE SUBSTRATE - A bonding body includes: an aluminum member composed of aluminum; and a metal member composed of any one of copper, nickel, and silver, wherein the aluminum member and the metal member are bonded together. In a bonding interface between the aluminum member and the metal member, a Ti layer and an Al—Ti—Si layer are formed, the Ti layer being disposed at the metal member side in the bonding interface, and the Al—Ti—Si layer being disposed between the Ti layer the aluminum member and containing Si which is solid-solubilized into Al | 2016-02-04 |
20160035661 | SUPPORT MEMBER, WIRING SUBSTRATE, METHOD FOR MANUFACTURING WIRING SUBSTRATE, AND METHOD FOR MANUFACTURING SEMICONDUCTOR PACKAGE - A wiring substrate includes a support member, and a wiring member formed on one side of the support member. The support member includes metal foils and at least one resin layer alternately layered, so that one of the metal foils is provided as a first outermost layer on the one side of the support member and another one of the metal foils is provided as a second outermost layer on another side of the support member. The first outermost layer includes thick and thin foils that are peelably adhered. The thick foil contacts the at least one resin layer. One surface of the thin foil faces an outer side of the support member. The wiring member includes wiring layers and an insulating layer alternately layered on the thin foil. The number of the metal foils and the number of the wiring layers are the same. | 2016-02-04 |
20160035662 | SEMICONDUCTOR DEVICES WITH CLOSE-PACKED VIA STRUCTURES HAVING IN-PLANE ROUTING AND METHOD OF MAKING SAME - The invention relates to a semiconductor structure, comprising a substrate of a semiconductor material having a first side (FS) and an opposite second side (BS). There is at least one conductive wafer-through via (V) comprising metal, and at least one recess (RDL) provided in the first side of the substrate and in the semiconductor material of the substrate. The recess is filled with metal and seamlessly connected with the wafer-through via. The exposed surfaces of the metal filled via and the metal filled recess are essentially flush with the substrate surface on the first side of the substrate. There is also provide an interposer comprising the above structure, further comprising contacts for attaching circuit boards and integrated circuits on opposite sides of the interposer. A method of making the structure is also provided. | 2016-02-04 |
20160035663 | Semiconductor Package System and Method - A first protective layer is formed on a first die and a second die, and openings are formed within the first protective layer. The first die and the second die are encapsulated such that the encapsulant is thicker than the first die and the second die, and vias are formed within the openings. A redistribution layer can also be formed to extend over the encapsulant, and the first die may be separated from the second die. | 2016-02-04 |
20160035664 | SEMICONDUCTOR PACKAGE ON PACKAGE STRUCTURE AND METHOD OF FORMING THE SAME - A package on package structure may be formed by fabricating or providing a bottom package having a substrate, at least one die on top of the substrate, and bonding pads on the top of the substrate. Next, a frame is formed on the bonding pads and connected to the bonding pads. Next, a package material is molded over the top of the substrate to encapsulate the frame, the die, and the pads or substantially encapsulates these components. Next, a portion of the molded package material is removed to expose at least a portion of the frame. The exposed frame portions are formed such that a desired fan in or fan out configuration is obtained. Next, a non-conductive layer is formed on the exposed frame. Last, a second package having a die or chip is connected to the exposed portion of the frame to form a package on package structure. | 2016-02-04 |
20160035665 | CIRCUIT ARRANGEMENT AND METHOD FOR MANUFACTURING THE SAME - A circuit arrangement is provided, which may include: an embedding package chip carrier; a first chip and a second chip arranged over the embedding package chip carrier, each of the first chip and the second chip comprising: a control terminal, a first controlled terminal, and a second controlled terminal, wherein the control terminal and the first controlled terminal are arranged on a first side of the chip, and wherein the second controlled terminal is arranged on a second side of the chip, wherein the second side is opposite the first side; wherein the first chip is arranged on the embedding package chip carrier such that its first side is facing towards the embedding package chip carrier; and wherein the second chip is arranged on the embedding package chip carrier such that its first side is facing away from the embedding package chip carrier. | 2016-02-04 |
20160035666 | PACKAGES WITH MOLDING STRUCTURES AND METHODS OF FORMING THE SAME - A method includes molding a device die in a molding material, wherein a metal pillar of the device die is exposed through a surface of the molding material. A substrate is adhered to the molding material. The substrate includes a redistribution layer that further includes redistribution lines. A plating is performed to fill a through-opening in the substrate to form a through-via. The through-via is plated on the metal pillar of the device die. An electrical connector is formed to electrically couple to the through-via. | 2016-02-04 |
20160035667 | Methods of Packaging Semiconductor Devices and Packaged Semiconductor Devices - Methods of packaging semiconductor devices and packaged semiconductor devices are disclosed. In some embodiments, a method of packaging a semiconductor device includes providing a protective film, coupling dies to the protective film, and disposing a molding material around the dies. The protective film includes a substantially opaque material at predetermined wavelengths of light. | 2016-02-04 |
20160035668 | AUTOMATED SHORT LENGHT WIRE SHAPE STRAPPING AND METHODS OF FABRICATING THE SAME - An automatic short length wire shape generation and strapping and method of fabricating such wires is provided. The method of manufacturing includes breaking of a wiring into adjacent short length wires which are below a maximum short length effect length. The adjacent short length wires are formed in a same wiring level of an integrated circuit. The method further includes forming a conductive strap in a single deposition process which overlaps and is in contact with the adjacent short length wires. | 2016-02-04 |
20160035669 | ROUTING PATHS AND SEMICONDUCTOR DEVICES INCLUDING THE SAME - A semiconductor device may include a global line coupled to a source, and a plurality of local lines coupled to a plurality of targets, respectively, and coupled to the global line. The local lines may be configured to have cross-sectional areas. The cross-sectional areas may increase in proportion to distances from the source to the respective targets. | 2016-02-04 |
20160035670 | Semiconductor Device Packages, Packaging Methods, and Packaged Semiconductor Devices - Semiconductor device packages, packaging methods, and packaged semiconductor devices are disclosed. In some embodiments, a package for a semiconductor device includes a back side interconnect structure, and a winding of an inductor disposed in a material layer of the back side interconnect structure. A molding material is coupled to the back side interconnect structure. The package includes an integrated circuit die mounting region disposed within the molding material. | 2016-02-04 |
20160035671 | Structure of Integrated Inductor - This invention discloses an integrated inductor structure, including a first metal trace, a second metal trace, and a connecting metal trace. Tow terminals of the connecting metal trace are respectively connected to the first metal trace and the second metal trace through at least a connecting structure. The connected first metal trace, the connecting metal trace and the second metal trace together form an inductor structure. The connecting structure is connected to a connecting area of the first metal trace. The connecting area of the first metal trace has a first width. A smallest width of the first metal trace is a second width. The second width is smaller than the first width. | 2016-02-04 |
20160035672 | SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING THE SAME | 2016-02-04 |
20160035673 | SEMICONDUCTOR DEVICE HAVING A FUSE ELEMENT - A portion-to-be-melted of a fuse is surrounded by plates, so that heat to be generated in a meltdown portion of the fuse under current supply can be confined or accumulated in the vicinity of the meltdown portion of the fuse. This makes it possible to facilitate meltdown of the fuse. The meltdown portion of the fuse in a folded form, rather than in a single here a fuse composed of a straight-line form, is more successful in readily concentrating the heat generated in the fuse under current supply into the meltdown portion, and in further facilitating the meltdown of the fuse. | 2016-02-04 |
20160035674 | AUTOBAHN INTERCONNECT IN IC WITH MULTIPLE CONDUCTION LANES - A topological insulator is grown on an IC wafer in a vacuum chamber as a thin film interconnect between two circuits in the IC communicating with each other. As the TI is being grown, magnetic doping of the various TI sub-layers is varied to create different edge states in the stack of sub-layers. The sub-edges conduct in parallel with virtually zero power dissipation. Conventional metal electrodes are formed on the IC wafer that electrically contact the four corners of the TI layer (including the side edges) to electrically connect a first circuit to a second circuit via the TI interconnect. The TI interconnect thus forms two independent conducting paths between the two circuits, with each path being formed of a plurality of sub-edges. This allows bi-direction communications without collisions. Since each electrode contacts many sub-edges in parallel, the overall contact resistance is extremely low. | 2016-02-04 |
20160035675 | LOW RESISTIVITY DAMASCENE INTERCONNECT - A damascene interconnect structure may be formed by forming a trench in an ILD. A diffusion barrier may be deposited on trench surfaces, followed by a first liner material. The first liner material may be removed from a bottom surface of the trench. A second liner material may be directionally deposited on the bottom. A conductive seed layer may be deposited on the first and second liner materials, and a conductive material may fill in the trench. A CMP process can remove excess material from the top of the structure. A damascene interconnect may include a dielectric having a trench, a first liner layer arranged on trench sidewalls, and a second liner layer arranged on a trench bottom. A conductive material may fill the trench. The first liner material may have low wettability and the second liner material may have high wettability with respect to the conductive material. | 2016-02-04 |
20160035676 | Semiconductor Devices and Methods of Fabricating the Same - Semiconductor devices may include a substrate including an active region defined by a device isolation layer, source/drain regions in the active region, word lines extending in a first direction parallel to the active region and being arranged in a second direction crossing the first direction, a bit line pattern extending in the second direction and crossing over a portion of the active region positioned between the word lines, and a graphene pattern covering at least a portion of the bit line pattern. | 2016-02-04 |
20160035677 | METHOD FOR FORMING A PACKAGE ARRANGEMENT AND PACKAGE ARRANGEMENT - A method for forming a package arrangement is provided, which may include: arranging at least one chip over a carrier; at least partially encapsulating the at least one chip with encapsulation material, wherein the encapsulation material is formed such that at least a portion of the carrier is uncovered by the encapsulation material; forming an electrically conductive structure over the encapsulation material and on the portion of the carrier uncovered by the encapsulation material; removing the carrier; and then forming a redistribution structure over the chip and the electrically conductive structure, wherein the redistribution structure electrically couples the electrically conductive structure and the chip. | 2016-02-04 |
20160035678 | SEMICONDUCTOR PACKAGE AND METHOD OF MANUFACTURING THE SAME - The semiconductor package includes: a substrate having at least one circuit layer; at least one electronic component mounted on at least one surface of the substrate; a molded part formed on the surface of the substrate to enclose the electronic component; at least one via formed in the molded part to be electrically connected to the circuit layer of the substrate; and a semiconductive pattern connected to one end of a plated tail connected to the circuit layer connected to the via and exposed to the exterior of the substrate. | 2016-02-04 |
20160035679 | DEVICES AND METHODS RELATED TO DUAL-SIDED RADIO-FREQUENCY PACKAGE HAVING SUBSTRATE CAVITY - Devices and method related to dual-sided radio-frequency package having substrate cavity. In some embodiment, a packaged RF device includes a packaging substrate configured to receive a plurality of components, the packaging substrate including a first side and a second side, the second side of the packaging substrate defining a pocket. The packaged RF device also includes a shielded package implemented on the first side of the packaging substrate, the shielded package including an RF circuit, the shielded package configured to provide RF shielding for at least a portion of the RF circuit. The packaged RF device further includes a component mounted substantially within the pocket of the second side of the packaging substrate. | 2016-02-04 |
20160035680 | SEMICONDUCTOR PACKAGE WITH CONFORMAL EM SHIELDING STRUCTURE AND MANUFACTURING METHOD OF SAME - A semiconductor package includes a substrate having a front side, a bottom side, and a sidewall along a perimeter of the substrate, a plurality of solder pads on the bottom side, at least one EM shielding contact structure on the bottom side and partially exposed on the sidewall, a semiconductor device mounted on the front side, a mold compound on the front side and covering the semiconductor device, and an EM shielding layer conformally covering the mold compound and the sidewall. The EM shielding layer is in direct contact with the exposed portion of the EM shielding contact structure on the sidewall. | 2016-02-04 |
20160035681 | SEMICONDUCTOR DEVICE STRUCTURES INLCUDING A DISTRIBUTED BRAGG REFLECTOR - A method of forming a semiconductor device structure comprises forming at least one reflective structure comprising at least two dielectric materials having different refractive indices over at least one radiation-sensitive structure, the at least one reflective structure configured to substantially reflect therefrom radiation within a predetermined wavelength range and to substantially transmit therethrough radiation within a different predetermined wavelength range. Additional methods of forming a semiconductor device structure are described. Semiconductor device structures are also described. | 2016-02-04 |
20160035682 | INTEGRATED CIRCUIT WITH BACKSIDE STRUCTURES TO REDUCE SUBSTRATE WARP - Wafer bowing induced by deep trench capacitors is ameliorated by structures formed on the reverse side of the wafer. The structures on the reverse side include tensile films. The films can be formed within trenches on the back side of the wafer, which enhances their effect. In some embodiments, the wafers are used to form 3D-IC devices. In some embodiments, the 3D-IC device includes a high voltage or high power circuit. | 2016-02-04 |
20160035683 | SEMICONDUCTOR DEVICE - A highly reliable semiconductor device capable of heavy current conduction and high temperature operation has a module structure in which a semiconductor chip and a circuit pattern are electrically connected via a wire. A front surface metal film is formed on a front surface electrode of the chip, and the wire is bonded to the front surface metal film by wire bonding. The chip has a front surface electrode on the front surface of an Si substrate or an SiC substrate, and has a rear surface substrate on the rear surface thereof. The front surface metal film is a Ni film or a Ni alloy film of having a thickness ranging from 3 μm to 7 μm. The wire is an Al wire having an increased recrystallizing temperature and improved strength due to controlling the crystal grain sizes before wire bonding to a range of 1 μm to 20 μm. | 2016-02-04 |
20160035684 | Bump Pad Structure - An embodiment is a bump bond pad structure that comprises a substrate comprising a top layer, a reinforcement pad disposed on the top layer, an intermediate layer above the top layer, an intermediate connection pad disposed on the intermediate layer, an outer layer above the intermediate layer, and an under bump metal (UBM) connected to the intermediate connection pad through an opening in the outer layer. Further embodiments may comprise a via mechanically coupling the intermediate connection pad to the reinforcement pad. The via may comprise a feature selected from the group consisting of a solid via, a substantially ring-shaped via, or a five by five array of vias. Yet, a further embodiment may comprise a secondary reinforcement pad, and a second via mechanically coupling the reinforcement pad to the secondary reinforcement pad. | 2016-02-04 |
20160035685 | TIN ALLOY ELECTROPLATING SOLUTION FOR SOLDER BUMPS INCLUDING PERFLUOROALKYL SURFACTANT - Disclosed is a tin-based electroplating solution for forming solder bumps of a flip chip package. The tin-based electroplating solution includes tin methanesulfonate, silver methanesulfonate, methanesulfonic acid, a fluorinated surfactant, an aromatic polyoxyalkylene ether, and water. Also disclosed is a method for forming solder bumps by using the electroplating solution. The method includes (1) electroplating a silicon wafer having a protective layer through which an electrode pad is exposed and an under bump metallurgy (UBM) layer with a copper or copper/nickel plating solution to form copper or copper/nickel pillars on the under bump metallurgy layer and (2) electroplating the pillars with the tin-based electroplating solution to form solder bumps. | 2016-02-04 |
20160035686 | CHIP ATTACHMENT SYSTEM - Forming the chip attachment system includes obtaining a chip having a bump core on a die. The method also includes obtaining an intermediate structure having a transfer pad on a substrate. The method further includes transferring the transfer pad from the substrate to the bump core such that the transfer pad becomes a solder layer on the bump core. | 2016-02-04 |
20160035687 | BUMP STRUCTURAL DESIGNS TO MINIMIZE PACKAGE DEFECTS - A method of forming a chip package includes providing a chip with a plurality of first bumps, wherein the plurality of first bumps has a first height. The method further includes providing a substrate with a plurality of second bumps, wherein the plurality of second bumps has a second height. The method further includes bonding the plurality of first bumps to the plurality of second bumps to form a first bump structure of the chip package, wherein the first bump structure has a standoff, wherein a ratio of a sum of the first height and the second height to the standoff is equal to or greater than about 0.6 and less than 1. | 2016-02-04 |
20160035688 | SEMICONDUCTOR COMPONENT, SEMICONDUCTOR-MOUNTED PRODUCT INCLUDING THE COMPONENT, AND METHOD OF PRODUCING THE PRODUCT - A semiconductor component includes a semiconductor package having a mountable face, a bump, and a coating part. The bump is made of first solder and is formed on the mountable face. The coating part formed of a first composition containing solder powder made of second solder, a flux component, and a first thermosetting resin binder coats the top end of the bump. | 2016-02-04 |
20160035689 | CHIP INTEGRATION MODULE, CHIP PACKAGE STRUCTURE, AND CHIP INTEGRATION METHOD - The present invention provides a chip integration module, including a die, a passive device, and a connecting piece, where the die is provided with a die bonding portion, the passive device is provided with a passive device bonding portion, the die bonding portion of the die and the passive device bonding portion of the passive device are disposed opposite to each other, and the connecting piece is disposed between the die bonding portion and the passive device bonding portion and is connected to the die bonding portion and the passive device bonding portion. The chip integration module of the present invention achieves easy integration and has low costs. Moreover, a path connecting the die to the passive device becomes shorter, which can improve performance of the passive device. The present invention further discloses a chip package structure and a chip integration method. | 2016-02-04 |
20160035690 | SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD OF SEMICONDUCTOR DEVICE - A solder joint layer has a structure in which plural fine-grained second crystal sections ( | 2016-02-04 |
20160035691 | SEMICONDUCTOR DEVICE AND METHOD OF FABRICATING SAME - A semiconductor device includes, an alloy layer sandwiched between a first Ag layer formed on a mounting board or circuit board and a second Ag layer formed on a semiconductor element, wherein the alloy layer contains an intermetallic compound of Ag | 2016-02-04 |
20160035692 | STACKED PACKAGING IMPROVEMENTS - A plurality of microelectronic assemblies are made by severing an in-process unit including an upper substrate and lower substrate with microelectronic elements disposed between the substrates. In a further embodiment, a lead frame is joined to a substrate so that the leads project from this substrate. Lead frame is joined to a further substrate with one or more microelectronic elements disposed between the substrates. | 2016-02-04 |
20160035693 | SEMICONDUCTOR TSV DEVICE PACKAGE FOR CIRCUIT BOARD CONNECTION - An electronic device includes a circuit board and a semiconductor device package. The semiconductor device package includes a laminate layer. The semiconductor device package includes a semiconductor die having an active side, an inactive side opposite the active side, and through-silicon vias (TSVs) conductively connecting the active side to the inactive side and conductively connecting the semiconductor die to one of the laminate layer and the circuit board. The semiconductor device package includes a laminate layer having a side attached to the active side or the inactive side semiconductor die. The semiconductor device package includes solder balls at the side of the laminate layer attached to the semiconductor die, around the semiconductor die, and attached to the circuit board. | 2016-02-04 |
20160035694 | METHOD OF MANUFACTURING ELECTRONIC DEVICE, AND ELECTRONIC COMPONENT MOUNTING DEVICE - An electronic component mounting device, includes a stage in which a plurality of stage portions are defined, a first heater provided in the plurality of stage portions respectively, and the first heater which can be controlled independently, a mounting head arranged over the stage, and a second heater provided in the mounting head. | 2016-02-04 |
20160035695 | METHOD OF MANUFACTURING SEMICONDUCTOR DEVICE - A semiconductor device includes a common wire that sequentially connects three or more pads; bonding portions at which a side surface of the wire is bonded to the pads; and looping portions looped from the bonding portions onto the other pads adjacent to the pads, the bonding portions and the looping portions are formed alternately. When the pads are recessed from the surface of semiconductor chips, the common wire is crushed to a thickness greater than the recess depth of the pads to be made into a flat shape. Thus, on the semiconductor device, wire connection is performed with a smaller bonding count while reducing damage to the semiconductor chips, and at the same time bonding is performed efficiently to the electrodes recessed from the surface of the semiconductor chips. | 2016-02-04 |
20160035696 | METHOD FOR FORMING PACKAGE STRUCTURE - A method for forming a package structure is provided, which includes: providing a pre-packaged panel including a first encapsulation layer, which includes multiple integrating units each including at least one semiconductor chip with multiple first pads, and first metal bumps are disposed on the first pads; providing a circuit board including a first surface and a second surface, where the circuit board includes multiple carrying units each including multiple input pads on the first surface and multiple output pads on the second surface; mounting the pre-packaged panel on the first surface to form multiple package units; forming a filling layer by filling a space between the first surface and the pre-packaged panel; forming second metal bumps on the output pads on the second surface; cutting the structure based on the multiple package units to form multiple independent package structures. Accordingly, the package structure improves package efficiency. | 2016-02-04 |
20160035697 | MINIATURIZED SMD DIODE PACKAGE AND PROCESS FOR PRODUCING THE SAME - A process for producing a miniaturized SMD diode package involves using a diode chip whose bottom surface has a positive electrode and a negative electrode, using a circuit board instead of a conventional lead frame during packaging, and using Charge-Coupled Device (CCD) image registration technology to perform chip bonding; the beneficial advantages brought from the process for producing the same including to simplify producing process and reduce manufacturing cost, to improve accuracy and precision of producing the miniaturized SMD diode package due to using a circuit board instead of conventionally used lead frame, and to ensure the produced miniaturized SMD diode package possesses excellent diode characteristics without distortion or defect. | 2016-02-04 |
20160035698 | STACK PACKAGE - A stack package includes a substrate, a stack of semiconductor chips mounted to the substrate, a side semiconductor chip disposed on one side of the stack, and adhesive interposed between the lower surface of the side semiconductor chip and the stack of semiconductor chips and which attaches the side semiconductor chip to the stack. | 2016-02-04 |
20160035699 | Power Semiconductor Package Having Vertically Stacked Driver IC - In one implementation, a semiconductor package includes a control conductive carrier having a die side and an opposite input/output (I/O) side connecting the semiconductor package to a mounting surface. The semiconductor package also includes a control FET of a power converter switching stage attached to the die side of the control conductive carrier, and a driver integrated circuit (IC) for driving the control FET. The driver IC is situated above the control FET and is electrically coupled to the control FET by at least one conductive buildup layer formed over the control conductive carrier. | 2016-02-04 |
20160035700 | CHIP PACKAGE AND CHIP ASSEMBLY - A chip package is provided. The chip package may include an electrically conductive carrier; at least one first chip including a first side and a second side opposite of the first side, with its second side being electrically contacted to the electrically conductive carrier; an insulating layer over at least a part of the electrically conductive carrier and over at least a part of the first side of the chip; at least one second chip arranged over the insulating layer and next to the first chip; encapsulating material over the first chip and the second chip; and electrical contacts which extend through the encapsulation material to at least one contact of the at least one first chip and to at least one contact of the at least one second chip. | 2016-02-04 |
20160035701 | SEMICONDUCTOR TSV DEVICE PACKAGE FOR CIRCUIT BOARD CONNECTION - An electronic device includes a circuit board and a semiconductor device package. The semiconductor device package includes a laminate layer. The semiconductor device package includes a semiconductor die having an active side, an inactive side opposite the active side, and through-silicon vias (TSVs) conductively connecting the active side to the inactive side and conductively connecting the semiconductor die to one of the laminate layer and the circuit board. The semiconductor device package includes a laminate layer having a side attached to the active side or the inactive side semiconductor die. The semiconductor device package includes solder balls at the side of the laminate layer attached to the semiconductor die, around the semiconductor die, and attached to the circuit board. | 2016-02-04 |
20160035702 | VERTICALLY INTEGRATED WAFERS WITH THERMAL DISSIPATION - Technologies are generally described related to three-dimensional integration of integrated circuits (ICs) with spacing for heat dissipation. According to some examples, a self-aligned silicide may be formed in a temporary silicon layer and removed subsequent to bonding of the wafers to achieve improved contact between the combined ICs and enhanced heat dissipation through added spacing between the ICs. | 2016-02-04 |
20160035703 | DIE STACKING TECHNIQUES IN BGA MEMORY PACKAGE FOR SMALL FOOTPRINT CPU AND MEMORY MOTHERBOARD DESIGN - A microelectronic package can include a substrate comprising a dielectric element having first and second opposite surfaces, and a microelectronic element having a face extending parallel to the first surface. The substrate can also include a plurality of peripheral edges extending between the first and second surfaces defining a generally rectangular or square periphery of the substrate. The substrate can further include a plurality of contacts and terminals, the contacts being at the first surface, the terminals being at at least one of the first or second surfaces. The microelectronic elements can have a plurality of edges bounding the face, and a plurality of element contacts at the face electrically coupled with the terminals through the contacts of the substrate. Each edge of the microelectronic element can be oriented at an oblique angle with respect to the peripheral edges of the substrate. | 2016-02-04 |
20160035704 | BACKSIDE THROUGH SILICON VIAS AND MICRO-CHANNELS IN THREE DIMENSIONAL INTEGRATION - Technologies are generally described related to electrical connectivity and heat mitigation in three dimensional integrated circuit (IC) integration through backside through silicon vias (TSVs) and micro-channels. In some examples, micro-channels may be formed in a wafer using a reactive ion etching (RIE) or similar fabrication process. Upon alignment and bonding of two wafers, selected micro-channels may be converted into TSVs by a further RIE or similar process and filled. | 2016-02-04 |
20160035705 | SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD THEREFOR - A chip laminate in this semiconductor device has a structure consisting of a first semiconductor chip and a second semiconductor chip laminated together. The first semiconductor chip has a circuit-forming layer and a first bump electrode formed on one surface and a second bump electrode formed on the other surface. The second semiconductor chip has a circuit-forming layer and a third bump electrode formed on one surface and a fourth bump electrode formed on the other surface. The first semiconductor chip and the second semiconductor chip are laminated together such that the circuit-forming layer on the first semiconductor chip and the circuit-forming layer on the second semiconductor chip face each other and the first and third bump electrodes are electrically connected to each other. | 2016-02-04 |
20160035706 | SEMICONDUCTOR DEVICE FOR BATTERY POWER VOLTAGE CONTROL - A voltage generated in any of a plurality of semiconductor chips is supplied to another chip as a power supply voltage to realize a stable operation of a semiconductor device in which the semiconductor chips are stacked in the same package. For example, two chips are stacked with each other, first to third pads are disposed along corresponding sides of the respective chips, which are arranged close and in parallel to each other, and these pads are commonly connected to each other with first to third metal wires, respectively. In another example, fourth and fifth pads are disposed along a side different from a side along which the first to third pads are disposed, and further connected to each other with a fourth metal wire directly between the chips. | 2016-02-04 |
20160035707 | STACKED STRUCTURE OF SEMICONDUCTOR CHIPS HAVING VIA HOLES AND METAL BUMPS - A stacked structure comprises a semiconductor chip which includes a substrate having at least one substrate via hole penetrating through the substrate; at least one backside metal layer formed on a backside of the substrate covering an inner surface of the substrate via hole and at least part of the backside of the substrate; at least one front-side metal layer formed on the front-side of the substrate and electrically connected to the at least one backside metal layer on a top of at least one of the at least one substrate via hole; at least one electronic device formed on the front-side of the substrate and electrically connected to the at least one front-side metal layer; and at least one metal bump formed on at least one of the backside metal layer and the front-side metal layer. | 2016-02-04 |
20160035708 | STACK PACKAGES AND METHODS OF MANUFACTURING THE SAME - A stack package includes a substrate having connection terminals and a first chip on the substrate. The first chip has first connectors on edges thereof. A second chip is stacked on the first chip to expose outer portions of the first connectors. The second chip has second connectors on edges thereof. Connection members to connect the exposed outer portions of the first connectors to the connection terminals. Sidewall interconnectors to connect the exposed outer portions of the first connectors to the second connectors. The sidewall interconnectors extend from the exposed outer portions of the first connectors along sidewalls of the second chip to cover the second connectors. | 2016-02-04 |
20160035709 | Package on Package Devices and Methods of Packaging Semiconductor Dies - Package on package (PoP) devices and methods of packaging semiconductor dies are disclosed. A PoP device includes a first packaged die and a second packaged die coupled to the first packaged die. Metal stud bumps are disposed between the first packaged die and the second packaged die. The metal stud bumps include a stick region, a first ball region coupled to a first end of the stick region, and a second ball region coupled to a second end of the stick region. The metal stud bumps include a portion that is partially embedded in a solder joint. | 2016-02-04 |
20160035710 | LIGHT-EMITTING DEVICE AND LIGHTING DEVICE PROVIDED WITH THE SAME - A light-emitting device capable of ensuring an electric connection between a light-emitting element and an electrode without generating any problem in practical use, by both connecting methods with a solder and a connector, and a lighting device provided with the light-emitting device are provided. The light-emitting device according to the present invention has a plurality of LED chips, and a soldering electrode land and a connector connecting electrode land electrically connected to the chips, on a ceramic substrate. The soldering electrode land is formed of a first conductive material having a function to prevent diffusion to a solder, and the connector connecting electrode land is formed of a second conductive material having a function to prevent oxidation. | 2016-02-04 |
20160035711 | STACKED PACKAGE-ON-PACKAGE MEMORY DEVICES - 3D Stacked memory devices with copper pillars electrically connecting the package units are disclosed. A stacked package-on-package memory device includes a base chip package unit having a logic processing chip disposed on a base substrate; and a memory chip stack overlying the base chip unit. The memory chip stack includes a stack of packaged memory units. Each packaged memory unit including a memory chip on an IC substrate. Copper pillars are disposed on the back side of the IC substrate and electrically connected to the base substrate. | 2016-02-04 |
20160035712 | MICROELECTRONIC PACKAGE WITH STACKED MICROELECTRONIC UNITS AND METHOD FOR MANUFACTURE THEREOF - A microelectronic package may include a first microelectronic unit including a semiconductor chip having first chip contacts, an encapsulant contacting an edge of the semiconductor chip, and first unit contacts exposed at a surface of the encapsulant and electrically connected with the first chip contacts. The package may include a second microelectronic unit including a semiconductor chip having second chip contacts at a surface thereof, and an encapsulant contacting an edge of the chip of the second unit and having a surface extending away from the edge. The surfaces of the chip and the encapsulant of the second unit define a face of the second unit. Package terminals at the face may be electrically connected with the first unit contacts through bond wires electrically connected with the first unit contacts, and the second chip contacts through metallized vias and traces formed in contact with the second chip contacts. | 2016-02-04 |
20160035713 | SEMICONDUCTOR ELEMENT AND SEMICONDUCTOR DEVICE - A semiconductor device includes a voltage generation circuit configured to generate a specific voltage; a first terminal configured to output the specific voltage; a second terminal configured to receive a temperature sensitive voltage; an analog/digital conversion circuit configured to convert the specific voltage and the temperature sensitive voltage to digital values; a storage unit configured to store the specific voltage and the temperature sensitive voltage; and a third terminal configured to transmit the specific voltage and the temperature sensitive voltage to an external semiconductor device. | 2016-02-04 |
20160035714 | SEMICONDUCTOR DEVICE - A semiconductor device includes a plurality of bit lines that intersect an active region on a substrate and extend in a first direction, a contact pad formed on the active region between adjacent bit lines, and a plurality of spacers disposed on sidewalls of the plurality of bit lines. An upper portion of the contact pad is interposed between adjacent spacers, and a lower portion of the contact pad has a width greater than a distance between adjacent spacers. | 2016-02-04 |
20160035715 | SYSTEM FOR DESIGNING A SEMICONDUCTOR DEVICE, DEVICE MADE, AND METHOD OF USING THE SYSTEM - A semiconductor device includes an edge active cell, an inner active cell and a middle active cell. The edge active cell is located near an edge of the semiconductor device. The edge active cell includes a plurality of fingers. The inner active cell is adjacent to the edge active cell toward a central portion of the semiconductor device. The inner active cell includes a plurality of fingers and at least one of the plurality of fingers of the edge active cell is electrically connected to at least one of the plurality of fingers of the inner active cell. The middle active cell is located near the central portion of the semiconductor device. The middle active cell includes a plurality of fingers and each of the fingers of the middle active cell is electrically connected to each other. | 2016-02-04 |
20160035716 | STRUCTURES, METHODS AND APPLICATIONS FOR ELECTRICAL PULSE ANNEAL PROCESSES - Structures and methods are provided for nanosecond electrical pulse anneal processes. The method of forming an electrostatic discharge (ESD) N+/P+ structure includes forming an N+ diffusion on a substrate and a P+ diffusion on the substrate. The P+ diffusion is in electrical contact with the N+ diffusion. The method further includes forming a device between the N+ diffusion and the P+ diffusion. A method of annealing a structure or material includes applying an electrical pulse across an electrostatic discharge (ESD) N+/P+ structure for a plurality of nanoseconds. | 2016-02-04 |
20160035717 | STRUCTURES, METHODS AND APPLICATIONS FOR ELECTRICAL PULSE ANNEAL PROCESSES - Structures and methods are provided for nanosecond electrical pulse anneal processes. The method of forming an electrostatic discharge (ESD) N+/P+ structure includes forming an N+ diffusion on a substrate and a P+ diffusion on the substrate. The P+ diffusion is in electrical contact with the N+ diffusion. The method further includes forming a device between the N+ diffusion and the P+ diffusion. A method of annealing a structure or material includes applying an electrical pulse across an electrostatic discharge (ESD) N+/P+ structure for a plurality of nanoseconds. | 2016-02-04 |
20160035718 | ELECTROSTATIC DISCHARGE DEVICES AND METHODS OF MANUFACTURE - Electrostatic discharge (ESD) devices and methods of manufacture are provided. The method includes forming a plurality of fin structures and a mesa structure from semiconductor material. The method further includes forming an epitaxial material with doped regions on the mesa structure and forming gate material over at least the plurality of fin structures. The method further includes planarizing at least the gate material such that the gate material and the epitaxial material are of a same height. The method further includes forming contacts in electrical connection with respective ones of the doped regions of the epitaxial material. | 2016-02-04 |
20160035719 | SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING THE SAME - Both a HEMT and a SBD are formed on a nitride semiconductor substrate. The nitride semiconductor substrate comprises a HEMT gate structure region and an anode electrode region. A first laminated structure is formed at least in the HEMT gate structure region, and includes first to third nitride semiconductor layers. A second laminated structure is formed at least in a part of the anode electrode region, and includes first and second nitride semiconductor layers. The anode electrode contacts the front surface of the second nitride semiconductor layer. At least in a contact region in which the front surface of the second nitride semiconductor layer contacts the anode electrode, the front surface of the second nitride semiconductor layer is finished to be a surface by which the second nitride semiconductor layer forms a Schottky junction with the anode electrode. | 2016-02-04 |
20160035720 | COMBINING ZTCR RESISTOR WITH LASER ANNEAL FOR HIGH PERFORMANCE PMOS TRANSISTOR - An integrated circuit containing a PMOS transistor may be formed by implanting boron in the p-channel source drain (PSD) implant step at a dose consistent with effective channel length control, annealing the PSD implant, and subsequently concurrently implanting boron into a polysilicon resistor with a zero temperature coefficient of resistance using an implant mask which also exposes the PMOS transistor, followed by a millisecond anneal. | 2016-02-04 |
20160035721 | Common Drain Semiconductor Device Structure and Method - In one embodiment, a common drain semiconductor device includes a substrate, having two transistors integrated therein. The substrate also includes a plurality of active regions on a major surface of the substrate. The active regions of each transistor may be interleaved. | 2016-02-04 |
20160035722 | SEMICONDUCTOR DEVICES AND STRUCTURES - An Integrated Circuit device, including: a first layer including first transistors; and a second layer including second transistors overlaying the first layer, where the first transistors are facing down and the second transistors are facing up, and where the second layer includes a through layer via of less than 300 nm diameter. | 2016-02-04 |
20160035723 | MACRO DESIGN OF DEVICE CHARACTERIZATION FOR 14NM AND BEYOND TECHNOLOGIES - The disclosure provides methods and devices for separately determining the channel resistance and the extension resistance of a FinFET. An exemplary embodiment includes forming first and second fins parallel to each other, forming at least one fin portion, connecting the first and second fins, forming a gate perpendicular to the first and second fins, over the at least one fin portion, forming a first source and a first drain over the first fin at opposite sides of the gate, and forming a second source and a second drain over the second fin, separate from the first source and drain, at opposite sides of the gate, wherein each of the first and second sources and first and second drains includes an extension region. | 2016-02-04 |
20160035724 | TUNGSTEN GATES FOR NON-PLANAR TRANSISTORS - The present description relates to the field of fabricating microelectronic devices having non-planar transistors. Embodiments of the present description relate to the formation of gates within non-planar NMOS transistors, wherein an NMOS work-function material, such as a composition of aluminum, titanium, and carbon, may be used in conjunction with a titanium-containing gate fill barrier to facilitate the use of a tungsten-containing conductive material in the formation of a gate electrode of the non-planar NMOS transistor gate. | 2016-02-04 |
20160035725 | TUNGSTEN GATES FOR NON-PLANAR TRANSISTORS - The present description relates to the field of fabricating microelectronic devices having non-planar transistors. Embodiments of the present description relate to the formation of gates within non-planar NMOS transistors, wherein an NMOS work-function material, such as a composition of aluminum, titanium, and carbon, may be used in conjunction with a titanium-containing gate fill barrier to facilitate the use of a tungsten-containing conductive material in the formation of a gate electrode of the non-planar NMOS transistor gate. | 2016-02-04 |
20160035726 | FIN SIDEWALL REMOVAL TO ENLARGE EPITAXIAL SOURCE/DRAIN VOLUME - A FinFET device includes a dielectric layer formed over a semiconductor substrate and having an upper dielectric layer surface. A fin of semiconductor material extends upwards from the substrate through an opening in the dielectric layer. A base portion of the fin, which is recessed below the upper dielectric layer surface, includes a base channel region that separates first and second base source/drain regions. An upper channel region extends upwards from the base channel region and terminates in an upper fin surface disposed above the upper dielectric layer surface. A gate electrode straddles the upper channel region and is separated from the upper channel region by a gate dielectric. First and second epitaxial source/drain regions meet the first and second base source/drain regions, respectively, at first and second interfaces, respectively. The first and second interfaces are recessed in the opening and arranged below the upper dielectric layer surface. | 2016-02-04 |
20160035727 | CMOS STRUCTURE WITH BENEFICIAL NMOS AND PMOS BAND OFFSETS - A CMOS structure with beneficial nMOS and pMOS band offsets is disclosed. A first silicon germanium layer is formed on a semiconductor substrate. A second silicon germanium layer is formed on the first silicon germanium layer. The second silicon germanium layer has a higher germanium percentage than the first silicon germanium layer. Furthermore, the germanium concentration of the two layers is selected such that there is a beneficial band offset for both N-type field effect transistors and P-type field effect transistors in a CMOS structure. | 2016-02-04 |
20160035728 | RETROGRADE DOPED LAYER FOR DEVICE ISOLATION - Embodiments herein provide device isolation in a complimentary metal-oxide fin field effect transistor. Specifically, a semiconductor device is formed with a retrograde doped layer over a substrate to minimize a source to drain punch-through leakage. A set of high mobility channel fins is formed over the retrograde doped layer, each of the set of high mobility channel fins comprising a high mobility channel material (e.g., silicon or silicon-germanium). The retrograde doped layer may be formed using an in situ doping process or a counter dopant retrograde implant. The device may further include a carbon liner positioned between the retrograde doped layer and the set of high mobility channel fins to prevent carrier spill-out to the high mobility channel fins. | 2016-02-04 |
20160035729 | Meander Line Resistor Structure - A system comprises a first transistor comprising a first drain/source region and a second drain/source region, a second transistor comprising a third drain/source region and a fourth drain/source region, wherein the first transistor and the second transistor are separated by an isolation region, a first resistor formed by at least two vias, wherein a bottom via of the first resistor is in direct contact with the first drain/source region, a second resistor formed by at least two vias, wherein a bottom via of the second resistor is in direct contact with the second drain/source region, a bit line connected to the third drain/source region through a plurality of bit line contacts and a capacitor connected to the fourth drain/source region through a capacitor contact. | 2016-02-04 |
20160035730 | SEMICONDUCTOR DEVICE - A semiconductor device according to this invention includes a support film that supports a lower electrode of a capacitor at an upper portion, and the support film includes a first insulating material having a stress within a range of +700 MPa to −700 MPa. Use of such a support film prevents a phenomenon in which the capacitor lower electrode is twisted. Preferably, the support film has a rate etched by hydrofluoric acid of 1.0 nm/sec or less and more preferably, the support film includes a silicon carbon nitride film. | 2016-02-04 |
20160035731 | SEMICONDUCTOR DEVICES AND METHODS OF MANUFACTURING SEMICONDUCTOR DEVICES - A method of manufacturing a semiconductor device includes forming an isolation pattern on a substrate to define active patterns each having a first contact region at a center portion thereof and second and third contact regions at edge portions thereof. The method further includes forming a buried gate structure at upper portions of the isolation pattern and the active patterns, forming a first insulation layer on the isolation pattern and the active patterns, and etching a portion of the first insulation layer and an upper portion of the first contact region to form a preliminary opening exposing the first contact region. The method still further includes etching the isolation pattern to form an opening, forming an insulation pattern on a sidewall of the opening, and forming a wiring structure contacting the first contact region in the opening. | 2016-02-04 |
20160035732 | THREE-DIMENSIONAL NON-VOLATILE MEMORY DEVICE - A semiconductor device includes at least one first conductive layer stacked on a substrate where a cell region and a contact region are defined; at least one first slit passing through the first conductive layer, second conductive layers stacked on the first conductive layer; a second slit passing through the first and second conductive layers and connected with one side of the first slit, and a third slit passing through the first and second conductive layers and connected with the other side of the first slit. | 2016-02-04 |
20160035733 | SEMICONDUCTOR CIRCUIT STRUCTURE - A NAND flash circuit structure includes two select gates disposed on a substrate, and an even number of spaced-apart word lines disposed between the two select gates. The select gate is provided with a first portion and a second portion. The thickness of the first portion and the second portion are different. | 2016-02-04 |
20160035734 | METHOD FOR MANUFACTURING A SEMICONDUCTOR DEVICE - The performances of a semiconductor device are improved. In a method for manufacturing a semiconductor device, in a memory cell region, a control gate electrode formed of a first conductive film is formed over the main surface of a semiconductor substrate. Then, an insulation film and a second conductive film are formed in such a manner as to cover the control gate electrode, and the second conductive film is etched back. As a result, the second conductive film is left over the sidewall of the control gate electrode via the insulation film, thereby to form a memory gate electrode. Then, in a peripheral circuit region, a p type well is formed in the main surface of the semiconductor substrate. A third conductive film is formed over the p type well. Then, a gate electrode formed of the third conductive film is formed. | 2016-02-04 |
20160035735 | ANTIFUSE ELEMENT UTILIZING NON-PLANAR TOPOLOGY - Techniques for providing non-volatile antifuse memory elements and other antifuse links are disclosed herein. In some embodiments, the antifuse memory elements are configured with non-planar topology such as FinFET topology. In some such embodiments, the fin topology can be manipulated and used to effectively promote lower breakdown voltage transistors, by creating enhanced-emission sites which are suitable for use in lower voltage non-volatile antifuse memory elements. In one example embodiment, a semiconductor antifuse device is provided that includes a non-planar diffusion area having a fin configured with a tapered portion, a dielectric isolation layer on the fin including the tapered portion, and a gate material on the dielectric isolation layer. The tapered portion of the fin may be formed, for instance, by oxidation, etching, and/or ablation, and in some cases includes a base region and a thinned region, and the thinned region is at least 50% thinner than the base region. | 2016-02-04 |
20160035736 | High Endurance Non-Volatile Memory Cell - The present disclosure relates to a non-volatile memory cell structure, and an associated method. A non-volatile memory cell includes two transistors spaced apart from one another with floating gates connected together by a floating gate bridge. During the operation, the non-volatile memory cell is programmed and erased from one first transistor and read from the other second transistor. Since the floating gates of the two transistors are connected together and insulated from other ambient layers, stored charges can be controlled from the first transistor and affect a threshold of the second transistor. | 2016-02-04 |
20160035737 | SYSTEM AND METHOD OF UV PROGRAMMING OF NON-VOLATILE SEMICONDUCTOR MEMORY - A method of forming a semiconductor memory storage device that includes forming first and second doped regions of a first type in a semiconductor substrate and laterally spaced from one another, forming a gate dielectric extends over the semiconductor substrate between the first and second doped regions, forming a floating gate on the gate dielectric, and forming an ultraviolet (UV) light blocking material vertically disposed above the floating gate such that the floating gate remains electrically charged after the semiconductor memory storage device is exposed to UV light. | 2016-02-04 |
20160035738 | Contact Hole Collimation Using Etch-Resistant Walls - Contact holes are constrained to their designated active areas by etch-resistant walls so that they cannot contact adjacent active areas. Etch-resistant walls provide outer limits for any contact hole bending that may occur and thus keep contact holes substantially vertical. Mask openings for contact hole formation may be large so that they overlap etch-resistant walls. | 2016-02-04 |
20160035739 | SEMICONDUCTOR DEVICE AND A MANUFACTURING METHOD THEREOF - The performances of a semiconductor device are improved. The semiconductor device has a first control gate electrode and a second control gate electrode spaced along the gate length direction, a first cap insulation film formed over the first control gate electrode, and a second cap insulation film formed over the second control gate electrode. Further, the semiconductor device has a first memory gate electrode arranged on the side of the first control gate electrode opposite to the second control gate electrode, and a second memory gate electrode arranged on the side of the second control gate electrode opposite to the first control gate electrode. The end at the top surface of the first cap insulation film on the second control gate electrode side is situated closer to the first memory gate electrode side than the side surface of the first control gate electrode on the second control gate electrode side. | 2016-02-04 |
20160035740 | NON-VOLATILE MEMORY DEVICE AND METHOD FOR MANUFACTURING SAME - According to an embodiment, a non-volatile memory device includes electrodes, an inter-layer insulating film between the electrodes and at least one semiconductor layer extending through the electrodes and the inter-layer insulating film. The device includes a charge storage layer between the semiconductor layer and each electrode, a first insulating film between the charge storage layer and the semiconductor layer, and a second insulating film. The second insulating film includes a first portion between the charge storage layer and each electrode, a second portion between each electrode and the inter-layer insulating film, and a third portion that links the first portion and the second portion. In a cross-section of the third portion parallel to the first direction and a second direction toward each electrode from the charge storage layer, a curved surface on the charge storage layer side has a curvature radius larger than a surface on the electrodes side. | 2016-02-04 |
20160035741 | NON-VOLATILE MEMORY DEVICE - According to an embodiment, a non-volatile memory device includes first electrodes arranged in a first direction, a second electrode disposed on a side of the first electrodes in the first direction, a semiconductor layer extending in the first direction through the first electrodes and the second electrode, and a memory film provided between the semiconductor layer and each of the first electrodes. The semiconductor layer includes crystal grains and has a first portion and a second portion, the first portion being adjacent to the first electrodes, and the second portion being adjacent to at least a part of the second electrode, wherein the first portion includes a larger crystal grain than a crystal grain in the second portion. | 2016-02-04 |
20160035742 | SPACER PASSIVATION FOR HIGH-ASPECT RATIO OPENING FILM REMOVAL AND CLEANING - A method of making a semiconductor device includes forming a stack of alternating layers of a first material and a second material over a substrate, etching the stack to form at least one opening in the stack such that a damaged region is located on a bottom surface of the at least one opening, forming a masking layer on a sidewall of the at least one opening while the bottom surface of the at least one opening is not covered by the masking layer, and further etching the bottom surface of the at least one opening remove the damaged region. | 2016-02-04 |
20160035743 | FIELD EFFECT TRANSISTOR (FET) WITH SELF-ALIGNED CONTACTS, INTEGRATED CIRCUIT (IC) CHIP AND METHOD OF MANUFACTURE - Field Effect Transistors (FETs), Integrated Circuit (IC) chips including the FETs, and a method of forming the FETs and IC. FET locations and adjacent source/drain regions are defined on a semiconductor wafer, e.g., a silicon on insulator (SOI) wafer. Source/drains are formed in source/drains regions. A stopping layer is formed on source/drains. Contact spacers are formed above gates. Source/drain contacts are formed to the stopping layer, e.g., after converting the stopping layer to silicide. The contact spacers separate source/drain contacts from each other. | 2016-02-04 |
20160035744 | ARRAY SUBSTRATE AND DISPLAY DEVICE - An array substrate and a display device, the array substrate comprises a fan-out area ( | 2016-02-04 |
20160035745 | DISPLAY SUBSTRATE AND FABRICATING METHOD THEREOF, DISPLAY PANEL, AND DISPLAY DEVICE - The present invention provides a display substrate and a fabricating method thereof, a display panel, and a display device. The display substrate comprises a base substrate, gate lines and data lines formed on the base substrate, and at least one pixel unit defined by the gate lines and the date lines, wherein, each pixel unit comprises a thin film transistor and a pixel electrode, and in each pixel unit, a drain electrode of the thin film transistor is electrically connected with the pixel electrode by at least part of an edge region of at least one side of the drain electrode. The technical solution of the present invention can increase the number of contact points and/or contact area for connecting the pixel electrode and the drain electrode, and thus display quality is improved. | 2016-02-04 |
20160035746 | ARRAY SUBSTRATE, METHOD FOR MANUFACTURING THE SAME AND DISPLAY DEVICE - Disclosed is an array substrate, a method of manufacturing the same, and a display device in use of the array substrate. The array substrate includes a gate electrode layer and a pixel electrode layer on a substrate. The gate electrode layer and the pixel electrode layer are stacked in contact with each other. The pixel electrode layer includes a first part and a second part separated from each other, the gate electrode layer includes a first part. The first part of the gate electrode layer and the first part of the pixel electrode layer are positioned as face-to-face. The gate electrode includes the first part of the gate electrode layer and the first part of the pixel electrode layer, and the pixel electrode includes the second part of the pixel electrode layer. The patterns of gate electrode layer and pixel electrode layer are manufactured with the same mask, which reduces the number of masks. | 2016-02-04 |
20160035747 | ARRAY SUBSTRATE AND FABRICATION METHOD THEREOF - An array substrate and a fabrication method thereof are provided. The array substrate comprises a plurality of wiring regions (S-S′) disposed in a non-display region, a plurality of signal lines ( | 2016-02-04 |
20160035748 | ARRAY SUBSTRATE, METHOD FOR MANUFACTURING THEREOF, AND DISPLAY DEVICE - Disclosed is an array substrate, a method for manufacturing the same, and a display device. The array substrate includes: a base substrate and a plurality of data lines disposed on the base substrate, The base substrate comprises a plurality of attaching areas in which the end of each data line attaches to the base substrate, and non-attaching areas between each two adjacent attaching areas, and a height layer is disposed between a passivation layer and the base substrate in the non-attaching area. By interposing a height layer between the passivation layer and the base substrate in the non-attaching area, the height difference between the passivation layer in the attaching area and the non-attaching area is decreased or disappeared, then the problem of fall-off of the passivation layer is solved, and the reliability of the product is increased. | 2016-02-04 |
20160035749 | ARRAY SUBSTRATE HAVING INTEGRATED GATE DRIVER AND METHOD OF FABRICATING THE SAME - An array substrate includes: a substrate; a gate connecting line on the substrate in a gate circuit area; a gate insulating layer on the gate connecting line; an active pattern on the gate insulating layer; a source connecting line and a pixel pattern sequentially disposed on the active pattern; an interlayer insulating layer and an organic pattern sequentially disposed on the gate insulating layer; a first passivation layer on the organic pattern; and a conductive pattern on the first passivation layer, the conductive pattern coupled to the gate connecting line and to the pixel pattern. | 2016-02-04 |
20160035750 | THIN FILM TRANSISTOR ARRAY PANEL AND MANUFACTURING METHOD THEREOF - A thin film transistor array panel is provided. A thin film transistor is positioned on a substrate. A first passivation layer is positioned on the thin film transistor. A common electrode is positioned on the first passivation layer. A second passivation layer positioned on the common electrode. A pixel electrode is positioned on the second passivation layer. The pixel electrode is coupled to the thin film transistor through a first contact hole penetrating the first passivation layer, the common electrode, and the second passivation layer. A first part of the first contact hole formed in the common electrode is larger than a second part of the first contact hole formed in the second passivation layer. | 2016-02-04 |
20160035751 | DISPLAY DEVICE AND DISPLAY PANEL THEREOF - A display panel is provided. A display panel includes a plurality of pixels and a plurality of gate lines. The pixels include a first pixel, a second pixel and a third pixel. The gate lines include a first gate line, a second gate line and a third gate line. The first gate line drives the first pixel. The second gate line drives the second pixel. The third gate line drives the third pixel. The first gate line, the second gate line and the third gate line are disposed sequentially and driven at different time. The first pixel and the second pixel are arranged respectively at two opposite sides of the first gate line and the second gate line. The second pixel and the third pixel are arrange between the second gate line and the third gate line. | 2016-02-04 |
20160035752 | Display Device and Method of Manufacturing the Same - A display device and a method of manufacturing the same are disclosed, in which a sensing electrode for sensing a touch of a user is built in a display panel, whereby a separate touch screen is not required on an upper surface of the display panel and thus thickness and manufacturing cost are reduced. | 2016-02-04 |
20160035753 | Complementary Thin Film Transistor and Manufacturing Method Thereof, Array Substrate, Display Apparatus - The present invention provides a complementary thin film transistor and a manufacturing method thereof, an array substrate and a display apparatus, relates to the field of manufacturing technology of thin film transistor, and can solve the problem that active layer materials of first and second thin film transistors in a complementary thin film transistor of the prior art have influence with each other. The manufacturing method of the present invention comprises steps of: forming a pattern comprising an active layer of a first thin film transistor and a protective layer on a base by a patterning process, and the protective layer is at least located above the active layer of the thin film transistor; and forming a pattern of an active layer of a second thin film transistor on the base subjected to above step by a patterning process. The present invention may be applied to various circuits and systems. | 2016-02-04 |
20160035754 | SEMICONDUCTOR DEVICE, MANUFACTURING METHOD THEREOF, AND DISPLAY APPARATUS - Provided is a semiconductor device including a buffer layer that is on a substrate and includes an inclined surface; a crystalline silicon layer that is on the buffer layer; a gate electrode that is on the crystalline silicon layer while being insulated from the crystalline silicon layer; and a source electrode and a drain electrode that are each electrically connected to the crystalline silicon layer, the angle between the substrate and the inclined surface being in a range of about 17.5 degrees to less than about 70 degrees. | 2016-02-04 |
20160035755 | ARRAY SUBSTRATE AND MANUFACTURING METHOD THEREOF, DISPLAY DEVICE - The present invention provides array substrate and manufacturing method thereof and display device. The manufacturing method comprises: forming patterns including active regions of first and second TFTs by patterning process on substrate; forming gate insulation layer on the substrate; forming patterns including gates of the TFTs by patterning process on the substrate; forming isolation layer on the substrate; forming, on the substrate, second contacting vias for connecting sources and drains of the TFTs to respective active regions and first contacting via for connecting gate of the second TFT to source of the first TFT; and on the substrate, forming patterns of corresponding sources and drains on the second contacting vias above active regions of the TFTs, and meanwhile forming connection line for connecting gate of the second TFT to source of the first TFT above the first contacting via above gate of the second TFT. | 2016-02-04 |
20160035756 | THIN FILM TRANSISTOR, METHOD FOR MANUFACTURING THIN FILM TRANSISTOR, ARRAY SUBSTRATE, METHOD FOR MANUFACTURING ARRAY SUBSTRATE, AND DISPLAY DEVICE - The present disclosure relates to the field of display technology, and provides a TFT, a method for manufacturing the TFT, an array substrate, a method for manufacturing the array substrate, and a display device. The method for manufacturing the TFT includes a step of forming a pattern including a source electrode, a drain electrode and an active layer by a single patterning process, wherein the source electrode, the drain electrode and the active layer are arranged at an identical layer, and the active layer is arranged between the source electrode and the drain electrode. | 2016-02-04 |