| 05th week of 2010 patent applcation highlights part 69 |
| Patent application number | Title | Published |
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| 20100030902 | Method for managing a communication between a server device and a customer device - A method is described for managing a communication between a server device and a customer device. The method comprises interchanging between the server device and the customer device one or more parameter messages that are comprising a parameter description for a parameter name. The parameter description does consist of an hierarchical tree-like structure of characters with each level separated by a predefined character (dot). The method further comprises a step of instantiating by an instantiating device of the customer device, an iterator associated to an index, for a next level of a parameter-sub-tree being part of the global parameter description, and a step of recalling an object array for the parameter-sub-tree with the next level having different values for its index starting with a predefined start-value and ending with a predefined end-value. | 2010-02-04 |
| 20100030903 | MODEM AND CONFIGURATION METHOD THEREOF - A modem includes a dynamic host configuration protocol (DHCP) module, a point-to-point protocol over Ethernet (PPPoE) module, and a network monitor module. The DHCP module automatically establishes a DHCP connection over a communication network, and generates a first notification signal after the DHCP connection is established. The PPPoE module automatically establishes a PPPoE connection over the communication network and automatically configures parameters of an Internet access service over the communication network and generates a second notification signal after the PPPoE connection is established. The network monitor module determines current network properties of the communication network upon receipt of the first notification signal and/or the second notification signal, and selectively configures parameters of the Internet access service and a voice over Internet protocol (VoIP) service. | 2010-02-04 |
| 20100030904 | USER DEVICE, CONTROL METHOD THEREOF, AND IMS USER EQUIPMENT - There is provided a user device that is equipped with IMS functionality. The user device includes: searching means for searching, based on UPnP technology, a UPnP network for another user device that has IMS subscription information, establishing means for establishing a session with the other user device discovered by the searching means, retrieving means for retrieving the IMS subscription information from the other user device via the session, and sending means for sending a first SIP register message including the IMS subscription information to an IMS network. | 2010-02-04 |
| 20100030905 | Technique for providing services in a service provisioning network - The invention relates to techniques for providing services in a service provisioning network ( | 2010-02-04 |
| 20100030906 | RE-ESTABLISHING A CONNECTION FOR AN APPLICATION LAYER VIA A SERVICE LAYER - A method and system for establishing a connection with a server after a connection has been broken is provided. A connection system in a service layer of a client detects that a connection between the client and the server has been broken. Upon detecting the broken connection, the connection system of the service layer automatically attempts to re-establish an application-level connection to the server. If the connection system can re-establish an application-level connection to the server, then it need not notify the application layer of the broken connection. | 2010-02-04 |
| 20100030907 | Method and Arrangement for the Composition of a First and a Second Communication Access Network - A method and an associated arrangement for the registration of a first communication access network N | 2010-02-04 |
| 20100030908 | METHOD AND SYSTEM FOR TRIGGERING INGESTION OF REMOTE CONTENT BY A STREAMING SERVER USING UNIFORM RESOURCE LOCATOR FOLDER MAPPING - A method and system to trigger ingestion of remote content or playlists by a streaming server using URL folder mapping is disclosed. The streaming server maintains a URL Map having entries that map a URL folder referenced in the streaming URL to a content server folder located on the content server. This folder level mapping enables maintaining a many-to-many relationship between multiple content identified at the streaming server and their corresponding content located at the content server. | 2010-02-04 |
| 20100030909 | CONTRIBUTION AWARE PEER-TO-PEER LIVE STREAMING SERVICE - A method and system for live streaming in a peer-to-peer network are described including determining peer entitled and excess degree, identifying and contacting a potential parent peer and executing a contribution aware connection policy. | 2010-02-04 |
| 20100030910 | SoC DEVICE WITH INTEGRATED SUPPORTS FOR ETHERNET, TCP, iSCSi, RDMA AND NETWORK APPLICATION ACCELERATION - A method for processing data is disclosed and may include performing by one or more processors and/or circuits on a chip that handles a plurality of networking protocols, receiving data for one or more network connections corresponding to one or more of the plurality of networking protocols. The chip may be configured for handling the received data based on whether the one or more of the plurality of networking protocols associated with the received data includes transmission control protocol and/or remote direct memory access protocol. The received data may be processed based on the configuration. At least one RDMA marker may be removed from the received data when the received data includes the RDMA protocol, and/or the received data is processed based on a transmission control protocol session identification within the received data. | 2010-02-04 |
| 20100030911 | DATA TRANSFER ACCELERATION SYSTEM AND ASSOCIATED METHODS - A method for accelerating data transfer over a network between a first computer and a second computer includes establishing a plurality of connections for transferring data. The plurality of connections may be established between the first computer and the second computer and may be defined as a virtual circuit. The method may also include de-multiplexing the data into a plurality of data packets and assigning sequence numbers to each of the data packets. The method may further include transmitting the plurality of data packets through the virtual circuit in an order corresponding to the assigned sequence numbers, and receiving the plurality of data packets regardless of the assigned sequence number. The method may still further include sequencing the plurality of data packets into an order corresponding to the assigned sequence number and multiplexing the plurality of data packets. | 2010-02-04 |
| 20100030912 | Method for the transmission of data in a communication network - A method for transmitting data in a communication network, features network management-controlled transmission of data via a data transmission channel that connects network nodes. According to the method, data is transmitted at a minimum desired transmission rate that results from a temporal usage of the data transmission channel. | 2010-02-04 |
| 20100030913 | COMMUNICATION CONTROLLING METHOD FOR NETWORK MANAGING DEVICE - The present invention relates to a communication controlling method, and more particularly, to a communication controlling method for a network managing device that can control a speed of a network and a transmission/reception amount of packets according to a communication situation. A communication controlling method for a network managing device includes the steps of judging a speed of a connected network or a transmission/reception amount of packets, setting an increase/decrease amount of an event transmission interval of a network device according to the judgment result, and transmitting the set increase/decrease amount of the event transmission interval to the network device through the network. | 2010-02-04 |
| 20100030914 | METHODS, SYSTEMS, AND COMPUTER READABLE MEDIA FOR THROTTLING TRAFFIC TO AN INTERNET PROTOCOL (IP) NETWORK SERVER USING ALIAS HOSTNAME IDENTIFIERS ASSIGNED TO THE IP NETWORK SERVER WITH A DOMAIN NAME SYSTEM (DNS) - Methods, systems, and computer readable media for throttling traffic to an IP network server using alias hostname identifiers assigned to the IP network server with a domain name system are disclosed. One method includes maintaining a plurality of weight values and corresponding alias hostname identifiers for the IP network server that are associated with the IP network server in a DNS system. The method further includes throttling network traffic sent to an IP network server by sending, from the IP network server, messages to nodes that send the traffic to the IP network server, where the messages selectively enable or disable traffic flow to the individual alias hostnames. | 2010-02-04 |
| 20100030915 | SYSTEM AND METHOD FOR ROUTING COMMANDS IN A MODULARIZED SOFTWARE SYSTEM - Converged network management application and system is provided that delivers a management platform as a service that can view and/or manage all managed networks in the aggregate, or any one of them individually (including individual devices within the managed networks), in a secure and efficient manner, providing continuously available intelligence in real time on the managed networks and systems, and overcoming integration issues including conflicting address schemas, the need to avoid unnecessary infrastructure, and the need acquire all necessary information in real time within applicable memory and bandwidth constraints. | 2010-02-04 |
| 20100030916 | METHOD AND SYSTEM FOR DISTRIBUTING CLOCK SIGNALS - A system and method for distributing accurate time signals comprises a plurality of base stations distributed over an area and a plurality of time receivers. The plurality of base stations receive time signals from a GPS system and transmits time signal packets. The plurality of time receives time signal packets from one or more base stations. Each time receiver is located at or near a measurement point and is operable to estimate a corrected time by a triangulation process from a received time signal packet. | 2010-02-04 |
| 20100030917 | Signal processing apparatus, signal processing method, and program - A signal processing apparatus includes: a connecting means for use in connecting to a different device; a signal control means for changing a control signal to be outputted to the different device through the connecting means for a predetermined period; a changing means for changing the predetermined period; a determining means for determining for each of the predetermined periods changed by the changing means whether the different device stably makes a response to a change in the control signal caused by the signal control means; and a deciding means for deciding a shortest predetermined period from the predetermined periods determined by the determining means that the different device stably makes a response, as a standby time for the different device connected through the connecting means. | 2010-02-04 |
| 20100030918 | TRANSPORT CONTROL CHANNEL PROGRAM CHAIN LINKED BRANCHING - A computer program product, apparatus, and method for processing a transport control channel program with chain linked branching in an I/O processing system are provided. The method includes receiving a command message at a control unit from an I/O subsystem to perform an I/O operation. The method further includes reading a chain linked flag in the command message indicating that a subsequent command message for the I/O operation follows the command message. The method also includes reading a serialization flag in the command message requesting that device status be returned to the I/O subsystem in order to select the subsequent command message. The method additionally includes executing one or more commands in the command message, and transmitting the device status to the I/O subsystem in response to executing the one or more commands in combination with the serialization flag. | 2010-02-04 |
| 20100030919 | TRANSPORT CONTROL CHANNEL PROGRAM MESSAGE PAIRING - A method, apparatus, and computer program product for processing a chained-pair linked transport control channel program in an I/O processing system is provided. The method includes receiving a first command message at a control unit specifying that a device command word (DCW) list is encoded in a data message associated with the first command message as part of the chained-pair linked transport control channel program. The method further includes receiving a second command message chained-pair linked to the first command message, the second command message specifying data attributes associated with the DCW list. The method additionally includes extracting the DCW list from the data message in response to receiving the data message, and executing the DCW list. | 2010-02-04 |
| 20100030920 | TRANSPORT CONTROL CHANNEL PROGRAM CHAIN LINKING - A method, apparatus, and computer program product for processing a chain linked transport control channel program in an I/O processing system is provided. The method includes receiving a first command message at a control unit specifying a first predetermined sequence number for performing a first set of one or more commands as part of an I/O operation. The method further includes receiving a second command message specifying a second predetermined sequence number for performing a second set of one or more commands as part of the I/O operation. The method also includes comparing the sequence numbers to a next expected predetermined sequence number to determine an order of performing the commands. The method additionally includes executing the commands in the determined order to perform the I/O operation. | 2010-02-04 |
| 20100030921 | STORAGE DEVICE WITH DISPLAY UNIT AND METHOD OF DISPLAYING INFORMATION - A portable storage device includes a display unit that allows a user to easily determine the content stored in the storage device independent of any connection to another device. The storage device extracts information that represents data stored in the data storage unit based on user settings or a search history and displays the information. Accordingly, the information stored in the storage device may be easily categorized and identified. | 2010-02-04 |
| 20100030922 | COMPUTER PERIPHERAL DEVICE IMPLEMENTED AS OPTIC STORAGE DEVICE OR/AND REMOVABLE DISK BY SOFTWARE EMULATION AND IMPLEMENTING METHOD THEREOF - The present invention relates to a method of implementing an internal memory of a computer peripheral device as an optical storage device or/and a removable disk by software emulation. The computer peripheral device does not include additional hardware for driving the computer peripheral device as an optical storage device or/and a removable disk. A part of the internal memory of the computer peripheral device functions as a virtual optical storage device or/and a removable disk through software emulation. To achieve this, an emulation program is added to the computer peripheral device. The internal memory stores a program for recognizing the operating system and hardware type of a host as well as a device utilization application. | 2010-02-04 |
| 20100030923 | I/O DEVICE N_PORT ID VIRTUALIZATION - An I/O device obtains multiple unique N_Port IDs (identifiers) for a NPIV N_Port ID Virtualization (NPIV) capable physical adapter. Fabric management routines are able to assign the multiple unique N_Port IDs to distinct fabric zones. LUNs (logical unit numbers) are able to be associated with the multiple unique N_Port IDs such the LUNs associated with unique N_Port ID do not exceed a limitation. The I/O device is able to associate different resources with different unique N_Port IDs to limit the scope of actions of one or more hosts. The I/O device is able to configure one or more LUNs by the multiple unique N_Port IDs to control access. Different unique N_Port IDs are able to be configured to have different quality of service attributes and/or different levels of security. The I/O device may include multiple independent logical partitions (LPARs) and assign each multiple unique N_Port IDs. | 2010-02-04 |
| 20100030924 | HIGH SIGNAL LEVEL COMPLIANT INPUT/OUTPUT CIRCUITS - A signal interface circuit has a signal path for communicatively coupling host circuitry to peripheral circuitry of multiple peripherals. Communication signals in the signal path are of a peripheral signal level. The signal path has electronic components adapted for use in communicating signals between the host circuitry and the peripheral circuitry. The electronic components in the signal path have reliability limits less than the peripheral signal level. The configuration of the electronic components in the signal path allow communication of signals at the peripheral signal level. | 2010-02-04 |
| 20100030925 | PRINTER AND CONTROL METHOD THEREOF - A printer includes: a USB connector that is detachably connected to a USB interface forming a data communication channel through which data can be exchanged between the printer and an external device; a second connector that is constantly connected to a second interface that is provided independently of the USB interface and forms a data communication channel through which data can be exchanged between the printer and the external device; a USB connection detection section that detects whether the USB interface is connected to the USB connector; a signal channel selection section that receives a switch control signal from the USB connection detection section and switches a data communication channel from the data communication channel using the second interface through which data is exchanged between the printer and external device to a data communication channel using the USB interface; a signal conversion section that is provided between the signal channel selection section and second connector and coverts USB data signal into a data signal for the second interface and vice versa; and a USB controller that controls USB connection. | 2010-02-04 |
| 20100030926 | SIGNALING DEVICE FOR DETECTING THE PRESENCE OF AN OBJECT - A sheet switch ( | 2010-02-04 |
| 20100030927 | GENERAL PURPOSE HARDWARE ACCELERATION VIA DEIRECT MEMORY ACCESS - A method and system in which one or more hardware accelerators are directly accessible via a direct memory access controller (DMAC) including an internal mechanism. In some embodiments, the internal mechanism may include a local interconnect in the DMAC. In other embodiments, a DMAC structure includes a mechanism that provides for streaming data through hardware accelerators and allows for simultaneous reads and writes among multiple endpoint pairs transferring data. For added flexibility and increased independence from a microprocessor, a DMAC may include a command decoder that discovers, decodes and interprets commands in a data stream. | 2010-02-04 |
| 20100030928 | MEDIA PROCESSING METHOD AND DEVICE - A media processing system and device with improved power usage characteristics, improved audio functionality and improved media security is provided. Embodiments of the media processing system include an audio processing subsystem that operates independently of the host processor for long periods of time, allowing the host processor to enter a low power state. Other aspects of the media processing system provide for enhanced audio effects such as mixing stored audio samples into real-time telephone audio. Still other aspects of the media processing system provide for improved media security due to the isolation of decrypted audio data from the host processor. | 2010-02-04 |
| 20100030929 | DEVICE FOR CONNECTION WITH A STORAGE DEVICE AND A HOST - A dual-interface connector for providing an interface to a storage device and an interface to a host and for connecting between a storage device and a host includes a storage device interface, for connecting with a storage device, and a host interface, for connecting with a host. A controller is operable in at least two distinct modes of operation. In a first mode of operation, the controller enables a session to be opened, by the host, between the storage device and the host when the storage device is connected to the storage device interface and the host is connected to the host interface. In a second mode of operation, the controller is operative, if an open session exists between the storage device and the host, to maintain the open session between the storage device and the host even after the storage device is disconnected from the storage device interface. | 2010-02-04 |
| 20100030930 | BANDWIDTH CONSERVING PROTOCOL FOR COMMAND-RESPONSE BUS SYSTEM - A command-response bus protocol reduces the number of response transactions generated on a bus. According to an embodiment, an array of data is divided into a number of packets and transmitted over the bus in respective transactions. The transactions each include a writeback flag, which is enabled for the last packet but otherwise disabled. When a receiver of the packets observes the enabled writeback flag, it generates a response transaction. The response transaction indicates either that all packets of the array were received properly or that the commanded operation has been completed for the entire array. Overall, the number of bus transactions are reduced with respect to alternative schemes that require a response transaction for each transmitted packet. | 2010-02-04 |
| 20100030931 | Scheduling proportional storage share for storage systems - A system for scheduling proportional sharing of storage shares includes one or more hosts which are IO attached to storage system including a storage coordinator, a buffer, and one or more storage devices which are provided as one or more storage shares. A storage share scheduler of the storage coordinator propagates an IO request to the one or more storage devices when a ranking value tagged to the IO request is higher than and/or equal to that of other IO requests. The storage share scheduler stores an IO request in the buffer when the ranking value of the IO request is lower than that of at least one other IO request. The storage share scheduler schedules the IO request stored in the buffer to be propagated when the ranking value is higher than and/or equal to the ranking value of the other IO requests. | 2010-02-04 |
| 20100030932 | SYSTEM AND METHOD OF PROCESSING DATA ON A PERIPHERAL DEVICE - A system and method for processing data on a peripheral device that is operatively coupled to a host computing system via a peripheral bus. The compression of input data transmitted to the peripheral device and/or the size of the storage provided on the peripheral device may enhance the efficiency of the processing of the data on the peripheral device by obviating a bottleneck caused by the relatively slow transfer of data between the host computing system and the peripheral device. | 2010-02-04 |
| 20100030933 | NON-VOLATILE MEMORY STORAGE DEVICE AND OPERATION METHOD THEREOF - A non-volatile memory storage device has a non-volatile memory, e.g., a flash memory, and a controller coupled to the non-volatile memory. The controller comprises a plurality of control circuits and an arbitration circuit. Each control circuit is configured to generate a request to update the chip-enable (CE) signals for non-volatile memory, and the arbitration circuit is configured to determine when the requests are acknowledged. The arbitration circuit generates acknowledge signals to the control circuits when all of the requests of the control circuits have been received by the arbitration circuit. The CE signals for non-volatile memory are updated when requests are acknowledged. | 2010-02-04 |
| 20100030934 | Bus Termination System and Method - A memory system includes a number of integrated circuit chips coupled to a bus. Each of the integrated circuit chips has an input/output node coupled to the bus, the input/output node having a programmable on-die termination resistor. The input/output node of one of the integrated circuit chips is accessed via the bus. The programmable on-die termination resistor of each of the integrated circuit chips is independently set to a termination resistance. The termination resistance is determined by a transaction type and which of the plurality memory devices is being accessed, which information can be transmitted over a separate transmission control bus. | 2010-02-04 |
| 20100030935 | Modbus Register Data Reformatting - A Modbus data protocol register formatting system and method are disclosed. The system and method provide for the Modbus communications protocol request and recall of data stored in a register in the data base native format, and the conversion of the data into a different requested format. The system and method similarly provide for the writing of data into a device register from a known variable format into the data base native format. The ability to convert the data by a format converter after recalling the data, or before storing the data, obviates the need to store or write data in different or multiple formats. The inventive method uses a modified register mapping that comprises defined mapping elements identifying the data address location, the requested data format, along with the data variable. The register mapping is fully variable to provide for a wide range of data formats and data address formats. The inventive system uses, in addition to the Modbus master and slave devices, a format converter that converts the data recalled into the requested data format, or converts the data to be written into the slave device native data format. | 2010-02-04 |
| 20100030936 | INTEGRATED CIRCUIT AND ELECTRONIC DEVICE | 2010-02-04 |
| 20100030937 | Method and system for redundantly controlling a slave device - The disclosure provides a control and data transmission installation for redundantly controlling a slave device, which may be a field transmitter. The effect achieved by the control and data transmission installation is that essentially seamless control of a field transmitter can be assured even when a control device fails. The control and data transmission installation has at least two control devices and at least one slave device which are connected to one another by a communication network. The slave device contains addressable output interfaces for receiving output and status data. Each control device has a device for producing and transmitting status and output data for a separate output interface of the slave device, and the slave device has an evaluation device which controls the forwarding of received output data for further use in response to the status signals received from the control devices. | 2010-02-04 |
| 20100030938 | CONTROLLER AND METHOD FOR DIRECT MEMORY ACCESS - A DMA controlling method comprises the steps of: building a linking table, wherein the linking table records the status of each memory block and of a pointer pointing to a next memory block; activating a first memory block; receiving an interrupt signal and linking to a next associated memory block after the first memory block finishes a data transfer; activating the next associated block; and updating the linking table to release the first memory block for reuse. | 2010-02-04 |
| 20100030939 | REQUEST CONTROLLER, PROCESSING UNIT, ARRANGEMENT, METHOD FOR CONTROLLING REQUESTS AND COMPUTER PROGRAM PRODUCT - An request controller for controlling requests of a processing unit. The request controller may include an request controller input for receiving an request and an request processing unit connected to the request controller input. The request may request to switch a context of said processing unit or to switch the processing unit from a current an operation to another operation. The request processing unit may decide on the request based on a decision criterion. An request controller output may be connected to the request processing unit, for outputting information about at least granted request request. The request processing unit may include a control logic unit including: a state input for receiving information about a current state of a system including the processing unit; and a request input for receiving information about a received request request. The control logic unit may be arranged to determine whether the received request belongs to the current state of the processor, to grant the request when the received request does belong to the current state and to reject the request in case the request does not belong to the current state. The control logic unit may further include a control logic output for outputting an request grant signal when the request is granted. | 2010-02-04 |
| 20100030940 | DEVICE AND METHOD FOR SCHEDULING TRANSACTIONS OVER A DEEP PIPELINED COMPONENT - A device and a method, the device has transaction scheduling capabilities, and includes: (i) a memory unit adapted to output data at a first data rate, (ii) a data transaction initiator adapted to receive data at a second data rate that is lower than the first data rate; (iii) a deep pipelined crossbar characterized by a latency; and (iv) a data rate converter connected between the deep pipelined crossbar and the data transaction initiator; wherein the data rate converter is adapted to schedule a transaction of data unit from the memory unit in response to the latency of the deep pipelined crossbar, the first data rate, the second data rate, and size of an available storage space, within the data rate converter allocated for storing data from the memory unit. | 2010-02-04 |
| 20100030941 | METHOD AND SYSTEM FOR CONNECTING MULTIPLE IDE DEVICES TO A USB APPARATUS USING A SINGLE USB-TO-IDE ADAPTER - A single USB-to-IDE adapter ( | 2010-02-04 |
| 20100030942 | ENCODED CHIP SELECT FOR SUPPORTING MORE MEMORY RANKS - Method and systems are disclosed for increasing the number of ranks supported in a memory system. In one embodiment, a plurality of predefined subsets of memory chips on a memory module is selected. A chip select signal uniquely identifying the selected subset of memory chips is generated. The chip select signal is encoded as a multi-bit word having a bit width that is less than the number of predefined subsets of memory chips. Each bit of the encoded chip select signal is transmitted along a separate chip select line. The transmitted chip select signal is decoded to determine the identity of the selected subset of memory chips. The selected subset of memory chips identified by the decoded chip select signal are read or written. | 2010-02-04 |
| 20100030943 | Semiconductor Memory - A semiconductor memory having a burst mode reading function in synchronization with a clock signal comprises a memory array composed of a plurality of memory cells, a sync read control circuit for releasing an upper group of the received address as a memory access address and a lower group of the received address as a burst address in synchronization with the clock signal, a sense amplifier for releasing an output data from each of the memory cells selected by the memory address, a decoder for decoding the burst address, a address latch for latching the decoded burst address in synchronization with the clock signal, a page selector for holding the output data and selecting corresponding one of the output data determined by the burst address of the address latch, and an output latch for latching the output data in synchronization with the clock signal. | 2010-02-04 |
| 20100030944 | Method and Apparatus for Storing Data in Solid State Memory - A method and a storage device for storing data in a flash memory drive are disclosed. In order to increase data throughput, the drive includes a cache memory including a tag memory and a plurality of flash devices coupled via a plurality of channels to the cache memory. | 2010-02-04 |
| 20100030945 | FLASH MEMORY ALLOCATING METHOD - An allocating method for a flash memory is disclosed. The allocating method includes the following steps: adjusting a preliminary data storage capacity corresponding to the flash memory for determining a real data storage capacity of the flash memory; adjusting a preliminary spare area capacity corresponding to the flash memory for determining a real spare area capacity of the flash memory, wherein a total capacity of the preliminary data storage capacity and the preliminary spare area capacity is equal to the total capacity of the real data storage capacity and the real spare area capacity; and allocating the real data storage capacity and the real spare area capacity to the flash memory, wherein the real data storage capacity stores data, and the real spare area capacity stores parity codes generated by an error codes correction algorithm performed upon the stored data in the real data storage capacity. | 2010-02-04 |
| 20100030946 | STORAGE APPARATUS, MEMORY AREA MANAGING METHOD THEREOF, AND FLASH MEMORY PACKAGE - A storage device is provided, which allows a write area associated with a data area of interest to be allocated according to write performance of a host computer. The storage apparatus includes one or more flash memory packages having a plurality of flash memories and stores data transmitted from one or more host computers. A storage area provided by the one or more flash memory packages includes a first area that is an area for storing actual data formed by one or more logical devices and a second area that is an area for storing a write instruction from the host computer to the logical device. The first and second areas are provided in each of the one or more flash memory packages. The apparatus further includes a monitoring section monitoring the frequency of write instructions from the host computer and a changing section for changing the size of the second area according to the frequency of write instructions. | 2010-02-04 |
| 20100030947 | HIGH-SPEED SOLID STATE STORAGE SYSTEM - A solid state storage device includes a main memory cell array and a sub-memory area. The main memory cell array stores data in a flash memory, whereas the sub-memory includes a non-volatile random access memory for storing data. The data storage speed of the non-volatile random access memory of the sub-memory area is faster than the data storage speed of the flash memory of the main memory cell area. The sub-memory area of the solid state storage device also stores address mapping information therein, so that the address mapping information does not have to be transferred to the main memory cell area and a portion of the main memory cell area does not have to be designated for a non-volatile memory for storing the address mapping information. | 2010-02-04 |
| 20100030948 | SOLID STATE STORAGE SYSTEM WITH DATA ATTRIBUTE WEAR LEVELING AND METHOD OF CONTROLLING THE SOLID STATE STORAGE SYSTEM - A solid state storage system is disclosed capable of performing wear leveling utilizing attributes of different types of data. The solid state storage system performs a control operation such that logical addresses are configured to be mapped to physical addresses of pages in multiple planes of a memory area. In addition, the continuous logical addresses are mapped to the physical addresses of the pages of the different planes. The logical addresses are subsequently grouped so as to define multiple data areas for programming data having different attributes. Accordingly, the data is allocated so as to reduce a life time deviation between planes. | 2010-02-04 |
| 20100030949 | Non-volatile memory devices and control and operation thereof - An improved non-volatile erase block memory device apparatus and method is described that incorporates an improved addressing scheme to provide for extended addressing allowing redundant erase blocks that are not utilized to repair general use erase blocks of the main memory array to be accessed and utilized as additional storage space by an end user. The additional storage space formed by the unused redundant erase blocks and the specified storage space of the main memory array is presented to the end user as a single contiguous address space. Additionally, the redundant erase blocks can be utilized to repair any damaged erase block in the memory array of the non-volatile erase block memory or Flash memory device regardless of bank placement. | 2010-02-04 |
| 20100030950 | CYCLIC BUFFER MECHANISM FOR RECEIVING WIRELESS DATA UNDER VARYING DATA TRAFFIC CONDITIONS - A method of ensuring that data sent to a handheld wireless communications device is written to non-volatile memory is disclosed. In a device, where data is initially written to a first volatile memory and then written to a second volatile memory before being written from the second volatile memory to a non-volatile memory, software code is implemented that causes the writing of the data to non-volatile memory concurrently with the writing of the data to the second volatile memory. The software code may incorporate operating system commands (such as Windows OS). | 2010-02-04 |
| 20100030951 | NONVOLATILE MEMORY SYSTEM - A Flash memory system is implemented in a system-in-package (SIP) enclosure, the system comprising a Flash memory controller and a plurality Flash memory devices. An SIP relates to a single package or module comprising a number of integrated circuits (chips). The Flash memory controller is configured to interface with an external system and a plurality of memory devices within the SIP. The memory devices are configured in a daisy chain cascade arrangement, controlled by the Flash memory controller through commands transmitted through the daisy chain cascade. | 2010-02-04 |
| 20100030952 | Memory Module, Memory System, and Information Device - A memory system including large-capacity ROM and RAM in which high-speed reading and writing are enabled is provided. | 2010-02-04 |
| 20100030953 | HIGH-SPEED SOLID STATE STORAGE SYSTEM HAVING A NON-VOLATILE RAM FOR RAPIDLY STORING ADDRESS MAPPING INFORMATION - A solid state storage system incorporating a non-volatile randome access memory (NVRAM) that exhibits a reduced storage time is presented. The solid state storage system includes a memory area, a controller, and an information storage area. The controller is configured to control the memory area. The information storage area controlled by the controller and is configured to store logical address mapping information and physical address mapping information of the memory area. | 2010-02-04 |
| 20100030954 | INFORMATION PROCESSING SYSTEM AND SEMICONDUCTOR STORAGE DEVICE - A random access memory includes a data signal line, a data-synchronization signal line for a data synchronization signal which provides a synchronization signal when data is transmitted to the data signal line, and a setting module. The setting module determines whether the data signal line is set to be a data signal line for common input/output use, a data signal line for output-only use, or a data signal line for input-only use, and further determines whether the data-synchronization signal line is set to be a data-synchronization signal line for common input/output use, a data-synchronization signal line for output-only use, or a data-synchronization signal line for input-only use. | 2010-02-04 |
| 20100030955 | MASK KEY SELECTION BASED ON DEFINED SELECTION CRITERIA - An improved data system permits power efficient mask key write operations. A mask key selector implements criteria-based selection of mask keys for mask key write operations on blocks data. In one embodiment, a first set of mask keys is compared to data bytes of a data block that will be written to memory. The comparison culls keys from the list of candidates that match unmasked data bytes, that is, values that will be written to memory as “changed” data. A mask key is selected from the resulting set of candidates so a memory write operation consumes less power (relative to selection of other keys), or so that the operation minimizes switching noise. The selected mask key is then substituted by a controller into masked data values, and a modified data block is transmitted to memory, with the memory detecting masked data by identifying mask keys in the modified data block. | 2010-02-04 |
| 20100030956 | APPARATUS AND METHOD TO STORE ORIGINAL POINT-IN-TIME DATA - A method to store point-in-time data, comprising establishing a block size, providing source data storage comprising (S) blocks, and target data storage comprising (T) blocks. The method configures (B) source storage segments and (B) target storage segments, and receives updated point-in-time data for original point-in-time data written to an (i)th source storage segment. The method then determines if a (j)th target storage segment comprises available storage capacity to store the original point-in-time data. If a (j)th target storage segment comprises available storage capacity to store the original point-in-time data, the method writes the original point-in-time data to that (j)th target storage segment. | 2010-02-04 |
| 20100030957 | VIRTUAL TAPE SYSTEM - A virtual tape system includes an actual tape device having a magnetic tape which stores data. The virtual tape system includes a virtual tape storage device which stores data stored in the actual tape device as a virtual tape volume, first computers to be connected to a host computer which instructs a storing of data in the actual tape device, and a reading of data from the actual tape device, control an interface with the host computer, second computers which control the virtual tape volume of the virtual tape storage device, third computers which control a writing of the data into the actual tape device, and a local disk controller which stores the data in one of storage devices mounted one in each of the first computers, each of the second computers, and each of the third computers. | 2010-02-04 |
| 20100030958 | Random Number Generation For a Host System Using a Hard Disk Drive - A hard disk drive is provided for enhancing random number generation. In particular embodiments, the hard disk drive includes a storage subsystem and a controller. The controller generates a random number based on information associated with the storage subsystem. The controller transmits the random number to a host system. | 2010-02-04 |
| 20100030959 | SNAPSHOT SYSTEM - A storage system including: a disk device including an original volume and a plurality of snapshot generations; and a storage control unit which includes a processor unit. The processor unit receives write data to a storage area of the original volume, and determines whether data stored in the storage area of the original volume is already copied to the snapshot volume or not; if the data stored in the storage area of original volume is not already copied to snapshot volume, the processor unit copies the data from original volume to the snapshot volume, when a use capacity of the snapshot volume is larger than threshold amount by the copy, the processor unit indicates a specified snapshot generation, the processor unit migrates data of the specified snapshot generation from the snapshot volume to tape device; the processor unit deletes information of the specified snapshot generation in the snapshot volume. | 2010-02-04 |
| 20100030960 | RAID ACROSS VIRTUAL DRIVES - A plurality of physical drives is grouped into a physical drive group. The plurality of physical drives comprises at least a first physical drive and a second physical drive. At least the first physical drive and the second physical drive are striped to create at least a first virtual drive and a second virtual drive. The first virtual drive is comprised of storage space residing on the first physical drive and the second virtual drive is comprised of storage space residing on the second physical drive. Storage data is distributed across at least the first virtual drive and the second virtual drive using at least one redundant array of independent disks (RAID) technique to create at least a first virtual volume and a second virtual volume. When a physical drive fails, data from the failed physical drive may be reconstructed using temporary stripes from a virtual drive. | 2010-02-04 |
| 20100030961 | FLASH MEMORY CONTROLLER FOR ELECTRONIC DATA FLASH CARD - An electronic data flash card is accessible by a host computer, and includes a processing unit connected to a flash memory device that stores a data file, and an input-output interface circuit activated so as to establish a communication with the host computer. In an embodiment, the electronic data flash card uses a USB input/output interface circuit for communication with the host computer. A flash memory controller includes an index for converting logical addresses sent by the host computer into physical addresses associated with sectors of the flash memory device. The index is controlled by arbitration logic referencing to values from various look up tables and valid data stored in the flash memory device. The flash memory controller further includes a first-in-first-out unit (FIFO) for recycling obsolete sectors of the flash memory device in the background process so that they are available for reprogramming. | 2010-02-04 |
| 20100030962 | STORAGE FACILITY FOR DATA HANDLING DEVICES - A storage device for use in combination with a data handling device such as a PC, hand held communications device, and the like, of the type having a data port for receiving ancillary apparatus such as memory cards. The device may be in the form of a tray, or may have recesses shaped to accommodate various objects to be stored at the data handling device. These objects may have data handling functions, such as memory cards, or may be small personal effects such as coins and toiletry items. The tray may have prongs which face the data port, for guiding the tray into place during insertion and securing the tray in place. The tray may also have a cover to retain the objects when either inserted in the data port or not. | 2010-02-04 |
| 20100030963 | MANAGING STORAGE OF CACHED CONTENT - A method of controlling storage of content on a storage device includes communicating with a storage device configured to cache content; and determining a storage cost for caching a first set of data objects on the storage device. The determining is based, at least in part, on characteristics of the first set of data objects and on characteristics of the storage device. Also provided is a storage system that includes a storage device capable of caching media content, a storage device agent and a cache manager. The storage device agent is operative to communicate with the storage device and with the cache manager, and to provide a storage cost to the cache manager. The storage device agent determines the storage cost for caching a data object on the storage device based, at least in part, on characteristics of the data object and on characteristics of the storage device. | 2010-02-04 |
| 20100030964 | METHOD AND SYSTEM FOR SECURING INSTRUCTION CACHES USING CACHE LINE LOCKING - A method and system is provided for securing micro-architectural instruction caches (I-caches). Securing an I-cache involves providing security critical instructions to indicate a security critical code section; and implementing an I-cache locking policy to prevent unauthorized eviction and replacement of security critical instructions in the I-cache. Securing the I-cache may further involve dynamically partitioning the I-cache into multiple logical partitions, and sharing access to the I-cache by an I-cache mapping policy that provides access to each I-cache partition by only one logical processor. | 2010-02-04 |
| 20100030965 | DISOWNING CACHE ENTRIES ON AGING OUT OF THE ENTRY - Caching where portions of data are stored in slower main memory and are transferred to faster memory between one or more processors and the main memory. The cache is such that an individual cache system must communicate to other associated cache systems, or check with such cache systems, to determine if they contain a copy of a given cached location prior to or upon modification or appropriation of data at a given cached location. The cache further includes provisions for determining when the data stored in a particular memory location may be replaced. | 2010-02-04 |
| 20100030966 | Cache memory and cache memory control apparatus - Disclosed herein is a cache memory including: a tag storage section including entries each including a tag address and a pending indication portion, at least one of the entries being to be referred to by a first address portion of an access address; a data storage section; a tag control section configured to compare a second address portion of the access address with the tag address included in each of the entries referred to to detect an entry whose tag address matches the second address portion, and, when the pending indication portion included in the detected entry indicates pending, cause an access related to the access address to be suspended; and a data control section configured to select data corresponding to the detected entry from among the data storage section, when the pending indication portion included in the detected entry does not indicate pending. | 2010-02-04 |
| 20100030967 | METHOD AND SYSTEM FOR SECURING INSTRUCTION CACHES USING SUBSTANTIALLY RANDOM INSTRUCTION MAPPING SCHEME - A method and system is provided for securing micro-architectural instruction caches (I-caches). Securing an I-cache involves maintaining a different substantially random instruction mapping policy into an I-cache for each of multiple processes, and for each process, performing a substantially random mapping scheme for mapping a process instruction into the I-cache based on the substantially random instruction mapping policy for said process. Securing the I-cache may further involve dynamically partitioning the I-cache into multiple logical partitions, and sharing access to the I-cache by an I-cache mapping policy that provides access to each I-cache partition by only one logical processor. | 2010-02-04 |
| 20100030968 | Methods of Cache Bounded Reference Counting - A computer implemented method of cache bounded reference counting for computer languages having automated memory management in which, for example, a reference to an object “Z” initially stored in an object “O” is fetched and the cache hardware is queried whether the reference to the object “Z” is a valid reference, is in the cache, and has a continuity flag set to “on”. If so, the object “O” is locked for an update, a reference counter is decremented for the object “Z” if the object “Z” resides in the cache, and a return code is set to zero to indicate that the object “Z” is de-referenced and that its storage memory can be released and re-used if the reference counter for the object “Z” reaches zero. Thereafter, the cache hardware is similarly queried regarding an object “N” that will become a new reference of object “O”. | 2010-02-04 |
| 20100030969 | Consistency Model for Object Management Data - A method and apparatus are provided for maintaining cache coherency of object management data in a computer system. The computer system is configured with a bit mask to represent changes in object management data. All changes in an object are reflected by setting an associated bit in the bit mask. A cache update of object management data is limited to the bit(s) set in the bit mask. | 2010-02-04 |
| 20100030970 | Adaptive Spill-Receive Mechanism for Lateral Caches - Improving cache performance in a data processing system is provided. A cache controller monitors a counter associated with a cache. The cache controller determines whether the counter indicates that a plurality of non-dedicated cache sets within the cache should operate as spill cache sets or receive cache sets. The cache controller sets the plurality of non-dedicated cache sets to spill an evicted cache line to an associated cache set in another cache in the event of a cache miss in response to an indication that the plurality of non-dedicated cache sets should operate as the spill cache sets. The cache controller sets the plurality of non-dedicated cache sets to receive an evicted cache line from another cache set in the event of the cache miss in response to an indication that the plurality of non-dedicated cache sets should operate as the receive cache sets. | 2010-02-04 |
| 20100030971 | CACHE SYSTEM, CACHE SYSTEM CONTROL METHOD, AND INFORMATION PROCESSING APPARATUS - To provide a cache system that can dynamically change a cache capacity by memory areas divided into plural. The cache system includes a line counter that counts the number of effective lines for each memory area. The effective line is a cache line in which effective cache data is stored. Cache data to be invalidated at the time of changing the cache capacity is selected based on the number of effective lines counted by the line counter. | 2010-02-04 |
| 20100030972 | Device, system and method of accessing data stored in a memory. - Device, system and method of accessing data stored in a memory. For example, a device may include a memory to store a plurality of data items to be accessed by a processor; a cache manager to manage, a cache within the memory, the cache including a plurality of pointer entries, wherein each pointer entry includes an identifier of a respective data item and a pointer to an address of the data item; and a search module to receive from the cache manager an identifier of a requested data item, search the plurality of pointer entries for the identifier of the requested data item and, if a pointer entry is detected to include an identifier of a respective data item that matches the identifier of the requested data item then, provide the cache manager with the pointer from the detected entry. Other embodiments are described and claimed. | 2010-02-04 |
| 20100030973 | CACHE DIRECTED SEQUENTIAL PREFETCH - A technique for performing stream detection and prefetching within a cache memory simplifies stream detection and prefetching. A bit in a cache directory or cache entry indicates that a cache line has not been accessed since being prefetched and another bit indicates the direction of a stream associated with the cache line. A next cache line is prefetched when a previously prefetched cache line is accessed, so that the cache always attempts to prefetch one cache line ahead of accesses, in the direction of a detected stream. Stream detection is performed in response to load misses tracked in the load miss queue (LMQ). The LMQ stores an offset indicating a first miss at the offset within a cache line. A next miss to the line sets a direction bit based on the difference between the first and second offsets and causes prefetch of the next line for the stream. | 2010-02-04 |
| 20100030974 | SYSTEM AND METHOD FOR FETCHING INFORMATION TO A CACHE MODULE USING A WRITE BACK ALLOCATE ALGORITHM - A write back allocate system that includes: (i) a store request circuit; (ii) a processor, adapted to generate a store request that comprises an information unit and an information unit address; and (iii) a cache module, connected to the store request circuit and to a high level memory unit. A single cache module line includes multiple segments, each segment is adapted to store a single information unit. A content of a cache module line is retrieved from the high level memory unit by generating a fetch burst that includes multiple segment fetch operations. The store request circuit includes a snooper and a controller. The snooper detects a portion of an address of a cache segment of a cache line that is being fetched during a fetch burst. The controller is adapted to request from the cache module to receive the information unit before a completion of the fetch burst if the portion of the address of the cache segment matches a corresponding portion of the information unit address. | 2010-02-04 |
| 20100030975 | APPARATUS AND METHOD FOR HANDLING PAGE PROTECTION FAULTS IN A COMPUTING SYSTEM - Method and apparatus for handling page protection faults in combination particularly with the dynamic conversion of binary code executable by a one computing platform into binary code executed instead by another computing platform. In one exemplary aspect, a page protection fault handling unit ( | 2010-02-04 |
| 20100030976 | CONTROL DEVICE - A control device is connected to a processor, a memory module, and a specification information storage memory for storing specification information indicating specifications of the memory module. The control device includes: a readout unit that reads the specification information from the specification information storage memory when power is turned on to the control device; a storage unit that stores the specification information read from the specification information storage memory; and a transfer unit that receives a specification information read instruction from the processor, and that transfers the specification information stored in the storage unit to the processor.a | 2010-02-04 |
| 20100030977 | REGISTER CONTROL CIRCUIT AND REGISTER CONTROL METHOD - A register control circuit that controls a register specified by an inputted address includes a signal output that outputs a first control signal and a second control signal based on the inputted address, a selector that selects data of a register specified by the first control signal outputted from the signal output, a logical operator that performs a logical operation of write data outputted from a processor and the data selected by the selector to output an operation result, and a storage that stores data in the register specified by the first control signal by selecting one of the write data and the operation results as the data based on the second control signal outputted from the signal output. | 2010-02-04 |
| 20100030978 | MEMORY CONTROLLER, MEMORY CONTROL METHOD, AND IMAGE PROCESSING DEVICE - A memory controller controls a memory access to each memory region out of one or more memory regions in SIMD unit. The memory controller includes: a pointer-calculation hardware unit that increments by unit SIMD a value of an access control pointer corresponding to each of the memory regions at different timings corresponding to an access mode set beforehand in each memory region; and a memory-access-control hardware unit that calculates an access destination address in each of the memory regions based on a value of an access control pointer in the memory region, and causes a memory access in SIMD unit to be performed to the calculated access destination address. | 2010-02-04 |
| 20100030979 | DATA MANAGEMENT METHOD, AND STORAGE APPARATUS AND CONTROLLER THEREOF - A data management method, a controller and a storage apparatus thereof are provided. The method is adapted for a storage apparatus having a plurality of blocks. Parts of the blocks are linked to configure a plurality of mother and child blocks (M&C block). The data management method includes: (a) checking whether a mother and child block currently to be written with data is the same of a mother and child block which has been most lately written with data; (b) when it is determined that the mother and child block currently to be written with data is not the same of the mother and child block which has been most lately written with data, saving a transient data of the mother and child block currently to be written with data to a mother and child block transient relationship table. | 2010-02-04 |
| 20100030980 | MEMORY CONTROL DEVICE, MEMORY DEVICE, AND MEMORY CONTROL METHOD - The memory control device according to the present invention includes a command generating unit which divides the memory access request issued by the master into access commands each of which is for one of the memory devices, a command issuing units which issue each of the access commands to the memory devices, a data control unit which switches data between a master and memories, and the command generating unit switch between control for outputting an identical physical address to the memory units and control for outputting different physical addresses to the memory devices, depending on when the physical addresses of the memory devices are identical and when the physical addresses of the memory devices are different, each of the memory devices corresponds to one of the divided access commands. | 2010-02-04 |
| 20100030981 | Method of Clustering Shared Access Hybrid Hard Drives - A method, apparatus, and article of manufacture are provided for managing a hybrid storage device based upon the properties associated therewith. The storage device includes flash memory and physical storage. Select data is written to the flash memory and is not subject to flushing to the physical storage, and select data is either written directly to the physical storage or written to the flash memory and is subject to flushing to the physical storage. | 2010-02-04 |
| 20100030982 | BACKING UP DIGITAL CONTENT THAT IS STORED IN A SECURED STORAGE DEVICE - A third party facilitates preparation of a backup SSD for backing up a source SSD. Digital data of the source SSD, which includes protected and sensitive data and information, is copied to the backup SSD either by and via the third party or directly from the source SSD but under supervision of the third party. The digital data of the source SSD is copied to the backup SSD under stringent rules and only if each party (i.e., the source SSD, destination SSD, and third party) proves to a counterpart device with which it operates that it is authorized to send to it digital data or to receive therefrom digital data, depending on the device with which that party operates. | 2010-02-04 |
| 20100030983 | Backup without overhead of installed backup agent - Methods and apparatus involve providing computing backup for virtual representations on a physical hardware platform without the attendant overhead of an installed backup agent per each of the virtual representations. Representatively, a hardware platform has a processor and memory upon and a plurality of virtual machines are configured on the processor and memory as guest computing devices by way of scheduling control of a hypervisor layer. A common I/O path between the virtual machines and the hardware platform exists in the hypervisor layer and a single backup agent for the entirety of the virtual machines monitors data flows in the common I/O path. In this way, each virtual machine avoids dedicated backup agents, and their attendant overhead, especially by avoiding backup agents configured uniquely per a guest operating system, a guest file system, etc. Some other features contemplate particular I/O paths, operating systems, hypervisors, domains, and computer program products. | 2010-02-04 |
| 20100030984 | Method and system for optimizing data backup - There is provided a method for optimizing a data backup. The method comprising determining a backup project size, the backup project size identifying the quantity of data to be backed up; detecting available recording devices for transferring the data backup to storage media; receiving an input corresponding to at least one user specified optimization variable, wherein the at least one user specified optimization variable comprises an upper limit on the length of each of the calculated plurality of data streams; utilizing the at least one user specified optimization variable to calculate a plurality of data streams for performing the data backup; and assigning subsets of the plurality of data streams to the available recording devices to optimize the data backup. | 2010-02-04 |
| 20100030985 | Data backup apparatus - In a data backup apparatus using memory as the data backup apparatus of an electronic device, the data backup apparatus includes a data backup module and a memory controller. The data backup module includes an interface card, and the interface card includes a plurality of memories which are carriers of backup data, and the memories are movably inserted into memory slots. The memory controller is provided for storing, reading and backing up data. With the memories, the data storage capacity can be expanded, and users can operate a start means to drive a memory controller to back up data directly into the data backup module. The invention can enhance the data backup speed and reduce human operating errors, so as to improve the security and efficiency of the data backup operation of the electronic device. | 2010-02-04 |
| 20100030986 | STORAGE SYSTEM CONTROL METHOD - An apparatus for copying data to another apparatus including a receiving buffer, includes: a transmitting buffer including a plurality of areas for temporary storing data of the copying; and a processor for executing a process, including: receiving information indicative of an instantaneous vacant area of the receiving buffer of the another apparatus, the vacant area being capable of temporarily storing data that could be transmitted from the transmitting buffer, determining an area of the transmitting buffer that stores data to be transmitted subsequently in reference to the information of the vacant area, and transmitting data stored in the determined area of the transmitting buffer to the receiving buffer of the another apparatus. | 2010-02-04 |
| 20100030987 | DATA STORING LOCATION MANAGING METHOD AND DATA STORAGE SYSTEM - A data storing location managing method including generating an access frequency of a storing area accessed in a first storage apparatus according to a command received, copying data stored in the storing area of the first storage apparatus to a storing area of a second storage apparatus when the access frequency of the storing area of the first storage apparatus is greater than a reference value, and replacing location information of the storing area of the first storage apparatus with location information of the storing area of the second storage apparatus. | 2010-02-04 |
| 20100030988 | VIRTUALIZING SWITCH AND COMPUTER SYSTEM - A virtualizing switch includes a storage virtualizing section for making the host computer recognize storage areas prepared by combining storage areas of a physical storage devices as virtual storage devices, a data copying section for executing data copying between the virtual storage devices, a range locking section for dividing a storage area for storing data to be copied of a virtual storage device of a copy source into storage area parts having a previously set division size and inhibiting access to a divided storage area part, an instruction number counting section for counting the number of access instructions to the divided storage area part that is inhibited by the range locking section, and a divided capacity changing section for changing the division size based on the number of instructions counted by the instruction number counting section. | 2010-02-04 |
| 20100030989 | STORAGE MANAGEMENT METHOD AND STORAGE CONTROL APPARATUS - A storage control apparatus that stores backup target in a predetermined storage area of a storage apparatus includes a determination unit for determining whether or not the backup target data has been modified, and a backup processing unit for performing the backup processing for the backup target data when the determination unit determines that the backup target data has been modified. | 2010-02-04 |
| 20100030990 | External memory management apparatus and external memory management method - An objective is to prevent a downloaded application from accessing data in an external memory unrelated to the application, and to achieve safer management of access to the external memory. An external memory function module | 2010-02-04 |
| 20100030991 | ELECTRONIC DEVICE AND METHOD FOR UPDATING BIOS THEREOF - This invention discloses a method for updating a basic input/output system (BIOS). The BIOS is stored in a memory of an electronic device. An embedded controller (EC) is electrically connected to the memory and a processor. The processor is electrically connected to the memory and executes the BIOS. The method for updating the BIOS includes the following steps. First, a write instruction is sent to the EC. Afterward, the EC receives the write instruction and sends a system management interrupt (SMI) to the processor. Then, the processor receives the SMI and sends an identification code to the EC. Then, the EC receives the identification code and determines whether the identification code matches a security code. If the identification code matches the security code, the EC allows the memory to be writable to update the BIOS. | 2010-02-04 |
| 20100030992 | INITIALIZING OF A MEMORY AREA - A method for initializing a memory area, the method includes: receiving a request to access a first memory sub of a first memory area that comprises multiple memory sub areas; and initializing the first memory sub area if a first memory area initialization indicator differs from a first memory sub area initialization request indicator; wherein the first memory area initialization request indicator is a multiple bit variable indicative of a time of a last request to initialize the first memory area and the first memory sub area initialization indicator is a multiple bit variation indicative of a time of a request to initialize the first memory area that resulted in a last initialization of the first memory sub area. | 2010-02-04 |
| 20100030993 | Memory Access Control Device, Memory Access Control Method, Data Storage Method and Memory Access Control Program - An access control device which increases memory access efficiency to data stored in a memory according to the present invention comprises a plurality of groups of the memory, divides and stores the data in different memory areas of the plurality of groups of the memory distinguished based on the predetermined bits of an access address to the plurality of groups of the memory, and accesses the data stored in the different memory areas of the plurality of groups of the memory simultaneously in the same clock cycle of access to the memory. | 2010-02-04 |
| 20100030994 | METHODS, SYSTEMS, AND COMPUTER READABLE MEDIA FOR MEMORY ALLOCATION AND DEALLOCATION - Methods, systems, and computer readable media for memory allocation and de-allocation are disclosed. According to one aspect, a method for allocation and de-allocation of memory includes dividing a memory space into a plurality of records of fixed size and maintaining an allocation map for indicating, for each record in the memory space, whether the record is allocated or unallocated. The method also includes maintaining a set of lists of unallocated blocks, where a block is a group of contiguous records, where the size of a block is the number of contiguous records in the block, and where each list lists unallocated blocks of a particular size. The method also includes processing requests for allocation and de-allocation of memory. Processing a request for memory allocation includes using the set of lists to find an unallocated block of the smallest size that is equal to or greater than the amount of memory requested to be allocated. Processing a request for memory de-allocation includes using the allocation map to combine the deallocated memory block with an unallocated block contiguous to the deallocated memory block and add the combined blocks to the list indicating unallocated blocks of the size of the combined memory blocks. | 2010-02-04 |
| 20100030995 | METHOD AND APPARATUS FOR APPLYING DATABASE PARTITIONING IN A MULTI-TENANCY SCENARIO - A method and apparatus for applying database partitioning in a multi-tenancy scenario is disclosed, the method includes providing, in each database table of a partitioned database system storing tenant data, a partition key field for storing a respective partition key for each tenant within a plurality of tenants. The respective partition key for each tenant is designated for each tenant according to a partition designated for the each respective tenant and the corresponding relationships between partitions and partition keys in the database partitioning mechanism of the partitioned database system. The respective partition key is used by the partitioned database system to perform database partitioning operations on the data of each respective tenant. | 2010-02-04 |
| 20100030996 | System and Method for Forensic Identification of Elements Within a Computer System - A system and method for employing memory forensic techniques to determine operating system type, memory management configuration, and virtual machine status on a running computer system. The techniques apply advanced techniques in a fashion to make them usable and accessible by Information Technology professionals that may not necessarily be versed in the specifics of memory forensic methodologies and theory. | 2010-02-04 |
| 20100030997 | VIRTUAL MEMORY MANAGEMENT - A method for managing a virtual memory system configured to allow multiple page sizes is described. Each page size has at least one table associated with it. The method involves maintaining entries in the tables to keep track of the page size for which the effective address is mapped. When a new effective address to physical address mapping needs to be made for a page size, the method accesses the appropriate tables to identify prior mappings for another page size in the same segment. If no such conflicting mapping exists, it creates a new mapping in the appropriate table. A formula is used to generate an index to access a mapping in a table. | 2010-02-04 |
| 20100030998 | Memory Management Using Transparent Page Transformation - Memory space is managed to release storage area occupied by pages similar to stored reference pages. The memory is examined to find two similar pages, and a transformation is obtained. The transformation enables reconstructing one page from the other. The transformation is then stored and one of the pages is discarded to release its memory space. When the discarded page is needed, the remaining page is fetched, and the transformation is applied to the page to regenerate the discarded page. | 2010-02-04 |
| 20100030999 | Process and Method for Logical-to-Physical Address Mapping in Solid Sate Disks - An embodiment of the invention relates to a mass storage device including a nonvolatile memory device with a plurality of memory management blocks and an address translation table formed with pointers to locations of the memory management blocks. A volatile memory device is included with an address index table formed with pointers to the pointers to the locations of the memory management blocks. The address index table is stored in the nonvolatile memory upon loss of bias voltage. Changes to the address translation table are accumulated in the volatile memory and written to the address translation table when at least a minimum quantity of the changes has been accumulated. The changes to the logical block address translation table accumulated in the volatile memory are written to a page in the address translation table after prior data in the page has been updated, written to another page, and then erased. | 2010-02-04 |
| 20100031000 | APPARATUS, SYSTEM, AND METHOD FOR VALIDATING THAT A CORRECT DATA SEGMENT IS READ FROM A DATA STORAGE DEVICE - An apparatus, system, and method are disclosed for validating that correct data is read from a storage device. A read request receiver module receives a read storage request to read a data segment of a file or object stored on a data storage device. The storage request includes one or more source parameters for the data segment. The source parameters include one or more virtual addresses that identify the data segment. A hash generation module generates one or more hash values from the virtual addresses. A read data module reads the requested data segment and returns one or more data packets and corresponding stored hash values stored with the data packets. The stored hash values were generated from a data segment written to the data storage device that contains data of the data packets. A hash check module verifies that the generated hash values match the respective stored hash values. | 2010-02-04 |
| 20100031001 | SERIAL MEMORY DEVICE AND SIGNAL PROCESSING SYSTEM - In a serial memory device which performs reception and transmission of command, address, and data via serial communication with a host controller, a base address holding circuit holds a base address which serves as a base for effective address calculation. An address operation circuit calculates an effective address based on the base address and an address input from the host controller. | 2010-02-04 |
