05th week of 2010 patent applcation highlights part 33 |
Patent application number | Title | Published |
20100027292 | LIGHT GUIDING STRUCTURE - The present invention relates to a light guiding structure, comprises: a printed circuit board for carrying following units; a light guiding column retained on the printed circuit board; at least one light-emitting member disposed on the printed circuit board and provided beside the light guiding column, and lights emitted by the light-emitting member can be refracted or reflected by the light guiding column for increasing the brightness of lateral light emitting. | 2010-02-04 |
20100027293 | Light Emitting Panel - A light emitting panel comprises a light guiding medium having at least one light emitting face and a plurality of light sources (LEDs) configured to couple light into an edge of the light guiding medium at four or fewer locations around the edge. A pattern of optical features (discontinuities) is provided on at least one face of the light guiding medium for promoting emission of light from the light emitting face. The pattern of features is configured such as to reduce a variation in emitted light intensity over substantially the entire surface of the light emitting face such that the variation is less than or equal to about 25%. The pattern of features is configured in part in dependence on a light intensity distribution within the light guiding medium and the spacing, size, shape and/or number of features per unit area can depend on distance from each light source. | 2010-02-04 |
20100027294 | OPTICAL SHEET AND METHOD OF MANUFACTURING THE SAME - An optical sheet includes a base film in which light is incident from a lower side, a plurality of prism patterns and a diffusion member. The prism patterns are protruded to be spaced apart from each other on the base film to enhance the front luminance of light incident from the lower side of the base film. The diffusion member is disposed between prism patterns to have a diffusion surface in parallel with the base film. The diffusion member includes a plurality of diffusion dots capable of enhancing the luminance uniformity of light incident from the lower side of the base film. Thus, front luminance and luminance uniformity may be enhanced due to a juxtaposition of the prism patterns and the diffusion portion, and the viewing angle of the LCD device may be enhanced. | 2010-02-04 |
20100027295 | OPTICAL SHEET AND LIQUID CRYSTAL DISPLAY INCLUDING THE SAME - An optical sheet and a liquid crystal display (LCD) including the same are provided. The optical sheet may include a base film; and a protrusion layer including a plurality of protrusions and disposed over the base film, wherein the base film includes a first layer over which the protrusion layer is disposed, and a second layer over which the first layer is disposed, wherein at least one of the first layer and the second layer includes a wavy surface where the first layer is disposed over the second layer. Therefore, it is possible to improve a haze of the optical sheet while maintaining an optical transmissivity of the optical sheet. | 2010-02-04 |
20100027296 | BACKLIGHT STRUCTURE - A backlight structure includes: light source modules | 2010-02-04 |
20100027297 | Step-Up Converter Systems and Methods - Methods and systems with a step-up converter are provided based on a boost converter. In one aspect, a step-up converter includes: a boost converter having a first inductor; a second inductor paired on a core with the first inductor; and a rectifier circuit coupled with the second inductor to generate a direct current output. | 2010-02-04 |
20100027298 | System and method for synchronous rectifier drive that enables converters to operate in transition and discontinuous mode - A synchronous rectifier is switched in accordance with a primary switch transition and a reference signal representing current in a current storage device to which the synchronous rectifier is coupled. A current emulator provides a signal representing current in the current storage device as a volt-second product so that current stored in the current storage device while the primary switch is on is discharged by the synchronous rectifier. The use of a current emulator provides an inexpensive solution for controlling synchronous rectifier transitions without resorting to more expensive current sensing solutions that are commercially impracticable. Blanking intervals are provided for avoiding false transitions of the synchronous rectifier when the primary switch turns on and after the synchronous rectifier turns off. The disclosed system and method can be applied to flyback converters for a synchronous rectifier on the secondary side of a transformer, or the inductor of buck converters. | 2010-02-04 |
20100027299 | SYSTEMS AND METHODS FOR ADAPTIVE SWITCHING FREQUENCY CONTROL IN SWITCHING-MODE POWER CONVERSION SYSTEMS - Switching-mode power conversion system and method thereof. The system includes a primary winding configured to receive an input voltage and a secondary winding coupled to the primary winding. Additionally, the system includes a compensation component configured to receive the input voltage and generate at least a clock signal based on at least information associated with the input voltage, and a signal generator configured to receive at least the clock signal and generate at least a control signal based on at least information associated with the clock signal. Moreover, the system includes a gate driver configured to receive at least the control signal and generate a drive signal based on at least information associated with the control signal, and a first switch configured to receive the drive signal and affect a first current flowing through the primary winding. | 2010-02-04 |
20100027300 | SYSTEMS AND METHODS FOR PRIMARY-SIDE REGULATION IN OFF-LINE SWITCHING-MODE FLYBACK POWER CONVERSION SYSTEM - Switching-mode power conversion system and method thereof. The system includes a primary winding configured to receive an input voltage, and a secondary winding coupled to the primary winding and configured to, with one or more first components, generate, at an output terminal, an output voltage and an output current. Additionally, the system includes an auxiliary winding coupled to the secondary winding and configured to, with one or more second components, generate, at a first terminal, a detected voltage. Moreover, the system includes an error amplifier configured to receive the detected voltage and a first reference voltage and generate an amplified voltage based on at least information associated with a difference between the detected voltage and the first reference voltage. Also, the system includes a compensation component configured to receive the amplified voltage and generate a second reference voltage based on at least information associated with the amplified voltage. | 2010-02-04 |
20100027301 | BAND-PASS CURRENT MODE CONTROL SCHEME FOR SWITCHING POWER CONVERTERS WITH HIGHER-ORDER OUTPUT FILTERS - A DC-DC converter is described that contains multiple estimators and is self-oscillation. The converter also contains at least a fourth order output filter. The converter contains both feedback and feed-forward paths. The estimators estimate the current through inductors in the filter by sensing the voltage across the inductors. | 2010-02-04 |
20100027302 | CONVERTER WITH REDUCED HARMONIC WAVES - Converter and method for controlling a converter with power semiconductor switches, having a filter ( | 2010-02-04 |
20100027303 | Devices and Methods for Converting or Buffering a Voltage - Embodiments of the invention relate to devices and methods for converting or buffering a voltage including an inductor configured to perform at least a primary function and to be reused to contribute to converting or buffering the voltage as a secondary function. | 2010-02-04 |
20100027304 | ELECTRICAL POWER SYSTEM WITH HIGH-DENSITY PULSE WIDTH MODULATED (PWM) RECTIFIER - An electrical power system includes an alternating current (AC) power source configured to output an AC signal, a single phase pulse-width modulated (PWM) rectifier coupled to the AC power source and to an electrical load; a DC link capacitor coupled in parallel to the load and the PWM rectifier; and an active ripple energy storage circuit. The active ripple energy storage circuit has a first terminal, a second terminal and a third terminal, the active ripple energy storage circuit being coupled in parallel to the electrical load, the PWM rectifier and the DC link capacitor via the first terminal and the second terminal, the third terminal being coupled to the second terminal, the active ripple energy storage circuit being configured to selectively absorb and discharge at least part of the ripple energy | 2010-02-04 |
20100027305 | ELECTRIC POWER CONTROL DEVICE AND VEHICLE WITH THE SAME - Power lines are connected to neutral points of motor generators, respectively, and an electric power is transmitted and received between a vehicle and a load outside the vehicle via the power lines. In this transmission, an ECU simultaneously PWM-controls all phases of one of inverters, and controls the other inverter to keep continuously the conducting state. | 2010-02-04 |
20100027306 | PRIMARY RESONANT INVERTER CIRCUIT FOR FEEDING A SECONDARY CIRCUIT - A primary circuit ( | 2010-02-04 |
20100027307 | MEMORY DETECTING CIRCUIT - A memory detecting circuit includes five switch elements and two indication devices. A first switch element is connected to a standby power, and also connected to memory sockets of a first channel to receive a first memory detecting signal. A second switch element is connected to the first switch element and the standby power. A third switch element is connected to the second switch element and the standby power, and also connected to memory sockets of a second channel to receive a second memory detecting signal. A fourth switch element is connected to the third switch element and the standby power. A fifth switch element is connected to the fourth switch element and the standby power. When there are memories installed into the memory sockets of the first channel and the second channel, the second indication device indicates that the memories run in a dual channel mode. | 2010-02-04 |
20100027308 | SEMICONDUCTOR STORAGE DEVICE - A semiconductor storage device includes a memory cell array having memory cells positioned at respective intersections between a plurality of first wirings and a plurality of second wirings, each of the memory cells having a rectifier element and a variable resistance element connected in series, and a control circuit selectively driving the first and second wirings. The control circuit applies a first voltage to the selected first wiring and applies a second voltage to the selected second wiring to apply a certain potential difference to a selected memory cell positioned at a intersection between the selected first and second wirings, and brings at least one of nonselected first wirings into a floating state. | 2010-02-04 |
20100027309 | SEMICONDUCTOR MEMORY DEVICE INCLUDING PLURALITY OF MEMORY CHIPS - A semiconductor memory device includes a plurality of memory chips each including a chip identification (ID) generation circuit. The chip ID generation circuits of the respective memory chips are operatively connected together in a cascade configuration, and the chip ID generation circuits are activated in response to application of a power supply voltage the memory device to sequentially generate respective chip ID numbers of the plurality of device chips | 2010-02-04 |
20100027310 | APPARATUS AND METHODS FOR OPTICALLY-COUPLED MEMORY SYSTEMS - Optically-coupled memory systems are disclosed. In one embodiment, a system memory includes a carrier substrate, and a controller attached to the carrier substrate and operable to transmit and receive optical signals, and first and second memory modules. The module substrate of the first memory module has an aperture formed therein, the aperture being operable to provide an optical path for optical signals between the controller and an optical transmitter/receiver unit of the second memory module. Thus, the system memory provides the advantages of “free space” optical connection in a compact arrangement of memory modules. In an alternate embodiment, the first memory module includes a beam splitter attached to the module substrate proximate the aperture. In another embodiment, the first and second memory modules are staged on the carrier substrate to provide an unobstructed path for optical signals. In another embodiment, the optical transmitter/receiver unit projects outwardly from the module substrate to provide an unobstructed path for optical signals. | 2010-02-04 |
20100027311 | INTEGRATED CIRCUIT AND METHOD OF FORMING AN INTEGRATED CIRCUIT - An integrated circuit and a method of forming an integrated circuit. One embodiment includes a conductive line formed above a surface of a carrier. A slope of the sidewalls of the conductive line in a direction perpendicular to the surface of the carrier reveals a discontinuity and a width of the conductive line in an upper portion thereof is larger than the corresponding width in the lower portion. | 2010-02-04 |
20100027312 | Compact Virtual Ground Diffusion Programmable ROM Array Architecture, System and Method - A compact, shared source line and bit line architecture for a diffusion programmable ROM. In one embodiment, a ROM circuit or instance includes a plurality of storage cells organized as an array of rows columns. A shared source line is associated with a first pair of adjacent columns, the shared source line being maintained at a predetermined level, wherein source terminals of storage cells in the adjacent columns are electrically coupled to the shared source line. A shared bit line is associated with a second pair of adjacent columns, the shared bit line being maintained at the predetermined level, wherein drain terminals of storage cells in the adjacent columns are electrically coupled to the shared bit line. | 2010-02-04 |
20100027313 | F-SRAM Before Package Solid Data Write - A process of polarizing a programmable data storage component of an integrated circuit by polarizing the ferroelectric capacitors in the same orientation and then removing power from the integrated circuit. A process polarizing a programmable data storage component of an integrated circuit by polarizing the ferroelectric capacitors in the same orientation, then removing power from the integrated circuit. A process of polarizing a programmable data storage component of an integrated circuit by polarizing corresponding ferroelectric capacitors in same orientations, then removing power from the integrated circuit. An integrated circuit containing a programmable data storage component and a ferroelectric capacitor polarization circuit that is configured to polarize a first data ferroelectric capacitor and a second data ferroelectric capacitor in desired polarization configurations by applying biases to a first state node, a second state node, a first plate node, and a second plate node. | 2010-02-04 |
20100027314 | Preservation circuit and methods to maintain values representing data in one or more layers of memory - Circuitry and methods for restoring data in memory are disclosed. The memory may include at least one layer of a non-volatile two-terminal cross-point array that includes a plurality of two-terminal memory elements that store data as a plurality of conductivity profiles and retain stored data in the absence of power. Over a period of time, logic values indicative of the stored data may drift such that if the logic values are not restored, the stored data may become corrupted. At least a portion of each memory may have data rewritten or restored by circuitry electrically coupled with the memory. Other circuitry may be used to determine a schedule for performing restore operations to the memory and the restore operations may be triggered by an internal or an external signal or event. The circuitry may be positioned in a logic layer and the memory may be fabricated over the logic layer. | 2010-02-04 |
20100027315 | Resistive memory device and writing method thereof - A resistive memory device operates to sequentially activate bit lines, which are divided into plural groups, after precharging all of word and bit lines in a writing operation. The device is able to write a large amount of data therein at a high frequency, with a reduced the chip size. | 2010-02-04 |
20100027316 | NON-VOLATILE MEMORY DEVICE AND METHOD OF OPERATING THE SAME - A non-volatile memory device having a stack structure, and a method of operating the non-volatile memory device In which the non-volatile memory device includes a plurality of variable resistors arranged in at least one layer. At least one layer selection bit line and a plurality of bit lines coupled to the plurality of the variable resistors are provided. A plurality of selection transistors coupled between the plurality of the bit lines and the plurality of the variable resistors are provided. | 2010-02-04 |
20100027317 | SEMICONDUCTOR MEMORY DEVICE - A semiconductor memory device comprising: a memory cell array in which memory cells each containing a variable resistive element and a rectifier element connected in series are arranged at intersections of a plurality of first wirings and a plurality of second wirings; and a control circuit for selectively driving said first wirings and said second wirings; wherein said control circuit applies a first voltage to said selected first wiring, and changes said first voltage based on the position of said selected memory cell within said memory cell array to apply a second voltage to said selected second wiring, so that a predetermined potential difference is applied to a selected memory cell arranged at the intersection between said selected first wiring and said selected second wiring. | 2010-02-04 |
20100027318 | NONVOLATILE SEMICONDUCTOR MEMORY DEVICE - A nonvolatile semiconductor memory device comprises a cell array including plural MATs (unit cell arrays) arranged in matrix, each MAT containing a plurality of first lines, a plurality of second lines intersecting the plurality of first lines, and a plurality of memory cells connected at intersections of the first and second lines between both lines, each memory cell containing an electrically erasable programmable variable resistive element of which resistance is nonvolatilely stored as data; and a plurality of write/erase circuits connected to the MATs and operative to execute data write or erase to the memory cells inside the MATs in accordance with input data. A part of the plurality of write/erase circuits writes data to memory cells inside a corresponding MAT while another part of the plurality of write/erase circuits erases data from memory cells inside a corresponding MAT at the same time. | 2010-02-04 |
20100027319 | RESISTANCE CHANGE ELEMENT, METHOD FOR MANUFACTURING THE SAME, AND SEMICONDUCTOR MEMORY - A resistance change element including a first electrode; a second electrode; and an oxide film, including an oxide of the first electrode, formed at sides of the first electrode and sandwiched between the first electrode and the second electrode in a plurality of regions, wherein at least one of the regions includes a resistance part whose resistance value changes in accordance with a voltage applied to the first and second electrodes. | 2010-02-04 |
20100027320 | RESISTANCE VARIABLE ELEMENT, RESISTANCE VARIABLE MEMORY APPARATUS, AND RESISTANCE VARIABLE APPARATUS - A resistance variable element ( | 2010-02-04 |
20100027321 | Non-Volatile Single-Event Upset Tolerant Latch Circuit - A non-volatile single-event upset (SEU) tolerant latch is disclosed. The non-volatile SEU tolerant latch includes a first and second inverters connected to each other in a cross-coupled manner. The gates of transistors within the first inverter are connected to the drains of transistors within the second inverter via a first feedback resistor. Similarly, the gates of transistors within the second inverter are connected to the drains of transistors within the first inverter via a second feedback resistor. The non-volatile SEU tolerant latch also includes a pair of chalcogenide memory elements connected to the inverters for storing information. | 2010-02-04 |
20100027322 | SEMICONDUCTOR INTEGRATED CIRCUIT AND MANUFACTURING METHOD THEREFOR - In this invention, high manufacturing yield is realized and variations in threshold voltage of each MOS transistor in a CMOS•SRAM is compensated. Body bias voltages are applied to wells for MOS transistors of each SRAM memory cell in any active mode of an information holding operation, a write operation and a read operation of an SRAM. The threshold voltages of PMOS and NMOS transistors of the SRAM are first measured. Control information is respectively programmed into control memories according to the results of determination. The levels of the body bias voltages are adjusted based on the programs so that variations in the threshold voltages of the MOS transistors of the CMOS•SRAM are controlled to a predetermined error span. A body bias voltage corresponding to a reverse body bias or an extremely shallow forward body bias is applied to a substrate for the MOS transistors with an operating voltage applied to the source of each MOS transistor. | 2010-02-04 |
20100027323 | MAGNETIC RECORDING ELEMENT - A magnetic recording element is disclosed for which current density required for writing is low and structure of the element is simple. It comprises a ferromagnetic fine wire formed on a Si substrate, current electrodes that contact ends of the ferromagnetic fine wire, and voltage electrodes joined to the ferromagnetic fine wire and current electrodes to measure voltage across part of the ferromagnetic fine wire in cooperation with the current electrodes. A magnetic domain wall is induced in the ferromagnetic fine wire when the element is manufactured. A depression is formed in the surface on top of the ferromagnetic fine wire between the voltage electrodes, and between one of the current electrodes and one of the voltage electrodes. Voltage is measured between the two voltage electrodes when reading current is applied, to determine whether the magnetic domain wall is present between the two voltage electrodes, whereby recorded data can be identified. | 2010-02-04 |
20100027324 | VARIABLE INTEGRATED ANALOG RESISTOR - The invention relates to the use of chalcogenide devices exhibiting negative differential resistance in integrated circuits as programmable variable resistor components. The present invention is a continuously variable integrated analog resistor made of a chalcogenide material, such as a GeSeAg alloy. Continuously variable resistor states are obtained in the material via application of an electrical pulse to it. The pulse sequence, duration and applied potential determine the value of the resistance state obtained. | 2010-02-04 |
20100027325 | INTEGRATED CIRCUIT INCLUDING AN ARRAY OF MEMORY CELLS AND METHOD - An integrated circuit including an array of memory cells and method. In one embodiment, each memory cell includes a resistively switching memory element and a selection diode for selecting one cell from the plurality of memory cells. The memory element is coupled with its top to a first selection line and with its bottom side to the selection diode, the diode further being coupled to the bottom side of a second selection line. | 2010-02-04 |
20100027326 | Memory device, memory system having the same, and programming method of a memory cell - A method of writing multi-bit data to a semiconductor memory device with memory cells storing data defined by a threshold value, the method comprising, for each memory cell, writing a least significant bit, verifying completion of writing the least significant bit, verifying including comparing a written value to one of a low least significant bit verification value and a high least significant bit verification value, and writing a next significant bit upon completion of writing the least significant bit. | 2010-02-04 |
20100027327 | Nonvolatile Memory Devices Having Variable-Resistance Memory Cells and Methods of Programming the Same - Nonvolatile memory devices include an array of variable-resistance memory cells and a write driver electrically coupled to the array. The write driver is configured to drive a bit line in the array of variable-resistance memory cells with a stair-step sequence of at least two unequal bit line voltages during an operation to program a variable-resistance memory cell in said array. This stair-step sequence of at least two unequal bit line voltages includes a precharge voltage (e.g., Vcc-Vth) at a first step and a higher boosted voltage (e.g., Vpp-Vth) at a second step that follows the first step. | 2010-02-04 |
20100027328 | Multilevel Variable Resistance Memory Cell Utilizing Crystalline Programming States - A method of programming an electrical variable resistance memory device. When applied to variable resistance memory devices that incorporate a phase-change material as the active material, the method utilizes a plurality of crystalline programming states. The crystalline programming states are distinguishable on the basis of resistance, where the resistance values of the different states are stable with time and exhibit little or no drift. As a result, the programming scheme is particularly suited to multilevel memory applications. The crystalline programming states may be achieved by stabilizing crystalline phases that adopt different crystallographic structures or by stabilizing crystalline phases that include mixtures of two or more distinct crystallographic structures that vary in the relative proportions of the different crystallographic structures. The programming scheme incorporates at least two crystalline programming states and further includes at least a third programming state that may be a crystalline, amorphous or mixed crystalline-amorphous state. | 2010-02-04 |
20100027329 | Synchronous Page-Mode Phase-Change Memory with ECC and RAM Cache - Phase-change memory (PCM) cells store data using alloy resistors in high-resistance amorphous and low-resistance crystalline states. The time of the memory cell's set-current pulse can be 100 ns, much longer than read or reset times. The write time thus depends on the write data and is relatively long. A page-mode caching PCM device has a lookup table (LUT) that caches write data that is later written to an array of PCM banks. Host data is latched into a line FIFO and written into the LUT, reducing write delays to the relatively slow PCM. Host read data can be supplied by the LUT or fetched from the PCM banks. A multi-line page buffer between the PCM banks and LUT allows for larger block transfers using the LUT. Error-correction code (ECC) checking and generation is performed for data in the LUT, hiding ECC delays for data writes into the PCM banks. | 2010-02-04 |
20100027330 | MAGNETIC MEMORY DEVICE AND METHOD FOR READING MAGNETIC MEMORY CELL USING SPIN HALL EFFECT - A magnetic memory device includes a substrate for reading and a magnetic memory cell. The substrate has a channel layer. The magnetic memory cell is formed on the substrate and has a magnetized magnetic material that transfers spin data to electrons passing the channel layer. Data stored in the magnetic memory cell are read by a voltage across both side ends of the channel layer that is generated when the electrons passing the channel layer deviate in the widthwise direction of the channel layer by a spin Hall effect. | 2010-02-04 |
20100027331 | MEMORY AND READING METHOD THEREOF - A method for reading a memory, which includes a memory cell having a first half cell and a second half cell, includes the following steps. A first voltage is applied to the memory cell to determine whether a threshold voltage of the first half cell is higher than a predetermined value or not. If the threshold voltage of the first half cell is higher than the predetermined value, a second voltage higher than the first voltage is applied to the memory cell to read data stored in the second half cell, otherwise a third voltage lower than the first voltage is applied to the memory cell to read the data stored in the second half cell. | 2010-02-04 |
20100027332 | FLASH MEMORY PROGRAMMING - A method, device and system are provided for programming a flash memory device, the method including executing a bit line setup operation, and executing a channel pre-charge operation simultaneously with the bit line setup operation, the channel pre-charge operation including applying a channel pre-charge voltage to all word lines; and the device including a voltage generator disposed for providing each of a program voltage, a read voltage, a pass voltage, and a channel pre-charge voltage, a high-voltage switch connected to the voltage generator and disposed for switchably providing one of the program voltage, read voltage, pass voltage, or channel pre-charge voltage, and control logic connected to the high-voltage switch and disposed for simultaneously executing a bit line setup operation and a channel pre-charge operation, the channel pre-charge operation comprising controlling the high-voltage switch to apply the channel pre-charge voltage to both selected and unselected word lines of the device. | 2010-02-04 |
20100027333 | Nonvolatile Semiconductor Memory Device - A memory cell array has a first and a second storage area. The first storage area has a memory elements selected by an address signal. The second storage area has a memory elements selected by a control signal. A control circuit has a fuse element. When the fuse element has been blown, the control circuit inhibits at least one of writing and erasing from being done on the second storage area. | 2010-02-04 |
20100027334 | EEPROM CHARGE RETENTION CIRCUIT FOR TIME MEASUREMENT - An electronic charge retention circuit for time measurement, implanted in an array of EEPROM memory cells, each including a selection transistor in series with a floating-gate transistor, the circuit including, on any one row of memory cells: a first subassembly of at least a first cell, the thickness of the dielectric of the tunnel window of the floating-gate transistor of which is less than that of the other cells; a second subassembly of at least a second cell, the drain and source of the floating-gate transistor of which are interconnected; a third subassembly of at least a third cell; and a fourth subassembly of at least a fourth cell, the tunnel window of which is omitted, the respective floating gates of the transistors of the cells of the four subassemblies being interconnected. | 2010-02-04 |
20100027335 | Memory device and wear leveling method - The memory device selects any one of a first memory cell and a second memory cell based on a number of times that the first memory cell is erased, an elapsed time after the first memory cell is erased, a number of times that the second memory cell is erased, and an elapsed time after the second memory cell is erased, and program data in the selected memory cell. The memory device may improve distribution of threshold voltage of memory cells and endurance of the memory cells. | 2010-02-04 |
20100027336 | Non-volatile memory device and associated programming method using error checking and correction (ECC) - A programming method for a non-volatile memory device includes performing a programming operation to program memory cells, when the programmed memory cells are determined to include memory cells that failed to be programmed and when a current program loop is a maximum program loop, determining whether a number of the memory cells that failed to be programmed corresponds to a number of memory cells that can successfully undergo ECC (error checking and correction), when the number of the memory cells that failed to be programmed is less than the number of the memory cells that can successfully undergo ECC, reading data so as to determine whether a number of error bits of the memory cells that failed to be programmed can successfully undergo ECC, and, when the memory cells that failed to be programmed can successfully undergo ECC, ending a programming operation. | 2010-02-04 |
20100027337 | Nonvolatile memory device extracting parameters and nonvolatile memory system including the same - The nonvolatile memory device includes a memory cell array having a plurality of memory blocks and a control logic circuit configured to store a parameter to access at least one of the plurality of memory blocks, configured to detect a variation of the parameter while accessing the at least one the memory block, and configured to store the varied parameter into the memory cell array in accordance with a result of the detection, wherein the control logic circuit is configured to utilize the varied parameter, which is stored in the memory cell array, while accessing the at least one memory block. | 2010-02-04 |
20100027338 | SEMICONDUCTOR DEVICE AND A MANUFACTURING METHOD THEREOF - A semiconductor device includes at least two adjacent memory cell blocks, each of the memory cell blocks having a plurality of memory cell units, each of memory cell units having a plurality of electrically reprogrammable and erasable memory cells connected in series, a plurality of cell gates for selecting the plurality of memory cells within the two adjacent memory cell blocks, each of the plurality of cell gates being formed with roughly rectangular closed loops or roughly U shaped open loops, each of the loops being connected to a corresponding cell of the memory cells in a corresponding memory cell unit of the plurality of memory cell units within one of the two adjacent memory cell blocks and being connected to a corresponding memory cell of the memory cells in a corresponding memory cell unit of the plurality of memory cell units within the other memory cell block of the two adjacent memory cell blocks and a plurality of pairs of first and second selection gates for selecting the memory cell block, the plurality of cell gates being located between one pair of the first and second selection gates within a corresponding block of the memory cell block. | 2010-02-04 |
20100027339 | PAGE BUFFER AND METHOD OF PROGRAMMING AND READING A MEMORY - A page buffer and method of programming and reading a memory are provided. The page buffer includes a first latch, a second latch, a data change unit and a program control unit. The first latch includes a first terminal for loading data of the lower page and the upper page. The second latch includes a first terminal for storing the data of the lower page and the upper page from the first latch. The data change unit is coupled to a second terminal of the first latch for changing a voltage of the second terminal of the first latch to a low level. The program control unit is coupled to the first terminal of the second latch and the cells, and controlled by the voltage of the first terminal of the first latch for respectively programming the data of the lower page and the upper page to a target cell. | 2010-02-04 |
20100027340 | PATTERN DEPENDENT STRING RESISTANCE COMPENSATION - Pattern dependent string resistance compensation of a memory device is generally described. In one example, an electronic device includes a first string of memory cells and a first bit line coupled with the first string of memory cells wherein a memory cell of the first string of memory cells is read, in part, by pre-charging the first bit line through the first string of memory cells to compensate for resistance of unselected cells in the first string of memory cells. | 2010-02-04 |
20100027341 | NONVOLATILE SEMICONDUCTOR MEMORY DEVICE AND NONVOLATILE SEMICONDUCTOR MEMORY SYSTEM - A memory may include word lines; bit lines; cells provided corresponding to intersections between the word lines and the bit lines; sense amplifiers detecting data; a column decoder selecting a certain bit line for the sense amplifiers to output read data or receive write data; a row decoder configured to select a certain word line; a charge pump supplying power to the sense amplifiers, the column decoder, and the row decoder; a logic circuit controlling the sense amplifiers, the column decoder, and the row decoder based on an address selecting the memory cells; a first power source input applying a voltage to the logic circuit; and a second power source input applying a voltage higher than a voltage of the first power source input to the charge pump, and to supply power to the charge pump at least at a data reading time and a data writing time. | 2010-02-04 |
20100027342 | Memory device and memory data determination method - A memory device and a memory data determination method are provided. The memory device may estimate a threshold voltage shift of a first memory cell based on data before the first memory cell is programmed and a target program threshold voltage of the first memory cell. The memory device may generate a metric of a threshold voltage shift of a second memory cell based on the estimated threshold voltage shift of the first memory cell. Also, the memory device may determine data stored in the second memory cell based on the metric. | 2010-02-04 |
20100027343 | Non-Volatile Memory Monitor - The invention provides circuits, systems, and methods for monitoring a non-volatile memory (NVM) cell, or an array of NVM cells. The monitor is capable of switching from a normal operating state to an evaluation state, monitoring for one or more particular characteristics, and returning to the normal operating state. Alternative embodiments of the invention are disclosed using various triggers and producing outputs capable of reporting or feeding back to influence the operation of the monitoring systems and methods, the NVM circuitry, or an external system. The invention includes an energy conservation feature, in that no power is consumed in the normal operating state, and low power in the evaluation state. | 2010-02-04 |
20100027344 | SEMICONDUCTOR MEMORY DEVICE - A drain voltage generator circuit includes a first switching element coupled between a first power supply voltage and an output end of the drain voltage generator circuit, a second switching element coupled in parallel to the first switching element and having a smaller current capability than that of the first switching element, and a control circuit for turning ON the second switching element and then the first switching element, and generates a voltage to supply to a drain of a memory cell. A source of the memory cell is set to be floated or grounded by a transistor. | 2010-02-04 |
20100027345 | ERASABLE NON-VOLATILE MEMORY DEVICE USING HOLE TRAPPING IN HIGH-K DIELECTRICS - A non-volatile memory is described having memory cells with a gate dielectric. The gate dielectric is a multilayer charge trapping dielectric between a control gate and a channel region of a transistor to trap positively charged holes. The multilayer charge trapping dielectric comprises at least one layer of high-K. | 2010-02-04 |
20100027346 | Asymmetric Single Poly NMOS Non-Volatile Memory Cell - An asymmetric non-volatile memory (NVM) cell for a CMOS IC formed by a standard CMOS process flow used to form both low voltage and high voltage transistors on a substrate. The NVM cell includes an NMOS floating gate transistor and an optional select transistor. The floating gate transistor includes an elongated floating gate having a first portion disposed over the channel region C | 2010-02-04 |
20100027347 | Three-Terminal Single Poly NMOS Non-Volatile Memory Cell - A three terminal non-volatile memory (NVM) cell for a CMOS IC is formed by a standard CMOS process flow. The NVM cell includes two transistors that share a common floating gate. The floating gate includes a first portion disposed over the channel region of the first (NMOS) transistor, a second portion disposed over the channel region of the second (NMOS or PMOS) transistor, and a third portion extending into an enlarged drain diffusion area away from the channel regions, whereby the gate-to-drain capacitance is higher than the gate-to-source capacitances. A pocket implant or CMOS standard LV N-LDD is formed under the second transistor to enhance CHE programming. Both HV LDD and LV LDD implants are introduced together enabling LDD implant merging under the floating gate extension. The floating gate is formed using substantially T-shaped, C-shaped, U-shaped, Y-shaped or O-shaped polysilicon structures. Various array addressing schemes are disclosed. | 2010-02-04 |
20100027348 | PROGRAM METHOD OF FLASH MEMORY DEVICE - A program method of a flash memory device includes inputting a first data and a second data to a page buffer coupled to memory cells including an even page and an odd page, pre-programming a first memory cell of the odd page using the first data, programming a second memory cell of the even page using the second data, and programming the pre-programmed first memory cell using the first data. | 2010-02-04 |
20100027349 | CURRENT SENSING SCHEME FOR NON-VOLATILE MEMORY - A current sensing scheme for non-volatile memory is disclosed comprising an apparatus for determining one or more memory cell states in a non-volatile memory device. The apparatus having a first memory cell coupled to a first bitline and a first sensing element coupled to the first bitline, the first sensing element operable to sense a voltage corresponding to a state of the memory cell wherein the sensed voltage is independent of a bitline voltage discharge over time of the first memory cell. | 2010-02-04 |
20100027350 | FLASH MEMORY PROGRAMMING AND VERIFICATION WITH REDUCED LEAKAGE CURRENT - A flash memory system configured in accordance with an example embodiment of the invention employs a virtual ground array architecture. During programming operations, target memory cells are biased with a positive source bias voltage to reduce or eliminate leakage current that might otherwise conduct through the target memory cells. A positive source bias voltage may also be applied to target memory cells during verification operations (program verify, soft program verify, erase verify) to reduce or eliminate leakage current that might otherwise introduce errors in the verification operations. | 2010-02-04 |
20100027351 | Memory device and memory programming method - A memory device and a memory programming method are provided. The memory device may program data in a multi-level cell (MLC) or a multi-bit cell (MBC) memory device. The memory device may include a memory cell array, a programming unit and a program level stabilization unit. The memory cell array may include a plurality of multi-level cells. The programming unit may be configured to program a first data page in the plurality of multi-level cells and to program a second data page in the plurality of multi-level cells having the programmed first data page. The program level stabilization unit may be configured to stabilize a program level of at least one of the first data page and the second data page. | 2010-02-04 |
20100027352 | NON-VOLATILE SEMICONDUCTOR MEMORY DEVICE - In a non-volatile semiconductor memory device, variations in voltage applied to a bit line when an erase voltage applying step is repeatedly executed are suppressed, thereby reducing variations in Vt after erasure. A memory array includes memory cells arranged in an array, a plurality of word lines, and a plurality of bit lines and main bit lines. The memory array also includes a usable region which can store data and an isolation region which cannot store data. Each bit line provided in the usable region is connected via a select transistor to the corresponding main bit line. At least one main bit line is connected not only to a bit line of the usable region, but also to a bit line of the isolation region via a select transistor. | 2010-02-04 |
20100027353 | Erase Method of Flash Device - In an erase method of a flash device, including a page buffer configured to transfer a virtual voltage in response to a discharge signal and further comprising strings each including memory cells and coupled to the page buffer via a respective bit line, applying a ground voltage to a gate of each of the memory cells and erasing the memory cells coupled to a selected bit line by supplying the virtual voltage wherein the virtual voltage is applied to the selected bit line and a unselected bit line. | 2010-02-04 |
20100027354 | SEMICONDUCTOR MEMORY DEVICE AND METHOD FOR TESTING SAME - A semiconductor memory device includes data input/output terminals (DQ | 2010-02-04 |
20100027355 | PLANAR DOUBLE GATE TRANSISTOR STORAGE CELL - A semiconductor device suitable for use as a storage cell includes a semiconductor body having a top surface and a bottom surface, a top gate dielectric overlying the semiconductor body top surface, an electrically conductive top gate electrode overlying the top gate dielectric, a bottom gate dielectric underlying the semiconductor body bottom surface, an electrically conductive bottom gate electrode underlying the bottom gate dielectric, and a charge trapping layer. The charge trapping layer includes a plurality of shallow charge traps, adjacent the top or bottom surface of the semiconductor body. The charge trapping layer may be of aluminum oxide, silicon nitride, or silicon nanoclusters. The charge trapping layer may located positioned between the bottom gate dielectric and the bottom surface of the semiconductor body. | 2010-02-04 |
20100027356 | Dynamic On-Die Termination of Address and Command Signals - A system includes a plurality of memory devices arranged in a fly-by topology, each of the memory devices having on-die termination (ODT) circuitry for connection to an address and control (RQ) bus. The ODT circuitry has at least one input for controlling termination of one or more signal lines of the RQ bus. Application of a first logic level to the at least one input enables termination of the one or more signal lines. Application of a second logic level to the at least one input disables termination of the one or more signal lines. | 2010-02-04 |
20100027357 | Memory System Having Distributed Read Access Delays - A system having a plurality of memory cells organized in rows and columns. Each column includes upper and lower sets of memory cells connected to corresponding common upper/lower bit lines. Each column includes an evaluation circuit coupled to the upper and lower bit lines and configured to evaluate signals on these bit lines and to produce an output signal. Each of the upper and lower bit lines has an associated bit line delay, one of which is greater than the other. The evaluation circuit has first and second inputs which have associated evaluation delays, one of which is greater than the other. In each column, the bit line having the greater bit line delay is connected to the evaluation circuit input having the smaller evaluation delay, and the bit line having the smaller bit line delay is connected to the evaluation circuit input having the greater evaluation delay. | 2010-02-04 |
20100027358 | Semiconductor memory device capable of read out mode register information through DQ pads - A semiconductor memory device is provided that is capable of reading out mode register information stored in a register adapted for LPDDR2 (Low Power DDR2), through DQ pads. The semiconductor memory device includes a mode register control unit configured to receive address signals, a mode register write signal and a mode register read signal and generate a flag signal and at least one output information signal, and a global I/O line latch unit for transferring the output information signal to a global I/O line in response to the flag signal. | 2010-02-04 |
20100027359 | Memory test circuit which tests address access time of clock synchronized memory - A circuit for testing an access time of a clock synchronization type memory, includes a delay circuit, a sampling circuit and a coincidence detection circuit. The delay circuit generates a delayed clock obtained by delaying, by a time acceptable for a memory performance, a clock inputted to a memory. The sampling circuit takes in and outputs an output from the memory at the timing of the delayed clock. The coincidence detection circuit detects coincidence or non-coincidence by comparing the output from the sampling circuit with an expected value for the output from the memory. | 2010-02-04 |
20100027360 | INTEGRATED CIRCUIT HAVING AN ARRAY SUPPLY VOLTAGE CONTROL CIRCUIT - An integrated circuit comprises a plurality of memory cells and an array supply voltage control circuit. The plurality of memory cells are organized in rows and columns. A row comprises a word line and all of the memory cells coupled to the word line. A column comprises a bit line pair and all of the memory cells coupled to the bit line pair. The array supply voltage control circuit is coupled to the plurality of memory cells. The array supply voltage control circuit is for receiving a power supply voltage and for providing a reduced power supply voltage to memory cells of a selected column during a write operation in response to a voltage differential on the bit line pair of the selected column. | 2010-02-04 |
20100027361 | Information Handling System with SRAM Precharge Power Conservation - An information handling system (IHS) includes a processor with on-chip or off-chip SRAM array. After a read operation, a control circuit may instruct the SRAM array to conduct a precharge operation, or alternatively, instruct the SRAM array to conduct an equalize bitline voltage operation. A read operation may follow the precharge operation or the equalize bitline voltage operation. The control circuit may instruct the SRAM array to conduct an equalize bitline voltage operation if an equalized voltage of a bitline pair exhibits more that a predetermined amount of voltage. Otherwise, the control circuit instructs the SRAM array to conduct a precharge operation before the next read operation. | 2010-02-04 |
20100027362 | SEMICONDUCTOR MEMORY DEVICE FOR LOW VOLTAGE - A semiconductor memory device includes a first cell array including a plurality of unit cells and a bit line sense amplifying unit for sensing and amplifying data signals stored in the unit cells. Each unit cell is provided with a PMOS transistor and a capacitor. Therefore, the semiconductor memory device efficiently operates with low voltage without any degradation of operation speed. | 2010-02-04 |
20100027363 | REFRESH CONTROLLER AND REFRESH CONTROLLING METHOD FOR EMBEDDED DRAM - The present invention provides a refresh controller for embedded DRAM, configured to receive an external access signal and generate refresh enabling signal REFN, refresh address signal CRA and confliction signal, said embedded DRAM comprising a plurality of memory groups, said controller comprising: a status controlling module that generates refresh enabling signal REFN and last refresh signal last_ccr according to the refresh interval and clock cycles; a refresh searching module that searches in said plurality of memory bank groups for at least one memory bank group that is to be refreshed in the refresh interval, and generates refresh address signal CRA according to the external access signal and the searched memory bank group; a scoreboard module that records the status of each of said plurality of memory bank groups according to said refresh address signal CRA and external access signal; and a confliction detecting module that generates confliction signal according to said external access signal, last refresh signal last_ccr and the status of each of said memory banks. A corresponding refresh controlling method is also provided in the present invention. | 2010-02-04 |
20100027364 | MULTI-PORT MEMORY DEVICE HAVING SELF-REFRESH MODE - The multi-port memory device includes a mode input/output controller for receiving a flag signal and generating a self-refresh entry signal and a self-refresh escape signal, a refresh interval signal generator for providing a self-refresh interval signal notifying a self-refresh interval in response to the self-refresh entry signal and the self-refresh escape signal, a refresh cycle signal generator for periodically generating a cycle-pulse signal during an activation of the self-refresh interval signal, an internal refresh signal generator for producing an internal refresh signal in response to the self-refresh entry signal and the cycle-pulse signal, and an internal address counter for generating an internal address in response to the internal refresh signal. | 2010-02-04 |
20100027365 | NON-VOLATILE MEMORY DEVICE CAPABLE OF SUPPLYING POWER - A non-volatile memory device capable of supplying power is provided. The non-volatile memory device includes an electrical storage device for supplying a stored power, a charging control circuit coupled to the electrical storage device, a non-volatile memory, an input/output (I/O) interface, and a power control circuit. The I/O interface connects an electronic apparatus for transmitting an external power output from the electronic apparatus to the non-volatile memory and the charging control circuit, such that the charging control circuit could control a charging current and a charging voltage of the electrical storage device. The power control circuit converts the stored power into a backup power, and monitors whether a voltage value of the external power is less than a predetermined value. If the result is positive, the power control circuit controls the charging control circuit to stop charging the electrical storage device, and outputs the backup power through the I/O interface. | 2010-02-04 |
20100027366 | SEMICONDUCTOR MEMORY DEVICE - In a semiconductor memory device, a voltage rise due to IR-DROP is suppressed which occurs when a ground voltage is applied to a memory cell during a program operation. Discharge transistors are provided between the ground and bit lines connected to the source and drain of the memory cell. The discharge transistors receive mutually independent discharge control signals which are generated and outputted from a DS decoder driver at the respective gates thereof. To the bit line which applies the ground voltage to the memory cell, the ground voltage can be set using the discharge transistor. | 2010-02-04 |
20100027367 | ROW MASK ADDRESSING - Electronic apparatus, systems, and methods may operate structures to access a portion of a row of a memory array without accessing the entire row. Additional apparatus, systems, and methods are disclosed. | 2010-02-04 |
20100027368 | READ COMMAND TRIGGERED SYNCHRONIZATION CIRCUITRY - A memory READ command triggered clock synchronization mode turns on a clock synchronization circuit only for memory READ operations. The clock synchronization circuit achieves a signal lock with the reference clock signal in less time than the column address strobe latency. Precise memory READ operations are thus possible without wasting power when such operations are not performed by allowing the clock synchronization circuitry to be turned off. | 2010-02-04 |
20100027369 | SEMICONDUCTOR INTEGRATED CIRCUIT DEVICE - A clock-generating circuit for forming internal clock signals by comparing a signal obtained by delaying, through a variable delay circuit, an input clock signal input through an external terminal with the input clock signal through a phase comparator circuit, and so controlling the delay time of the variable delay circuit that they are brought into agreement with each other, wherein the clock-generating circuit and an internal circuit to be operated by the clock signals formed thereby are formed on a common semiconductor substrate, and an element-forming region in which the clock-generating circuit is formed is electrically isolated from an element-forming region in which the digital circuit is constituted on the semiconductor substrate relying upon the element-isolation technology. The power-source passages, too, are formed independently of other digital circuits. | 2010-02-04 |
20100027370 | Process to generate water based adhesives and their use - Process to generate a water based adhesive by mixing a re-dispersible powder adhesive and water, optionally together with other components, characterized by mixing a re-dispersible powder adhesive, water and optionally other components such that the final water based adhesive contains a re-dispersed powder adhesive in an amount of about 0.5% to 80% by weight and has a Brookfield viscosity (23° C./20 RPM) from about 10 to 250000 mPas, wherein : the mixing is carried out as a micro-batch or a continuous process with a volume of the mixing chamber of about 0.001 to 200 litres and with a mixing time of about 0.01 to 500 seconds, and the ratio of the diameter of at least one mixer blade to the diameter of the mixing chamber is about 0.50 to 0.99. | 2010-02-04 |
20100027371 | Closed Blending System - Methods and systems for blending a dry material with a fluid in a closed environment are disclosed. A liquid component is supplied from a liquid delivery system to a mixing chamber. A dry component or a high solid content slurry is then supplied from a dry material tank or an external proppant storage to the mixing chamber. The dry component or high solid content slurry is then mixed with the liquid component in a closed system to prepare a desired mixture. | 2010-02-04 |
20100027372 | MICROCHIP FOR FORMING EMULSION AND METHOD FOR MANUFACTURING THE SAME - A microchip for forming an emulsion has a first glass substrate, a second glass substrate and a silicon substrate. The silicon substrate has formed therein a first fluid flow path through which a first fluid flows and a second fluid flow path through which a second fluid that is not mixed with the first fluid flows. The first fluid flow path has a plurality of branched flow paths that join at a joint portion. The second fluid flow path communicates with the joint portion. The silicon substrate has formed therein an emulsion formation flow path that faces an edge portion of the second fluid flow path at the joint portion. An emulsion composed of the first fluid and the second fluid that is surrounded by the first fluid is formed in the emulsion formation flow path. | 2010-02-04 |
20100027373 | Food processing machine - A food processing assembly ( | 2010-02-04 |
20100027374 | Methods and Systems for Efficiently Acquiring Towed Streamer Seismic Surveys - Methods and systems for efficiently acquiring towed streamer marine seismic data are described. One method and system comprises positioning a plurality of source-only tow vessels and one or more source-streamer tow vessels to acquire a wide- and/or full-azimuth seismic survey without need for the spread to repeat a path once traversed. Another method and system allows surveying a sub-sea geologic feature using a marine seismic spread, the spread smartly negotiating at least one turn during the surveying, and shooting and recording during the turn. This abstract is provided to comply with the rules requiring an abstract, allowing a searcher or other reader to quickly ascertain the subject matter of the technical disclosure. It is submitted with the understanding that it will not be used to interpret or limit the scope or meaning of the claims. 37 CFR 1.72(b). | 2010-02-04 |
20100027375 | Method of summing dual-sensor towed streamer signals using seismic reflection velocities - A merged particle velocity signal is generated by merging a recorded vertical particle velocity signal, scaled in an upper frequency range using a time-dependent arrival angle as determined by velocity analysis, with a simulated particle velocity signal, calculated in a lower frequency range from a recorded pressure signal using a time-varying filter based on the time-dependent arrival time. Combined pressure and vertical particle velocity signals are generated by combining the recorded pressure and merged velocity signals. | 2010-02-04 |
20100027376 | Optimizing Seismic Processing and Amplitude Inversion Utilizing Statistical Comparisons of Seismic to Well Control Data - A method for obtaining enhanced seismic data and optimized inverted reflectivities includes computing statistical well characterizations based upon band-limited well reflectivities for a subsurface region. Sets of processed seismic data are computed by applying differing processing sequences to seismic data corresponding to the subsurface region. Inverted reflectivities are computed by inverting the sets of processed seismic data. Statistical seismic characterizations are computed based upon the inverted reflectivities. Statistical difference measurements (SDMs) are computed between the statistical well and seismic characterizations. An optimal processing sequence is selected based upon the computed SDMs. Enhanced seismic data is obtained by processing the seismic data corresponding to the subsurface region. An optimal seismic inversion algorithm is obtained based upon the computed SDMs. The seismic data is inverted using the optimal seismic inversion algorithm to produce a set of optimized inverted reflectivities. | 2010-02-04 |
20100027377 | Locating oil or gas actively by exciting a porous oil and gas saturated system to give off its characteristic resonance response, with optional differentiation of oil, gas and water - This patent deals with methods to selectively excite and analyze the resonance phenomena existing in an enclosed oil, gas and or water reservoir, thereby locating its presence, by doing qualitative and quantitative estimates of its extent via forward modeling. The oil, gas or water reservoir is represented as a fluid filled crack system or as a fluid saturated sponge located in solid rock. This patent covers the actively excited response and details methods to optimize the excitation. Due to interaction between either fluid filled fractures or fluid saturated rock lenses and the surrounding rock, the incident seismic energy is amplified in specific frequency ranges corresponding to the resonance frequencies of such systems. Measurements are made over the survey area, singly or in arrays. These are first used to determine qualitatively the resonance behavior, by relating them to resonance signal sources and possibly their direction. Overall statistical analysis assesses dominant frequencies in the spectrum. H/V analysis excludes resonance effects in rock structures. Time windows are used in the frequency domain to help isolate oscillations in a cursory manner in the noise, which can then be refined to extract oscillation parameters more precisely with the Sompi method. Such found oscillations can then be related to oscillator properties from theoretical and numerical model simulations. A direction analysis with array measurements can be used to locate sources in the earth. Dimensions of the source are estimated via mapping techniques of strong signal areas. The influence of gas bubbles on the fluid velocity, expected to often present, enhances the impedance difference significantly, leading to a stronger resonance effect; to take this into consideration is an important part of this patent. A qualitative method in form of a numerical simulation using one of several specific physical concepts is used for further analysis. For instance the oscillation behavior is known from existing fluid dynamic research for cracks. A single or an assemblage of cracks can be used. For fluid saturated rock pillows with significant over-pressure there is a simplified theoretical model presented. Numerical models using Biot's theory for higher precision results represent a further example. By using a successive forward modeling/investigation with feedback, more details about the fluid saturated area below the surface are gained. It is also possible to determine the type of fluid present with the techniques of this patent. The physical properties of oil, water and gas affect the oscillating characteristics (frequency and Q value) of fluid filled fractures and fluid filled pillows enclosed in rock. These differences in the oscillations allow determining the type of fluid present. Specifically a qualitative survey method and a quantitative method based on a numerical modeling in conjunction with the Monte Carlo method are used to relate the oscillation characteristics to fluid properties. In the Monte Carlo method only fluid parameters are varied, while all other parameters are kept constant. There are specific dependencies on crack length in the case of cracks which needs to be properly estimated to obtain good results. We expect similar constraints for liquid filled pillows. The uniqueness of this method is that it is directly sensitive to the oil or gas itself, because the resonance effect is only present when a fluid is there. Non fluid related oscillations due to impedance differences have shear waves involved and can be excluded using H/V technique. In summary the patent uses techniques to relate the actual measurement with a numerical model based on specific physical concepts, and so arriving at relevant conclusions about the reservoir. | 2010-02-04 |
20100027378 | METHODS FOR DETECTING HUMANS - A method of detecting a human, that includes (a) measuring the ultrasonic signal emitted from human footsteps; (b) measuring the human body motion Doppler signature; reviewing the measurements of steps (a) and (b); and (d) determining the presence of a human. | 2010-02-04 |
20100027379 | Ultrasonic Through-Wall Communication (UTWC) System - Apparatus for communicating information across a solid wall has one or two outside ultrasonic transducers coupled to an outside surface of the wall and connected to a carrier generator for sending an ultrasonic carrier signal into the wall and for receiving an output information signal from the wall. One or two inside ultrasonic transducers are coupled to an inside surface of the wall and one of them introduces the output information signal into the wall. When there are two inside transducers inside the wall, one receives the carrier signal and the second transmits the carrier after it is modulated by the output information from the sensor. When there is one inside transducer, the output information from the sensor is transmitted by changing the reflected or returned signal from the inside transducer. A power harvesting circuit inside the wall harvests power from the carrier signal and uses it to power the sensor. | 2010-02-04 |
20100027380 | Sensor unit having a directional aperture - A casing of a sensor unit has a directional aperture, structure or sail. The sensor is used in a distributed system for measuring, processing and displaying information from a plurality of sensors comprises a plurality of sensor units. A method for quick detection of offenders of oil, gas or other pipes, by monitoring the protective cathodic voltage and detecting quick changes in the voltage. A method for detecting leakage from a pipe using multiple channels/inputs, wherein a low frequency range input measures seismic noises, and a high frequency range input measures cavitation noises, and wherein a leakage indication is issued if both the low frequency and high frequency noises are simultaneously detected. A low power consumption Wireless communications protocol is used. | 2010-02-04 |
20100027381 | TIMEPIECE DISPLAYING THE CURRENT TIME AND INCLUDING AT LEAST FIRST AND SECOND DEVICES DISPLAYING A TIME-RELATED QUANTITY - Timepiece displaying the current time and including at least first and second display devices for a time-related quantity, the first and second display devices each being driven by a drive mechanism including a drive wheel ( | 2010-02-04 |
20100027382 | HAIRSPRING FOR A BALANCE WHEEL/HAIRSPRING RESONATOR - Hairspring for a balance wheel/hairspring resonator, comprising n blades, where n≧2, which are fastened via at least one of their respective homologous ends and wound in spirals with an angular offset capable of neutralizing the lateral forces liable to be exerted on its central arbor when one of the ends of each blade is moved angularly around said central arbor relative to its other end. | 2010-02-04 |
20100027383 | TRANSPARENT MEMBER, TIMEPIECE, AND METHOD OF MANUFACTURING A TRANSPARENT MEMBER - A transparent member has a transparent substrate, and an antireflection coating that has a high index of refraction layer made of silicon nitride and a low index of refraction layer made of silicon oxide alternately laminated on at least a part of a surface of the substrate. The content of silicon nitride in the region to a depth of 150 nm from the outside surface of the antireflection coating is 30-50 vol %. | 2010-02-04 |
20100027384 | OPTICAL HEAD DEVICE, OPTICAL INFORMATION RECORDING/REPRODUCING DEVICE AND ERROR SIGNAL GENERATION METHOD - A diffractive optical element generates main and two sub beams from an output light of a light source. An objective lens focuses the main and two sub beams on an optical recording medium. An optical detector receives the main and two sub beams reflected by the optical recording medium. The diffractive optical element is divided into six regions having different optical characteristics by a tangential direction division line corresponding to the tangential direction of the optical recording medium, first and second radial direction division lines corresponding to the radial direction thereof. A light in the first sub beam passing an intersection of the first radial and tangential direction division lines passes a region near the center of the objective lens. A light in the second sub beam passing an intersection of the second radial and the tangential direction division lines passes a region near the center of the objective lens. | 2010-02-04 |
20100027385 | ABERRATION CORRECTING DEVICE, OPTICAL HEAD, AND OPTICAL DISC APPARATUS - An aberration correcting device includes: a first transparent electrode; a second transparent electrode; and a liquid crystal layer disposed between the first transparent electrode and the second transparent electrode, having refractive index varying according to an electric field applied to the liquid crystal layer, wherein the first transparent electrode has a first circular dividing line and a second circular dividing line formed outside the first circular division line arranged to be concentric with the second circular dividing line, and wherein a region between the first circular dividing line and the second circular dividing line is radially divided by plural radial dividing lines. | 2010-02-04 |
20100027386 | OPTICAL PICKUP APPARATUS, FOCAL-POINT ADJUSTING METHOD, AND OPTICAL DISC APPARATUS - An optical pickup apparatus is provided with an angle adjusting element. The angle adjusting element changes a propagation direction of luminous fluxes of four luminous flux regions set about an optical axis of the laser light, out of laser light reflected by a disc, and mutually disperses the luminous fluxes. A signal light region in which signal light only is present appears on a detecting surface of a photodetector. A sensor pattern for signal light is placed at a position irradiated with the signal light within this region. A sensor pattern for a coma aberration detection is placed on an inner side of this region. | 2010-02-04 |
20100027387 | INFORMATION RECORDING APPARATUS, MEDIUM, AND PROGRAM - An information recording apparatus changes a write strategy to reduce a pulse width of a write pulse to write a minimum mark, and records data based on the changed write strategy. | 2010-02-04 |
20100027388 | INFORMATION REPRODUCING APPARATUS AND METHOD, AND COMPUTER PROGRAM - An information reproducing apparatus ( | 2010-02-04 |
20100027389 | BUFFERING CONTROL METHOD, AND BUFFERING CONTROL DEVICE - When receiving the reproduced data from the optical disc and buffering same, the buffering from the correct position can be started on the basis of the synchronous signal and the address information included in the sub data which was received simultaneously. | 2010-02-04 |
20100027390 | SIGNAL CONVERSION MODULE AND OPTICAL DISC APPARATUS USING THE SAME - The MTD has some problems. Firstly, even if an input bandwidth is widened to obtain a larger SNR gain, an increase in the SNR gain cannot always be obtained due to the clock jitter that increases clock noise. Secondly, noise is sometimes superimposed on the clock supplied to an ADC when a transmission path connecting a clock-signal source to an ADC has a certain distance or when a certain form of mounting these members is employed. The noise lowers the performance. Provided is an optical disc apparatus including: a means for regulating loosely the bandwidth of a pulsed read signal; a means for boosting high-frequency components of a waveform of a driving signal of a laser diode; and a means for synchronizing autonomously a driving clock of the ADC and a DAC with a clock of the pulsed read signal. | 2010-02-04 |
20100027391 | Control apparatus and method for content reproducing - In a content reproducing system ( | 2010-02-04 |