| 05th week of 2010 patent applcation highlights part 23 |
| Patent application number | Title | Published |
|---|
| 20100026292 | METHOD AND APPARATUS FOR MEASURING MAGNETIC ANISOTROPY OF A CONDUCTIVE WIRE OR TAPE - A method and apparatus for measuring the magnetic field anisotropy of critical currents in conductive wires and conductive tapes having lengths of at least one meter. In one embodiment, the method and apparatus are adapted to measure the magnetic field anisotropy of critical currents in superconducting wires and tapes. The apparatus includes a magnetic field generation assembly that is capable of generating a magnetic field. The magnetic field is orthogonal to a current passing through a conductive wire or conductive tape positioned on an axis of the assembly. The magnetic field generation assembly and magnetic field are rotatable about the axis. | 2010-02-04 |
| 20100026293 | METHOD FOR ESTIMATING FORMATION SKIN DAMAGE FROM NUCLEAR MAGNETIC RESONANCE MEASUREMENTS - A method for determining skin factor of a subsurface rock formation from within a wellbore drilled therethrough includes measuring a nuclear magnetic resonance property of the formation at a plurality of lateral depths therein. The measured nuclear magnetic resonance property is used to estimate the skin factor. | 2010-02-04 |
| 20100026294 | BLIP DESIGN FOR RANDOM SAMPLING COMPRESSED SENSING OF FLYBACK 3D-MRSI - A method of providing a magnetic resonance spectral image (MRSI) is provided. A magnetic resonance imaging excitation is applied. Data is acquired, comprising applying an oscillating gradient in a first dimension and applying blips in at least a second dimension in a pseudo-random order to acquire pseudo-random temporally undersampled spectral data in at least two planes. The pseudo-random order is used to reconstruct a magnetic resonance spectral image in at least two dimensions. | 2010-02-04 |
| 20100026295 | Magnetic resonance imaging apparatus and method - A magnetic resonance imaging apparatus includes a movement unit which moves a subject placed in a static magnetic field, a collector which collects data corresponding to a magnetic resonance signal emitted from the subject, a detector which detects a position of a particular section of the subject in the static magnetic field, a reconstruction unit which reconstructs an image, based on the collected data, when the detected position falls within an allowable area, and a controller which controls the movement unit to compensate for a deviation of the detected position from a reference position. | 2010-02-04 |
| 20100026296 | MAGNETIC RESONANCE IMAGING APPARATUS - A magnetic resonance imaging apparatus enabling highly precise spectrum measurement even when resonance frequency changes during MRS or MRSI measurement is provided. | 2010-02-04 |
| 20100026297 | METHOD FOR RELAXATION-COMPENSATED FAST MULTI-SLICE CHEMICAL EXCHANGE SATURATION TRANSFER MRI - A volumetric APT imaging sequence is provided that acquires multi-slice images immediately after a single long continuous wave (CW) RF irradiation, wherein the relaxation-induced loss of CEST contrast is compensated for during post-processing. Thus, a fast volumetric pH-weighted APT imaging technique is provided. | 2010-02-04 |
| 20100026298 | Method for imaging Acoustically induced rotary saturation with a magnetic resonance imaging system - A method for producing a magnetic resonance image indicative of mechanical waves applied to a subject is provided. Mechanical waves are applied to the subject at a selected frequency to induce oscillatory motion in tissues within the subject at the same frequency. A spin-lock radiofrequency pulse, having a resonance frequency matched to that of the induced oscillatory motion, is applied to the subject. This results in a spin-lock condition, during which transverse magnetization experiences rotary saturation resulting from magnetic field fluctuations produced by the oscillatory motion. Image data is acquired from the saturated transverse magnetization and images are reconstructed. As a result of the rotary saturation, these images exhibit darkening in those voxel locations affected by the oscillatory motion. In this manner, an image indicative of the applied mechanical waves is produced. | 2010-02-04 |
| 20100026299 | METHOD FOR RADIO-FREQUENCY NUCLEAR MAGNETIC RESONANCE IMAGING - Accumulated spin magnetization phase within a RF MRI procedure can be used for providing an orderly k-space traversal. By operating a transmit array adapted to produce two B1 fields in alternation, where the B1 fields are substantially uniform in amplitude over a sample volume of the MRI setup, and the B1 fields have respective spatial phase distributions such that selection of a difference in spatial derivatives of the spatial phase distributions permits control over a size of a step in k-space applied by successive refocusing pulses for generating the B1 fields in alternation. Each alternating refocusing pulse issued within a T2 time causes a step through k-space in an encoding direction determined by the difference in spatial derivatives. | 2010-02-04 |
| 20100026300 | METHOD FOR IDENTIFYING A SAMPLE IN A CONTAINER, E.G. WHEN CONDUCTING A TRAVELER SURVEY IN THE CHECK-IN AREA, BY DETERMINING THE RESONANCE FREQUENCY AND THE QUALITY OF A DIELECTRIC RESONATOR TO WHICH THE CONTAINER IS ARRANGED - A method and apparatus for identifying a sample in a container, provide for the container with the sample being disposed relative to a resonator, a high-frequency signal being coupled into the resonator for exciting a resonant mode of the resonator, the resonant electric field of the resonator penetrating part of the sample in the container, the resonance curve of at least one resonant mode being measured with and without the sample, and the sample being identified based on the determined change in the resonance frequency compared to a measurement without sample. | 2010-02-04 |
| 20100026301 | Detector arrangement - A detector arrangement with a plurality of detector units is disclosed, to each of which a data processing unit is assigned. An embodiment of the detector arrangement includes a cooling system with cooling units which are thermoconductively connected to the detector units and data processing units for cooling. The cooling units are connected to a distribution unit by which a coolant may be supplied to the cooling units in parallel. | 2010-02-04 |
| 20100026302 | NMR CryoMAS probe for high-field wide-bore magnets - All critical circuit components, including the sample coils, are located along with the spinner assembly in a region that may be evacuated to high vacuum for thermal insulation and high-voltage operation. A hermetically sealed spinner assembly simultaneously satisfies the requirements of hermeticity, low total emissivity, rf compatibility, spinning performance, magnetic compatibility, and high filling factor by utilizing metal construction except for the central region near the rf sample coils. Hence, it is possible to maintain high vacuum in the region external to the MAS spinner assembly even over a broad range of bearing and drive gas temperatures. A bundle of optical fibers is provided for tachometry for spin rates up to 60 kHz. The use of alumina disc capacitors allows the noise contributions from the most critical capacitors to be reduced to a minor fraction of the total and simplifies high voltage operation. | 2010-02-04 |
| 20100026303 | DOUBLY RESONANT HIGH FIELD RADIO FREQUENCY SURFACE COILS FOR MAGNETIC RESONANCE - A radio frequency coil comprises an annular conductor or parallel annular conductors ( | 2010-02-04 |
| 20100026304 | Method and Apparatus for Analysing Geological Features - An apparatus ( | 2010-02-04 |
| 20100026305 | Method and Apparatus for Imaging Boreholes - A method and apparatus for imaging wellbores is provided that in one aspect may include inducing an electrical signal into a formation, receiving a current signal responsive to the induced electrical signal by at least one measure electrode placed in a pad disposed in the wellbore, generating an impedance signal in response to the received current signal using a receiver circuit placed in the pad and coupled to the at least one measure electrode and providing an image of the wellbore wall using the impedance signal. | 2010-02-04 |
| 20100026306 | METHOD AND APPARATUS FOR TELEMATICS-BASED VEHICLE NO-START PROGNOSIS - A system and method for determining the status of a vehicle battery to determine whether the battery may not have enough charge to start the vehicle. The method includes collecting data relating to the battery on the vehicle and collecting data relating to the battery at a remote back-office. Both the vehicle and the remote data center determine battery characteristics based on the collected data and the likelihood of a vehicle no-start condition, where the algorithm used at the remote back-office may be more sophisticated. The data collected at the remote back-office may include vehicle battery information transmitted wirelessly from the vehicle, and other information, such as temperature, battery reliability, miles that the vehicle has driven per day, ambient temperature, high content vehicle, etc. Both the vehicle and the remote back-office may determine the battery open circuit voltage. | 2010-02-04 |
| 20100026307 | METHODS FOR PREDICTING THE FUTURE PERFORMANCE OF FUEL CELL STACKS AND INDIVIDUAL FUEL CELLS - Method embodiments for analyzing the future performance of a fuel cell stack comprise the steps of: a) generating a first polarization curve data by experimentally measuring the voltage of a fuel cell stack across a current range at a first interval; b) dividing the current range into a plurality of discrete current ranges; c) calculate an average voltage value for each discrete current range; d) fitting all average voltage values to produce a first average polarization curve; e) conducting steps a) through d) at a second interval to produce a second average polarization curve; f) comparing the first average polarization curve to the second polarization curve to calculate the drop in voltage and thereby the fuel cell stack degradation; and g) utilizing the calculated drop in voltage between the first and second polarization curves to predict the polarization of the fuel cells at future time intervals. | 2010-02-04 |
| 20100026308 | CIRCUIT FOR MEASURING BATTERY VOLTAGE AND METHOD FOR BATTERY VOLTAGE MEASUREMENT USING THE SAME - The present invention relates to circuit for measuring battery voltage and method for battery voltage measurement using the same. In the circuit for measuring battery voltage and method for battery voltage measurement using the same, three or more capacitors, which form a closed loop and are sequentially connected, are provided, and voltages of voltage sources are measured by using the three or more capacitors in turn, which prevents measurement errors from occurring due to residual charges in the capacitors and enables more precise measurement. Further, according to the present invention, since the three or more capacitors are alternately charged and discharged, the delay in time is decreased, and the voltages of the plurality of voltage sources can be measured at one time. Therefore, it is possible to reduce the amount of time required to measure battery voltage. | 2010-02-04 |
| 20100026309 | Modular Electrical System and Method for its Operation - A modular electrical system including a first current-emitting source module and a first current-consuming sink module which is connected to the first current-emitting source module is provided. The first sink module has a first sink identification means to identify maximum power requirement of the first sink module. The object of providing power balancing between a first source module and a first sink module is achieved in that the first source module has a first source identification means for identifying the power capacity of the first source module, wherein in order to calculate a power ratio of the system the first sink identification means and the first source identification means are connected to a two-wire line for the purpose of generating a differential voltage. | 2010-02-04 |
| 20100026310 | Communication System Fault Location Using Signal Ingress Detection - Detecting ingress of a transmitted signal into a cable communication system due to a radio frequency signal transmitted from a moving vehicle and interrogation of transmitter location over a separate wireless link provides monitoring of shielding integrity or flaws there in a cable communication system. The location of a shielding flaw may then be precisely located in a closed loop fashion without risking overload of the cable communication system or interference with upstream signaling therein by detecting ingress signal strength and controlling transmitted signal strength while providing a user-perceptible indication of ingress signal strength which is compensated for the control of transmitted signal strength and thus indicates proximity of a hand-held instrument or transmitter to said shielding flaw. | 2010-02-04 |
| 20100026311 | BOOSTING SYSTEM FAILURE DIAGNOSIS DEVICE, BOOSTING CIRCUIT CONTROLLER AND VEHICLE - A boosting converter and a boosting control unit are mounted on a vehicle. A failure diagnosis unit makes a failure diagnosis of an atmospheric pressure sensor based on a detection result of the atmospheric pressure sensor and on a detection result of an intake pressure sensor detecting engine intake pressure that changes in accordance with a change in the atmospheric pressure. Boosting control unit controls an output voltage of the boosting converter based on the detection result of atmospheric pressure sensor and the detection result of intake pressure sensor. | 2010-02-04 |
| 20100026312 | System and Method for Power System Component Testing - A method of testing a power system component is disclosed. The method comprises coupling a test set to the power system component and displaying a test form on a display integral with the test set. The method also comprises inputting at least a first test control parameter into the test form using an interface integral with the test set. The method also comprises stimulating the power system component using the test set to produce a first response of the power system component, wherein the stimulating is performed based at least in part on the first test control parameter. The method also comprises displaying a first test result in the test form on the display, wherein the first test result is based on the first response. | 2010-02-04 |
| 20100026313 | Capacitance Structures for Defeating Microchip Tampering - Apparatus, method and program product may detect an attempt to tamper with a microchip by detecting an unacceptable alteration in a measured capacitance associated with capacitance structures proximate the backside of a microchip. The capacitance structures typically comprise metallic shapes and may connect using through-silicon vias to active sensing circuitry within the microchip. In response to the sensed change, a shutdown, spoofing, self-destruct or other defensive action may be initiated to protect security sensitive circuitry of the microchip. | 2010-02-04 |
| 20100026314 | SYSTEM AND METHOD FOR ON-CHIP JITTER INJECTION - High Speed I/O interfaces ( | 2010-02-04 |
| 20100026315 | SIGNAL MEASUREMENT SYSTEMS AND METHODS - Signal measuring systems, and measurement methods are disclosed. | 2010-02-04 |
| 20100026316 | ELECTRONIC APPARATUS NOISE MEASUREMENT METHOD - Second and third ports of a network analyzer are individually connected via cables to predetermined connection points on a differential transmission circuit on an object to be measured. A differential cable is connected to the differential transmission circuit. An antenna for receiving an electromagnetic wave radiated from the differential cable is connected to a first port of the network analyzer via a first cable. The network analyzer measures a three-port S parameter of the first, second, and third ports and calculates common-mode and normal-mode components of noise radiated from the differential cable. As a result, the source of noise in an electronic apparatus can be determined, and common-mode noise and normal-mode noise can be separately measured. | 2010-02-04 |
| 20100026317 | IMPEDANCE-BASED ARC FAULT DETERMINATION DEVICE (IADD) AND METHOD - Embodiments according to the present invention provide an Impedance-based Arc-Fault Determination Device (IADD) and method that, when attached to an electrical node on the power system and through observations on voltage, current and phase shift with a step load change, determine the effective Thevenin equivalent circuit or Norton equivalent circuit at the point of test. The device and method determine the expected bolted fault current at the test location of interest, which enables calculation of incident energy and the assignment of a flash-hazard risk category. | 2010-02-04 |
| 20100026318 | Coupling Loop - A coupling loop or antenna is provided that can be used with a system that determines the resonant frequency of a sensor by adjusting the phase and frequency of an energizing signal until the frequency of the energizing signal matches the resonant frequency of the sensor. In one embodiment multiple energizing loops energize an implanted sensor and a sensor coupling loop connected to an input impedance that is at least two times greater than the inductance of the sensor coupling loop receives the sensor signal. | 2010-02-04 |
| 20100026319 | SENSOR DEVICE, AND PORTABLE COMMUNICATION TERMINAL AND ELECTRONIC DEVICE USING THE SENSOR DEVICE - A sensor device for detecting a positional relationship between a first member and a second member, includes a first electrode provided on a surface of the first member and supplied with an alternating signal of a first frequency, a second electrode provided on a surface of the second member and supplied with an alternating signal of a second frequency, and a beat detector which detects a beat frequency component corresponding to a difference between the first and second frequencies indicative of the positional relationship between the first member and the second member, when the positional relationship between the first and second members changes to cause the first electrode to approach the second electrode. | 2010-02-04 |
| 20100026320 | Sensing device for measuring a position of nanoscale motion apparatus - A nanoscale motion apparatus comprises a fixed base, a movable platform, and means for moving the movable platform connected between the fixed base and the movable platform. A sensing device comprises a holder, at least two nanosensors, and a measurement plate. The holder is mounted on the fixed base. The nanosensors are configured on the holder. The measurement plate is mounted on the movable platform. The measurement plate can be sensed by the nanosensors so as to measure the corresponding variation between the fixed base and the movable platform. | 2010-02-04 |
| 20100026321 | CIRCUIT SYSTEM FOR A MICROMECHANICAL SENSOR ELEMENT HAVING A CAPACITOR ARRAY - A circuit system for a micromechanical sensor element having a capacitor array and a downstream amplifier for the useful signal of the capacitor array is described. Using this circuit system, setpoint deviations of the base capacitance of the capacitor array can easily be compensated. For this purpose, the circuit system includes a circuit using which a control signal is generated, which is decoupled from the useful signal of the capacitor array, but is a function of the base capacitance of the capacitor array, which is conveyed to the amplifier for controlling the gain. | 2010-02-04 |
| 20100026322 | Method for ascertaining burden resistance for a measurement transmitter - In a method for ascertaining burden resistance for a measurement transmitter, which is supplied with voltage via a first line-pair and which transmits a variable electrical-current signal via an electrical-current loop to a control system via a second line-pair, a test-voltage signal is capacitively coupled into the electrical-current loop and an associated electrical-current signal evaluated. An instantaneous value of the burden resistance is ascertained from a characterizing feature of the electrical-current signal, especially an RC time constant. Thus, already at start-up of a measurement transmitter, a burden resistance, which is too high, can be detected. | 2010-02-04 |
| 20100026323 | WAVEGUIDE GRATING STRUCTURE AND OPTICAL MEASUREMENT ARRANGEMENT - The present invention describes (bio)chemo-functional waveguide grating structures consisting of at least one (bio)chemo-functional waveguide grating structure unit or at least one (bio)chemo-functional sensor location with beam guidance permitting light beam separation, as well as detection methods for parallel analysis which are marking-free or based on marking. | 2010-02-04 |
| 20100026324 | SOIL MOISTURE SENSOR WITH LONG BATTERY LIFE - A power-efficient soil moisture sensor includes:
| 2010-02-04 |
| 20100026325 | METHOD AND DEVICE FOR DETECTING STRUCTURAL ABNORMALITIES IN A SPHERICAL PARTICLE, PARTICULARLY IN A NUCLEAR FUEL PARTICLE FOR HIGH TEMPERATURE OR VERY HIGH TEMPERATURE REACTORS - The method for detecting at least one structural defect in a spherical particle ( | 2010-02-04 |
| 20100026326 | Resistance Sensing for Defeating Microchip Exploitation - A method, program product and apparatus include resistance structures positioned proximate security sensitive microchip circuitry. Alteration in the position, makeup or arrangement of the resistance structures may be detected and initiate an action for defending against a reverse engineering or other exploitation effort. The resistance structures may be automatically and selectively designated for monitoring. Some of the resistance structures may have different resistivities. The sensed resistance may be compared to an expected resistance, ratio or other resistance-related value. The structures may be intermingled with false structures, and may be overlapped or otherwise arranged relative to one another to further complicate unwelcome analysis. | 2010-02-04 |
| 20100026327 | Electrical Signal Connector - An electrical signal connector which may be used for testing narrow-pitched chips or multi-chips, and causes no faulty connections between probes and pads or between probes and a circuit board even in a high temperature environment such as in a burn-in test is provided. The electrical signal connector has a probe unit in which a plurality of resin-made film probes, corresponding to one or more pads on a semiconductor chip to be tested, are supported in parallel on a plurality of support plates; a first probe holder of grid structure provided with a plurality of openings; and a second probe holder of the same configuration as that of the first probe holder, the second probe holder having projections at intersection points in the grid structure. The first and second probe holders are fastened to the circuit board with the projections of the second probe holder inserted in corresponding holes of the circuit board and the first probe holder being fastened to the circuit board with screws. No or very little difference exists between an outer diameter of an inserting section of the projection and an inner diameter of the corresponding hole in the circuit board in the vicinity of the center of the circuit board and larger difference exists therebetween in the rest of areas of the circuit board. | 2010-02-04 |
| 20100026328 | INSPECTING METHOD AND PROGRAM FOR OBJECT TO BE INSPECTED - An inspecting method for an object to be inspected is provided to bring probes of a probe card into electrical contact with a predetermined number of devices of target devices of the object at a time to inspect electrical characteristics of the target devices by moving a mounting table for mounting thereon the object under the control of a control unit. Upon completion of the inspection of the target devices, if inspection errors have occurred in specific devices of the target devices in a regular pattern, the target devices are re-examined, and when the re-examination is carried out, a contact position between the probe card and the object is displaced from a contact position in a previous inspection by a distance of at least one device to inspect electrical characteristics of the number of devices of the target devices at a time. | 2010-02-04 |
| 20100026329 | TEST APPARATUS AND ELECTRONIC DEVICE - Provided is a test apparatus that tests a device under test including an external interface circuit that transfers signals between an internal circuit inside a device and the outside of the device, the test apparatus comprising a pattern generating section that inputs, to the external interface circuit, a test pattern for testing the external interface circuit; an interface control section that causes the external interface circuit to loop back and output the test pattern; and an interface judging section that judges acceptability of the external interface circuit based on the test pattern looped back and output by the external interface circuit. | 2010-02-04 |
| 20100026330 | TESTBOARD WITH ZIF CONNECTORS, METHOD OF ASSEMBLING, INTEGRATED CIRCUIT TEST SYSTEM AND TEST METHOD INTRODUCED BY THE SAME - A testboard with ZIF connectors is disclosed. The testboard comprises a test substrate, a plurality of ZIF connectors and a plurality of detachably adjustable fastening means. Each ZIF connector has a plurality of second through-holes, and pairs of electric terminals are deposed on the bottom of each ZIF connector where each pair of electric terminals has a radial shape for contacting the test substrate. Each fastening means is disposed through the first through-holes and the second through-holes through the middle of each ZIF connector for adjusting the ZIF connectors on the test substrate in better contact and for replacing each ZIF connector on the test substrate with a replacement ZIF connector where the second through-holes are arranged to one another in a spaced interval along a longitudinal direction, and each ZIF connector has a ratio of its longitudinal length to its spaced interval ranging from 3:1 to 5:1. | 2010-02-04 |
| 20100026331 | Construction Structures and Manufacturing Processes for Integrated Circuit Wafer Probe Card Assemblies - Enhanced microfabricated spring contact structures and associated methods, e.g. such as for electrical contactors and interposers, comprise improvements to spring structures that extend from the substrate surface, and/or improvements to structures on or within the support substrate. Improved spring structures and processes comprise embodiments having selectively formed and etched, coated and/or plated regions, which are optionally further processed through planarization and/or annealment. Enhanced solder connections and associated processes provide a gap between substrates for componentry, and or improved manufacturing techniques using distributed spacers. Enhanced probe card assembly structures and processes provide improved planarization adjustment and thermal stability. | 2010-02-04 |
| 20100026332 | DEVICE AND METHOD FOR SENSING A POSITION OF A PROBE - A device for sensing a position of a probe relative to a reference medium, the probe comprising a heater element with a temperature dependent electrical resistance and being adapted to determine probe position by measuring a parameter associated to a thermal relaxation time of the heater element. | 2010-02-04 |
| 20100026333 | TEST APPARATUS AND PROBE CARD - Provided is a test apparatus including a test head main body | 2010-02-04 |
| 20100026334 | Testing Embedded Circuits With The Aid Of Test Islands - Embodiments of the present disclosure relate to a system and method for testing an embedded circuit in a semiconductor arrangement as part of an overall circuit that is located on a semiconductor wafer, the system and method comprising an arrangement comprising an overall circuit with at least one input and output. The overall circuit may be provided with an embedded circuit that is not directly connected to the inputs and outputs or may be connected thereto by being specially switched. Switching elements and test islands that are connected thereto may be provided such that the input or the output of the embedded circuit may be connected to the test islands via the switching elements in case of a test. The switching elements may be switched to said test mode in case of a test by applying a voltage to the test island, or the switching elements may be switched in this manner. The arrangement may thus allow for a flexible testing system and method while the used substrate area and the number of required inputs and outputs remain low. | 2010-02-04 |
| 20100026335 | LEAK CURRENT DETECTION CIRCUIT, BODY BIAS CONTROL CIRCUIT, SEMICONDUCTOR DEVICE, AND SEMICONDUCTOR DEVICE TESTING METHOD - A leak current detection circuit that improves the accuracy for detecting a leak current in a MOS transistor without enlarging the circuit scale. The leak current detection circuit includes at least one P-channel MOS transistor which is coupled to a high potential power supply and which is normally inactivated and generates a first leak current, at least one N-channel MOS transistor which is coupled between a low potential power and at least the one P-channel MOS transistor and which is normally inactivated and generates a second leak current, and a detector which detects a potential generated at a node between the at least one P-channel MOS transistor and the at least one N-channel MOS transistor in accordance with the first and second leak currents. | 2010-02-04 |
| 20100026336 | FALSE CONNECTION FOR DEFEATING MICROCHIP EXPLOITATION - An integrated circuit assembly and associated method of detecting microchip tampering may include multiple connections in electrical communication with a conductive layer. Defensive circuitry may inhibit analysis of the microchip where a connection no longer connects to the conductive layer. The defensive circuitry may similarly be initiated where a connection unintended to be in electrical communication with the conductive layer is nonetheless connected. | 2010-02-04 |
| 20100026337 | Interdependent Microchip Functionality for Defeating Exploitation Attempts - An integrated circuit assembly comprising a microchip that shares an interdependent function with a second, stacked microchip. Alternation of the physical arrangement or functionality of the microchips may initiate a defense action intended to protect security sensitive circuitry associated with one of the microchips. The microchips may communicate using through-silicon vias or other interconnects. | 2010-02-04 |
| 20100026338 | Fault triggerred automatic redundancy scrubber - A redundancy scrubber. The novel scrubber includes fault detection logic for detecting if a circuit has been upset and a mechanism for automatically rewriting data to the circuit when an upset is detected. In an illustrative embodiment, the scrubber corrects for upsets in a circuit comprised of a plurality of redundant circuits, each redundant circuit including a data port for receiving data and a load enable port for controlling when the redundant circuit should load new data. The fault detection logic processes the outputs from each of the redundant circuits and outputs a fault detect signal indicating whether an upset has been detected in one or more of the redundant circuits. The fault detect signal is coupled to the load enable ports, forcing the redundant circuits to immediately reload with corrected data from a voter or with new incoming data when an upset is detected. | 2010-02-04 |
| 20100026339 | ASICs Having More Features Than Generally Usable At One Time and Methods of Use - More ASIC functionality is crammed into a chip (or chip set) than can probably or definitely be operative at one time when the chip is packaged and inserted into a broader circuit. The excessive ASIC functionality is chosen to cope with different market development probabilities in a host of different market spaces and a subset of the excessive ASIC functionality is programmably activated in each market space after manufacture. In one embodiment, a mega-ASIC with excessive ASIC functionality crammed into it, has a universal core as well as plurality of programmably selectable ASIC function blocks. The ASIC function blocks are programmably activatable and de-activatable so that a mass produced can quickly respond to shifting market demands. | 2010-02-04 |
| 20100026340 | User-Accessible Freeze-Logic for Dynamic Power Reduction and Associated Methods - A programmable logic device (PLD) includes a configuration circuit, and first and second freeze-logic circuits. The configuration circuit provides configuration data for configuring programmable resources of the PLD during a configuration mode of the PLD. One of the two freeze-logic circuits provides a freeze logic signal during the configuration mode of the PLD. The other freeze-logic circuit provides a freeze logic signal during a user mode of the PLD. | 2010-02-04 |
| 20100026341 | MACROCELL AND METHOD FOR ADDING - A macrocell including an adder block with a plurality of bit-slice adders, a bypass path and a control unit adapted to receive a carry of a first neighboring macrocell, and to output a carry by generation within the adder block or by passage of the carry of the first neighboring macrocell through the bypass path to a second neighboring macrocell. The control unit is adapted to signal a validity of the carry output of the macrocell depending on a logical combination of states of the two carry output lines. The control unit is further adapted, depending on a validity signal of the first neighboring macrocell indicating a validity of the carry, to prevent forwarding the carry. | 2010-02-04 |
| 20100026342 | HIGH VOLTAGE INPUT RECEIVER USING LOW VOLTAGE TRANSISTORS - A high voltage input receiver using low voltage transistors is disclosed. In one embodiment, an input receiver circuit includes a comparator circuit and an inverter circuit. The comparator circuit includes a differential input module for generating a control signal by comparing an external voltage and a reference voltage, and a decision module for generating an inverter input signal based on the control signal. In addition, the reference voltage is used to set dc trip point of the input receiver. Moreover, the input receiver includes one or more stress protection modules to protect key components of the input receiver from exceeding their reliability limits. | 2010-02-04 |
| 20100026343 | CLOCKED SINGLE POWER SUPPLY LEVEL SHIFTER - First circuitry is powered by a first power supply domain and provides a data signal referenced to the first power supply domain. Second circuitry is powered by a second power supply domain that differs from the first power supply domain. The data signal becomes referenced to the second power supply domain by a clocked level shifter that couples the first circuitry to the second circuitry and buffers the data signal from the first power supply domain to the second power supply domain by only using a single supply voltage. The clocked level shifter is clocked by a signal that is used to precharge a first node and a second node of the clocked level shifter until the data signal is valid for at least a setup time period. The first and second nodes are precharged to establish a known state in the clocked level shifter. | 2010-02-04 |
| 20100026344 | METHODS, DEVICES, AND SYSTEMS FOR A HIGH VOLTAGE TOLERANT BUFFER - Methods, devices, and systems are disclosed, including those for a buffer having pre-driver circuitry configured to provide voltages to thin-gate dielectric transistors. One such buffer may comprise a plurality of pre-drivers wherein each pre-driver of the plurality of pre-drivers is operably coupled to a transistor of a plurality of transistors. The buffer may further comprise one or more clamping devices, wherein at least one transistor of the plurality of transistors has a gate coupled to at least one clamping device of the one or more clamping devices. | 2010-02-04 |
| 20100026345 | CIRCUIT, SYSTEM, AND METHOD FOR MULTIPLEXING SIGNALS WITH REDUCED JITTER - An apparatus having a plurality of power supply domains and a plurality of logic components. Each of the plurality of logic components residing within a different one of the plurality of power supply domains. Each of the plurality of logic components is configured to operate with a corresponding clock signal within a respective one of the plurality of power supply domains. | 2010-02-04 |
| 20100026346 | HIGH-DENSITY LOGIC TECHNIQUES WITH REDUCED-STACK MULTI-GATE FIELD EFFECT TRANSISTORS - Techniques for employing multi-gate field effect transistors (FETS) in logic circuits formed from logic gates are provided. Double-gate transistors that conduct only when both transistor gates are active can be used to reduce the number of devices hitherto required in series or “stacked” portions of logic gates. Circuit area can be reduced and performance can be enhanced. | 2010-02-04 |
| 20100026347 | SEMICONDUCTOR INTEGRATED CIRCUIT - A first counter detects a rising edge of a clock signal, and generates a first signal having a multiplied cycle of the clock signal. | 2010-02-04 |
| 20100026348 | HIGH SIGNAL LEVEL COMPLIANT INPUT/OUTPUT CIRCUITS - A signal driver for an interface circuit has a first stage level shifter to accept input signals and output signals at a first signal level. The signal driver also has a second stage level shifter coupled to the first stage level shifter to output signals at a second signal level. Electronic components of the first and second stage level shifter have reliability limits less than the second signal level. The first and second stage configurations of the first stage level shifter and the second stage level shifter prevents exposing the electronic components to terminal to terminal signal levels higher than the reliability limits when processing signals for output at the second signal level. | 2010-02-04 |
| 20100026349 | SQUARE TO PSEUDO-SINUSOIDAL CLOCK CONVERSION CIRCUIT AND METHOD - A square wave to pseudo-sinusoidal clock conversion circuit comprises first and second stages. The first stage includes a cross-coupled differential pairs input gain stage having positive and negative input sides. Responsive to a differential square wave clock input, the first stage provides a first pass balanced differential clock with pull-up and pull-down symmetry. The second stage comprises positive and negative output side push-pull with low pass filter circuits, wherein the positive and negative output side push-pull with low pass filter circuits are responsive to the first pass balanced differential clock from the first stage for producing an output pseudo-sinusoidal clock that comprises a nearly sinusoidal output with slew rate controlled and clock waveform pull-up and pull-down symmetry for each of a respective one of the positive and negative output sides. | 2010-02-04 |
| 20100026350 | CLOCK DATA RECOVERY DEVICE - A clock/data recovery device | 2010-02-04 |
| 20100026351 | System and Method to Improve the Efficiency of Synchronous Mirror Delays and Delay Locked Loops - A phase detection system for use with a synchronous mirror delay or a delay-locked loop in order to reduce the number of delay stages required, and therefore increase the efficiency, is disclosed. The invention includes taking a clock input signal and a clock delay or feedback signal, each having timing characteristics, and differentiating between four conditions based upon the timing characteristics of the signals. The phase detector and associated circuitry then determines, based upon the timing characteristics of the signals, which of a number of phase conditions the signals are in. Selectors select the signals to be introduced into the synchronous mirror delay or delay-locked loop by the timing characteristics of the phase conditions. The system is able to utilize the falling clock edge of the clock input signal, and the lock time is decreased under specific phase conditions. The invention increases the efficiency of the circuits by reducing the effective delay stages in the SMD or DLL while maintaining the operating range. | 2010-02-04 |
| 20100026352 | ALL DIGITAL FREQUENCY-LOCKED LOOP CIRCUIT METHOD FOR CLOCK GENERATION IN MULTICORE MICROPROCESSOR SYSTEMS - A (DFLL) circuit residing on a local core of a multi-core microprocessor for generating a local core clock with a frequency for driving the local core includes a micro-controller configured to receive core characterizing digital data; a ring oscillator configured to generate the local core clock for the local core, and having a delay chain disposed between an output and a feedback input of the ring oscillator, the delay chain having delay taps each receiving the local core clock enabling quantum changes in the frequency of the local core clock; and a counter device configured to continually validate the frequency by generating a digital signal representative of the frequency to the micro-controller, the micro-controller compares the frequency of the local core clock to a desired clock frequency, and selects one of the delay taps based on the comparison to adjust the frequency value of the local core clock. | 2010-02-04 |
| 20100026353 | Semiconductor device for constantly maintaining data access time - The semiconductor device may include a calibration circuit, a control unit, and a delay unit. The calibration circuit may be configured to output an output signal. The control unit may be configured to generate and output the control signal in response to the output signal of the calibration circuit. The control unit may generate the control signal by using a correlation between a signal transmission speed of the semiconductor device and the output signal of the calibration circuit. The delay unit may be configured to delay a clock signal in response to the control signal and output the delayed clock signal to the output driver. | 2010-02-04 |
| 20100026354 | Delay Amount Estimating Apparatus and Signal Transmitting Apparatus - A delay amount estimating apparatus includes a delay value search section that searches for a first delay value smaller than a delay setting value at which a given correlation value between an input signal and a feedback signal is provided, and also for a second delay value greater than the delay setting value, the feedback signal coming from a signal processing apparatus that applies signal processing on the input signal, wherein respective correlation values of the first delay value and the second delay value satisfy a given condition; and a delay estimating section that estimates a delay amount of the feedback signal relative to the input signal based on the first delay value and the second delay value. | 2010-02-04 |
| 20100026355 | Load drive device and control system of the same - A load drive device for driving an inductive load by PWM controlling a switching element includes synchronization control unit, a synchronization signal input terminal, and a synchronization signal output terminal. The synchronization control unit outputs the PWM signal to the switching element. The synchronization control unit receives a synchronization signal through the input terminal from an exterior. The synchronization control unit outputs the synchronization signal through the output terminal to an exterior. When the synchronization control unit does not receive the synchronization signal, the synchronization control unit outputs the synchronization signal such that a first switching period of the PWM signal is prevented from overlapping with a second switching period of a PWM signal of an external device. When the synchronization control unit receives the synchronization signal, the synchronization control unit generates the PWM signal based on the synchronization signal. | 2010-02-04 |
| 20100026356 | POLARITY SWITCHING MEMBER OF DOT INVERSION SYSTEM - A polarity switching member of a dot inversion system is revealed. A first transistor and a second transistor are disposed in a P-well while a N-well is arranged in the P-well, located between the first transistor and the second transistor. The N-well includes a third transistor and a fourth transistor. One end of the third transistor is coupled to one end of the first transistor to generate a first input end and one end of the fourth transistor is coupled to one end of the second transistor to generate a second input end. The other end of the first transistor, the other end of the second transistor, the other end of the third transistor, and the other end of the fourth transistor are coupled to generate an output end. Thereby, by switching of voltage polarity of the P-well and the N-well, a larger range of output voltage difference is achieved. | 2010-02-04 |
| 20100026357 | RESET SIGNAL FILTER - A reset signal filter includes a power voltage detector and a reset signal detector or includes only one reset signal detector. The power voltage detector includes a comparators and a basic logic gates (e.g. AND gate, OR gate, inverter, etc). The reset signal detector includes a comparator, N flip flops connected in series, an AND gate, an OR gate, a multiplexer and an output flip flop. The reset signal filter receives a first reset signal generated by a power voltage detector or a Schmitt trigger buffer and utilizes N flip flops to register the signal level of the first reset signal for N clock periods. Then the reset signal filter determines if the first rest signal is changed during N clock periods, and outputs a second reset signal. | 2010-02-04 |
| 20100026358 | PROTECTION AGAINST FAULT INJECTIONS OF AN ELECTRONIC CIRCUIT WITH FLIP-FLOPS - A method for detecting a disturbance of the state of a synchronous flip-flop of master-slave type including two bistable circuits in series, in which the bistable circuits are triggered by two first signals different from each other, and the level of an intermediary junction point between the two bistable circuits is compared both to the level present at the input of the master-slave flip-flop and to the level present at the output, which results in two second signals providing an indication as to the presence of a possible disturbance. | 2010-02-04 |
| 20100026359 | INTERFACE CIRCUIT FOR BRIDGING VOLTAGE DOMAINS - The invention is directed to an interface circuit for bridging voltage domains. The interface circuit receives an input signal, having a larger voltage domain, and safely provides the signal to an electronic device which has a smaller voltage domain. The interface circuit may include a transistor configured as a source follow so that an output of the transistor follows the input of the transistor. A blocking voltage may be provided at the input of the transistor to provide a voltage bias, blocking a range of input voltages to the transistor. The transistor may also have a blocking voltage at a drain terminal of the transistor, to block any output voltage above the blocking voltage. | 2010-02-04 |
| 20100026360 | RELAY CIRCUIT, INFORMATION PROCESSING APPARATUS, AND RELAY METHOD - A relay circuit for relaying signal transmission between a first circuit driven by a first voltage and a second circuit driven by a second voltage different from the first voltage, the relay circuit includes: a waveform shaping circuit that obtains a shaped voltage by shaping a waveform of the second voltage in order to make a change of the second voltage steeper; and a buffer circuit that is driven by the first voltage and interrupts a signal transmission by the buffer circuit if the shaped voltage obtained by the waveform shaping circuit falls to or below a predetermined value, the shaped voltage being input to the buffer circuit as a control signal. | 2010-02-04 |
| 20100026361 | LEVEL SHIFTER AND DRIVING CIRCUIT INCLUDING THE SAME - The present invention related to a driving circuit including a level shifter. The driving circuit according to exemplary embodiment of the present invention includes a first level shifter, a second level shifter, and a gate driver. The first level shifter includes a path along which a pulse-on current flows in response to an on-control signal and a path along which a pulse-off control flows in response to an off-control signal. The second level shifter includes a path along which an on-current flows in response to the on-control signal and a path along which an off-control flows in response to the off-control signal. The gate driver turns on the switch in response to the pulse-on current, maintains the turned-on switch in the turn-on state in response to the on-control current, turns off the switch in response to the pulse-off current, and maintains the turned-off switch in the turn-off state in response to the off-control current. | 2010-02-04 |
| 20100026362 | HIGH SIGNAL LEVEL COMPLIANT INPUT/OUTPUT CIRCUITS - A level detector has an input circuit adapted to accept signals of multiple signal levels for detecting a specific level. The signal levels include a first signal level and a larger second signal level. Electronic components of the input circuit have reliability levels less than the second signal level. A latch circuit is coupled to the input circuit for latching a signal consistent with a detected level of an accepted signal. | 2010-02-04 |
| 20100026363 | HIGH SIGNAL LEVEL COMPLIANT INPUT/OUTPUT CIRCUITS - A level shifter has at least one of either a pull up or a pull down circuit. The circuit is made of electronic components with reliability limits less than a maximum signal level output by the level shifter. The level shifter also has a timing circuit coupled to at least on of either the pull up or pull down circuit. The timing circuit controls a time of application of an input signal to at least one of either the pull up or pull down circuit preventing a terminal to terminal signal level experienced by the electronic components exceeding the reliability limits. | 2010-02-04 |
| 20100026364 | HIGH SIGNAL LEVEL COMPLIANT INPUT/OUTPUT CIRCUITS - An interface input has an input circuit adapted to receive input signal levels higher than a maximum signal level that a host circuitry's electronic components can reliably handle. The input circuit shifts the level of the input signal to a desired signal level. A keeper circuit is coupled to the input circuit and maintains trigger levels of the shifted signals consistent with the input signal level. | 2010-02-04 |
| 20100026365 | ROBUST CURRENT MIRROR WITH IMPROVED INPUT VOLTAGE HEADROOM - An apparatus comprising an input current source device, a first transistor, a second transistor and a level shifter device. The input current source device may provide a input current source. The first transistor may be configured to operate in saturation for mirroring the input current source to an output current source. The first transistor may have (i) a source node connected to a supply, and (ii) a drain connected to the input current source. The second transistor may also be configured to operate in saturation. The second transistor may have (i) a gate connected to a gate of the first transistor, (ii) a source connected to the supply, and (iii) a drain configured as an output current node. The level shifter device may comprise a third transistor, a first bias current source and a second bias current source. | 2010-02-04 |
| 20100026366 | Low Leakage Voltage Level Shifting Circuit - A voltage level shifting circuit for an integrated circuit system having an internal low voltage power supply (VCCL) and an external high voltage power supply (VCCH) is disclosed, the voltage level shifting circuit comprises a pair of cross coupled PMOS transistors connected to the VCCH, a NMOS transistor with a source connected to a ground (VSS) and a gate connected to a first signal swinging between the VCCL and the VSS, and a switching device coupled between a drain of one of the pair of PMOS transistors and a drain of the NMOS transistor, wherein the pair of PMOS transistors are high voltage transistors and the switching device is off when the VCCL is below a predetermined voltage level, and the switching device is on when the VCCL is above the predetermined voltage level. | 2010-02-04 |
| 20100026367 | DOUBLE-BALANCED SINUSOIDAL MIXING PHASE INTERPOLATOR CIRCUIT AND METHOD - A double-balanced sinusoidal mixing phase interpolator circuit comprises: a double-balanced gain stage having a first input for receiving a first phasor clock, a second input for receiving a second phasor clock, and a phase interpolator (PI) output, wherein the double-balance gain stage includes (i) a first gain stage having a positive input side and a negative input side for the first phasor clock and (ii) a second gain stage having a positive input side and a negative input side for the second phasor clock; and a sinusoidal digital-to-analog (DAC) stage coupled to the double-balanced gain stage and configured to implement sinusoidal weighting of positive and negative sides of differential DAC current for the first phasor clock and positive and negative sides of differential DAC current for the second phasor clock, wherein the sinusoidal weighting provides uniformly spaced phase steps in the phase interpolator (PI) output. | 2010-02-04 |
| 20100026368 | HIGH Q TRANSFORMER DISPOSED AT LEAST PARTLY IN A NON-SEMICONDUCTOR SUBSTRATE - An assembly involves an integrated circuit die that is bonded, e.g., flip-chip bonded, to a non-semiconductor substrate by a plurality of low-resistance microbumps. In one novel aspect, at least a part of a novel high-frequency transformer is disposed in the non-semiconductor substrate where the non-semiconductor substrate is the substrate of a ball grid array (BGA) integrated circuit package. At least one of the low-resistance microbumps connects the part of the transformer in the substrate to a circuit in the integrated circuit die. At two gigahertz, the novel transformer has a coupling coefficient k of at least at least 0.4 and also has a transformer quality factor Q of at least ten. The novel transformer structure sees use in coupling differential outputs of a mixer to a single-ended input of a driver amplifier in a transmit chain of an RF transceiver within a cellular telephone. | 2010-02-04 |
| 20100026369 | METHOD FOR MONITORING WHETHER THE SWITCHING THRESHOLD OF A SWITCHING TRANSDUCER LIES WITHIN A PREDEFINED TOLERANCE RANGE - The invention relates to a method for monitoring whether or not the switching threshold of a switching sensor lies within a predefined tolerance region. The switching sensor comprises a signal input, to which an input signal is applied, and a signal output via which a switch output signal is emitted that can take a first value when the input signal is larger than the switching threshold and, otherwise, takes a second value. A modulator signal generated by a modulator (MD) is used as an input signal, characterized in that the modulator signal changes continuously or cyclically between an output value, which defines the upper limit of the tolerance region, and a test value which is smaller than the output value and defines the lower limit of the tolerance region. According to the invention, the switch output signal pulses at the rate of the modulator signal between the first and the second value when the switching threshold of the switching sensor lies within the tolerance region. Otherwise, the switch output signal does not pulse. The pulsation of the switch output signal is monitored by means of an evaluation device (A), an alarm signal being triggered when the switch output signal does not pulse for at least a predefined test period. | 2010-02-04 |
| 20100026370 | HALF-BRIDGE CIRCUITS EMPLOYING NORMALLY ON SWITCHES AND METHODS OF PREVENTING UNINTENDED CURRENT FLOW THEREIN - A method for rendering a half-bridge circuit containing normally on switches such as junction field effect transistors (JFETS) inherently safe from uncontrolled current flow is described. The switches can be made from silicon carbide or from silicon. The methods described herein allow for the use of better performing normally on switches in place of normally off switches in integrated power modules thereby improving the efficiency, size, weight, and cost of the integrated power modules. As described herein, a power supply can be added to the gate driver circuitry. The power supply can be self starting and self oscillating while being capable of deriving all of its source energy from the terminals supplying electrical potential to the normally on switch through the gate driver. The terminal characteristics of the normally on switch can then be coordinated to the input-to-output characteristics of the power supply. | 2010-02-04 |
| 20100026371 | SWITCHING DEVICE AND SWITCHING ARRANGEMENTS FOR SWITCHING AT HIGH OPERATING VOLTAGE - A switching device for switching a high operating voltage is described. The switching device-includes a first switching arrangement with a first self-conducting switching element), which has a control connector and a first and second main connector for forming a switching section. The switching device may include a second switching arrangement having a first and a second connector for forming a switching section, which is wired serially in respect to the switching section of the first switching arrangement. The second switching arrangement includes an optically triggerable switching element for switching the switching section of the second switching arrangement so it becomes conductive. The second connector of the second switching arrangement is connected with the control connector of the first self-conducting switching element. | 2010-02-04 |
| 20100026372 | Power switch for transmitting a power source of low voltage between regular mode and deep-power-down mode - A low-voltage power switch includes a gate-controlled circuit and a switch. The gate-controlled circuit generates a control voltage lower than the voltage of ground according to a control signal. The switch includes a first end, a second end, and a control end. The first end of the switch is coupled to a power supply of a low voltage, the control end of the switch is coupled to the gate-controlled circuit for receiving the gate-controlled signal, and the second end of the switch couples the first end of the switch when the switch receives the gate-controlled signal for outputting the power supply of the low voltage. | 2010-02-04 |
| 20100026373 | Semiconductor device for charge pumping - Provided is a semiconductor device for performing charge pumping. The semiconductor device may include a first pumping unit, a second pumping unit, and a controller. The first pumping unit may be configured to output a boosted voltage via an output node by using a first input signal and the initial voltage, where the boosted voltage is greater than an initial voltage. The second pumping unit may be configured to output the boosted voltage via the output node by using a second input signal and the initial voltage. The controller may be configured to control the first and second pumping units. Each of the first and second pumping units may include an initialization unit, a boosting unit, and a transmission unit. The initialization unit may be configured to control a voltage of a boosting node to be equal to the initial voltage during an initialization operation. The boosting unit may be configured to boost the voltage of the boosting node based on the first and second input signals. Also, the transmission unit may be configured to control output of the boosted voltage. | 2010-02-04 |
| 20100026374 | Semiconductor integrated circuit with switching variable resistance device - A semiconductor integrated circuit having a switching variable resistance device with combined functions of a switching device and a variable resistance device is provided. The semiconductor integrated circuit includes a supply voltage input terminal that receives a supply voltage, a pulse generating unit that receives an input pulse and generates a variable amplitude pulse in response to the input pulse during a period of time, and a switching variable resistance unit that controls a current flowing into the supply voltage input terminal in response to the variable amplitude pulse, thereby limiting an inrush current and thus substantially reducing an temporary unstable effect on the supply voltage, which may be supplied from a power source. | 2010-02-04 |
| 20100026375 | CIRCUIT TO GENERATE CMOS LEVEL SIGNAL TO TRACK CORE SUPPLY VOLTAGE (VDD) LEVEL - A method, system, and apparatus circuit to generate CMOS level signal to track core supply voltage (VDD) level are disclosed. In one embodiment, a system of an integrated circuit includes an HHV generation circuit located in the integrated circuit to provide an HHV voltage signal to a subsystem circuit of the integrated circuit to replace a core voltage signal used by the subsystem circuit when the core voltage signal is below a specified value, an core voltage source located within the integrated circuit to provide the core voltage signal to the HHV generation circuit, and an external voltage source to provide an external voltage signal of an other entity located outside the integrated circuit to the HHV generation circuit. The system may include a pad driver circuit configured to associate the integrated circuit with the other entity. | 2010-02-04 |
| 20100026376 | BIAS CIRCUIT FOR A MOS DEVICE - A method and circuit for providing a bias voltage to a MOS device is disclosed. The method and circuit comprise utilizing at least one diode connected circuit to provide a voltage that tracks process, voltage and temperature variations of a semiconductor device. The method and circuit includes utilizing a current mirror circuit coupled to the at least one diode connected circuit to generate a bias voltage for the body of the semiconductor device from the voltage. The bias voltage allows for compensation for the process, voltage and temperature variations. | 2010-02-04 |
| 20100026377 | CIRCUIT AND METHOD FOR PROVIDING A DESIRED VOLTAGE DIFFERENCE, CIRCUIT AND METHOD FOR DETECTING, WHETHER A VOLTAGE DIFFERENCE BETWEEN TWO VOLTAGES IS BELOW A DESIRED VOLTAGE DIFFERENCE, AND PROTECTION CIRCUIT - A circuit for providing a desired voltage difference in dependence on a reference signal, the circuit including a first resistor; a second resistor; a regulation circuit configured to regulate a current flowing through the first resistor, such that a voltage difference across the first resistor is determined by the reference signal; and a current mirror, wherein the current mirror is configured to mirror the current flowing through the first resistor to obtain a mirrored current flowing through the second resistor, such that the desired voltage difference is obtained across the second resistor. | 2010-02-04 |
| 20100026378 | METHODS FOR DESIGNING INTEGRATED CIRCUITS EMPLOYING VOLTAGE SCALING AND INTEGRATED CIRCUITS DESIGNED THEREBY - Various embodiments of methods of designing an integrated circuit (IC). One embodiment of one such method includes: (1) generating a functional design for the IC, (2) determining performance objectives for the IC, (3) determining an optimization target voltage for the IC, (4) determining whether the IC needs voltage scaling to achieve the performance objectives at the optimization target voltage and, if so, whether the IC is to employ static voltage scaling or adaptive voltage scaling, (5) using the optimization target voltage to implement a layout from the functional IC design that meets the performance objectives and (6) performing a timing signoff of the layout at the optimization target voltage. | 2010-02-04 |
| 20100026379 | POWER STEALING CIRCUITRY FOR A CONTROL DEVICE - A power stealing circuit for stealing power to operate a control device is disclosed. In one illustrative embodiment, power may be periodically or intermittently diverted from a power source to a power stealing block. When power is diverted to the power stealing block, the power stealing block may steal power from the power source and store the stolen power on a storage device. The storage device may then provide operating power to a control device. In some embodiments, the power stealing block may include a first path for charging the storage device when a switch is ON, and a second path for charging the storage device when the switch is off. The switch may be switched OFF when, for example, when the voltage provided by the rectifier is greater than a threshold voltage, the voltage detected on the storage device is greater than a threshold value, and/or when a control signal from a controller disables the switch. | 2010-02-04 |
| 20100026380 | Reference Generating Apparatus and Sampling Apparatus Thereof - A reference generating apparatus and a sampling apparatus thereof are provided. The coding module is configured to code and decode a first reference signal to retrieve a second reference signal with less power than generating the first reference signal. The second reference signal is identical to the first reference signal in amplitude. | 2010-02-04 |
| 20100026381 | POWER SAVING CIRCUIT FOR PWM CIRCUIT - The present invention provides a power saving circuit for PWM circuit. The power saving circuit is utilized to control at least one internal circuit. The power saving circuit comprises a switching circuit which generates a switching signal. The power saving circuit controls the internal circuit in response to the switching. The power saving circuit disables the internal circuit for power saving when the switching signal is disabled. | 2010-02-04 |
| 20100026382 | External accessory to be attached to electronic apparatus and system - An external accessory that can be attached to and detached from an electronic apparatus equipped with a power source unit includes: a first power receiving unit that receives power from the power source unit of the electronic apparatus; a second power receiving unit that receives power from the power source unit of the electronic apparatus; a decision-making unit that makes a decision as to whether or not the first power receiving unit is receiving power; a function execution unit that executes a predetermined function by using power received at one of the first power receiving unit and the second power receiving unit; and a control unit that engages the function execution unit in operation continuously when an affirmative decision is made by the decision-making unit, and engages the function execution unit in operation intermittently when a negative decision is made by the decision-making unit. | 2010-02-04 |
| 20100026383 | DIRECT CURRENT (DC) OFFSET CORRECTION USING ANALOG-TO-DIGITAL CONVERSION - Techniques for reducing or eliminating DC (direct current) offset in transmitters are disclosed. An apparatus for DC offset reduction may include a converter, a digital engine, and a plurality of programmable current supplies. The converter is configured to provide digital representations of a plurality of DC currents associated, respectively, with a plurality of differential signal legs. The digital engine is configured to receive the digital representations and to produce instructions for generating compensating currents for the plurality of differential signal legs based on comparisons, respectively, between each of the digital representations and a calibration current. The programmable current supplies correspond, respectively, to the differential signal legs. The current supplies are configured to inject the compensating currents into the differential signal legs, respectively, to reduce DC offset between the differential signal legs, based upon the instructions. The instructions allow one-shot DC offset correction, instead of successive approximation for DC offset correction. | 2010-02-04 |
| 20100026384 | Method and Circuit for Protecting a MOSFET - The invention relates to a method and a corresponding circuit for protecting a power MOSFET from thermal overload when switching the MOSFET off and on, wherein the MOSFET is switched on again after at least a determined off-period has passed. | 2010-02-04 |
| 20100026385 | METHOD FOR CALIBRATING A POWER AMPLIFIER AND DEVICE USING THE SAME - A calibration device for a power amplifier includes a calculation unit, a first storage unit and a multiplier. The calculation unit is utilized for generating a calibration factor according to a value of a characteristic parameter of the power amplifier. The first storage unit coupled to the calculation unit, for storing the calibration factor. The multiplier is coupled to the first storage unit and a baseband unit, for multiplying a baseband signal outputted from the baseband unit by the calibration factor for generating an input signal to the power amplifier. | 2010-02-04 |
| 20100026386 | Amplifier front-end with low-noise level shift - An amplifier front-end comprises an input node for receiving a common-mode voltage V | 2010-02-04 |
| 20100026387 | INTEGRATED DOHERTY TYPE AMPLIFIER ARRANGEMENT WITH HIGH POWER EFFICIENCY - The present invention shows a Doherty type of amplifier arrangement comprising a plurality of parallel unit cells. Each unit cell is of relatively low power. Suitably it comprises a compensation circuit at the input of the main amplifier and peak amplifier stage. | 2010-02-04 |
| 20100026388 | Balanced Amplifying Device Having a Bypass Branch - A balanced amplifier includes a bypass branch ( | 2010-02-04 |
| 20100026389 | DUAL MODE POWER AMPLIFIER OUTPUT NETWORK - A dual mode power amplifier output network is provided that includes a load switch and an auto transformer having a primary winding and a secondary winding. The load switch is connected to the secondary winding of the auto transformer. | 2010-02-04 |
| 20100026390 | DETECTOR CIRCUIT AND SYSTEM FOR A WIRELESS COMMUNICATION - Provided are a detector circuit which has a simple circuit configuration, is capable of indicating an accurate power according to a load fluctuation of a radio frequency power amplifier or a difference in a modulation mode, and can be easily incorporated in the radio frequency power amplifier, and a wireless communication system using the detector circuit. The detector circuit 10 includes a detecting resistor 11 for detecting a part of a current flowing from a bias circuit 6, and a current-voltage conversion circuit 12 for converting a current obtained through the detecting resistor 11 into a voltage. A current supplied from the bias circuit 6 to the amplifying transistor 1 is detected, so that an output current from the amplifying transistor 1 fluctuates when a load on the radio frequency power amplifier fluctuates, and an input current and a current from the bias circuit fluctuate in proportion to the output current from the amplifying transistor 1, whereby an outputted detection voltage can follow a load fluctuation on the radio frequency power amplifier. | 2010-02-04 |
| 20100026391 | AMPLIFIER - There is provided a method and apparatus for maintaining a bias current (I | 2010-02-04 |
