05th week of 2010 patent applcation highlights part 17 |
Patent application number | Title | Published |
20100025692 | PIXEL STRUCTURE - A pixel structure formed on a substrate and electrically connected with a scan line and a data line, and including a semiconductor pattern and a pixel electrode is provided. The semiconductor pattern includes at least two channel areas, at least one doping area, a source area, and a drain area. The channel areas are located below the scan line and have different aspect ratios. The doping area is connected between the channel areas. The pixel electrode electrically connects the drain area, the source area is connected between one of the channel areas and the data line, and the drain area is connected between the other channel area and the pixel electrode. The scan line has different widths above different channel areas, and a length of each channel area is substantially equal to the width of the scan line. | 2010-02-04 |
20100025693 | Wide band gap semiconductor device including junction field effect transistor - A wide band gap semiconductor device has a transistor cell region, a diode forming region, an electric field relaxation region located between the transistor cell region and the diode forming region, and an outer peripheral region surrounding the transistor cell region and the diode forming region. In the transistor cell region, a junction field effect transistor is disposed. In the diode forming region, a diode is disposed. In the electric field relaxation region, an isolating part is provided. The isolating part includes a trench dividing the transistor cell region and the diode forming region, a first conductivity-type layer disposed on an inner wall of the trench, and a second conductivity-type layer disposed on a surface of the first conductivity-type layer so as to fill the trench. The first conductivity-type layer and the second conductivity-type layer provide a PN junction. | 2010-02-04 |
20100025694 | Apparatus and method for transformation of substrate - A method is disclosed for forming a layer of a wide bandgap material in a non-wide bandgap material. The method comprises providing a substrate of a non-wide bandgap material and converting a layer of the non-wide bandgap material into a layer of a wide bandgap material. An improved component such as wide bandgap semiconductor device may be formed within the wide bandgap material through a further conversion process. | 2010-02-04 |
20100025695 | ANNEALING METHOD FOR SEMICONDUCTOR DEVICE WITH SILICON CARBIDE SUBSTRATE AND SEMICONDUCTOR DEVICE - In an atmosphere in which a silicon carbide (SiC) substrate implanted with impurities is annealed to activate the impurities, by setting a partial pressure of H | 2010-02-04 |
20100025696 | Process for Producing a Silicon Carbide Substrate for Microelectric Applications - The process according to the present invention is adapted to produce a silicon carbide substrate for microelectronic applications; it comprises the following steps:
| 2010-02-04 |
20100025697 | OPTICAL MODULE - An optical module of the present invention includes a semiconductor device, a grounded metal member for mounting the semiconductor device thereon, a substrate for mounting the grounded metal member thereon, and a lead pin fixed to and insulated from the grounded metal member and soldered to the substrate. The lead pin is used to supply power to the semiconductor device. The grounded metal member has a protrusion on a surface thereof facing the substrate and wherein the protrusion of the grounded metal member is in contact with the substrate. | 2010-02-04 |
20100025698 | DISPLAY PANEL AND METHOD FOR MANUFACTURING THE SAME - A display panel includes a substrate having a display area and a blank area. The blank area includes at least one of a non-metal line region and a metal-line region. The non-metal line region includes a plurality of insulating patterns and a first conductive pattern layer formed on the substrate. The insulating patterns are isolated from each other by the first conductive pattern layer. The metal-line region includes an insulating multilayer formed on the substrate and a conductive pattern layer formed on the insulating multilayer. Several isolated zones are formed by the conductive pattern layer on the surface of the insulating multilayer. | 2010-02-04 |
20100025699 | LIGHT EMITTING DIODE CHIP PACKAGE - A light emitting diode (LED) chip package is provided. The LED chip package comprises a carrier, a first LED chip, a second LED chip and an encapsulant. The first LED chip is disposed on and electrically connected to the carrier, wherein the first LED chip is adapted for emitting a first light. The second LED chip is disposed on and electrically connected to the carrier, wherein the second LED chip is adapted for emitting a second light. The encapsulant has a doped phosphor, and encapsulates the first LED chip and the second LED chip, wherein the first light is adapted for exciting the doped phosphor to emit a third light. | 2010-02-04 |
20100025700 | WARM WHITE LIGHT EMITTING APPARATUS AND BACK LIGHT MODULE COMPRISING THE SAME - A warm white light emitting apparatus includes a first light emitting diode (LED)-phosphor combination to generatea base light that is white or yellowish white and a second LED-phosphor combination to generate a Color Rendering Index (CRI) adjusting light. The base light the CRI adjusting light together make a warm white light having a color temperature of 2500 to 4500K. | 2010-02-04 |
20100025701 | Method Of Fabricating Nitride-Based Semiconductor Light-Emitting Device And Nitride-Based Semiconductor Light-Emitting Device - A nitride-based semiconductor light-emitting device capable of suppressing reduction of characteristics and a yield and method of fabricating the same is described. The method of fabricating includes the steps of forming a groove portion on a nitride-based semiconductor substrate by selectively removing a prescribed region of a second region of the nitride-based semiconductor substrate other than a first region corresponding to a light-emitting portion of a nitride-based semiconductor layer up to a prescribed depth and forming the nitride-based semiconductor layer having a different composition from the nitride-based semiconductor substrate on the first region and the groove portion of the nitride-based semiconductor substrate. | 2010-02-04 |
20100025702 | SUBSTRATE-FREE FLIP CHIP LIGHT EMITTING DIODE - A substrate-free LED device is provided. The LED device comprises a substrate, an epitaxial layer disposed on the substrate, a first electrode disposed on a portion of the epitaxial layer, a second electrode disposed on another portion of the epitaxial layer, and a protection layer, disposed over the epitaxial layer. It is noted that in the LED device, the substrate comprises, for example but not limited to, high heat-sink substrate, and the protection layer comprises, for example but not limited to, high heat-sink, high transparent material. | 2010-02-04 |
20100025703 | Conductive Polymer Compositions in Opto-Electrical Devices - A conductive polymer composition comprising a conductive polymer in a solid polyelectrolyte. | 2010-02-04 |
20100025704 | HIGH EFFICIENCY LIGHTING DEVICE - A method for fabricating a high efficiency lighting device and the structure thereof are disclosed. The method includes the following steps: providing a light emitting diode structure; attaching a distributed-Bragg reflecting layer (DBR) to the light emitting diode structure by vapor deposition; and connecting the light emitting diode structure to a eutectic layer through the distributed-Bragg reflecting layer to form the high efficiency lighting device. | 2010-02-04 |
20100025705 | HIGH EFFICIENCY LIGHTING DEVICE AND MANUFACTURING METHOD THEREOF - A high efficiency luminous device and a manufacturing method thereof are disclosed. The high efficiency luminous device includes a LED structure, a first metal electrode, and a second metal electrode. The LED structure is for emitting light. The first metal electrode is formed on the LED structure, and the first metal electrode has a plurality of first openings therein. The second metal electrode is formed on the LED structure, and the second metal electrode has a plurality of second openings therein. The plurality of first openings and the plurality of second openings allow the light emitted from the LED structure to pass therethrough. | 2010-02-04 |
20100025706 | NANOPARTICLE BASED INORGANIC BONDING MATERIAL - A method for the production of a light emitting device is provided, comprising providing at least one LED | 2010-02-04 |
20100025707 | Optical Element, Radiation-Emitting Component and Method for Producing an Optical Element - An optical element comprising includes a base body containing a base material, and a filling body containing a filling material, wherein the filling body adheres to the base body. A radiation-emitting component and a method for producing an optical element are futhermore described. | 2010-02-04 |
20100025708 | LUMPED PLASMONIC "DIODE" AND LUMPED PLASMONIC "RECTIFIER" FOR OPTICAL FIELD RECTIFICATION AND LUMPED OPTICAL SECOND HARMONIC GENERATION - A lumped nanocircuit element design at IR and optical frequencies is provided that can effectively act as a lumped “diode” and a lumped “rectifier” for rectifying optical field displacement currents or optical electric field. The lumped nanocircuit element design can also act as a lumped second harmonic generator. The element is formed by juxtaposing an epsilon-negative nanoparticle with a nonlinear optical nanostructure. | 2010-02-04 |
20100025709 | Light emitting device - A light emitting device includes a light emitting element, a sealing material for sealing the light emitting element, a first filler included in the sealing material, and a second filler included in the sealing material. The second filler includes a particle diameter smaller than that of the first filler. | 2010-02-04 |
20100025710 | Semiconductor device and fabrication method thereof - There is provided a semiconductor device including: a semiconductor chip having a penetrating electrode penetrating through from a first main surface of the semiconductor chip to a second main surface on the opposite side thereof, a photoreceptor portion formed on the first main surface, and a first wire at a periphery of the photoreceptor portion; a light transmitting chip adhered to the first main surface at the periphery of the light transmitting chip, with a bonding layer interposed between the light transmitting chip and the first main surface, the light transmitting chip covering the light transmitting chip; and a light blocking resin layer formed only on the side surfaces of the light transmitting chip and the bonding layer. | 2010-02-04 |
20100025711 | OPTICAL BONDING COMPOSITION FOR LED LIGHT SOURCE - An optical bonding composition and LED light source comprising the composition are disclosed, as well as a method of making the LED light source. The LED light source may comprise: an LED die; an optical element optically coupled to the LED die; and a bonding layer comprising an amorphous organopolysiloxane network, the organopolysiloxane network comprising a silsesquioxane portion derived from (R | 2010-02-04 |
20100025712 | SEMICONDUCTOR COMPONENT AND ASSOCIATED PRODUCTION METHOD - The present invention relates to a semiconductor component and an associated production method, said component emitting at least two defined wavelengths with a defined intensity ratio. It is an object of the present invention to specify an optical semiconductor component and an associated production method, said component emitting at least two defined wavelengths with a defined intensity ratio. In this case, the intention is that both the wavelengths and the intensity ratio can be set extremely precisely. The semiconductor component according to the invention has a substrate ( | 2010-02-04 |
20100025713 | WAFER-SCALED LIGHT-EMITTING STRUCTURE - This invention discloses a wafer-scaled light-emitting structure comprising a supportive substrate; an anti-deforming layer; a bonding layer; and a light-emitting stacked layer, wherein the anti-deforming layer reduces or removes the deformation like warp caused by thinning of the substrate. | 2010-02-04 |
20100025714 | LIGHT-EMITTING DEVICE CONTAINING A COMPOSITE ELECTROPLATED SUBSTRATE - The application is related to a method of forming a substrate of a light-emitting diode by composite electroplating. The application illustrates a light-emitting diode comprising the following elements: a light-emitting epitaxy structure, a reflective layer disposed on the light-emitting epitaxy structure, a seed layer disposed on the reflective layer, a composite electroplating substrate disposed on the seed layer by composite electroplating, and a protection layer disposed on the composite electroplating substrate. | 2010-02-04 |
20100025715 | Ultra Dark Polymer - A method and a material for creating an antireflective coating on an integrated circuit. A preferred embodiment comprises applying a dark polymer material on a reflective surface, curing the dark polymer material, and roughening a top surface of the dark polymer material. The roughening can be achieved by ashing the dark polymer material in an ash chamber. The dark polymer material, preferably a black matrix resin or a polyimide black matrix resin, when ashed in an oxygen rich atmosphere for a short period of time, forms a surface that is capable of absorbing light as well as randomly refracting light it does not absorb. A protective cap layer may be formed on top of the ashed dark polymer material to provide protection for the dark polymer material. | 2010-02-04 |
20100025716 | LIGHTING SYSTEM - It is an object of the present invention to provide a lighting system having favorable luminance uniformity in a light-emitting region when the lighting system has large area. According to one feature of the invention, a lighting system comprises a first electrode, a second electrode, a layer containing a light-emitting substance formed between the first electrode and the second electrode, an insulating layer which is formed over a substrate in a grid form and contains a fluorescence substance, and a wiring formed over the insulating layer. The insulating layer and the wiring are covered with the first electrode so that the first electrode and the wiring are in contact with each other. | 2010-02-04 |
20100025717 | HIGHLY EFFICIENT GALLIUM NITRIDE BASED LIGHT EMITTING DIODES VIA SURFACE ROUGHENING - A gallium nitride (GaN) based light emitting diode (LED), wherein light is extracted through a nitrogen face (N-face) of the LED and a surface of the N-face is roughened into one or more hexagonal shaped cones. The roughened surface reduces light reflections occurring repeatedly inside the LED, and thus extracts more light out of the LED. The surface of the N-face is roughened by an anisotropic etching, which may comprise a dry etching or a photo-enhanced chemical (PEC) etching. | 2010-02-04 |
20100025718 | Top contact LED thermal management - An LED having enhanced heat dissipation is disclosed. For example, an LED die can have extended bond pads that are configured to enhance heat flow from an active region of the LED to a lead frame. A heat transmissive substrate can further enhance heat flow away from the LED die. By enhancing heat dissipation, more current can be used to drive the LED. The use of more current facilitates the production of brighter LEDs. | 2010-02-04 |
20100025719 | BOND PAD DESIGN FOR ENHANCING LIGHT EXTRACTION FROM LED CHIPS - An improved bond pad design for increased light extraction efficiency for use in light emitting diodes (LEDs) and LED packages. Embodiments of the present invention incorporate a structure that physically isolates the bond pads from the primary emission surface, forcing the current to flow away from the bond pads first before traveling down into the semiconductor material toward the active region. This structure reduces the amount of light that is generated in the area near the bond pads, so that less of the generated light is trapped underneath the bond pads and absorbed. | 2010-02-04 |
20100025720 | PACKAGING STRUCTURE AND METHOD FOR LIGHT-EMITTING DIODE - The present invention discloses a packaging structure for light-emitting diode, which comprises a grain to provide electroluminescence; a solder paste layer disposed on the bottom and perimeter of the grain to connect the grain with at least one support; and a heat-conducting layer disposed at the bottom of the grain to work as a heat-dissipating path for the grain, so that the aforementioned structure may significantly reduce the packaging thermal resistance of light-emitting diode. Further, the present invention also discloses a packaging method for light-emitting diode, which is capable of greatly reducing the packaging thermal resistance of light-emitting diode. | 2010-02-04 |
20100025721 | OPTICAL SEMICONDUCTOR DEVICE MODULE HAVING LEAF SPRINGS WITH DIFFERENT RECTANGULARLY-SHAPED TERMINALS - In an optical semiconductor device module constructed by an optical semiconductor device having a light emitting portion on its top surface, a mounting substrate adapted to mount the optical semiconductor device thereon, and at least one conductive leaf spring adapted to fix the optical semiconductor device to the mounting substrate and supply power to the optical semiconductor device, the leaf spring is formed by a plurality of rectangularly-shaped terminals, and natural frequencies of at least two of the rectangularly-shaped terminals are different from each other. | 2010-02-04 |
20100025722 | LIGHT EMITTING DEVICE, ITS MANUFACTURING METHOD AND ITS MOUNTED SUBSTRATE - A light emitting device according to the invention includes: a package including a generally quadrangular light emitting surface with a recess formed therein, a rear surface opposed to the light emitting surface, a first side surface generally orthogonal to the light emitting surface and the rear surface, and a second side surface opposed to the first side surface; and a light emitting element provided in the recess. At least one of the first side surface and the rear surface include a first and second feeder electrode surfaces and a mounting surface provided between the first feeder electrode surface and the second feeder electrode surface. A step difference is provided between the first feeder electrode surface and the mounting surface, and a step difference is provided between the second feeder electrode surface and the mounting surface. The first and second feeder electrode surfaces are set back from the mounting surface adjacent thereto. This structure is possible to make a light emitting device high in brightness and thin in thickness. | 2010-02-04 |
20100025723 | PACKAGE FOR PROTECTING A DEVICE FROM AMBIENT SUBSTANCES - A package ( | 2010-02-04 |
20100025724 | Resin Composition for LED Encapsulation - Disclosed is a resin composition for LED encapsulation including an organic oligosiloxane hybrid prepared by non-hydrolytic condensation of organoalkoxysilane. More particularly, the resin composition for LED encapsulation includes an organic oligosiloxane hybrid prepared by non-hydrolytic condensation of organoalkoxysilane with organosilanediol or non-hydrolytic condensation of a mixture containing organoalkoxysilane and metal alkoxide with organosilanediol. The prepared organic oligosilane hybrid has an inorganic network structure with a high degree of condensation and contains at least one organic group or organic functional group. In addition, an encapsulated LED fabricated using the above resin composition for LED encapsulation is provided. | 2010-02-04 |
20100025725 | SEMICONDUCTOR DEVICE AND METHOD FOR PRODUCTION THEREOF - A semiconductor device has a drift region ( | 2010-02-04 |
20100025726 | Lateral Devices Containing Permanent Charge - A lateral device includes a gate region connected to a drain region by a drift layer. An insulation region adjoins the drift layer between the gate region and the drain region. Permanent charges are embedded in the insulation region, sufficient to cause inversion in the insulation region. | 2010-02-04 |
20100025727 | ENHANCED SPONTANEOUS SEPARATION METHOD FOR PRODUCTION OF FREE-STANDING NITRIDE THIN FILMS, SUBSTRATES, AND HETEROSTRUCTURES - The present invention provides a superior method for the removal of nitride semiconductor thin films, thick films, heterostructures, and bulk material from initial substrates and/or templates. The method utilizes specially patterned mask layers between the initial substrates/templates and the nitride semiconductors to decrease adhesion between the nitride semiconductor and underlying material. Thermal stresses generated upon cooling the nitride semiconductor from its deposition temperature trigger spontaneous separation of the nitride semiconductor from the initial substrate or template at the mask layer. The invention remedies deficiencies in the prior art by providing a simple, reproducible, and effective means of removing initial substrates and templates from a variety of nitride semiconductor layers and structures. | 2010-02-04 |
20100025728 | RELAXATION AND TRANSFER OF STRAINED LAYERS - The invention relates to a process for fabricating a heterostructure. This process is noteworthy in that it comprises the following steps: a) a strained crystalline thin film is deposited on, or transferred onto, an intermediate substrate; b) a strain relaxation layer, made of crystalline material capable of being plastically deformed by a heat treatment at a relaxation temperature, at which the material constituting the thin film deforms by elastic deformation is deposited on the thin film; c) the thin film and the relaxation layer are transferred onto a substrate; and d) a thermal budget is applied at at least the relaxation temperature, so as to cause the plastic deformation of the relaxation layer and the at least partial relaxation of the thin film by elastic deformation, and thus to obtain the final heterostructure. | 2010-02-04 |
20100025729 | PASSIVATED III-V FIELD EFFECT STRUCTURE AND METHOD - An improved insulated gate field effect device ( | 2010-02-04 |
20100025730 | Normally-off Semiconductor Devices and Methods of Fabricating the Same - Normally-off semiconductor devices are provided. A Group III-nitride buffer layer is provided. A Group III-nitride barrier layer is provided on the Group III-nitride buffer layer. A non-conducting spacer layer is provided on the Group III-nitride barrier layer. The Group III-nitride barrier layer and the spacer layer are etched to form a trench. The trench extends through the barrier layer and exposes a portion of the buffer layer. A dielectric layer is formed on the spacer layer and in the trench and a gate electrode is formed on the dielectric layer. Related methods of forming semiconductor devices are also provided herein. | 2010-02-04 |
20100025731 | Cell of Semiconductor Device Having Gate Electrode Conductive Structures Formed from Linear Shaped Gate Electrode Layout Features Defined with Minimum End-to-End Spacing and Equal Number of PMOS and NMOS Transistors - A cell of a semiconductor device includes a diffusion level including a plurality of diffusion regions separated by inactive regions. The cell also includes a gate electrode level including conductive features defined to extend in only a first parallel direction. Adjacent ones of the conductive features that share a common line of extent in the first parallel direction are fabricated from respective originating layout features that are separated from each other by an end-to-end spacing having a size that is substantially equal across the gate electrode level region and is minimized to an extent allowed by a semiconductor device manufacturing capability. Some of the conductive features form respective PMOS and/or NMOS transistor devices. A number of the PMOS transistor devices is equal to a number of the NMOS transistor devices in the cell. The cell also includes a number of interconnect levels formed above the gate electrode level. | 2010-02-04 |
20100025732 | Cell of Semiconductor Device Having Sub-Wavelength-Sized Gate Electrode Conductive Structures Formed from Linear Shaped Gate Electrode Layout Features Defined with Minimum End-to-End Spacing and At Least Eight Transistors - A cell of a semiconductor device includes a diffusion level including a plurality of diffusion regions separated by inactive regions. The cell also includes a gate electrode level including conductive features defined to extend in only a first parallel direction. Adjacent ones of the conductive features that share a common line of extent in the first parallel direction are fabricated from respective originating layout features that are separated from each other by an end-to-end spacing having a size that is substantially equal and minimized across the gate electrode level. Some of the conductive features form respective PMOS and/or NMOS transistor devices. A total number of the PMOS and NMOS transistor devices in the cell is greater than or equal to eight. A width of the conductive features in the gate electrode level is less than a wavelength of light used in a photolithography process for their fabrication. | 2010-02-04 |
20100025733 | Cell of Semiconductor Device Having Sub-193 Nanometers-Sized Gate Electrode Conductive Structures Formed from Linear Shaped Gate Electrode Layout Features Defined with Minimum End-to-End Spacing and At Least Eight Transistors - A cell of a semiconductor device includes a diffusion level including a plurality of diffusion regions separated by inactive regions. The cell includes a gate electrode level including conductive features defined to extend in only a first parallel direction. Adjacent conductive features that share a common line of extent in the first parallel direction are fabricated from respective originating layout features that are separated from each other by an end-to-end spacing having a size that is substantially equal and minimized across the gate electrode level region. Some of the conductive features form respective PMOS and/or NMOS transistor devices. A total number of the PMOS and NMOS transistor devices in the cell is greater than or equal to eight. A width of the conductive features within a five wavelength photolithographic interaction radius is less than a wavelength of light of 193 nanometers as used in a photolithography process for their fabrication. | 2010-02-04 |
20100025734 | Cell of Semiconductor Device Having Sub-Wavelength-Sized Gate Electrode Conductive Structures Formed from Linear Shaped Gate Electrode Layout Features Defined with Minimum End-to-End Spacing and Equal Number of PMOS and NMOS Transistors - A cell of a semiconductor device includes a diffusion level including a plurality of diffusion regions separated by inactive regions. The cell also includes a gate electrode level including conductive features defined to extend in only a first parallel direction. Adjacent ones of the conductive features that share a common line of extent in the first parallel direction are fabricated from respective originating layout features that are separated from each other by an end-to-end spacing having a size that is substantially equal and minimized across the gate electrode level. Some of the conductive features form respective PMOS and/or NMOS transistor devices. A number of the PMOS transistor devices is equal to a number of the NMOS transistor devices in the cell. A width of the conductive features in the gate electrode level is less than a wavelength of light used in a photolithography process for their fabrication. | 2010-02-04 |
20100025735 | Cell of Semiconductor Device Having Sub-193 Nanometers-Sized Gate Electrode Conductive Structures Formed from Linear Shaped Gate Electrode Layout Features Defined with Minimum End-to-End Spacing and Equal Number of PMOS and NMOS Transistors - A cell of a semiconductor device includes a diffusion level including a plurality of diffusion regions separated by inactive regions. The cell includes a gate electrode level including conductive features defined to extend in only a first parallel direction. Adjacent conductive features that share a common line of extent in the first parallel direction are fabricated from respective originating layout features that are separated from each other by an end-to-end spacing having a size that is substantially equal and minimized across the gate electrode level region. Some of the conductive features form respective PMOS and/or NMOS transistor devices. A number of the PMOS transistor devices is equal to a number of the NMOS transistor devices in the cell. A width of the conductive features within a five wavelength photolithographic interaction radius is less than a wavelength of light of 193 nanometers as used in a photolithography process for their fabrication. | 2010-02-04 |
20100025736 | Cell of Semiconductor Device Having Gate Electrode Conductive Structures Formed from Linear Shaped Gate Electrode Layout Features Defined with Minimum End-to-End Spacing and At Least Eight Transistors - A cell of a semiconductor device includes a diffusion level including a plurality of diffusion regions separated by inactive regions. The cell also includes a gate electrode level including conductive features defined to extend in only a first parallel direction. Adjacent ones of the conductive features that share a common line of extent in the first parallel direction are fabricated from respective originating layout features that are separated from each other by an end-to-end spacing having a size that is substantially equal across the gate electrode level region and is minimized to an extent allowed by a semiconductor device manufacturing capability. Some of the conductive features form respective PMOS and/or NMOS transistor devices. A total number of the PMOS and NMOS transistor devices in the cell is greater than or equal to eight. The cell also includes a number of interconnect levels formed above the gate electrode level. | 2010-02-04 |
20100025737 | Field-effect transistor - A field-effect transistor according to the present invention includes a source electrode that is formed in an active region, and a drain electrode that is formed in the active region. Further, the field-effect transistor includes a gate electrode that is formed in the active region and disposed between the source electrode and the drain electrode, a field plate electrode that is formed in a vicinity of the gate electrode outside a region disposed between the gate electrode and the source electrode, and an FP pad that is included in the FP electrode, the FP pad being formed outside the active region and being grounded. | 2010-02-04 |
20100025738 | SOLID-STATE IMAGING DEVICE WITH VERTICAL GATE ELECTRODE AND METHOD OF MANUFACTURING THE SAME - A charge accumulation region of a first conductivity type is buried in a semiconductor substrate. A charge transfer destination diffusion layer of the first conductivity type is formed on a surface of the semiconductor substrate. A transfer gate electrode is formed on the charge accumulation region, and charge is transferred from the charge accumulation region to the charge transfer destination diffusion layer. | 2010-02-04 |
20100025739 | SEMICONDUCTOR DEVICE WITH LARGE BLOCKING VOLTAGE AND METHOD OF MANUFACTURING THE SAME - A normally-off type junction FET in which a channel resistance is reduced without lowering its blocking voltage is provided. In a junction FET formed with using a substrate made of silicon carbide, an impurity concentration of a channel region (second epitaxial layer) is made higher than an impurity concentration of a first epitaxial layer to be a drift layer. The channel region is formed of a first region in which a channel width is constant and a second region below the first region in which the channel width becomes wider toward the drain (substrate) side. A boundary between the first epitaxial layer and the second epitaxial layer is positioned in the second region in which the channel width becomes wider toward the drain (substrate) side. | 2010-02-04 |
20100025740 | Semiconductor Device and Method for Fabricating the Same - A method for fabricating a semiconductor device comprises forming a partial-insulated substrate comprising an insulating region located below both a channel region of a cell transistor and one of a storage node contact region and a bit line contact region, and forming a cell transistor comprising a fin region on the partial-insulated substrate. | 2010-02-04 |
20100025741 | SEMICONDUCTOR MEMORY DEVICE AND METHOD OF FABRICATING THE SAME - The present invention discloses a method of fabricating a semiconductor memory device including forming sequentially a gate insulating layer and a first conductive pattern on a semiconductor substrate; forming a protective layer on surfaces of the first conductive pattern and the gate insulating layer; performing an etching process to form a trench, the etching process being performed such that the protective layer remains on side walls of the first conductive pattern to form a protective pattern; forming an isolation layer in the trench; etching the isolation layer; removing the protective pattern above a surface of the isolation layer; and forming sequentially a dielectric layer and a second conductive layer on surfaces of the isolation layer, the protective pattern and the first conductive pattern. | 2010-02-04 |
20100025742 | TRANSISTOR HAVING A STRAINED CHANNEL REGION CAUSED BY HYDROGEN-INDUCED LATTICE DEFORMATION - A lattice distortion may be achieved by incorporating a hydrogen species into a semiconductor material, such as silicon, without destroying the lattice structure. For example, by incorporating the hydrogen species on the basis of an electron shower, a tensile strain component may be obtained in the channel of N-channel transistors. | 2010-02-04 |
20100025743 | TRANSISTOR WITH EMBEDDED SI/GE MATERIAL HAVING ENHANCED BORON CONFINEMENT - By incorporating a diffusion hindering species at the vicinity of PN junctions of P-channel transistors comprising a silicon/germanium alloy, diffusion related non-uniformities of the PN junctions may be reduced, thereby contributing to enhanced device stability and increased overall transistor performance. The diffusion hindering species may be provided in the form of carbon, nitrogen and the like. | 2010-02-04 |
20100025744 | SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING SAME - A semiconductor device includes a gate electrode over a semiconductor substrate, a channel region provided in the semiconductor substrate below the gate electrode, and a strain generation layer configured to apply stress to the channel region, the strain generation layer being configured to apply greater stress in absolute value to the source edge of the channel region than to the drain edge of the channel region. | 2010-02-04 |
20100025745 | METHOD OF FORMING A LOW CAPACITANCE SEMICONDUCTOR DEVICE AND STRUCTURE THEREFOR - In one embodiment a transistor is formed with a gate structure having an opening in the gate structure. An insulator is formed on at least sidewalls of the opening and a conductor is formed on the insulator. | 2010-02-04 |
20100025746 | METHODS, STRUCTURES AND SYSTEMS FOR INTERCONNECT STRUCTURES IN AN IMAGER SENSOR DEVICE - Methods, structures and systems for a substantially non-light blocking conductive interconnect structure for an imager sensor device. | 2010-02-04 |
20100025747 | METHOD FOR INITIALIZING FERROELECTRIC MEMORY DEVICE, FERROELECTRIC MEMORY DEVICE, AND ELECTRONIC EQUIPMENT - A method for initializing a ferroelectric memory device is provided. The method includes the steps of: packaging a ferroelectric memory device having memory cells arranged in an array, each of the memory cells having a ferroelectric film disposed between a lower electrode and an upper electrode; applying a potential between the lower electrode and the upper electrode in an examination step; and after the examination step, applying a first potential to the upper electrode and applying a second voltage higher than the first potential to the lower electrode, and thereafter conducting a heat treatment at a first temperature higher than an operation guarantee temperature. | 2010-02-04 |
20100025748 | SEMICONDUCTOR DEVICE WITH A DYNAMIC GATE-DRAIN CAPACITANCE - A semiconductor device with a dynamic gate drain capacitance. One embodiment provides a semiconductor device. The device includes a semiconductor substrate, a field effect transistor structure including a source region, a first body region, a drain region, a gate electrode structure and a gate insulating layer. The gate insulating layer is arranged between the gate electrode structure and the body region. The gate electrode structure and the drain region partially form a capacitor structure including a gate-drain capacitance configured to dynamically change with varying reverse voltages applied between the source and drain regions. The gate-drain capacitance includes at least one local maximum at a given threshold or a plateau-like course at given reverse voltage. | 2010-02-04 |
20100025749 | SEMICONDUCTOR DEVICE - A semiconductor device may include an isolation layer, gate electrodes, an insulating interlayer, an impurity region, a capping layer and a plug. The isolation layer may be formed in the substrate. The gate electrodes may be formed on the substrate. The insulating interlayer may be formed on the gate electrodes. The insulating interlayer may have a contact hole between the gate electrodes. The impurity region may be in the substrate exposed through the contact hole. The capping layer may be on the impurity region. The plug may be on the capping layer. Thus, the impurities may not be lost from the impurity region. As a result, the device may have improved electrical characteristics and reliability because depletion may not be generated in the electrode layer | 2010-02-04 |
20100025750 | MEMORY AND METHOD OF FABRICATING THE SAME - A memory and a method of fabricating the same are provided. The memory is disposed on a substrate in which a plurality of trenches is arranged in parallel. The memory includes a gate structure and a doped region. The gate structure is disposed between the trenches. The doped region is disposed at one side of the gate structure, in the substrate between the trenches and in the sidewalls and bottoms of the trenches. The top surface of the doped region in the substrate between the trenches is lower than the surface of the substrate under the gate structure by a distance, and the distance is greater than 300 Å. | 2010-02-04 |
20100025751 | SEMICONDUCTOR MEMORY DEVICE AND METHOD OF FABRICATING THE SAME - A semiconductor memory device and a method of fabricating the same which is suitable for fabrication of a non-volatile memory, such as an EEPROM, using a polysilicon-insulator-polysilicon (PIP) process. The semiconductor memory device includes isolation layers defining a tunneling region and a read transistor region of a semiconductor substrate, a lower polysilicon film formed on and/or over the tunneling region and the read transistor region, a dielectric film formed on and/or over the lower polysilicon film in the tunneling region, and an upper polysilicon film formed on and/or over the dielectric film. | 2010-02-04 |
20100025752 | CHARGE TRAP TYPE NON-VOLATILE MEMORY DEVICE AND METHOD FOR FABRICATING THE SAME - There is provided a charge trap type non-volatile memory device and a method for fabricating the same, the charge trap type non-volatile memory device including: a tunnel insulation layer formed over a substrate; a charge trap layer formed over the tunnel insulation layer, the charge trap layer including a charge trap polysilicon thin layer and a charge trap nitride-based layer; a charge barrier layer formed over the charge trap layer; a gate electrode formed over the charge barrier layer; and an oxide-based spacer formed over sidewalls of the charge trap layer and provided to isolate the charge trap layer. | 2010-02-04 |
20100025753 | SEMICONDUCTOR DEVICE - Provided is a semiconductor device including: source-drain regions formed on a silicon substrate with a channel forming region sandwiched therebetween; a word gate electrode formed on the channel forming region via a word gate insulating film not including a charge storage layer; a control gate formed on the silicon substrate on one side of the word gate electrode via a trap insulating film including a charge storage layer; and a control gate formed on the silicon substrate on the other side of the word gate electrode via a trap insulating film including a charge storage layer. A bottom of the word gate electrode is made to be higher than the control gate and a bottom of the control gate, and a level difference between the bottoms of the electrodes is made to be larger than a physical film thickness of the word gate insulating film. | 2010-02-04 |
20100025754 | SEMICONDUCTOR DEVICE AND A METHOD OF MANUFACTURING THE SAME - To improve characteristics of a semiconductor device having a nonvolatile memory. | 2010-02-04 |
20100025755 | SEMICONDUCTOR DEVICE - In the trap type memory chip the withstanding voltage is raised up, and then the electric current for reading out is increased. There are formed on the p-type semiconductor substrate | 2010-02-04 |
20100025756 | Dual Current Path LDMOSFET with Graded PBL for Ultra High Voltage Smart Power Applications - A dual current path LDMOSFET transistor ( | 2010-02-04 |
20100025757 | Conductive structure and vertical-type pillar transistor - In a conductive structure, method of forming the conductive structure, a vertical-type pillar transistor and a method of manufacturing the vertical-type pillar transistor, the conductive structure includes a pillar provided on a substrate. A first conductive layer pattern is provided on a sidewall of the pillar, at least a portion of the first conductive layer pattern facing the sidewall of the pillar. A second conductive layer pattern is provided on a surface of the first conductive layer pattern, the second conductive layer pattern facing the sidewall of the pillar. A hard mask pattern covers upper surfaces of the first conductive layer pattern and the pillar. The conductive structure includes an electric conductor with a relatively low resistance. The conductive structure may be used as an electrode of a memory device. | 2010-02-04 |
20100025758 | METHOD OF MANUFACTURING HIGH-INTEGRATED SEMICONDUCTOR DEVICE AND SEMICONDUCTOR DEVICE MANUFACTURED USING THE SAME - A semiconductor device comprises a plurality of vertical transistors each comprising barrier metal layers corresponding to source/drain regions in which a conduction region is formed under a channel region having a pillar form, and a bit line comprising a metal layer to connect the plurality of vertical transistors. | 2010-02-04 |
20100025759 | TRENCH TYPE SEMICONDUCTOR DEVICE AND FABRICATION METHOD FOR THE SAME - The trench type semiconductor device includes a gate insulating film placed on the bottom surface and the sidewall surface of the trench formed from the surface of a first base layer; a gate electrode placed on the gate insulating film and fills up into a trench; an interlayer insulating film covering the gate electrode; a second base layer placed on the surface of the first base layer, and is formed more shallowly than the bottom surface of the trench; a source layer placed on the surface of the second base layer; a source electrode connected to the second base layer in the bottom surface of a self-aligned contact trench formed in the second base layer by applying the interlayer insulating film as a mask, and is connected to the source layer in the sidewall surface; a drain layer placed at the back side of the first base layer; and a drain electrode placed at the drain layer, for achieving the minute structure by the self-alignment, reducing the on resistance, and improving the breakdown capability, and providing a fabrication method for the same. | 2010-02-04 |
20100025760 | SEMICONDUCTOR DEVICE - A semiconductor device includes a MOSFET cell having a super junction structure and a diode cell connected in parallel with the MOSFET cell and having the same plan shape as the MOSFET cell. The MOSFET cell includes an epitaxial layer of a first conductivity type formed on a semiconductor substrate, a gate electrode and a first column region of a second conductivity type formed in the epitaxial layer, a first base region of the second conductivity type formed on a surface of the epitaxial layer, and a source region of the first conductivity type formed on a surface of the first base region. The diode cell includes a second column region of the second conductivity type formed in the epitaxial layer and having a larger width than the first column region, and a second base region of the second conductivity type formed on the surface of the epitaxial layer. | 2010-02-04 |
20100025761 | DESIGN STRUCTURE, STRUCTURE AND METHOD OF LATCH-UP IMMUNITY FOR HIGH AND LOW VOLTAGE INTEGRATED CIRCUITS - Design structures, structures and methods of manufacturing structures for providing latch-up immunity for mixed voltage integrated circuits. The structure includes a diffused N-Tub structure embedded in a P-wafer and provided below a retrograde N-well to a non-isolated CMOS logic. | 2010-02-04 |
20100025762 | SEMICONDUCTOR STRUCTURE AND FABRICATION METHOD THEREOF - A semiconductor fabrication process according to the present invention defines an auxiliary structure with a plurality of spaces with a predetermined line-width in the oxide layer to prevent the conductive material in the spaces from being removed by etching or defined an auxiliary structure to rise the conductive structure so as to have the conductive structure being exposed by chemical mechanical polishing. Thus, the transmitting circuit can be defined without requiring an additional mask. Hence, the semiconductor fabrication process can reduce the number of required masks to lower the cost. | 2010-02-04 |
20100025763 | Semiconductor on Insulator Devices Containing Permanent Charge - A lateral SOI device may include a semiconductor channel region connected to a drain region by a drift region. An insulation region on the drift layer is positioned between the channel region and the drain region. Permanent charges may be embedded in the insulation region sufficient to cause inversion in the insulation region. The semiconductor layer also overlies a global insulation layer, and permanent charges are preferably embedded in at least selected areas of this insulation layer too. | 2010-02-04 |
20100025764 | SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD THEREOF - Provided is a manufacturing method for an offset MOS transistor capable of operating safely even under a voltage of 50 V or higher. In the offset MOS transistor which includes a LOCOS oxide film, the LOCOS oxide film formed in a periphery of a drain diffusion layer, in which a high withstanding voltage is required, is etched, and the drain diffusion layer is formed so as to spread into a surface region of a semiconductor substrate located below a region in which the LOCOS oxide film is thinned. As a result, end portions of the drain diffusion layer are covered by an offset diffusion layer, whereby electric field concentration occurring in a region of a lower portion of the drain diffusion layer can be relaxed. | 2010-02-04 |
20100025765 | DUAL GATE LDMOS DEVICES - An embodiment of an N-channel device has a lightly doped substrate in which adjacent or spaced-apart P and N wells are provided. A lateral isolation wall surrounds at least a portion of the substrate and is spaced apart from the wells. A first gate overlies the P well or the substrate between the wells or partly both. A second gate, spaced apart from the first gate, overlies the N-well. A body contact to the substrate is spaced apart from the isolation wall by a first distance within the space charge region of the substrate to isolation wall PN junction. When the body contact is connected to the second gate, a predetermined static bias Vg | 2010-02-04 |
20100025766 | TRANSISTOR DEVICE AND METHOD OF MANUFACTURING SUCH A TRANSISTOR DEVICE - A transistor device ( | 2010-02-04 |
20100025767 | SEMICONDUCTOR DEVICE - A semiconductor device includes N fins made of semiconductor regions aligned in parallel with each other in the top view plain, a gate electrode formed on both side surfaces of each of the N fins to cross the fins, source/drain layers formed in each of the N fins by sandwiching the gate electrode, a first wiring connected to one of the source/drain layers via a first contact formed in each of M fins, and a second wiring connected to the other one of the source/drain layers via a second contact formed in each of K fins. | 2010-02-04 |
20100025768 | SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD THEREOF - It is an object of the present invention to provide a method for preventing a breaking and poor contact, without increasing the number of steps, thereby forming an integrated circuit with high driving performance and reliability. The present invention applies a photo mask or a reticle each of which is provided with a diffraction grating pattern or with an auxiliary pattern formed of a semi-translucent film having a light intensity reducing function to a photolithography step for forming wires in an overlapping portion of wires. And a conductive film to serve as a lower wire of a two-layer structure is formed, and then, a resist pattern is formed so that a first layer of the lower wire and a second layer narrower than the first layer are formed for relieving a steep step. | 2010-02-04 |
20100025769 | ISOLATED HIGH PERFORMANCE FET WITH A CONTROLLABLE BODY RESISTANCE - The present invention provides a method of controlling bias in an electrical device including providing semiconductor devices on a bulk semiconductor substrate each including an active body region that is isolated from the active body region of adjacent devices, and providing a body resistor in electrical contact with the active body region of the bulk semiconductor substrate, wherein the body resistor provides for adjustability of the body potential of the semiconductor devices. In another aspect the present invention provides a semiconductor device including a bulk semiconductor substrate, at least one field effect transistor formed on the bulk semiconductor substrate including an isolated active body region, and a resistor in electrical communication with the isolated active body region. | 2010-02-04 |
20100025770 | GATE DIELECTRICS OF DIFFERENT THICKNESS IN PMOS AND NMOS TRANSISTORS - By providing a gate dielectric material of increased thickness for P-channel transistors compared to N-channel transistors, degradation mechanisms, such as negative bias threshold voltage instability, hot carrier injection and the like, may be reduced. Due to the enhanced reliability of the P-channel transistors, overall production yield for a specified quality category may be increased, due to the possibility of selecting narrower guard bands for the semiconductor device under consideration. | 2010-02-04 |
20100025771 | PERFORMANCE ENHANCEMENT IN PMOS AND NMOS TRANSISTORS ON THE BASIS OF SILICON/CARBON MATERIAL - A silicon/germanium material and a silicon/carbon material may be provided in transistors of different conductivity type on the basis of an appropriate manufacturing regime without unduly contributing to overall process complexity. Furthermore, appropriate implantation species may be provided through exposed surface areas of the cavities prior to forming the corresponding strained semiconductor alloy, thereby additionally contributing to enhanced overall transistor performance. In other embodiments a silicon/carbon material may be formed in a P-channel transistor and an N-channel transistor, while the corresponding tensile strain component may be overcompensated for by means of a stress memorization technique in the P-channel transistor. Thus, the advantageous effects of the carbon species, such as enhancing overall dopant profile of P-channel transistors, may be combined with an efficient strain component while enhanced overall process uniformity may also be accomplished. | 2010-02-04 |
20100025772 | SEMICONDUCTOR DEVICE COMPRISING A SILICON/GERMANIUM RESISTOR - In integrated circuits, resistors may be formed on the basis of a silicon/germanium material, thereby providing a reduced specific resistance which may allow reduced dimensions of the resistor elements. Furthermore, a reduced dopant concentration may be used which may allow an increased process window for adjusting resistance values while also reducing overall cycle times. | 2010-02-04 |
20100025773 | PROCESS FOR PRODUCING A CONTACT PAD ON A REGION OF AN INTEGRATED CIRCUIT, IN PARTICULAR ON THE ELECTRODES OF A TRANSISTOR - A region is locally modified so as to create a zone that extends as far as at least part of the surface of the region and is formed from a material that can be removed selectively with respect to the material of the region. The region is then covered with an insulating material. An orifice is formed in the insulating material emerging at the surface of the zone. The selectively removable material is removed from the zone through the orifice so as to form a cavity in place of the zone. The cavity and the orifice are then filled with at least one electrically conducting material so as to form a contact pad. | 2010-02-04 |
20100025774 | SCHOTTKY BARRIER INTEGRATED CIRCUIT - A Schottky barrier integrated circuit is disclosed, the circuit having at least one PMOS device or at least one NMOS device, at least one of the PMOS device or NMOS device having metal source-drain contacts forming Schottky barrier or Schottky-like contacts to the semiconductor substrate. The device provides a new distribution of mobile charge carriers in the bulk region of the semiconductor substrate, which improves device and circuit performance by lowering gate capacitance, improving effective carrier mobility | 2010-02-04 |
20100025775 | Replacement spacers for mosfet fringe capacatance reduction and processes of making same - A process includes planarizing a microelectronic device that includes a gate stack and adjacent trench contacts. The process also includes removing a gate spacer at the gate stack and replacing the gate spacer with a dielectric that results in a lowered overlap capacitance between the gate stack and an adjacent embedded trench contact. | 2010-02-04 |
20100025776 | DRIVE CURRENT ADJUSTMENT FOR TRANSISTORS BY LOCAL GATE ENGINEERING - In a memory cell, the drive current capabilities of the transistors may be adjusted by locally providing an increased gate dielectric thickness and/or gate length of one or more of the transistors of the memory cell. That is, the gate length and/or the gate dielectric thickness may vary along the transistor width direction, thereby providing an efficient mechanism for adjusting the effective drive current capability while at the same time allowing the usage of a simplified geometry of the active region, which may result in enhanced production yield due to enhanced process uniformity. In particular, the probability of creating short circuits caused by nickel silicide portions may be reduced. | 2010-02-04 |
20100025777 | METHOD FOR SUPPRESSING LATTICE DEFECTS IN A SEMICONDUCTOR SUBSTRATE - A method for suppressing the formation of leakage-promoting defects in a crystal lattice following dopant implantation in the lattice. The process provides a compressive layer of atoms, these atoms having a size greater than that of the lattice member atoms. The lattice is then annealed for a time sufficient for interstitial defect atoms to be emitted from the compressive layer, and in that manner energetically stable defects are formed in the lattice at a distance from the compressive layer. | 2010-02-04 |
20100025778 | TRANSISTOR STRUCTURE AND METHOD OF MAKING THE SAME - A transistor includes a gate structure of HfMoN. The work function of the gate structure can be modulated by doping the HfMoN with dopants including nitride, silicon or germanium. The gate structure of HfMoN of the present invention is applicable to PMOS, NMOS or CMOS transistors. | 2010-02-04 |
20100025779 | SHALLOW PN JUNCTION FORMED BY IN SITU DOPING DURING SELECTIVE GROWTH OF AN EMBEDDED SEMICONDUCTOR ALLOY BY A CYCLIC GROWTH/ETCH DEPOSITION PROCESS - A silicon/carbon alloy may be formed in drain and source regions, wherein another portion may be provided as an in situ doped material with a reduced offset with respect to the gate electrode material. For this purpose, in one illustrative embodiment, a cyclic epitaxial growth process including a plurality of growth/etch cycles may be used at low temperatures in an ultra-high vacuum ambient, thereby obtaining a substantially bottom to top fill behavior. | 2010-02-04 |
20100025780 | SEMICONDUCTOR DEVICE AND METHOD FOR MANUFACTURING SAME - A semiconductor device of the present invention includes: a semiconductor layer; a gate insulation film provided on the semiconductor layer and including at least one of Hf and Zr; and a gate electrode provided on the gate insulation film and including a carbonitride which includes at least one of Hf and Zr. | 2010-02-04 |
20100025781 | Transistors with Multilayered Dielectric Films and Methods of Manufacturing Such Transistors - Transistors that include multilayered dielectric films on a channel region are provided. The multilayered dielectric comprises a lower dielectric film that may have a thickness that is at least 50% the thickness of the multilayered dielectric film and that comprises a metal oxide, a metal silicate, an aluminate, or a mixture thereof, and an upper dielectric film on the lower dielectric film, the upper dielectric film comprising a Group III metal oxide, Group III metal nitride, Group XIII metal oxide or Group XIII metal nitride. A gate electrode is provided on the multilayered dielectric film. | 2010-02-04 |
20100025782 | TECHNIQUE FOR REDUCING SILICIDE NON-UNIFORMITIES IN POLYSILICON GATE ELECTRODES BY AN INTERMEDIATE DIFFUSION BLOCKING LAYER - Threshold variability in advanced transistor elements, as well as increased leakage currents, may be reduced by incorporating a barrier material in a polysilicon gate electrode. The barrier material results in a well-controllable and well-defined metal silicide in the polysilicon gate electrode during the silicidation sequence and during the further processing by significantly reducing the diffusion of a metal species, such as nickel, into the vicinity of the gate dielectric material. | 2010-02-04 |
20100025783 | Sensor apparatus for detecting variations in a dynamic quantity while suppressing detection deviations that are caused by bending deformation of a sensor chip - A miniaturized sensor such as a micro-accelerometer includes a sensor chip having a sensor element mounted thereon, with the sensor element being oriented with its central axes passing through the corners of the sensor chip. The corners of the sensor element are thereby located substantially apart from the corners of the sensor chip, so that bending deformation which displaces corners of the sensor chip is substantially prevented from causing displacement of corners of the sensor element. Detection inaccuracy resulting from such displacement can thereby be prevented or reduced. | 2010-02-04 |
20100025784 | FIBROUS MICRO-COMPOSITE MATERIAL - Fibrous micro-composite materials are formed from micro fibers. The fibrous micro-composite materials are utilized as the basis for a new class of MEMS. In addition to simple fiber composites and microlaminates, fibrous hollow and/or solid braids, can be used in structures where motion and restoring forces result from deflections involving torsion, plate bending and tensioned string or membrane motion. In one embodiment, fibrous elements are formed using high strength, micron and smaller scale fibers, such as carbon/graphite fibers, carbon nanotubes, fibrous single or multi-ply graphene sheets, or other materials having similar structural configurations. Cantilever beams and torsional elements are formed from the micro-composite materials in some embodiments. | 2010-02-04 |
20100025785 | FLIP-CHIP INTERCONNECTION THROUGH CHIP VIAS - An acoustic assembly that includes an integrated circuit package having an electrically conductive via configured to pass from an active portion of the integrated circuit package through a bottom portion of the integrated circuit package. The bottom portion is a bottom side of a substrate of the integrated circuit package. An acoustic element is positioned on the bottom side of the substrate and the via is arranged to electrically couple the active portion of the integrated circuit package to the acoustic element. In one embodiment, the acoustic element is an acoustic stack and the integrated circuit package is an ASIC. The assembly microbeamformed transducer. | 2010-02-04 |
20100025786 | Method for Manufacturing a Diaphragm on a Semiconductor Substrate and Micromechanical Component Having Such a Diaphragm - A method for manufacturing a diaphragm, on a semiconductor substrate, includes the method operations or tasks of a) providing a semiconductor substrate, b) producing trenches in the semiconductor substrate, webs made of semiconductor substrate remaining between the trenches, c) producing an oxide layer on the walls of the trenches with the aid of a thermal oxidation method, d) producing access openings in a cover layer produced in a preceding method operation or task on the semiconductor substrate, to expose the semiconductor substrate in the area of the webs, e) isotropic etching of the semiconductor substrate exposed in method operation or task d) using a method selective to the oxide layer and to the cover layer, at least one cavity being produced in the webs below the cover layer, which is laterally delimited by the oxide layer of at least one trench, and f) depositing a sealing layer to seal the access openings in the cover layer. | 2010-02-04 |
20100025787 | System and method for providing a high frequency response silicon photodetector - A Silicon photodetector contains an insulating substrate having a top surface and a bottom surface. A Silicon layer is located on the top surface of the insulating substrate, where the Silicon layer contains a center region, the center region being larger in thickness than the rest of the Silicon layer. A top Silicon dioxide layer is located on a top surface of the center region. A left wing of the center region and a right wing of the center region are doped. The Silicon photodetector also has an active region located within the center region, where the active region contains a tailored crystal defect-impurity combination and Oxygen atoms. | 2010-02-04 |
20100025788 | Solid-state image capturing device, method for manufacturing the same and electronic information device - In a solid-state image capturing device having the locations of photodiodes in each pixel unit to be different according to a sequence, the light receiving sensitivity and the luminance shading characteristic are improved. A circumferential portion of a microlens | 2010-02-04 |
20100025789 | IMAGING DEVICE, METHOD FOR MANUFACTURING THE IMAGING DEVICE AND CELLULAR PHONE - An imaging device includes a lens ( | 2010-02-04 |
20100025790 | IMAGE SENSOR AND METHOD OF MANUFACTURING THE SAME - Disclosed are an image sensor and a method of manufacturing the same. The image sensor includes a semiconductor substrate having first and second surfaces opposite to each other, an isolation layer defining an active region while extending from the first surface toward the second surface, a photodiode in the active region and extending from the first surface toward the second surface, a reflection part adjacent to the first surface and disposed corresponding to the photodiode, and a lens part adjacent to the second surface. | 2010-02-04 |
20100025791 | SOLID-STATE IMAGING DEVICE AND METHOD FOR MANUFACTURING SAME - An interconnect layer is formed on a lower face of a silicon wafer, a support substrate is adhered over a lower face of the interconnect layer, and a thickness reduction of the silicon wafer is performed from an upper face side. Next, a photodiode is formed in an upper face of the silicon wafer, and a microlens is formed at a position corresponding to the photodiode. An adhesive layer is formed on the silicon wafer in a region not covering the microlens, a low refractive index layer having a lower refractive index than the microlens is formed in a region covering the microlens, and a glass substrate is adhered to the silicon wafer by the adhesive layer. The support substrate is removed from the interconnect layer, and a solder ball is bonded to a lower face of the interconnect layer. Thereafter, a CMOS image sensor is manufactured by dicing the silicon wafer. | 2010-02-04 |