05th week of 2011 patent applcation highlights part 62 |
Patent application number | Title | Published |
20110029721 | Cascaded combination structure of flash disks to create security function - Disclosed is a cascaded combination structure of flash disks to create security function, comprising of a plurality of data disks and a key disk. Each of the data disks includes a public zone and a private zone matched with the key disk. When the key disk is series-connected with the data disks, the private zone can be displayed and load/save by a public program in the key disk. Accordingly, there can be secured and hid the data in the private zone so that the data in the private zone is unable to be embezzled by other illegal users. | 2011-02-03 |
20110029722 | ELECTRONIC CONTROL APPARATUS INCLUDING ELECTRICALLY REWRITABLE NON-VOLATILE MEMORY - The electronic control apparatus includes an electrically rewritable non-volatile memory, a writing voltage there of being larger in absolute value than a reading voltage thereof, and a control section configured to access the non-volatile memory to perform data writing or data reading. The non-volatile memory includes a first terminal to receive the writing voltage generated by a voltage generating means disposed outside the electronic control apparatus, the first terminal being electrically isolated from the external voltage generating means. | 2011-02-03 |
20110029723 | Non-Volatile Memory Based Computer Systems - Non-volatile memory based computer systems and methods are described. According to one aspect of the invention, at least one non-volatile memory module is coupled to a computer system as main storage. The non-volatile memory module is controlled by a northbridge controller configured to control the non-volatile memory as main memory. The page size of the at least one non-volatile memory module is configured to be the size of one of the cache lines associated with a microprocessor of the computer system. According to another aspect, at least one non-volatile memory module is coupled to a computer system as data read/write buffer of one or more hard disk drives. The non-volatile memory module is controlled by a southbridge controller configured to control the non-volatile memory as an input/out device. The page size of the at least one non-volatile memory module is configured in proportion to characteristics of the hard disk drives. | 2011-02-03 |
20110029724 | Partial Block Data Programming And Reading Operations In A Non-Volatile Memory - Data in less than all of the pages of a non-volatile memory block are updated by programming the new data in unused pages of either the same or another block. In order to prevent having to copy unchanged pages of data into the new block, or to program flags into superceded pages of data, the pages of new data are identified by the same logical address as the pages of data which they superceded and a time stamp is added to note when each page was written. When reading the data, the most recent pages of data are used and the older superceded pages of data are ignored. This technique is also applied to metablocks that include one block from each of several different units of a memory array, by directing all page updates to a single unused block in one of the units. | 2011-02-03 |
20110029725 | Switching Drivers Between Processors - Systems, methods, and computer software for operating a device can be used to operate the device in multiple modes. The device can be operated in a first operating mode adapted for processing data, in which a first processor executes a driver for a nonvolatile memory and a second processor performs processing of data stored in files on the nonvolatile memory. An instruction can be received to switch the device to a second operating mode adapted for reading and/or writing files from or to the nonvolatile memory. The driver for the nonvolatile memory can be switched from the first processor to the second processor in response to the instruction, and the driver for the nonvolatile memory can be executed on the second processor after performing the switch. A communications driver can be executed on the first processor in response to the instruction to switch the device to the second operating mode. | 2011-02-03 |
20110029726 | DATA UPDATING METHOD, MEMORY SYSTEM AND MEMORY DEVICE - A data updating method, a memory system and a memory device in which the memory device is connectable to a host device and has a memory section and a memory controller, the memory section consists of a first memory section which can be divided into partitions having multiple different attributes, and a work space which is managed by the memory controller, and the method of updating data which is stored in the memory device uses one of the writing methods which has been selected from among multiple different writing methods of writing data into the partition, depending on the attribute of the partition, to perform an updating process, and can securely update the data. | 2011-02-03 |
20110029727 | Disk Controller Configured to Perform Out of Order Execution of Write Operations - A controller for a disk drive includes first memory storing first write operations and second write operations received in a first order. A processor arranges the first write operations and the second write operations in a second order based on respective track sectors associated with the first and the second write operations. The second order is different than the first order. A memory controller transfers write operation data corresponding to the first write operations and the second write operations to a disk formatter in the second order in response to a single command from the processor. | 2011-02-03 |
20110029728 | METHODS AND APPARATUS FOR REDUCING INPUT/OUTPUT OPERATIONS IN A RAID STORAGE SYSTEM - Methods and systems for managing RAID volumes are disclosed. Metadata is associated with storage devices that comprise a RAID volume. The metadata identifies each of a plurality of portions as being either initialized or non-initialized. The number of I/O operations performed by a storage controller coupled with the storage devices is reduced in response to a request for the RAID volume based on the metadata. | 2011-02-03 |
20110029729 | ERASURE CODED DATA STORAGE CAPACITY AND POWER MANAGEMENT - A set of data is allocated into a plurality of data chunks, wherein the plurality of data chunks is thinly provisioned and erasure coded. A plurality of storage devices is divided into a first and a second set of storage devices, wherein the first set of storage devices is powered up and the second set of storage devices is powered down. The data chunks are distributed on the first set of storage devices to equally load each of the first set of storage devices. A storage device from the second set of storage devices is powered up to reassign the storage device from the second set of storage devices to the first set of storage devices. Data chunks are migrated to a reassigned storage device until the data chunks are evenly distributed on the first set of storage devices and the reassigned storage device. | 2011-02-03 |
20110029730 | DATA PROCESSING SYSTEM USING CACHE-AWARE MULTIPATH DISTRIBUTION OF STORAGE COMMANDS AMONG CACHING STORAGE CONTROLLERS - A data processing system includes a storage system and caching storage controllers coupled to the storage system and to a storage network. The storage controllers operate in an active-active fashion to provide access to volumes of the storage system from any of the storage controllers in response to storage commands from the storage network. The storage controllers employ a distributed cache protocol in which (a) each volume is divided into successive chunks of contiguous blocks, and (b) either chunk ownership may be dynamically transferred among the storage controllers in response to the storage commands, or storage commands sent to a non-owning controller may be forwarded to the owning controller. A multipathing initiator such as a server computer directs the storage commands to the storage controllers by (1) for each volume, maintaining a persistent association of the chunks of the volume with respective storage controllers, and (2) for each storage request directed to a target chunk, identifying the storage controller associated with the target chunk and sending a corresponding storage command to the identified storage controller. Chunk ownership tends to stabilize at individual storage controllers, reducing unnecessary transfer of cache data and metadata among the storage controllers. | 2011-02-03 |
20110029731 | DISPERSED STORAGE WRITE PROCESS - A dispersed storage (DS) method begins by issuing a plurality of write commands to a plurality of DS storage units. The method continues by receiving a write acknowledgement from one of the plurality of DS storage units to produce a received write acknowledgement. The method continues by issuing a plurality of commit commands to the plurality of DS storage units when a write threshold number of the received write acknowledgements have been received. The method continues by receiving a commit acknowledgement from a DS storage unit of the plurality of DS storage units to produce a received commit acknowledgement. The method continues by issuing a plurality of finalize commands to the plurality of DS storage units when a write threshold number of the received commit acknowledgements have been received. | 2011-02-03 |
20110029732 | STORAGE DEVICE CONTROLLER WITH A PLURALITY OF I/O PROCESSORS REQUESTING DATA FROM A PLURALITY OF STRIPE UNITS OF A LOGICAL VOLUME - Provided is a storage controller capable of improving the access performance to the storage device by preventing an I/O access request to the storage device from being concentrated on certain I/O processors among a plurality of I/O processor, and causing the plurality of I/O processors to issue the I/O access request in a well balanced manner. With this storage control system, a plurality of stripe units are formed by striping the logical volume into a stripe size of an arbitrary storage capacity, and information regarding which I/O processor among the plurality of I/O processors will output the I/O request to which stripe unit among the plurality of stripe units is stored as the control information in the memory. | 2011-02-03 |
20110029733 | ENDOSCOPY DEVICE SUPPORTING MULTIPLE INPUT DEVICES - The present invention provides a remote-head imaging system with a camera control unit capable of supporting multiple input devices. The camera control unit detects an input device to which it is connected and changes the camera control unit's internal functionality accordingly. Such changes include altering clock timing, changing video output parameters, and changing image processing software. In addition, a user is able to select different sets of software program instructions and hardware configuration information based on the head that is attached. The remote-head imaging system utilizes field-programmable circuitry, such as field-programmable gate arrays (FPGA), in order to facilitate the change in configuration. | 2011-02-03 |
20110029734 | Controller Integration - Roughly described, a data processing system comprises a central processing unit and a split network interface functionality, the split network interface functionality comprising: a first sub-unit collocated with the central processing unit and configured to at least partially form a series of network data packets for transmission to a network endpoint by generating data link layer information for each of those packets; and a second sub-unit external to the central processing unit and coupled to the central processing unit via an interconnect, the second sub-unit being configured to physically signal the series of network data packets over a network. | 2011-02-03 |
20110029735 | METHOD FOR MANAGING AN EMBEDDED SYSTEM TO ENHANCE PERFORMANCE THEREOF, AND ASSOCIATED EMBEDDED SYSTEM - A method for managing an embedded system is provided. The method includes selecting one of a first memory and a second memory according to at least one criterion, where the selected memory is a source from which the embedded system reads commands of a program, and an access speed of the first memory is different from that of the second memory; and controlling the embedded system to execute the program by utilizing the selected memory as the source. | 2011-02-03 |
20110029736 | STORAGE CONTROLLER AND METHOD OF CONTROLLING STORAGE CONTROLLER - The storage controller of the present invention is able to reduce the amount of purge message communication and increase the processing performance of the storage controller. Each microprocessor creates and saves a purge message every time control information in the shared memory is updated. After a series of update processes are complete, the saved purge messages are transmitted to each microprocessor. To the control information, attribute corresponding to its characteristics is established, and cache control and purge control are executed depending on the attribute. | 2011-02-03 |
20110029737 | EFFICIENTLY SYNCHRONIZING WITH SEPARATED DISK CACHES - In a method of synchronizing with a separated disk cache, the separated cache is configured to transfer cache data to a staging area of a storage device. An atomic commit operation is utilized to instruct the storage device to atomically commit the cache data to a mapping scheme of the storage device. | 2011-02-03 |
20110029738 | LOW-COST CACHE COHERENCY FOR ACCELERATORS - Embodiments of the invention provide methods and systems for reducing the consumption of inter-node bandwidth by communications maintaining coherence between accelerators and CPUs. The CPUs and the accelerators may be clustered on separate nodes in a multiprocessing environment. Each node that contains a shared memory device may maintain a directory to track blocks of shared memory that may have been cached at other nodes. Therefore, commands and addresses may be transmitted to processors and accelerators at other nodes only if a memory location has been cached outside of a node. Additionally, because accelerators generally do not access the same data as CPUs, only initial read, write, and synchronization operations may be transmitted to other nodes. Intermediate accesses to data may be performed non-coherently. As a result, the inter-chip bandwidth consumed for maintaining coherence may be reduced. | 2011-02-03 |
20110029739 | Storage system and control method for the same, and program - The present invention provides a criterion for determining whether or not to apply de-duplication processing. That is, by setting a reduction effect threshold to control switching the de-duplication between ON and OFF, the present invention allows operation such that the de-duplication is applied for a volume for which a high capacity-reduction effect is provided by the de-duplication processing, and in contrast, the de-duplication is not applied to maintain performance for a volume for which a low capacity-reduction effect is provided by the de-duplication processing. | 2011-02-03 |
20110029740 | COMMUNICATING METHOD APPLIED FOR STORAGE DEVICE - A communicating method between a storage device and an application program includes the following steps: the application program dynamically selects a block address in the storage device as a predetermined block address; and the application program performs a command write-in or state read-out process via the predetermined block address to communicate with the storage device. | 2011-02-03 |
20110029741 | DATA MANAGEMENT METHOD AND MEMORY DEIVCE - The invention provides a data management method for a memory device. In one embodiment, the memory device comprises a plurality of memories for data storage. First, write data and a write logical address is received from a host. The write logical address is then converted to a write physical address. A target memory corresponding to the write physical address is then determined. Whether the target memory is in a busy state is then checked. When the target memory is in the busy state, the write data is written to a buffer area of a substitute memory of the target memory. | 2011-02-03 |
20110029742 | COMPUTING SYSTEM UTILIZING DISPERSED STORAGE - A computing system comprises at least a processing module, a main memory, a memory controller, and a plurality of memory components. A method begins by the memory controller receiving a memory access request regarding a data segment. The method continues with the memory controller interpreting the memory access request to determine whether an error encoding dispersal function of the data segment is applicable. The method continues with the memory controller identifying at least a threshold number of memories based on the memory access request, wherein the threshold number of memories includes at least one of the main memory and/or one or more of the plurality of memory components, when the error encoding dispersal function is applicable. The method continues with the memory controller addressing the at least a threshold number of memories to facilitate the memory access request. | 2011-02-03 |
20110029743 | COMPUTING CORE APPLICATION ACCESS UTILIZING DISPERSED STORAGE - A computing core application access method begins by a processing module detecting selection of an application. The method continues with at least one of a memory controller and the processing module addressing a distributed application memory to retrieve a plurality of error coded program data slices and a plurality of error coded configuration data slices. The method continues with the at least one of a memory controller and the processing module reconstructing a data segment of a program from the plurality of error coded program data slices using an error coding dispersal function. The method continues with the at least one of a memory controller and the processing module reconstructing a data segment of a configuration information from the plurality of error coded configuration data slices using a second error coding dispersal function. The method continues with the at least one of a memory controller and the processing module storing the data segment of the program and the data segment of the configuration information in a main memory of the computing core. | 2011-02-03 |
20110029744 | DISPERSED STORAGE NETWORK VIRTUAL ADDRESS SPACE - A dispersed storage network utilizes a virtual address space to store data. The dispersed storage network includes a processing unit operable to slice a data segment of a data object into data slices and create a slice name for each of the data slices. The slice name includes an identifier of the data object and a virtual memory address of a virtual memory associated with the dispersed storage network. The processing unit further outputs each of the data slices and the respective slice names to a corresponding storage unit for storage of the data slices therein. | 2011-02-03 |
20110029745 | ELECTRONIC DEVICE AND CONTROL METHOD THEREOF - An electronic device comprises: a mounting unit in which a first storage medium to be mounted; an acquiring unit configured to acquire attribute information of a mounted storage medium; a first determining unit configured to determine whether or not the mounted storage medium is a storage medium having a function other than a storage function based on the attribute information; a transmitting unit configured to transmit a command that can be used in a function other than a storage function to the mounted storage medium, in a case where it is determined that the storage medium is not a storage medium having the function other than the storage function; and a second determining unit configured to determine whether or not the mounted storage medium has the function other than the storage function based on whether or not there is a response to the transmitted command. | 2011-02-03 |
20110029746 | RECONFIGURABLE MEMORY MODULE AND METHOD - A computer system includes a controller coupled to a plurality of memory modules each of which includes a memory hub and a plurality of memory devices divided into a plurality of ranks. The memory hub is operable to configure the memory module to simultaneously address any number of ranks to operate in a high bandwidth mode, a high memory depth mode, or any combination of such modes. | 2011-02-03 |
20110029747 | SYSTEM AND METHOD FOR ARCHIVING OF DATA - The invention relates to a method, a system and a computer program for archiving of data. An announcement signal, which identifies the data, which have to be archived, is sent from a source system to a destination system. A feedback signal, which identifies the announcement signal received by the destination system, is sent from the destination system to the source system, wherein it is determined from the feedback signal whether the announcement signal has been received by the destination system correctly. If it has been determined that the announcement signal has not been correctly received, at least parts of the announcement signal are resent from the source system to the destination system. The data identified by the announcement signal are sent from the source system to the destination system for archiving of data. | 2011-02-03 |
20110029748 | REMOTE COPY SYSTEM AND REMOTE COPY CONTROL METHOD - Proposed are a remote copy system and a remote copy control method capable of performing the operation of remote copy according to the user's usage status. Resource information representing a resource usage status is collected from a first storage apparatus installed at a primary site and a second storage apparatus installed respectively at one or more secondary sites, a transfer mode of differential data between snapshots to be transferred from the first storage apparatus to the second storage apparatus based on the collected resource information, and the first and second storage apparatuses are controlled so as to transfer the differential data from the first storage apparatus to the second storage apparatus based on the decided transfer mode. | 2011-02-03 |
20110029749 | SEMICONDUCTOR STORAGE SYSTEM FOR DECREASING PAGE COPY FREQUENCY AND CONTROLLING METHOD THEREOF - A semiconductor storage system includes a memory controller that classifies a memory block of a memory area into a data block and a buffer block. The buffer block corresponds to the data block. The memory controller compares the number of free pages of both the data block and the buffer block with the number of valid pages of the data block and the buffer block during mergence in order to select the merged target block. Depending on the result of the comparison, either the data block or the buffer block is selected as the merged target block. | 2011-02-03 |
20110029750 | METHOD AND APPARATUS FOR MANAGING DATA USING JAVA APPLICATION IN MOBILE TERMINAL - A method and apparatus for managing data acquired by means of a Java application in a mobile device having a backup interface to an external interface. At least one location information acquired by execution of a Java application is stored within an internal memory. A backup request signal for storing in an external memory the location information selected from among the at least one location information contained in an internal memory is detected. The selected location information is backed up to the external memory through a backup interface established between the internal memory and the external memory in response to the backup request signal. | 2011-02-03 |
20110029751 | ENHANCED BLOCK COPY - The present disclosure includes methods and apparatus for an enhanced block copy. One embodiment includes reading data from a source block located in a first portion of the memory device, and programming the data to a target block located in a second portion of the memory device. The first and second portions are communicatively coupled by data lines extending across the portions. The data lines are communicatively uncoupled between the first and second portions for at least one of the reading and programming acts. | 2011-02-03 |
20110029752 | FULLY-BUFFERED DUAL IN-LINE MEMORY MODULE WITH FAULT CORRECTION - A memory module comprises first memory that stores data in memory blocks; second memory that temporarily stores data from at least one of the memory blocks and third memory for storing a relationship between addresses of the at least one of the memory blocks in the first memory and corresponding addresses of the data from the at least one of the memory blocks in the second memory. Storage capacities of the second and third memories are less than a storage capacity of the first memory. A control module selectively transfers data in the at least one of the memory blocks in the first memory to the second memory and stores and retrieves data from the second memory for the at least one of the memory blocks based on the relationship during the testing. | 2011-02-03 |
20110029753 | DISPERSED STORAGE NETWORK VIRTUAL ADDRESS GENERATIONS - A dispersed storage device within a dispersed storage network includes a processing module for determining whether to add a new generation for a vault, in which the vault identifies at least one user having data to be stored. When the new generation is to be added to the vault, the processing module further assigns a vault generation identifier to the new generation, assigns a virtual address range of a virtual memory associated with the dispersed storage network to the new generation and maps the virtual address range to a physical memory for storage of the data therein. | 2011-02-03 |
20110029754 | MULTI-BIT-PER-CELL FLASH MEMORY DEVICE WITH NON-BIJECTIVE MAPPING - To store a plurality of input bits, the bits are mapped to a corresponding programmed state of one or more memory cells and the cell(s) is/are programmed to that corresponding programmed state. The mapping may be many-to-one or may be an “into” generalized Gray mapping. The cell(s) is/are read to provide a read state value that is transformed into a plurality of output bits, for example by maximum likelihood decoding or by mapping the read state value into a plurality of soft bits and then decoding the soft bits. | 2011-02-03 |
20110029755 | PROCESSOR AND ARITHMATIC OPERATION METHOD - A processor has a first table including an entry that associates a logical address with a physical address of a page that manages a virtual space address. The processor determines, when a target logical address accessed by one of threads is translated to the physical address, whether an entry corresponding to the target logical address is present in the first table, the target logical address is of a page accessed by a program. The processor determines, when the entry corresponding to the target logical address is not present in the first table, whether the target logical address has been accessed during the running of the program. The processor delays, when the target logical address has not yet been accessed, the process of reading the entry corresponding to the target logical address from a page table into the first table by a predetermined time to thereby delay the one thread. | 2011-02-03 |
20110029756 | Method and System for Decoding Low Density Parity Check Codes - A method for decoding a codeword in a data stream encoded according to a low density parity check (LDPC) code having an m×j parity check matrix H by initializing variable nodes with soft values based on symbols in the codeword, wherein a graph representation of H includes m check nodes and j variable nodes, and wherein a check node m provides a row value estimate to a variable node j and a variable node j provides a column value estimate to a check node m if H(m,j) contains a 1, computing row value estimates for each check node, wherein amplitudes of only a subset of column value estimates provided to the check node are computed, computing soft values for each variable node based on the computed row value estimates, determining whether the codeword is decoded based on the soft values, and terminating decoding when the codeword is decoded. | 2011-02-03 |
20110029757 | STREAM PROCESSOR AND TASK MANAGEMENT METHOD THEREOF - A stream processor includes a programmable main processor MP, and a coprocessor CP that executes an extension instruction, the extension instruction being different from a basic instruction executed by the main processor MP. The main processor MP includes a coprocessor controller CPC outputting the extension instruction to the coprocessor CP, and the coprocessor CP includes a task controller TC, the task controller controlling a task performed based on the extension instruction and outputting status information ST of the task on every clock. The coprocessor controller CPC controls the coprocessor CP based on the status information ST and a basic instruction executed by the main processor MP in background in advance. | 2011-02-03 |
20110029758 | CENTRAL PROCESSING UNIT MEASUREMENT FACILITY - A measurement sampling facility takes snapshots of the central processing unit (CPU) on which it is executing at specified sampling intervals to collect data relating to tasks executing on the CPU. The collected data is stored in a buffer, and at selected times, an interrupt is provided to remove data from the buffer to enable reuse thereof. The interrupt is not taken after each sample, but in sufficient time to remove the data and minimize data loss. | 2011-02-03 |
20110029759 | METHOD AND APPARATUS FOR SHUFFLING DATA - Method, apparatus, and program means for shuffling data. The method of one embodiment comprises receiving a first operand having a set of L data elements and a second operand having a set of L control elements. For each control element, data from a first operand data element designated by the individual control element is shuffled to an associated resultant data element position if its flush to zero field is not set and a zero is placed into the associated resultant data element position if its flush to zero field is not set. | 2011-02-03 |
20110029760 | NON-ATOMIC SCHEDULING OF MICRO-OPERATIONS TO PERFORM ROUND INSTRUCTION - A microprocessor executes an instruction specifying a floating-point input operand having a predetermined size and that instructs the microprocessor to round the floating-point input operand to an integer value using a rounding mode and to return a floating-point result having the same predetermined size. An instruction translator translates the instruction into first and second microinstructions. An execution unit executes the first and second microinstructions. The first microinstruction receives as an input operand the instruction floating-point input operand and generates an intermediate result from the input operand. The second microinstruction receives as an input operand the intermediate result of the first microinstruction and generates the floating-point result of the instruction from the intermediate result. The intermediate result is the same predetermined size as the instruction floating-point input operand. The microprocessor executes the first and second microinstructions such that the commencement of their executions may have indeterminate separation in time. | 2011-02-03 |
20110029761 | Method and apparatus of reducing CPU chip size - A new compression method and apparatus compresses instructions embedded in a CPU chip which significantly reduces the density of storage device of storing the program. Multiple groups of instructions in the form of binary code are compressed separately by a mapping unit indicating the starting location of a group of instructions which helps quickly recovering the corresponding instructions. A mapping unit is applied to interpret the corresponding address of a group of data for quickly recovering the corresponding instructions for a CPU to execute smoothly. | 2011-02-03 |
20110029762 | SEMICONDUCTOR DEVICE PERFORMING SERIAL PARALLEL CONVERSION - A first transfer circuit includes pipeline circuits having different number of stages, and switch circuits that exclusively supply the pipeline circuits with first and second read data. A second transfer circuit includes pipeline circuits having different number of stages, and switch circuits that exclusively supply the pipeline circuits with third and fourth read data. Outputs of the first and second transfer circuits are sequentially output from a multiplex circuit. When a first operation mode is selected, all the pipeline circuits are activated. When a second operation mode is selected, one of the pipeline circuits in the first transfer circuit and one of the pipeline circuits in the second transfer circuit are activated, whereas the others of the pipeline circuits are inactivated. | 2011-02-03 |
20110029763 | BRANCH PREDICTOR FOR SETTING PREDICATE FLAG TO SKIP PREDICATED BRANCH INSTRUCTION EXECUTION IN LAST ITERATION OF LOOP PROCESSING - A processor simultaneously issues instructions to multiple threads in a same instruction execution cycle. An instruction issuer controls issuance of an instruction for each of the multiple threads. A detector detects, for each of the multiple threads, whether a loop processing is currently being executed. A unit causes the instruction issuer to increase a number of instructions to be issued when the detector detects that the loop processing is currently being executed. | 2011-02-03 |
20110029764 | BIOS FIELD MAPPING - BIOS field mapping includes generating basic input/output system (BIOS) information by defining property identifications using a visual form code language and determining that a proprietary set-up service is accessible. The BIOS field mapping then includes converting the visual form code language to a binary format and storing the property identifications in binary format on a setup database as data hidden from an operating system. A BIOS driver may then request the property identifications causing a transfer of the property identifications to the BIOS driver. | 2011-02-03 |
20110029765 | COMPUTING DEVICE BOOTING UTILIZING DISPERSED STORAGE - A computing device boot-up method begins by a processing module detecting a boot-up of the computing device. The method continues with the processing module addressing a distributed basic input/output system (BIOS) memory to retrieve a plurality of error coded BIOS data slices. The method continues with the processing module reconstructing BIOS data from the plurality of error coded BIOS data slices using an error coding dispersal function. The method continues with the computing device booting up in accordance with the BIOS data. | 2011-02-03 |
20110029766 | SYSTEM, APPARATUS, AND METHOD FOR BIOS LEVEL CONTEXTUAL CONFIGURATION OF RESOURCES - A system and method for a contextual control of resources of a computer. A plurality of detection modules may inform a configuration module of context changes and events. A database may store a plurality of configuration parameters and policies. A configuration module may configure a BIOS of a computer according to events, context and configuration policies. Other embodiments are described and claimed. | 2011-02-03 |
20110029767 | System and Method for Transforming Configuration Data Items in a Configuration Management Database - A system, method and apparatus for performing information transformations on an information stream composed of configuration items (CIs) for improving data quality and extending the capabilities of a configuration management database (CMDB). In one embodiment the data transformations ensure that a CMDB can be used to manage environments that use Network Address Translation by the modification of the signatures of analyzed CIs so that the resulting set of CIs is unique. The modification is applied to augment the signature with a domain specific prefix so that, when loaded into the enterprise wide CMDB, a CI is uniquely identified. | 2011-02-03 |
20110029768 | METHOD FOR TRANSMITTING CONTENTS FOR CONTENTS MANAGEMENT TECHNOLOGY INTERWORKING, AND RECORDING MEDIUM FOR STORING PROGRAM THEREOF - A DRM technique interoperability system includes an exporter and an importer. The exporter cancels the DRM technique from the contents to which the DRM technique of a DRM device is applied to generate a contents stream, generates a plurality of packets from the contents stream, and transmits the packets to the importer. The importer receives a plurality of packets from the exporter, generates a contents stream from the plurality of packets, applies a DRM technique of a second DRM device to the contents stream, and provides it to the second DRM device. | 2011-02-03 |
20110029769 | METHOD FOR USING TRUSTED, HARDWARE IDENTITY CREDENTIALS IN RUNTIME PACKAGE SIGNATURE TO SECURE MOBILE COMMUNICATIONS AND HIGH VALUE TRANSACTION EXECUTION - A method for trusted package digital signature based on secure, platform-bound identity credentials. The selection of a document to be electronically signed by a user via a computing device is made. A hash for the document is determined. The hash is encrypted with a private key of the user to create a digital signature. The document, an identification credential, and the digital signature are sent to a recipient computing device residing on a network. The identification credential comprises a digital file used to cryptographically bind a public key to specific trusted hardware attributes attesting to the identity and integrity of the trusted computing device. The trusted computing device includes a cryptographic processor. | 2011-02-03 |
20110029770 | RADIO COMMUNICATION SYSTEM AND AUTHENTICATION PROCESSOR SELECTION METHOD - The present invention applies to a radio communication system that has a subscriber authentication server provided with a plurality of authentication processors and first and second authentication verification apparatuses that carry out each of authentication requests for first and second authentications to the subscriber authentication server for the same subscriber. In this radio communication system, the subscriber authentication server, upon success of the first authentication, reports to the first authentication verification apparatus identification information of the authentication processor that carried out the first authentication, and the first authentication verification apparatus reports to the second authentication verification apparatus the identification information that was reported from the subscriber authentication server. | 2011-02-03 |
20110029771 | Enrollment Agent for Automated Certificate Enrollment - Automated generation of certificates from a Certificate Authority through the use of an Enrollment Agent. Devices needing certificates generate the necessary keys and package public key information with other identifying information about the device and send this information to an Enrollment Agent. The Enrollment Agent takes this information and submits it on behalf of the device to a Certificate Authority, managing the interaction with the Certificate Authority on behalf of the device. The Certificate Authority signs the request, returning a certificate to the Enrollment Agent. The Enrollment Agent packages the certificate along with the other certificates needed to establish a chain of trust and returns these to the device. Certificates may be stored in the device in flash memory. The process is secure as long as the communications path between the devices and the Enrollment Agent is secure; a secure VPN or HTTPS: connection allows the devices and the Enrollment Agent to be in separate locations. | 2011-02-03 |
20110029772 | CLOUD-BASED APPLICATION WHITELISTING - Systems and methods for allowing authorized code to execute on a computer system are provided. According to one embodiment, an in-memory cache is maintained having entries containing execution authorization information regarding recently used modules. After authenticating a module, its execution authorization information is added to the cache. Activity relating to a module is intercepted. A hash value of the module is generated. The module is authenticated with reference to a multi-level whitelist including a global whitelist, a local whitelist and the cache. The authentication includes first consulting the cache and if the module is not found, then looking up its hash value in the local whitelist and if it is not found, then looking it up in the global whitelist. Finally, the module is allowed to be loaded and executed if its hash value matches a hash value of an approved code modules within the global whitelist. | 2011-02-03 |
20110029773 | Optical Network Terminal Management Control Interface-Based Passive Optical Network Security Enhancement - A network component comprising at least one processor coupled to a memory and configured to exchange security information using a plurality of attributes in a management entity (ME) in an optical network unit (ONU) via an ONU management control interface (OMCI) channel, wherein the attributes provide security features for the ONU and an optical line terminal (OLT). Also included is an apparatus comprising an ONU configured to couple to an OLT and comprising an OMCI ME, wherein the OMCI ME comprises a plurality of attributes that support a plurality of security features for transmissions between the ONU and the OLT, and wherein the attributes are communicated via an OMCI channel between the ONU and the OLT and provide the security features for the ONU and the OLT. | 2011-02-03 |
20110029774 | SECURE COMMUNICATION BETWEEN A HARDWARE DEVICE AND A COMPUTER - A group of secret sets is provided, each set including a key and an assigned identifier. The sets are stored in a secure hardware device that can retrieve the key of any of the sets using the key's corresponding identifier. A set is stored in an application, and the application is executed on a computer coupled to the secure device. The application defines a session key, encrypts the session key using the key from the set stored in the application, generates session data including the stored set's identifier and the encrypted session key, and sends the session data to the secure device. The secure device obtains from the session data the encrypted session key and the identifier, retrieves the key corresponding to the identifier, and uses the retrieved key to decrypt the session key. The session key is then used to encrypt and decrypt communications between the secure device and the computer. | 2011-02-03 |
20110029775 | COMMUNICATION CUTOFF DEVICE, SERVER DEVICE AND METHOD - A network monitor device | 2011-02-03 |
20110029776 | WIRELESS PERSONAL AREA NETWORK ACCESS METHOD BASED ON PRIMITIVE - A wireless personal area network access method based on the primitive, includes: a coordinator broadcasts a beacon frame to the device which requests connecting to the wireless personal area network (WPAN), the beacon frame includes the authentication request information for the device and the authentication and a key management tool supported by the coordinator; the device authenticates the authentication request information, when the coordinator has an authentication request to the device, the coordinator and the device execute the authentication based on the primitive and obtains the conversation key. | 2011-02-03 |
20110029777 | BOOTSTRAP OF NFC APPLICATION USING GBA - The present invention provides a bootstrap system comprising a network system and a mobile handset where the mobile handset can easily receive services of NFC bootstrap application. The handset is effectively authenticated after a bootstrap controller in the network verifies whether a user credential derived in the mobile handset and a user credential separately received from a network server are equal. The application setting is sent to a handset from a bootstrap controller via ad-hoc near field communication (NFC) between the mobile handset and the bootstrap controller. Then the user of the mobile handset can receive various services of the NFC application after the network server delivers the user credential to the service devices with NFC interface. | 2011-02-03 |
20110029778 | METHOD FOR DISTRIBUTED IDENTIFICATION, A STATION IN A NETWORK - The present invention relates to a method for identifying and/or, authenticating, and/or authorizing a first radio station in a radio network, comprising the steps of (a) at the first radio station, transmitting to a second radio station a first radio station identifier computed from a set of identity parameters based on the identity of the first radio station, comprising at least one identity parameter, (b) at the first radio station, transmitting at least one identity parameter from the set of identity parameters, (c) at the second radio station, comparing an authentication identifier computed on the basis of the transmitted identity parameter to the first radio station identifier for enabling a subsequent communication between the first and second radio stations. | 2011-02-03 |
20110029779 | INFORMATION PROCESSING APPARATUS, PROGRAM, STORAGE MEDIUM AND INFORMATION PROCESSING SYSTEM - Provided is an information processing apparatus including a reception unit that receives a request for access to an IC chip from an application having access right information for accessing to the IC chip, an acquisition unit that acquires an authentication information for authenticating the application from an external server based on the access right information contained the request for access received by the reception unit, an authentication unit that authenticates the application based on the authentication information obtained by the acquisition unit, and a control unit that controls an access of the application to the IC chip based on an authentication result by the authentication unit. | 2011-02-03 |
20110029780 | Systems and Methods for Conducting Transactions and Communications Using a Trusted Third Party - Systems and methods are provided for managing the transfer of electronic files. In one embodiment, a sender transfers an encrypted version of a file (such as a digitally encoded audio track, movie, document, or the like) to someone who wishes to receive it. The receiver computes a hash of the encrypted file, and sends it to a trusted third party. The trusted third party compares the hash that was computed by the receiver with another hash computed by the sender. If the two hashes match, the third party sends the file decryption key to the receiver. In some embodiments, the receiver may also send the third party payment information so that the sender, the content owner, and/or the third party can be paid for their role in the transaction. In a preferred embodiment, the payment information is only sent to, and/or used by, the third party once the third party has confirmed to the satisfaction of the receiver that the encrypted file in the receiver's possession will decrypt correctly. In some embodiments, the sender computes a hash of the encrypted version of the file and sends it directly to the third party. In other embodiments, the sender encrypts this hash using a key associated with the third party and sends the encrypted hash to the receiver, who then forwards it to the third party. | 2011-02-03 |
20110029781 | SYSTEM, METHOD, AND APPARATUS FOR GRADUATED DIFFICULTY OF HUMAN RESPONSE TESTS - A server to implement human response tests of graduated difficulty can suppress access by spambots. The server includes a network interface and a test controller. The network interface connects the server to a network and facilitates electronic communications between the server and a client computer coupled to the network. The test controller is coupled to the network interface. The test controller implements a human response test with a level of difficulty on the client computer in response to an access request by the client computer. The level of difficulty of the human response test is dependent on a determination whether the access request is deemed to originate from a spambot. | 2011-02-03 |
20110029782 | Handling Expired Passwords - A method of operating a server comprises receiving an authorisation request comprising a password, accessing an expiry date for the password, transmitting a response comprising the expiry date, ascertaining whether the password has expired, and receiving a new password, if the password has expired. Optionally, the transmitted response further comprises a date representing the last use of the password and/or an integer value representing a retry parameter. | 2011-02-03 |
20110029783 | METHOD AND SYSTEM FOR SECURE HARDWARE PROVISIONING - Provisioning a computer related product, comprising manufacturing a product at a product manufacturing entity; maintaining a product control database at product authenticity responsible entity; assigning a first identifier to the product for the purpose of establishing a boot integrity identity of the product, said first identifier being an asymmetric private-public encryption key pair stored in the product control database; storing a copy of the public part of said first identifier (public boot integrity key) in a memory of the product; assigning a second identifier to the product for the purpose of establishing a logistics identity of the product, said second identifier comprising manufacturing information such as a serial number for the product; storing said second identifier indicating the logistics identity in the product control database; assigning a third identifier for the product for the purpose of establishing a production identity of the product, said third identifier being an asymmetric private-public encryption key pair generated by activating an encryption key generator chip provided in the product; extracting and storing a copy of the public part of said third identifier indicating a production identity in the product control database; maintaining the private part of said third identifier indicating a production identity in a storage means of the product. | 2011-02-03 |
20110029784 | METHOD OF PROCESSING DATA PROTECTED AGAINST FAULT INJECTION ATTACKS AND ASSOCIATED DEVICE - A method of cryptographic processing of data (X), in particular a method protected against fault injection attacks, and an associated device. The processing includes at least one transformation ( | 2011-02-03 |
20110029785 | DISK DRIVE DATA ENCRYPTION - Embodiments include methods, apparatus, and systems for storage device data encryption. One method includes encrypting data on a storage device with a key and then transmitting the key to a cryptographic module that encrypts the key to form a Binary Large Object (BLOB). The BLOB is transmitted to an array controller that is coupled to the storage device which stores the BLOB. | 2011-02-03 |
20110029786 | METHOD FOR ACCESSING AND TRANSFERRING DATA LINKED TO AN APPLICATION INSTALLED ON A SECURITY MODULE ASSOCIATED WITH A MOBILE TERMINAL, AND ASSOCIATED SECURITY MODULE, MANAGEMENT SERVER AND SYSTEM - A method is provided for transferring data linked to an application installed on a security module associated with a mobile terminal, the data being stored in a first secure memory area of the security module, suitable for receiving a request to access the data, to read the data, and to transmit or store the data after encryption. A method is also provided for accessing these data suitable for transmitting a request to access, to receive and to decrypt the encrypted data. A security module, a management server, and a system implementing the transfer and access methods are also provided. | 2011-02-03 |
20110029787 | METHODS AND APPARATUS FOR POWER ALLOCATION IN A STORAGE SYSTEM - Methods and systems for improved management of power allocation among a plurality of devices coupled to a controller. The controller and devices exchange messages to request, grant, and release allocations of power from a common power supply. In some embodiments, the controller may be a SAS/SATA controller and the messages exchanged may be SAS/SATA frames and/or primitives. In exemplary embodiments, the messages may request/grant a particular amount of power for each of one or more voltage levels provided by the power supply. In other exemplary embodiments, the messages may designate the duration of time during which the requesting device may utilize the allocated power. A power status message from the device to the controller may indicate a change in the power consumption by the device. Responsive to the power status message the controller may re-allocate power previously allocated to a device that has completed use thereof. | 2011-02-03 |
20110029788 | Power Limiting In Redundant Power Supply Systems - A redundant power supply system includes power limit logic and plural power supplies. The power limit logic is configured to impose a first power limit threshold on the power supply system during a first time period in which one or more of the plural power supplies is being enabled, and a second power limit threshold higher than the first power limit threshold during a second time period. | 2011-02-03 |
20110029789 | POWER MANAGING SYSTEM - A power managing system includes a power supply, a first converter, a second converter, and a complex programmable logic device. The power supply outputs a first verification signal and a first power upon the condition that the power supply receives a power supply on signal from a motherboard. The first and second converters convert the first power to a second power, a third power, and output a second verification signal, a third verification signal respectively. The complex programmable logic device outputs an enable signal to the motherboard to make the motherboard receive the first, the second, and the third powers upon the condition that the complex programmable logic device receives the first, the second, and the third verification signals. | 2011-02-03 |
20110029790 | System and Method for Policing Bad Powered Devices in Power Over Ethernet - A system and method for policing bad powered devices in power over Ethernet. Degradation of components within powered devices can lead to noise and ripple that exceed specified thresholds. This noise and ripple can adversely impact the operation of the power sourcing equipment. A noise detector implemented in the power sourcing equipment can detect the presence of such noise and ripple and modify the application of power to the particular port. | 2011-02-03 |
20110029791 | POWER SUPPLY CIRCUIT FOR VIDEO CARD CHIPSET - A power supply circuit is capable of providing power to a video card chipset. The video card chipset includes a first power supply pin and a second power supply pin. The power supply circuit includes a power input, a first filtering circuit, and a second filtering circuit. The first filtering circuit is connected between the power source and the first power supply pin to filter the power provided to first power supply pin of the video card chipset. The second filtering circuit is connected between the power source and the second power supply pin to filter the power provided to second power supply pin of the video card chipset. | 2011-02-03 |
20110029792 | INFORMATION PROCESSING APPARATUS AND POWER SUPPLYING CONTROL METHOD - According to one embodiment, an information processing apparatus which supplies power to a communication partner device, includes: a communication module which performs communication with the communication partner device; a power supplying module which supplies power to the communication partner device using a power supply for driving the information processing apparatus; a power supplying determination module which determines whether the power supplying module supply power or not; and a device identification module which determines whether the communication partner device has a function to be charged by the power supplying module. The power supplying determination module drives the power supplying module using the power supply when the device identification module determines that the communication partner device has a to-be-charged function, while the power supplying determination module does not drive the power supplying module when the device identification module determines that the communication partner device does not have the to-be-charged function. | 2011-02-03 |
20110029793 | GENERATING A SIGNAL TO REDUCE COMPUTER SYSTEM POWER CONSUMPTION FROM SIGNALS PROVIDED BY A PLURALITY OF POWER SUPPLIES - A signal suitable for signaling a computer system to reduce power consumption is generated from a plurality of power supplies. The signal is asserted when at least one of the power supplies of the plurality of power supplies signals impairment, and at least one of the power supplies of the plurality of power supplies signals that the power supply is supplying current above a threshold level. | 2011-02-03 |
20110029794 | POWER SUPPLY CIRCUIT FOR AUDIO CODEC CHIP AND METHOD FOR PROVIDING POWER SUPPLY TO AUDIO CODEC CHIP - A power supply circuit is provided. The power supply circuit includes an audio codec chip and a voltage absorbing circuit. The audio codec chip has a power input terminal. The power input terminal is connected to a power source terminal. The voltage absorbing circuit is connected between the power source terminal and the power input terminal of the audio codec chip so as to decrease a divided voltage accomplished with a voltage from the power source terminal to low level. A method configured for starting up an audio codec chip on a computer motherboard in a normal manner is also provided. | 2011-02-03 |
20110029795 | DEVICE FOR POWERING AN ELECTRONIC CIRCUIT, IN PARTICULAR A DIGITAL CIRCUIT, AND ASSOCIATED METHOD - A device for powering an electronic circuit that applies at least a first voltage or a second voltage, different from the first voltage, to the electronic circuit. The device includes a performance monitor that receives an item of information defining a constraint and determines a first duration and a second duration, such that the operation of the electronic circuit at a first frequency associated with the first voltage for the first duration, and at a second frequency associated with the second voltage for the second duration, complies with the constraint. The device applies the first voltage and the first frequency to the circuit for the first duration and the second voltage and the second frequency for the second duration. | 2011-02-03 |
20110029796 | System and Method for Adjusting an Energy Efficient Ethernet Control Policy Using Measured Power Savings - A system and method for adjusting an energy efficient Ethernet (EEE) control policy using measured power savings. An EEE-enabled device can be designed to report EEE event data. This reported EEE event data can be used to quantify the actual EEE benefits of the EEE-enabled device, debug the EEE-enabled device, and adjust the EEE control policy. | 2011-02-03 |
20110029797 | MANAGING MEMORY POWER USAGE - Methods of method of managing memory power usage in a computing device having two or more memory modules. By monitoring a system working set size of the computing device, a determination can be made if all active memory modules are needed for the system working set size. If not all active memory modules are needed for the system working set size, one or more of the active memory modules can be selected for power down. By evacuating data from the selected one or more memory modules, placing the evacuated one or more memory modules in a power-down state, and removing the powered-down memory modules from the active memory of the computing device, memory power usage can be reduced. | 2011-02-03 |
20110029798 | Power Consumption Monitor and Method Therefor - A power supply unit of an information handling system determines that a power consumption module of the information handling system is available. If the power consumption module is available, the power supply unit measures input power of the power supply unit and provides a representation of the input power to the power consumption module in response to receiving a power measurement request from the power consumption module. If the power supply unit determines that the power consumption module is not available, the power supply unit measures input power of the power supply unit and stores a representation of the input power at the power supply unit independent of a power measurement request from the power consumption module. | 2011-02-03 |
20110029799 | Power management system and method - A power management system comprises a power management module configured to receive a requested duration for powering an electronic device by a battery, the power management module configured to control use of power-consuming elements of the electronic device based on a prioritization of the power-consuming elements to enable powering of the electronic device by the battery for at least the requested duration. | 2011-02-03 |
20110029800 | System and Method for Pre-Detection in a Power Over Ethernet System - A system and method for pre-detection in a power over Ethernet (PoE) system. A power sourcing equipment (PSE) is designed to measure a port voltage upon application of a small current source. A microcontroller controls the current source based on a comparison of the measured port voltage to a threshold voltage. | 2011-02-03 |
20110029801 | Method and System for Balancing Receive-Side Supply Load - Described are digital communication systems that transmit and receive parallel sets of data symbols. Differences between successive sets of symbols induce changes in the current used to express the symbol sets, and thus introduce supply ripple. A receiver adds compensation current to reduce supply ripple. The compensation current is calculated based upon prior data samples rather than the current symbols, and consequently increases the maximum instantaneous current fluctuations between adjacent symbol sets as compared with circuits that do not include the compensation. The frequency response of the power-distribution network filters out the increased data dependence of the local supply current, however, and consequently reduces the fluctuations of total supply current. Some embodiments provide compensation currents for both transmitted and received symbols. | 2011-02-03 |
20110029802 | INFORMATION PROCESSING SYSTEM - An information processing device having low power consumption without affecting interruption request response speed. The device specifies a waiting time until execution of a given event and makes a system call and includes a first timer circuit for a first cycle; a second timer circuit for a second cycle shorter than the first cycle; a timeout supervisor which stores the waiting time; and a first cycle supervisor which stores waiting time until the next interruption request. The timeout supervisor stores the time calculated by subtraction of the waiting time stored in the first cycle supervisor from that in the timeout supervisor upon an interruption request from the first timer; and if the waiting time stored in the timeout supervisor is shorter than the first cycle, the second cycle time is subtracted from the time stored in the timeout supervisor upon an interruption request from the second timer circuit. | 2011-02-03 |
20110029803 | CLOCK RECOVERY OF SERIAL DATA SIGNAL - A method and a receiver for recovering clock timing information from a serial data signal by determining data symbol transition times. The method comprises determining data symbol transition times of the serial data according to a first determination scheme, and further data symbol transition times of the serial data according to a second determination scheme. The transition times are then combined by a voting process, wherein the first determination scheme votes for the transition times that it determined, and wherein the second determination scheme votes for the transition times that it determined. The actual transition times are then determined as being the times that have the most votes. | 2011-02-03 |
20110029804 | FLEET MISSION MANAGEMENT SYSTEM AND METHOD USING HEALTH CAPABILITY DETERMINATION - A system and method are provided for planning and controlling a plurality of machines. A mission is assigned to each machine of the plurality of machines. A plurality of system capabilities is computed in each machine and, from the plurality of computed system capabilities, a machine mission capability is computed for each machine. The mission of one or more of the machines may be selectively reassigned based on the computed machine mission capability of each machine. | 2011-02-03 |
20110029805 | REPAIRING PORTABLE EXECUTABLE FILES - A portable executable file can be repaired by identifying an invalid field of a portable executable file. A likelihood of repairing the invalid field of the portable executable file is determined. A repair model for repairing the invalid field of the portable executable file is generated, and the invalid field of the portable executable file is repaired based upon, at least in part, the repair model. | 2011-02-03 |
20110029806 | METHOD, DEVICE AND COMMUNICATION SYSTEM TO AVOID LOOPS IN AN ETHERNET RING SYSTEM WITH AN UNDERLAYING 802.3ad NETWORK - A method is provided to be run in a network, the network comprising several network elements that are connected via a ring, wherein one of the network element is a ring master comprising a primary port and a secondary port. The method comprises the steps of (i) a failure is detected by the ring master; and (ii) the ring master checks for a second message and based on the content of the second message unblocks the secondary port. Also an associated device as well as a communication system comprising such device are provided. | 2011-02-03 |
20110029807 | IMPLEMENTING ENHANCED MEMORY RELIABILITY USING MEMORY SCRUB OPERATIONS - A method and circuit for implementing enhanced memory reliability using memory scrub operations to determine a frequency of intermittent correctable errors, and a design structure on which the subject circuit resides are provided. A memory scrub for intermittent performs at least two reads before moving to a next memory scrub address. A number of intermittent errors is tracked where an intermittent error is identified, responsive to identifying one failing read and one passing read of the at least two reads. | 2011-02-03 |
20110029808 | SYSTEM AND METHOD OF WEAR-LEVELING IN FLASH STORAGE - A flash storage device tracks performs wear-leveling by tracking data errors that occur when dynamic data is read from a storage block of the flash storage device and moving the dynamic data to an available storage block of the flash storage device. Additionally, the flash storage device identifies a storage block containing static data and moves the static data to the storage block previously containing the dynamic data. | 2011-02-03 |
20110029809 | METHOD AND APPARATUS FOR DISTRIBUTED STORAGE INTEGRITY PROCESSING - A distributed storage integrity system in a dispersed storage network includes a scanning agent and a control unit. The scanning agent identifies an encoded data slice that requires rebuilding, wherein the encoded data slice is one of a plurality of encoded data slices generated from a data segment using an error encoding dispersal function. The control unit retrieves at least a number T of encoded data slices needed to reconstruct the data segment based on the error encoding dispersal function. The control unit is operable to reconstruct the data segment from at least the number T of the encoded data slices and generate a rebuilt encoded data slice from the reconstructed data segment. The scanning agent is located in a storage unit and the control unit is located in the storage unit or in a storage integrity processing unit, a dispersed storage processing unit or a dispersed storage managing unit. | 2011-02-03 |
20110029810 | AUTOMATED FAILURE RECOVERY OF SUBSYSTEMS IN A MANAGEMENT SYSTEM - Systems and methods for automated failure recovery of subsystems of a management system are described. The subsystems are built and modeled as services, and their management, specifically their failure recovery, is done in a manner similar to that of services and resources managed by the management system. The management system consists of a microkernel, service managers, and management services. Each service, whether a managed service or a management service, is managed by a service manager. The service manager itself is a service and so is in turn managed by the microkernel. Both managed services and management services are monitored via in-band and out-of-band mechanisms, and the performance metrics and alerts are transported through an event system to the appropriate service manager. If a service fails, the service manager takes policy-based remedial steps including, for example, restarting the failed service. | 2011-02-03 |
20110029811 | SYSTEM AND METHOD FOR SUPPORTING COMPENSATION WORK - A method for supporting compensation work comprises the steps of associating a data structure with a compensation function, and associating the data structure with the at least one event that can be encountered during execution of a forward work. The data structure contains a pair of pointers, which includes a first pointer to a code to be executed for the compensation function, and a second pointer to a stack frame of a closest lexically enclosing scope of a declaration of the compensation function in a computer program text. | 2011-02-03 |
20110029812 | METHOD AND SYSTEM FOR RECOVERING SIP TRANSACTION - A method and system for recovering a SIP transaction. The method including monitoring an event related to transaction change; recording information related to the event; and regenerating a transaction by use of the recorded information upon failover. A system is also provided to carry out the steps of the method. Through the present invention, a transaction may be regenerated upon occurrence of failure during the transaction period, thereby enabling transaction-level failover and noticeably reducing the information load needed to recorded compared with the prior art. The present invention not only improves reliability of a SIP-based service but also requires less overhead for transaction recovery. | 2011-02-03 |
20110029813 | CIRCUITS AND METHODS FOR PROCESSING MEMORY REDUNDANCY DATA - An interface processes memory redundancy data on an application specific integrated circuit (ASIC) with self-repairing random access memory (RAM) devices. The interface includes a state machine, a counter, and an array of registers. The state machine is coupled to a redundancy chain. The redundancy chain includes coupled redundant elements of respective memory elements on the ASIC. In a shift-in mode, the interface shifts data from each of the elements in the redundancy chain and compresses the data in the array of registers. The interface communicates with a test access port coupled to one or more eFuse devices to store and retrieve the compressed data. In a shift-out mode, the interface decompresses the data stored in the array of registers and shifts the decompressed data to each unit in the redundancy chain. The interface functions absent knowledge of the number, bit size and type of self-repairing RAM devices in the redundancy chain. | 2011-02-03 |
20110029814 | TEST SYSTEM AND TEST METHOD THEREOF - A test system and a test method thereof. The test system includes an electronic device and a test device. The electronic device includes a plurality of output interfaces and provides a corresponding test signal via the output interfaces according to a group of operation commands. The test device includes a transforming unit, a multiplexer unit, a processor unit and a plurality of test interfaces which are respectively coupled to the output interfaces. The transforming unit transforms the test signals received via the test interfaces. The multiplexer unit selects the transformed test signals. The processor unit controls the multiplexer unit to select one of the transformed test signals, and determines whether the transformed test signal being selected conforms a predetermine condition for generating a test result signal. The processor unit controls the communication unit to transmit the test result signal to the electronic device according to the test result signal. | 2011-02-03 |
20110029815 | Electronic Device and Method for Operating the Electronic Device - The invention describes an electronic device and a method for operating the electronic device. The electronic device includes one or more circuit components. The electronic device further includes one or more fuses and one or more non-volatile memories to disable the access of at least one of the one or more circuit components. Each of the one or more non-volatile memories includes one or more firmware, which are used to program at least one bit to manage the access of the at least one circuit component. The method includes performing a power-up sequence in a power cycle for the electronic device. The method further includes determining a state of circuit and a state of a bit for selectively enabling a test function. | 2011-02-03 |
20110029816 | PERSONAL COMPUTER DIAGNOSTIC TEST BEFORE EXECUTING OPERATING SYSTEM - A personal computer component diagnostic method is executed to recognize the status or potential problems of a computer before executing an operating system. The personal computer component diagnostic method comprising: calling a BIOS program; executing a component basic diagnostic program; and executing a component functional test after executing a predetermined step. The component functional test includes a CPU MSR/MTRR test, a hard disk S.M.A.R.T. test, a boot path test and a PCI device scanning test. | 2011-02-03 |
20110029817 | ABNORMALITY DETECTION METHOD, DEVICE AND PROGRAM - Model data is generated from performance information sorted by day of the week, time period, and process status by a performance information analysis section and a process status analysis section. An abnormality determination section detects abnormality using appropriate model data. What the graph of an expected status is like, how much the graph of the current status that has been determined abnormal differs from the graph of the expected status, and how much the current status is like the expected status are displayed allowing a system manager to observe detailed information about abnormality determination. | 2011-02-03 |
20110029818 | INFORMATION PROCESSING DEVICE - An information processing device may comprise a log file creating unit and a first storage controlling unit. The log file creating unit may be configured to create, each time information is input, one log file that includes log information indicating an input of the information. The storage controlling unit may be configured to store, each time the one log file is created, the one log file in a storage area. | 2011-02-03 |
20110029819 | SYSTEM AND METHOD FOR PROVIDING PROGRAM TRACKING INFORMATION - There is provided a system and method of providing program tracking information. An exemplary method comprises compiling a program into a plurality of instruction bundles. The exemplary method also comprises placing an instruction to store program tracking information in a local path table or a global path table into at least one of the plurality of instruction bundles. | 2011-02-03 |
20110029820 | NATIVE CODE MODULE SECURITY FOR 64-BIT INSTRUCTION SET ARCHITECTURES - Some embodiments provide a system that executes a native code module. During operation, the system obtains the native code module. Next, the system loads the native code module into a secure runtime environment. Finally, the system safely executes the native code module in the secure runtime environment by using a set of software fault isolation (SFI) mechanisms that maintain control flow integrity for the native code module and constrain store instructions in the native code module by bounding a valid memory region of the native code module with one or more guard regions. | 2011-02-03 |