| 05th week of 2011 patent applcation highlights part 44 |
| Patent application number | Title | Published |
|---|
| 20110027916 | DETECTION APPARATUS FOR DETECTING PARTICLES - The invention relates to a detection apparatus for detecting particles ( | 2011-02-03 |
| 20110027917 | MANUFACTURING METHOD OF SEMICONDUCTOR DEVICE - To provide a manufacturing method of a semiconductor device capable of placing a larger number of alignment marks for lithography and PCM and at the same time, preventing information leakage from the PCM. In a portion of a first scribe region sandwiched between first semiconductor chip regions, a first region and a second region are placed in parallel to each other. The first region is equipped with at least one monitor selected from a first monitor for electrically evaluating at least either one of an active element (such as transistor) and a passive element (such as resistor or capacitor), a second monitor for dimensional control, and a third monitor for measuring film thickness. In the second region, an alignment mark for lithography is placed. In the cutting step, the first region is cut off. | 2011-02-03 |
| 20110027918 | INSPECTION METHOD AND MANUFACTURING METHOD OF LIGHT-EMITTING DEVICE - In a light-emitting element provided with a thick layer of a plurality of EL layers which are partitioned by a charge generation layer between a pair of electrodes, a portion which a conductive foreign substance enters between the pair of electrodes emits stronger light at a voltage lower than a voltage required when a normal portion starts emitting light. In a light-emitting element provided with a plurality of EL layers which are partitioned by a charge generation layer between a pair of electrodes, a voltage may be applied thereto in the forward direction. Then, an abnormal light-emission portion may be detected because the portion emits light at a luminance of 1 (cd/m | 2011-02-03 |
| 20110027919 | Measurement and control of strained devices - A method that includes measuring stress on at least one of a monitor substrate, a production substrate, and a proxy device on a production substrate to produce stress data, measuring shape on at least one of a proxy device on a production substrate and a production device on a production substrate to produce shape data, and inputting the stress data and the shape data into an elastic deformation calculation to determine a stress value for a production device. | 2011-02-03 |
| 20110027920 | LIGHT EMITTING DEVICE AND METHOD FOR MANUFACTURING THE SAME - An object of the present invention is to realize a light emitting device having low power consumption and high stability, in addition to improve extraction efficiency of light generated in a light emitting element. At least an interlayer insulating film (including a planarizing film), an anode, and a bank covering an edge portion of the anode contain chemically and physically stable silicon oxide, or are made of a material containing silicon oxide as its main component in order to accomplish a light emitting device having high stability. Generation of heat in a light emitting panel can be suppressed in addition to increase in efficiency (luminance/current) of a light emitting panel according to the structure of the present invention. Consequently, synergistic effect on reliability of a light emitting device is obtained. | 2011-02-03 |
| 20110027921 | METHOD FOR MANUFACTURING SEMICONDUCTOR LIGHT EMITTING DEVICE - According to one embodiment, a method for manufacturing a semiconductor light emitting device includes forming a separation groove on a major surface of a substrate. A semiconductor layer including a light emitting layer is formed on the substrate. The separation groove separates the semiconductor layer into a plurality of elements. The method includes forming an insulating film on the major surface of the substrate. The insulating film covers the semiconductor layer and a bottom surface of the separation groove provided on the substrate. The method includes separating the substrate from the semiconductor layer by irradiating the semiconductor layer with laser light from an surface of the substrate opposite to the major surface. An edge portion of irradiation area of the laser light is positioned near an edge portion of the semiconductor layer neighboring the separation groove. | 2011-02-03 |
| 20110027922 | SEMICONDUCTOR LIGHT EMITTING DEVICE MANUFACTURE METHOD - A semiconductor light emitting device manufacture method is provided which can manufacture a semiconductor light emitting device of high quality. A first substrate of an n-type ZnO substrate is prepared. A lamination structure including an optical emission layer made of ZnO based compound semiconductor is formed on the first substrate. A p-side conductive layer is formed on the lamination structure. A first eutectic material layer made of eutectic material is formed on the p-side conductive layer. A second eutectic material layer made of eutectic material is formed on a second substrate. The first and second eutectic material layers are eutectic-bonded to couple the first and second substrates. After the first substrate is optionally thinned, an n-side electrode is formed on a partial surface of the first substrate. | 2011-02-03 |
| 20110027923 | ORGANIC LIGHT EMITTING DEVICE AND MANUFACTURING METHOD THEREOF - An organic light emitting device and a manufacturing method thereof are provided. The organic light emitting device includes a first display substrate, a second display substrate, and a first adhesive force improving member. The first display substrate includes a first substrate, a first electrode, organic light emitting patterns, a first spacer, and a second electrode. The first electrode is formed on an entire surface of the first substrate, and the organic light emitting patterns are disposed on the first electrode. The first spacer corresponds to the organic light emitting pattern and is disposed on the first electrode. The second electrode covers the organic light emitting patterns and the first spacer. The second display substrate includes a second substrate, and a first driving signal delivery part. The first adhesive force improving member electrically/physically couples the second electrode to the first driving signal delivery part. | 2011-02-03 |
| 20110027924 | SURFACE EMITTING LASER, METHOD FOR MANUFACTURING SURFACE EMITTING LASER, AND IMAGE FORMING APPARATUS - A surface emitting laser includes a lower multilayer mirror and an upper multilayer mirror which are provided on a substrate. A first oxidizable layer is partially oxidized to form a first current confinement layer including a first conductive region and a first insulating region. A second oxidizable layer is partially oxidized to form a second current confinement layer including a second conductive region and a second insulating region, a boundary between the first conductive region and the first insulating region being disposed inside the second current confinement layer in an in-plane direction of the substrate. The first oxidizable layer and the second oxidizable layer or layers adjacent to the respective oxidizable layers are adjusted so that when both layers are oxidized under the same oxidizing conditions, the oxidation rate of the first oxidizable layer is lower than that of the second oxidizable layer. | 2011-02-03 |
| 20110027925 | SURFACE EMITTING LASER, METHOD FOR PRODUCING SURFACE EMITTING LASER, AND IMAGE FORMING APPARATUS - A surface emitting laser includes a lower multilayer mirror, an active layer, and an upper multilayer mirror stacked onto a substrate. A first current confinement layer having a first electrically conductive region and a first insulating region is formed above or below the active layer using a first trench structure. A second current confinement layer having a second electrically conductive region and a second insulating region is formed above or below the first current confinement layer using a second trench structure. The first and second trench structures extend from a top surface of the upper multilayer mirror towards the substrate such that the second trench structure surrounds the first trench structure. When the surface emitting laser is viewed in an in-plane direction of the substrate, a boundary between the first electrically conductive region and the first insulating region is disposed inside the second electrically conductive region. | 2011-02-03 |
| 20110027926 | Optical semiconductor device having diffraction grating disposed on both sides of waveguide and its manufacture method - An active layer ( | 2011-02-03 |
| 20110027927 | LIGHT-EMITTING DIODE CUTTING METHOD AND PRODUCT THEREOF - A light-emitting diode (LED) cutting method includes the following steps: (A) positioning and retaining an LED chip or an LED epitaxial substrate on a chip retainer; (B) introducing a liquid medium to serve as a sound wave reflection layer medium between a cutting tool and the chip; (C) activating a power source to drive a magnetostrictive or piezoelectric ceramic material mounted on a machine to serve as a power source by inducing volume expansion/compression that generates up-and-down piston-like movement; and (D) operating the cutting tool of a proper shape that has a surface on which super hard micro-particles of diamond, CBN, or SiC are electroformed to carry out up-and-down piston-like reciprocal motion on the material retained on the chip retainer to drive the super hard micro-particles on the surface of the cutting tool into a pre-cut workpiece to perform breaking cutting. | 2011-02-03 |
| 20110027928 | PULSED LASER DEPOSITION OF HIGH QUALITY PHOTOLUMINESCENT GaN FILMS - High quality GaN films exhibiting strong room temperature blue photoluminescence with negligible impurity emissions are grown by a Pulsed Laser Deposition process in which process parameters are controlled to attain plasma particle energy of a target material plume directed from the target on the substrate structure below 5 eV at the deposition surface. Among the process parameters, a distance between the deposition surface and the target, a pressure level of the reaction gas in the processing chamber, and an energy density of the pulsed laser beam directed to the target are controlled, in combination, to attain the required low plasma particle energy of the plume below 5 eV in vicinity of the deposition surface. | 2011-02-03 |
| 20110027929 | METHOD OF FABRICATING MICRO-ELECTROMECHANICAL SYSTEM MICROPHONE STRUCTURE - A method of fabricating a micro-electromechanical system microphone structure is disclosed. First, a substrate defining a MEMS region and a logic region is provided, and a surface of the substrate has a dielectric layer thereon. Next, at least one metal interconnect layer is formed on the dielectric layer in the logic region, and at least one micro-machined metal mesh is simultaneously formed in the dielectric layer of the MEMS region. Therefore, the thickness of the MEMS microphone structure can be effectively reduced. | 2011-02-03 |
| 20110027930 | Low Temperature Wafer Level Processing for MEMS Devices - Microelectromechanical systems (MEMS) are small integrated devices or systems that combine electrical and mechanical components. It would be beneficial for such MEMS devices to be integrated with silicon CMOS electronics and packaged in controlled environments and support industry standard mounting interconnections such as solder bump through the provisioning of through-wafer via-based electrical interconnections. However, the fragile nature of the MEMS devices, the requirement for vacuum, hermetic sealing, and stresses placed on metallization membranes are not present in packaging conventional CMOS electronics. Accordingly there is provided a means of reinforcing the through-wafer vias for such integrated MEMS-CMOS circuits by in filling a predetermined portion of the through-wafer electrical vias with low temperature deposited ceramic materials which are deposited at temperatures below 350° C., and potentially to below 250° C., thereby allowing the re-inforcing ceramic to be deposited after fabrication of the CMOS electronics. | 2011-02-03 |
| 20110027931 | Method for making solar cells with sensitized quantum dots in the form of nanometer metal particles - There is disclosed a method for making solar cells with sensitized quantum dots in the form of nanometer metal crystals. Firstly, a first substrate is provided. Then, a silicon-based film is grown on a side of the first substrate. A pattern mask process is executed to etch areas of the silicon-based film. Nanometer metal particles are provided on areas of the first substrate exposed from the silicon-based film. A metal electrode is attached to an opposite side of the first substrate. A second substrate is provided. A transparent conductive film is grown on the second substrate. A metal catalytic film is grown on the transparent conductive film. The second substrate, the transparent conductive film and the metal catalytic film together form a laminate. The laminate is inverted and provided on the first substrate. Finally, electrolyte is provided between the first substrate and the metal catalytic film. | 2011-02-03 |
| 20110027932 | SOLID-STATE IMAGE PICKUP DEVICE AND METHOD FOR PRODUCING THE SAME - A solid-state image pickup device includes an element isolation insulating film electrically isolating pixels on the surface of a well region; a first isolation diffusion layer electrically isolating the pixels under the element isolation insulating film; and a second isolation diffusion layer electrically isolating the pixels under the first isolation diffusion layer, wherein a charge accumulation region is disposed in the well region surrounded by the first and second isolation diffusion layers, the inner peripheral part of the first isolation diffusion layer forms a projecting region, an impurity having a conductivity type of the first isolation diffusion layer and an impurity having a conductivity type of the charge accumulation region are mixed in the projecting region, and a part of the charge accumulation region between the charge accumulation region and the second isolation diffusion layer is abutted or close to the second isolation diffusion layer under the projecting region. | 2011-02-03 |
| 20110027933 | METHOD OF TEXTURING SOLAR CELL AND METHOD OF MANUFACTURING SOLAR CELL - Methods of texturing and manufacturing a solar cell are provided. The method of texturing the solar includes texturing a surface of a substrate of the solar cell using a wet etchant, and the wet etchant includes a surfactant. | 2011-02-03 |
| 20110027934 | PHOTOELECTRIC CONVERSION APPARATUS AND IMAGE PICKUP SYSTEM USING PHOTOELECTRIC CONVERSION APPARATUS - A photoelectric conversion apparatus includes: a first interlayer insulation film disposed on a semiconductor substrate; a first plug disposed in a first hole in the first interlayer insulation film, and serving to electrically connect between a plurality of active regions disposed in the semiconductor substrate, between gate electrodes of a plurality of MOS transistors, or between the active region and the gate electrode of the MOS transistor, not through the wiring of the wiring layer; and a second plug disposed in a second hole in the first interlayer insulation film, the second plug being electrically connected to the active region, wherein a wiring arranged over the second plug and closest to the second plug is electrically connected to the second plug, and the wiring electrically connected to the second plug forms a portion of dual damascene structure. By such a structure, incidence efficiency of light onto a photoelectric conversion element can be improved. | 2011-02-03 |
| 20110027935 | Method for making a full-spectrum solar cell with an anti-reflection layer doped with silicon quantum dots - In a method for making a full-spectrum solar cell, there is provided an ordinary solar cell with an anti-reflection layer. The anti-reflection layer is coated with a film of silicon nitride and/or silicon oxide. The silicon/nitrogen ratio and/or the silicon/oxygen ratio and the temperature are regulated, thus forming a silicon-rich film via doping the anti-reflection layer with silicon from the film of silicon nitride and/or silicon oxide. The precipitation of the silicon in the silicon-rich film is executed based on a mechanism of phase separation, thus forming silicon quantum dots of various sizes in the anti-reflection layer. | 2011-02-03 |
| 20110027936 | LIGHT GUIDE ARRAY FOR AN IMAGE SENSOR - An image sensor pixel that includes a photoelectric conversion unit supported by a substrate and an insulator adjacent to the substrate. The pixel includes a cascaded light guide that is located within an opening of the insulator and extends above the insulator such that a portion of the cascaded light guide has an air interface. The air interface improves the internal reflection of the cascaded light guide. The cascaded light guide may include a self-aligned color filter having air-gaps between adjacent color filters. These characteristics of the light guide eliminate the need for a microlens. Additionally, an anti-reflection stack is interposed between the substrate and the light guide to reduce backward reflection from the image sensor. Two pixels of having different color filters may have a difference in the thickness of an anti-reflection film within the anti-reflection stack. | 2011-02-03 |
| 20110027937 | METHODS OF FORMING PHOTOVOLTAIC DEVICES - A template for growth of an anticipated semiconductor film has a deformation textured substrate. The template also has an intermediate epitaxial film coupled to the deformation textured substrate, the intermediate epitaxial film being chemically compatible and substantially lattice matched with the anticipated semiconductor film. A method of manufacturing a template for the growth of an anticipated semiconductor is also disclosed. A substrate is deformed to produce a textured surface. An intermediate epitaxial film, chemically compatible and substantially lattice matched with the anticipated semiconductor film, is deposited. A further disclosed photovoltaic device has a semiconductor layer, a deformation textured substrate, and an intermediate epitaxial film coupled to the deformation textured substrate. The intermediate epitaxial film is chemically compatible and substantially lattice matched with the semiconductor layer. The semiconductor layer is epitaxially grown on the intermediate epitaxial film. | 2011-02-03 |
| 20110027938 | METHOD OF FABRICATING THIN FILM SOLAR CELL AND APPARATUS FOR FABRICATING THIN FILM SOLAR CELL - Disclosed is a method of fabricating a thin film solar cell including introducing a reaction solution into a reaction chamber, fixing a supporter onto a loader, disposing the loader in the reaction chamber to immerse the supporter into the reaction solution, and heating the supporter and coating a buffer layer. In addition, an apparatus of fabricating a thin film solar cell including a reaction chamber mounted with an inlet of a reaction solution and an outlet of waste water, and a loader disposed in the reaction chamber and being capable of moving up and down, is disclosed. | 2011-02-03 |
| 20110027939 | Methods of Forming Variable Resistance Memory Cells, and Methods of Etching Germanium, Antimony, and Tellurium-Comprising Materials - A method of etching a material that includes comprising germanium, antimony, and tellurium encompasses exposing said material to a plasma-enhanced etching chemistry comprising Cl | 2011-02-03 |
| 20110027940 | Method for fabricating copper-containing ternary and quaternary chalcogenide thin films - An apparatus for depositing a solid film onto a substrate from a reagent solution includes reservoirs of reagent solutions maintained at a sufficiently low temperature to inhibit homogeneous reactions within the reagent solutions. The chilled solutions are dispensed through showerheads, one at a time, onto a substrate. One of the showerheads includes a nebulizer so that the reagent solution is delivered as a fine mist, whereas the other showerhead delivers reagent as a flowing stream. A heater disposed beneath the substrate maintains the substrate at an elevated temperature at which the deposition of a desired solid phase from the reagent solutions may be initiated. Each reagent solution contains at least one metal and either S or Se, or both. At least one of the reagent solutions contains Cu. The apparatus and its associated method of use are particularly suited to forming films of Cu-containing compound semiconductors. | 2011-02-03 |
| 20110027941 | METHOD OF FORMING MONOLITHIC CMOS-MEMS HYBRID INTEGRATED, PACKAGED STRUCTURES - A method of forming Monolithic CMOS-MEMS hybrid integrated, packaged structures includes the steps of providing: providing a semiconductor substrate with pre-fabricated cmos circuits on the front side and a polished back-side with through substrate conductive vias; forming at least one opening in the polished backside of the semiconductor substrate by appropriately protecting the front-side; applying at least one filler material in the at least one opening on the semiconductor substrate; positioning at least one prefabricated mems, nems or cmos chip on the filler material, the chip including a front face and a bare back face with the prefabricated mems/nems chips containing mechanical and dielectric layers; applying at least one planarization layer overlying the substrate, filler material and the chip; forming at least one via opening on a portion of the planarization layer interfacing pads on the chip and the through substrate conductive vias; applying at least one metallization layer overlying the planarization layer on the substrate and the chip connecting the through substrate conductive vias to the at least one chip; applying at least one second insulating layer overlying the metallization layer; performing at least one micro/nano fabrication etching step to release the mechanical layer on the prefabricated mems/nems chips; positioning protective cap to package the integrated device over the mems/nems device area on the pre-fabricated chips. | 2011-02-03 |
| 20110027942 | SEMICONDUCTOR PACKAGE - A semiconductor package is disclosed. One embodiment provides a semiconductor package singulated from a wafer includes a chip defining an active surface, a back side opposite the active surface, and peripheral sides extending between the active surface and the back side; a contact pad disposed on the active surface; and a metallization layer extending from the contact pad onto a portion of the peripheral sides of the chip. | 2011-02-03 |
| 20110027943 | Stud Bumps as Local Heat Sinks During Transient Power Operations - A thermal management configuration for a flip chip semiconductor device is disclosed. The device includes a high power silicon based die having a metal bonding surface. A plurality of interconnects are formed on the metal surface and connected to a substrate. A plurality of thermal management stud bumps are formed on the metal bonding surface, the thermal management stud bumps positioned distinct from the interconnects and local to die hot spots, exposed ends of the thermal management stud bumps spaced from the substrate. | 2011-02-03 |
| 20110027944 | METHOD OF FORMING ELECTRICAL CONNECTIONS - A method of forming electrical connections to a semiconductor wafer. A semiconductor wafer comprising an insulation layer is provided. The insulation layer has a surface. A patterned mask layer is formed over the surface of the insulation layer. The patterned mask layer exposes portions of the surface of the insulation layer through a plurality of holes. The portions of the plurality of holes are filled with a metal material comprising copper to form elongated columns of the metal material. The elongated columns of the metal material have a sidewall surface. The patterned mask layer is removed to expose the sidewall surface of the elongated columns of the metal material. A protection layer is formed on the exposed sidewall surface of the elongated columns of the metal material. | 2011-02-03 |
| 20110027945 | SUBSTRATE FOR MOUNTING DEVICE AND METHOD FOR PRODUCING THE SAME, SEMICONDUCTOR MODULE AND METHOD FOR PRODUCING THE SAME, AND PORTABLE APPARATUS PROVIDED WITH THE SAME - A substrate for mounting a device comprises: an insulating resin layer; a plurality of projected electrodes that are connected electrically to a wiring layer provided on one major surface of the insulating resin layer, and that project toward the insulating resin layer from the wiring layer; and a counter electrode provided at a position corresponding to each of the plurality of projected electrodes on the other major surface of the insulating resin layer. Among the projected electrodes, a projected length of part of the projected electrodes is smaller than that of the other projected electrodes; and the projected electrode and the counter electrode corresponding thereto are capacitively-coupled, and the projected electrode and the counter electrode are connected electrically. | 2011-02-03 |
| 20110027946 | Horizontal Coffee-Stain Method Using Control Structure To Pattern Self-Organized Line Structures - A modified coffee-stain method for producing self-organized line structures and other very fine features that involves disposing a solution puddle on a target substrate, and then controlling the peripheral boundary shape of the puddle using a control structure that contacts the puddle's upper surface. The solution is made up of a fine particle solute dispersed in a liquid solvent wets and becomes pinned to both the target substrate and the control structure. The solvent is then caused to evaporate at a predetermined rate such that a portion of the solute forms a self-organized “coffee-stain” line structure on the target substrate surface that is contacted by the peripheral puddle boundary. The target structure is optionally periodically raised to generate parallel lines that are subsequently processed to form, e.g., TFTs for large-area electronic devices. | 2011-02-03 |
| 20110027947 | PRINTING METHOD FOR HIGH PERFORMANCE ELECTRONIC DEVICES - A method of depositing elongated nanostructures that allows accurate positioning and orientation is described. The method involves printing or otherwise depositing elongated nanostructures in a carrier solution. The deposited droplets are also elongated, usually by patterning the surface upon which the droplets are deposited. As the droplet evaporates, the fluid flow within the droplets is controlled such that the nanostructures are deposited either at the edge of the elongated droplet or the center of the elongated droplet. The described deposition technique has particular application in forming the active region of a transistor. | 2011-02-03 |
| 20110027948 | METHOD FOR MANUFACTURING A FINFET DEVICE - A method for manufacturing a FinFET device includes: providing a substrate having a mask disposed thereon; covering portions of the mask to define a perimeter of a gate region; removing uncovered portions of the mask to expose the substrate; covering a part of the exposed substrate with another mask to define at least one fin region; forming the at least one fin and the gate region through both masks and the substrate, the gate region having side walls; disposing insulating layers around the at least one fin and onto the side walls; disposing a conductive material into the gate region and onto the insulating layers to form a gate electrode, and then forming source and drain regions. | 2011-02-03 |
| 20110027949 | SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING THE SAME - Provided is a semiconductor device formed to an SOI substrate including a MOS transistor in which a parasitic MOS transistor is suppressed. The semiconductor device formed on the SOI substrate by employing a LOCOS process is structured such that a part of a polysilicon layer to becomes a gate electrode includes: a first conductivity type polysilicon region corresponding to a region of the silicon active layer which has a constant thickness and is to become a channel; and second conductivity type polysilicon regions corresponding to LOCOS isolation edges in each of which a thickness of the silicon active layer decreases. | 2011-02-03 |
| 20110027950 | METHOD FOR FORMING A SEMICONDUCTOR DEVICE HAVING A PHOTODETECTOR - A method is provided for integrating a germanium photodetector with a CMOS circuit. The method comprises: forming first and second isolation regions in a silicon substrate; forming a gate electrode in the first isolation region; implanting source/drain extensions in the silicon substrate adjacent to the gate electrode; forming a first sidewall spacer on the gate electrode; implanting source/drain regions in the silicon substrate; removing the first sidewall spacer from the gate electrode; forming a first protective layer over the first and second isolation regions; removing a portion of the first protective layer to form an opening over the second isolation region; forming a semiconductor material comprising germanium in the opening; forming a second protective layer over the first and second isolation regions; selectively removing the first and second protective layers from the first isolation region; and forming contacts to the transistor and to the semiconductor material. | 2011-02-03 |
| 20110027951 | SHARED GATE FOR CONVENTIONAL PLANAR DEVICE AND HORIZONTAL CNT - A semiconductor structure in which a planar semiconductor device and a horizontal carbon nanotube transistor have a shared gate and a method of fabricating the same are provided in the present application. The hybrid semiconductor structure includes at least one horizontal carbon nanotube transistor and at least one planar semiconductor device, in which the at least one horizontal carbon nanotube transistor and the at least one planar semiconductor device have a shared gate and the at least one horizontal carbon nanotube transistor is located above a gate of the at least one planar semiconductor device. | 2011-02-03 |
| 20110027952 | FORMATION OF A CHANNEL SEMICONDUCTOR ALLOY BY DEPOSITING A HARD MASK FOR THE SELECTIVE EPITAXIAL GROWTH - A growth mask provided for the deposition of a threshold adjusting semiconductor alloy may be formed on the basis of a deposition process, thereby obtaining superior thickness uniformity. Consequently, P-channel transistors and N-channel transistors with an advanced high-k metal gate stack may be formed with superior uniformity. | 2011-02-03 |
| 20110027953 | Laminated Stress Overlayer Using In-SITU Multiple Plasma Treatments for Transistor Improvement - Integrated circuits (ICs) commonly contain pre-metal dielectric (PMD) liners with compressive stress to increase electron and hole mobilities in MOS transistors. The increase is limited by the thickness of the PMD liner. The instant invention is a multi-layered PMD liner in an integrated circuit which has a higher stress than single layer PMD liners. Each layer in the inventive PMD liner is exposed to a nitrogen-containing plasma, and which has a compressive stress higher than 1300 MPa. The PMD liner of the instant invention is composed of 3 to 10 layers. The hydrogen content of the first layer may be increased to improve transistor properties such as flicker noise and Negative Bias Temperature Instability (NBTI). An IC containing the inventive PMD liner and a method for forming same are also claimed. | 2011-02-03 |
| 20110027954 | METHOD TO IMPROVE TRANSISTOR TOX USING SI RECESSING WITH NO ADDITIONAL MASKING STEPS - A method of forming a transistor device is provided wherein a gate structure is formed over a semiconductor body of a first conductivity type. The gate structure is formed comprising a protective cap thereover and defining source/drain regions laterally adjacent thereto. A first implant is performed of a second conductivity type into both the gate structure and the source/drain regions. The semiconductor body is etched to form recesses substantially aligned to the gate structure wherein the first implant is removed from the source/drain regions. Source/drain regions are implanted or grown by a selective epitaxial growth. | 2011-02-03 |
| 20110027955 | Source/Drain Carbon Implant and RTA Anneal, Pre-SiGe Deposition - A semiconductor device system, structure, and method of manufacture of a source/drain to retard dopant out-diffusion from a stressor are disclosed. An illustrative embodiment comprises a semiconductor substrate, device, and method to retard sidewall dopant out-diffusion in source/drain regions. A semiconductor substrate is provided with a gate structure, and a source and drain on opposing sides of the gate structure. Recessed regions are etched in a portion of the source and drain. Doped stressors are embedded into the recessed regions. A barrier dopant is incorporated into a remaining portion of the source and drain. | 2011-02-03 |
| 20110027956 | Method of Fabricating a Device Using Low Temperature Anneal Processes, a Device and Design Structure - A method of fabricating a device using a sequence of annealing processes is provided. More particularly, a logic NFET device fabricated using a low temperature anneal to eliminate dislocation defects, method of fabricating the NFET device and design structure is shown and described. The method includes forming a stress liner over a gate structure and subjecting the gate structure and stress liner to a low temperature anneal process to form a stacking force in single crystalline silicon near the gate structure as a way to memorized the stress effort. The method further includes stripping the stress liner from the gate structure and performing an activation anneal at high temperature on device. | 2011-02-03 |
| 20110027957 | METHOD OF DOPING SEMICONDUCTORS - A method of doping a semiconductor body is provided herein. In one embodiment, a semiconductor body is exposed to an activated hydrogen gas for a predetermined time period and temperature. The activated hydrogen gas that is configured to react with a surface of a semiconductor body. The activated hydrogen gas breaks existing bonds in the substrate (e.g., silicon-silicon bonds), thereby forming a reactive layer comprising weakened (e.g., silicon-hydrogen (Si—H) bonds, silanol (Si—OH) bonds) and/or dangling bonds (e.g., dangling silicon bonds). The dangling bonds, in addition to the easily broken weakened bonds, comprise reactive sites that extend into one or more surfaces of the semiconductor body. A reactant (e.g., n-type dopant, p-type dopant) may then be introduced to contact the reactive layer of the semiconductor body. The reactant chemically bonds to reactive sites comprised within the reactive layer, thereby resulting in a doped layer within the semiconductor body comprising the reactant. | 2011-02-03 |
| 20110027958 | Methods of Forming Silicide Regions and Resulting MOS Devices - A semiconductor device with improved roll-off resistivity and reliability are provided. The semiconductor device includes a gate dielectric overlying a semiconductor substrate, a gate electrode overlying the gate dielectric, a gate silicide region on the gate electrode, a source/drain region adjacent the gate dielectric, and a source/drain silicide region on the source/drain region, wherein the source/drain silicide region and the gate silicide region have different metal compositions. | 2011-02-03 |
| 20110027959 | Tunnel Field-Effect Transistors with Superlattice Channels - A semiconductor device includes a channel region; a gate dielectric over the channel region; a gate electrode over the gate dielectric; and a first source/drain region adjacent the gate dielectric. The first source/drain region is of a first conductivity type. At least one of the channel region and the first source/drain region includes a superlattice structure. The semiconductor device further includes a second source/drain region on an opposite side of the channel region than the first source/drain region. The second source/drain region is of a second conductivity type opposite the first conductivity type. At most, one of the first source/drain region and the second source/drain region comprises an additional superlattice structure. | 2011-02-03 |
| 20110027960 | Methods of Forming Strontium Titanate Films - Embodiments of the current invention include methods of forming a strontium titanate (SrTiO | 2011-02-03 |
| 20110027961 | Semiconductor Component and Method of Manufacture - A semiconductor component that includes an integrated passive device and method for manufacturing the semiconductor component. Vertically integrated passive devices are manufactured above a substrate. In accordance with one embodiment, a resistor is manufactured in a first level above a substrate, a capacitor is manufactured in a second level that is vertically above the first level, and a copper inductor is manufactured in a third level that is vertically above the second level. The capacitor has aluminum plates. In accordance with another embodiment, a resistor is manufactured in a first level above a substrate, a copper inductor is manufactured in a second level that is vertically above the first level, and a capacitor is manufactured in a third level that is vertically above the second level. The capacitor may have aluminum plates or a portion of the copper inductor may serve as one of its plates. | 2011-02-03 |
| 20110027962 | TRENCH DECOUPLING CAPACITOR FORMED BY RIE LAG OF THROUGH SILICON VIA (TSV) ETCH - A trench decoupling capacitor is formed using RIE lag of a through silicon via (TSV) etch. A method includes etching a via trench and a capacitor trench in a wafer in a single RIE process. The via trench has a first depth and the capacitor trench has a second depth less than the first depth due to RIE lag. | 2011-02-03 |
| 20110027963 | METHOD OF MANUFACTURING SEMICONDUCTOR DEVICE - A method of manufacturing a semiconductor device may include, but is not limited to the following processes. A first insulating film is formed over a substrate. A second insulating film is formed on the first insulating film. An electrode penetrating the first and the second insulating films is formed. A part of the second insulating film and a part of the electrode are removed so that a first hole is formed in the second insulating film. A first portion of the electrode is exposed through the first hole. A part of the first portion of the electrode is removed by an isotropic etching. | 2011-02-03 |
| 20110027964 | DOPING METHOD FOR SEMICONDUCTOR DEVICE - A doping method for a semiconductor device includes forming a trench in a semiconductor substrate, forming a doped layer doped with a dopant over the undoped layer, and forming a doped region into which the dopant is diffused, wherein the doped region is a portion of the semiconductor substrate in contact with the doped layer. | 2011-02-03 |
| 20110027965 | SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD THEREOF - The active region of an NMOS transistor and the active region of a PMOS transistor are divided by an STI element isolation structure. The STI element isolation structure is made up of a first element isolation structure formed so as to include the interval between both active regions, and a second element isolation structure formed in the region other than the first element isolation structure. | 2011-02-03 |
| 20110027966 | Method for Fabricating Isolation Layer in Semiconductor Device - A method for fabricating an isolation layer in a semiconductor device, comprising: forming a trench in a semiconductor substrate; forming a flowable insulation layer on the trench and the semiconductor substrate; converting the flowable insulation layer to a silicon oxide layer by implementing a curing process comprising continuously heating the flowable insulation layer; and forming an isolation layer by planarizing the silicon oxide layer. | 2011-02-03 |
| 20110027967 | METHOD FOR INSERTION BONDING AND DEVICE THUS OBTAINED - A method for insertion bonding and a device thus obtained are disclosed. In one aspect, the device includes a first substrate having a front main surface and at least one protrusion at the front main surface. The device includes a second substrate having a front main surface and at least one hole extending from the front main surface into the second substrate. The protrusion of the first substrate is inserted into the hole of the second substrate. The hole is formed in a shape wherein the width is reduced in the depth direction and wherein the width of at least a part of the hole is smaller than the width of the protrusion at the location of the metal portion thereof. The protrusion is deformed during insertion thereof in the hole to provide a bond between the part of the hole and the metal portion. | 2011-02-03 |
| 20110027968 | SEMICONDUCTOR DEVICE - A semiconductor device including a plurality of field-effect transistors which are stacked with a planarization layer interposed therebetween over a substrate having an insulating surface, in which semiconductor layers in the plurality of field-effect transistors are separated from semiconductor substrates, and the semiconductor layers are bonded to an insulating layer formed over the substrate having an insulating surface or an insulating layer formed over the planarization layer. | 2011-02-03 |
| 20110027969 | METHOD FOR PRODUCING SEMICONDUCTOR SUBSTRATE - There is provided a method for suppressing the occurrence of defects such as voids or blisters even in the laminated wafer having no oxide film wherein hydrogen ions are implanted into a wafer for active layer having no oxide film on its surface to form a hydrogen ion implanted layer, and ions other than hydrogen are implanted up to a position that a depth from the surface side the hydrogen ion implantation is shallower than the hydrogen ion implanted layer, and the wafer for active layer is laminated onto a wafer for support substrate, and then the wafer for active layer is exfoliated at the hydrogen ion implanted layer. | 2011-02-03 |
| 20110027970 | METHOD FOR DICING WAFER AND PROCESS FOR MANUFACTURING LIQUID-DISCHARGING HEAD USING THE DICING METHOD - A method for dicing a wafer having a first face in which opening are arranged along dicing streets. The method includes a step of affixing a dicing tape to the first face such that the dicing tape lies over the openings and adhesive regions of the dicing tape are exposed in the openings and a step of treating the dicing tape to reduce the adhesive strength of the adhesive regions. | 2011-02-03 |
| 20110027971 | METHOD OF CUTTING A SUBSTRATE, METHOD OF PROCESSING A WAFER-LIKE OBJECT, AND METHOD OF MANUFACTURING A SEMICONDUCTOR DEVICE - A laser beam machining method and a laser beam machining device capable of cutting a work without producing a fusing and a cracking out of a predetermined cutting line on the surface of the work, wherein a pulse laser beam is radiated on the predetermined cut line on the surface of the work under the conditions causing a multiple photon absorption and with a condensed point aligned to the inside of the work, and a modified area is formed inside the work along the predetermined determined cut line by moving the condensed point along the predetermined cut line, whereby the work can be cut with a rather small force by cracking the work along the predetermined cut line starting from the modified area and, because the pulse laser beam radiated is not almost absorbed onto the surface of the work, the surface is not fused even if the modified area is formed. | 2011-02-03 |
| 20110027972 | METHOD OF CUTTING A SUBSTRATE AND METHOD OF MANUFACTURING A SEMICONDUCTOR DEVICE - A laser beam machining method and a laser beam machining device capable of cutting a work without producing a fusing and a cracking out of a predetermined cutting line on the surface of the work, wherein a pulse laser beam is radiated on the predetermined cut line on the surface of the work under the conditions causing a multiple photon absorption and with a condensed point aligned to the inside of the work, and a modified area is formed inside the work along the predetermined determined cut line by moving the condensed point along the predetermined cut line, whereby the work can be cut with a rather small force by cracking the work along the predetermined cut line starting from the modified area and, because the pulse laser beam radiated is not almost absorbed onto the surface of the work, the surface is not fused even if the modified area is formed. | 2011-02-03 |
| 20110027973 | METHOD OF FORMING LED STRUCTURES - One embodiment of fabricating a p-down light emitting diode (LED) structure comprises depositing a high crystal quality p type contact layer, depositing an active region on top of the p type contact layer, and depositing an n type contact layer on top of the active region using a hydride vapor phase epitaxy (HVPE) process. The high crystal quality p type contact layer is deposited at high temperature to ensure the high crystal quality of the p type film. The n type contact layer is formed on top of the active region in a HVPE chamber at a low temperature to prevent thermal damage to the quantum wells in the active region below the n type contact layer. The processing chamber used to form the p type contact layer is a separate processing chamber than the processing chamber used to form the n type contact layer. | 2011-02-03 |
| 20110027974 | INDIUM SURFACTANT ASSISTED HVPE OF HIGH QUALITY GALLIUM NITRIDE AND GALLIUM NITRIDE ALLOY FILMS - One embodiment of depositing a gallium nitride (GaN) film on a substrate comprises providing a source of indium (In) and gallium (Ga) and depositing a monolayer of indium (In) on the surface of the gallium nitride (GaN) film. The monolayer of indium (In) acts as a surfactant to modify the surface energy and facilitate the epitaxial growth of the film by suppressing three dimensional growth and enhancing or facilitating two dimensional growth. The deposition temperature is kept sufficiently high to enable the indium (In) to undergo absorption and desorption on the gallium nitride (GaN) film without being incorporated into the solid phase gallium nitride (GaN) film. The gallium (Ga) and indium (In) can be provided by a single source or separate sources. | 2011-02-03 |
| 20110027975 | SUBSTRATE FOR GROWING A III-V LIGHT EMITTING DEVICE - A substrate including a host and a seed layer bonded to the host is provided, then a semiconductor structure including a light emitting layer disposed between an n-type region and a p-type region is grown on the seed layer. In some embodiments, a bonding layer bonds the host to the seed layer. The seed layer may be thinner than a critical thickness for relaxation of strain in the semiconductor structure, such that strain in the semiconductor structure is relieved by dislocations formed in the seed layer, or by gliding between the seed layer and the bonding layer an interface between the two layers. In some embodiments, the host may be separated from the semiconductor structure and seed layer by etching away the bonding layer. | 2011-02-03 |
| 20110027976 | METHOD OF FORMING CHALCOGENIDE THIN FILM - The present invention concerns a method of forming a chalcogenide thin film for a phase-change memory. In the method of forming a chalcogenide thin film according to the present invention, a substrate with a pattern formed is loaded into a reactor, and a source gas is supplied onto the substrate. Here, the source gas includes at least one source gas selected from germanium (Ge) source gas, gallium (Ga) source gas, indium (In) source gas, selenium (Se) source gas, antimony (Sb) source gas, tellurium (Te) source gas, tin (Sn) source gas, silver (Ag) source gas, and sulfur (S) source gas. A first purge gas is supplied onto the substrate in order to purge the source gas supplied onto the substrate, a reaction gas for reducing the source gas is then supplied onto the substrate, and a second purge gas is supplied onto the substrate in order to purge the reaction gas supplied onto the substrate. At least one operation, namely changing the supply time of the first purge gas and/or adjusting the internal pressure of the reactor is performed in such a way as to ensure that the deposition rate at an inner portion of the pattern is greater than the deposition rate at an upper portion of the pattern. According to the present invention, it is possible to form a chalcogenide thin film having an excellent gap-fill property by changing the purge time of the source gas or adjusting the internal pressure of the reactor in such a way as to ensure that the film forming rate at the inner portion of the pattern is greater than the film forming rate at the upper portion of the pattern. | 2011-02-03 |
| 20110027977 | DEPOSITION OF RUTHENIUM OR RUTHENIUM DIOXIDE - Methods of forming ruthenium or ruthenium dioxide are provided. The methods may include using ruthenium tetraoxide (RuO | 2011-02-03 |
| 20110027978 | METHODS FOR FABRICATING NON-PLANAR SEMICONDUCTOR DEVICES HAVING STRESS MEMORY - Embodiments of a method are provided for fabricating a non-planar semiconductor device including a substrate having a plurality of raised crystalline structures formed thereon. In one embodiment, the method includes the steps of amorphorizing a portion of each raised crystalline structure included within the plurality of raised crystalline structures, forming a sacrificial strain layer over the plurality of raised crystalline structures to apply stress to the amorphized portion of each raised crystalline structure, annealing the non-planar semiconductor device to recrystallize the amorphized portion of each raised crystalline structure in a stress-memorized state, and removing the sacrificial strain layer. | 2011-02-03 |
| 20110027979 | DIELECTRIC FILM, METHOD OF MANUFACUTRING SEMICONDUCTOR DEVICE USING DIELECTRIC FILM, AND SEMICONDUCTOR MANUFACTURING APPARATUS - To provide a method of manufacturing a dielectric film having a high dielectric constant. In an embodiment of the present invention, an HfN/Hf laminated film is formed on a substrate on which a thin silicon oxide film is formed and a dielectric film of a metal nitride made of a mixture of Hf, Si, O and N is manufactured by annealing treatment. According to the present invention, it is possible to (1) reduce an EOT, (2) reduce a leak current to Jg=1.0×10 | 2011-02-03 |
| 20110027980 | SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD THEREOF - The semiconductor device has a semiconductor layer, a gate electrode which covers an end portion of the semiconductor layer, and an insulating layer for insulating the semiconductor layer and the gate electrode. The film thickness of the insulating layer which insulates a region where an end portion of the semiconductor layer and the gate electrode overlap each other is thicker than the film thickness of the insulating layer which covers the central portion of the semiconductor layer. | 2011-02-03 |
| 20110027981 | NONVOLATILE SEMICONDUCTOR STORAGE DEVICE AND METHOD FOR MANUFACTURING SAME - A nonvolatile semiconductor storage device includes: a plurality of stacked units juxtaposed on a major surface of a substrate, each stacked unit aligning in a first direction parallel to the major surface of the substrate; and a gate electrode aligning parallel to the major surface in a second direction non-parallel to the first direction. Each of the plurality of stacked units includes a plurality of stacked semiconductor layers via an insulating layer. The plurality of stacked units are juxtaposed so that the spacings between adjacent stacked units are alternately a first spacing and a second spacing larger than the first spacing. The second spacing is provided at a periodic interval four times a size of a half pitch F of the bit line. The gate electrode includes a protruding portion that enters into a gap of the second spacing between the stacked units. A first insulating film, a charge storage layer, and a second insulating film are provided between a side face of the semiconductor layer and the protruding portion. | 2011-02-03 |
| 20110027982 | SEMICONDUCTOR DEVICE - A method of manufacturing a semiconductor device according to the present invention includes the steps of introducing first impurities of a first conductivity type into a main surface of a semiconductor substrate | 2011-02-03 |
| 20110027983 | Method for Manufacturing a Semiconductor Device - A manufacturing method of a semiconductor device wherein a metal pad is etched to form a trench in which a central part is concave in form, or to form a trench in the shape of a cylinder or a parallelepiped on the edge part of a metal pad. Accordingly, the contact area between a polymide isoindro quirazorindione (PIQ) or similar curable layer and the metal pad is increased and the bondability is improved. Accordingly, the technology of improving the characteristic of device by preventing the problem that the metal pad is excessively opened in a subsequent curing process and the layer of a lower portion of the metal pad is attacked is disclosed. | 2011-02-03 |
| 20110027984 | PROCESS OF FORMING AN ELECTRONIC DEVICE INCLUDING A CONDUCTIVE STUD OVER A BONDING PAD REGION - An electronic device can include an interconnect level including a bonding pad region. An insulating layer can overlie the interconnect level and include an opening over the bonding pad region. In one embodiment, a conductive stud can lie within the opening and can be substantially encapsulated. In another embodiment, the electronic device can include a barrier layer lying along a side and a bottom of the opening and a conductive stud lying within the opening. The conductive stud can substantially fill the opening. A majority of the conductive stud can lie within the opening. In still another embodiment, a process for forming an electronic device can include forming a conductive stud within the opening wherein from a top view, the conductive stud lies substantially completely within the opening. The process can also include forming a second barrier layer overlying the conductive stud. | 2011-02-03 |
| 20110027985 | SEMICONDUCTOR DEVICE HAVING AERIAL WIRING AND MANUFACTURING METHOD THEREOF - A semiconductor device includes a first aerial wiring including a first wiring layer which is formed in an air gap and contains Cu as a main component and a via layer which is electrically connected to the first wiring layer, is formed in an inter-level insulating film containing a preset constituent element and contains Cu as a main component, and a first porous film formed on the first aerial wiring. The semiconductor device further includes a first barrier film which is formed to cover the surface of the first aerial wiring and contains a compound of the preset constituent element and a preset metal element as a main component. | 2011-02-03 |
| 20110027986 | LOW COST METHOD OF FABRICATION OF VERTICAL INTERCONNECTIONS COMBINED TO METAL TOP ELECTRODES - A method is for forming a vertical interconnection through a dielectric layer between upper and lower electrically conductive layers of an integrated circuit. The method includes forming an opening through the dielectric layer and placing a solidifiable electrically conductive filler into the opening via a printing technique. The solidifiable electrically conductive filler is solidified to thereby form a solidified electrically conducting filler in the opening. A metallization layer is formed over the dielectric layer and the solidified electrically conducting filler to thereby form the vertical interconnection through the dielectric layer between the upper and lower electrically conductive layers of the integrated circuit. | 2011-02-03 |
| 20110027987 | Method and apparatus for manufacturing semiconductor device - A method for manufacturing a semiconductor device includes forming a laminated structure of a plurality of metal films on a semiconductor substrate using an electroless plating method. The forming of the metal films includes: performing an electroless plating process including a reduction reaction using a first plating tank; and performing an electroless plating process by only a substitution reaction using a second plating tank. The electroless plating process including the reduction reaction that is performed using the first plating tank is performed in a shading environment, and the electroless plating process performed by only the substitution reaction using the second plating tank is performed in a non-shading environment. | 2011-02-03 |
| 20110027988 | METHOD FOR FORMING BURIED WORD LINE IN SEMICONDUCTOR DEVICE - Provided is a method for forming a buried word line in a semiconductor device. The method includes forming a trench by etching a pad layer and a substrate, forming a conductive layer to fill the trench, planarizing the conductive layer until the pad layer is exposed, performing an etch-back process on the planarized conductive layer, and performing an annealing process in an atmosphere of a nitride-based gas after at least one of the forming of the conductive layer, the planarizing of the conductive layer, and the performing of the etch-back process on the planarized conductive layer. | 2011-02-03 |
| 20110027989 | INCREASED DENSITY OF LOW-K DIELECTRIC MATERIALS IN SEMICONDUCTOR DEVICES BY APPLYING A UV TREATMENT - A silicon-based low-k dielectric material is formed on the basis of a single precursor material, such as OMTCS, without incorporating a porogen species. To this end, the initial deposition of the low-k dielectric material may be formed on the basis of a reduced process temperature, while a subsequent treatment, such as a UV treatment, may allow the adjustment of the final material characteristics without causing undue out-gassing of volatile organic components. | 2011-02-03 |
| 20110027990 | SEMICONDUCTOR CHIP AND METHOD OF MANUFACTURING THE SAME - A semiconductor chip includes a semiconductor substrate, a through via provided in a through hole that passes through the semiconductor substrate, insulating layers laminated on the semiconductor substrate, a multi-layered wiring structure having a first wiring pattern and a second wiring pattern, and an external connection terminal provided on an uppermost layer of the multi-layered wiring structure, wherein the through via and the external connection terminal are connected electrically by the second wiring pattern. | 2011-02-03 |
| 20110027991 | Interconnect Structure for Semiconductor Devices - A cap layer for a copper interconnect structure formed in a first dielectric layer is provided. In an embodiment, the cap layer may be formed by an in-situ deposition process in which a process gas comprising germanium, arsenic, tungsten, or gallium is introduced, thereby forming a copper-metal cap layer. In another embodiment, a copper-metal silicide cap is provided. In this embodiment, silane is introduced before, during, or after a process gas is introduced, the process gas comprising germanium, arsenic, tungsten, or gallium. Thereafter, an optional etch stop layer may be formed, and a second dielectric layer may be formed over the etch stop layer or the first dielectric layer. | 2011-02-03 |
| 20110027992 | MEMORY DEVICE WITH IMPROVED DATA RETENTION - The present memory device include first and second electrodes, a passive layer between the first and second electrodes, and an active layer between the first and second and into which ions from the passive layer may be provided, and from which the ions may be provided into the passive layer. The active layer is made up of a base material and an impurity therein. The combined the material and impurity have a lower diffusion coefficient than the base material alone. | 2011-02-03 |
| 20110027993 | METHODS OF FORMING FINE PATTERNS OF SEMICONDUCTOR DEVICE - A method of forming fine patterns of a semiconductor device is provided. The method includes forming plural preliminary first mask patterns, which are spaced apart from each other by a first distance in a direction parallel to a surface of a substrate, on the substrate; forming an acid solution layer on the substrate to cover the plural preliminary first mask patterns; forming plural first mask patterns which are spaced apart from each other by a second distance larger than the first distance, of which upper and side portions are surrounded by acid diffusion regions having first solubility; exposing the first acid diffusion regions by removing the acid solution layer; forming a second mask layer having second solubility lower than the first solubility in spaces between the acid diffusion regions; and forming plural second mask patterns located between the plural first mask patterns, respectively, by removing the acid diffusion regions by the dissolvent. | 2011-02-03 |
| 20110027994 | POLISHING SLURRY FOR CMP - A polishing liquid for CMP has a composition loaded with, for example, an inorganic salt, a protective film forming agent and a surfactant capable of imparting a dissolution accelerating activity to enlarge a difference between polishing speed under non-load and polishing speed under load. By virtue of this polishing liquid for CMP, there can be simultaneously accomplished a speed increase for increasing CMP productivity, and wiring planarization for miniaturization and multilayer formation of wiring. | 2011-02-03 |
| 20110027995 | CLEANING SOLUTION FOR SUBSTRATE FOR SEMICONDUCTOR DEVICE - A cleaning solution of the present invention contains a sodium ion, a potassium ion, an iron ion, an ammonium salt of a sulfuric ester represented by General Formula (1), and water, and each content of the sodium ion, the potassium ion, and the iron ion is 1 ppb to 500 ppb. ROSO | 2011-02-03 |
| 20110027996 | SLURRY COMPOSITION FOR A CHEMICAL MECHANICAL POLISHING PROCESS, METHOD OF POLISHING AN OBJECT LAYER AND METHOD OF MANUFACTURING A SEMICONDUCTOR MEMORY DEVICE USING THE SLURRY COMPOSITION - A slurry composition for a chemical mechanical processing process includes about 0.05 to about 0.3 percent by weight of a ceria abrasive, about 0.005 to about 0.04 percent by weight of an anionic surfactant, about 0.0005 to about 0.003 percent by weight of a polyoxyethylene-based nonionic surfactant, about 0.2 to about 1.0 percent by weight of a salt of polyacrylic acid having an average molecular weight substantially greater than a molecular weight of the anionic surfactant, and a remainder of water. In addition, a method of polishing an object layer and a method of manufacturing a semiconductor device using the slurry composition are also provided. | 2011-02-03 |
| 20110027997 | POLISHING LIQUID FOR CMP AND POLISHING METHOD - The present invention can provide a polishing liquid for CMP having good dispersion stability and a high polishing rate in polishing of interlayer insulating films and a polishing method. Disclosed a polishing liquid for CMP comprising: a medium; and colloidal silica particles dispersed in the medium, a blending amount of the colloidal silica particles being 2.0 to 8.0% by mass relative to 100% by mass of the polishing liquid,
| 2011-02-03 |
| 20110027998 | Method of Manufacturing A Nano Structure By Etching, Using A Substrate Containing Silicon - A method of manufacturing a nano structure by etching, using a substrate containing Si. A focused Ga ion or In ion beam is irradiated on the surface of the substrate containing Si. The Ga ions or the In ions are injected while sputtering away the surface of the substrate so that a layer containing Ga or In is formed on the surface of the substrate. Dry etching by a gas containing fluorine (F) is performed with the layer containing the Ga or the In formed on the surface of the substrate taken as an etching mask, and the nano structure is formed having a pattern of at least 2 μm tin in depth according to a predetermined line width. | 2011-02-03 |
| 20110027999 | ETCH METHOD IN THE MANUFACTURE OF AN INTEGRATED CIRCUIT - The present invention provides a method for etching a substrate in the manufacture of a semiconductor device, the method comprising contacting a surface of the substrate with ions extracted from a plasma formed from a gas comprising one or more of an oxygen-containing species, a nitrogen-containing species and an inert gas, and separately contacting the surface of the substrate with a plasma formed from a gas comprising a fluorine-containing species. | 2011-02-03 |
| 20110028000 | METHODS OF ETCHING SILICON-CONTAINING FILMS ON SILICON SUBSTRATES - A method for selectively etching a silicon-containing film on a silicon substrate is disclosed. The method includes depositing a silicon-containing film on the silicon substrate. The method further includes baking the silicon-containing film to create a densified silicon-containing film, wherein the densified film has a first thickness. The method also includes exposing the silicon substrate to an aqueous solution comprising NH | 2011-02-03 |
| 20110028001 | SUBSTRATE PROCESSING APPARATUS AND METHOD - Disclosed is a substrate processing apparatus and method. The substrate processing apparatus includes a process chamber ( | 2011-02-03 |
| 20110028002 | SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING THE SAME - A method of forming a semiconductor device includes the following processes. A metal nitride film is formed with a thickness of 3 nm or less over a substrate. The metal nitride film is oxidized to form a metal oxide film. A set of the formation of the metal nitride film and the oxidation of the metal nitride film is repeated, to form a stack of the metal oxide films over the substrate. | 2011-02-03 |
| 20110028003 | Substrate processing with reduced warpage and/or controlled strain - Provided are systems and methods for processing the surface of substrates that scan a laser beam at one or more selected orientation angles. The orientation angle or angles may be selected to reduce substrate warpage. When the substrates are semiconductor wafers having microelectronic devices; the orientation angles may be selected to produce controlled strain and to improve electronic performance of the devices. | 2011-02-03 |
| 20110028004 | Inspection Method and Apparatus, Lithographic Apparatus, Lithographic Processing Cell and Device Manufacturing Method - A mark used in the determination of overlay error comprises sub-features, the sub-features having a smallest pitch approximately equal to the smallest pitch of the product features. The sensitivity to distortions and aberrations is similar as that for the product features. When the mark is developed the sub-features merge and the outline of the larger feature is developed. | 2011-02-03 |
| 20110028005 | VERTICAL BOAT FOR HEAT TREATMENT AND METHOD FOR HEAT TREATMENT OF SILICON WAFER USING THE SAME - The present invention is a vertical boat for heat treatment having an auxiliary supporting member removably attached to each of supporting parts of a boat body, the auxiliary supporting member on which a substrate to be treated is to be placed, in which the auxiliary supporting member has a guiding member attached to the supporting part and a substrate supporting plate on which the substrate to be treated is to be placed, a hole is formed on an upper surface of the guiding member, the substrate supporting plate is inserted and fitted into the hole of the guiding member so as to be fixed, a height position of a placing surface for the substrate to be treated is higher than a height position of the upper surface of the guiding member, the substrate supporting plate is composed of silicon carbide and the guiding member is composed of quartz. | 2011-02-03 |
| 20110028006 | Conductive Magnetic Coupling System - Technologies are described herein for a conductive magnetic coupling system. The system includes a signal supply component that provides electrical and/or data signals to a signal consumption component that utilizes the signal to provide an output. The two components are magnetically coupled together such that the magnetic coupling mechanisms not only provide the bonding mechanism for securing the components to one another, but also provide the electrical and communicative continuity that allows for the transfer of electrical and/or data signals between the two components. Aspects provide for the repositioning of the signal consumption component along any section of a signal supply component configured as a magnetic track system. Aspects further provide for a flexible, fluid impermeable signal supply component in which a signal consumption component is repositionable along its length. | 2011-02-03 |
| 20110028007 | BREADBOARD - The invention relates to a breadboard ( | 2011-02-03 |
| 20110028008 | PROGRAMMABLE STRUCTURE FOR PASSING PARAMETERS TO A CONTROLLER - An enclosure includes a base unit and an insertable unit wherein the base unit has an opening corresponding to the insertable unit. A single structure is formed when the insertable unit is inserted into the base. The base is electrically connected to a first electronic device, such as a solar panel. The insertable unit includes a second electronic device. The base and the insertable unit have connectors that make electrical connections when the insertable unit is inserted into the base unit. The base unit further includes electrical connectors connected to a memory device wherein the electrical connections correspond to matching connections in the insertable unit. Upon assembly the second electronic device reads data prepositioned in the memory device, thereby passing data to the second electronic device. The data may be parametric, characteristic, flag, or a serial number, for example. | 2011-02-03 |
| 20110028009 | IC socket having restraining mechanism - An IC socket includes a base receiving a number of contacts, a lid mounted upon the base, and at least one latch mounted in the base. The lid is able to be operated between a first position away from the base and a second position adjacent to the base. The latch is driven by the lid to open and close. At least one stopper is disposed on the lid and extends into a recess defined on the latch to lock with latch the latch when the lid located at the first position for preventing the lid from dropping from the base. | 2011-02-03 |
| 20110028010 | POWER CONNECTION APPARATUS - There is disclosed a power connection apparatus which can secure connection between a power socket and a power plug and which can simplify the connecting operation properties thereof. A handle rotatably attached to the power plug having terminals includes engaging claw disengageably engaged with engagement portion of the power socket having an electrode portion, an abutment portion which abuts on the power socket, and a grip portion. The rotation of the grip portion in such a direction as to come away from the power socket is limited by the angle of the rotation of the handle in a direction in which the grip portion comes close to the power socket. | 2011-02-03 |
| 20110028011 | TAMPER-RESISTANT ELECTRICAL WIRING DEVICE SYSTEM - A tamper-resistant electrical receptacle includes a cover defining a set of cover apertures; and a slider defining an aperture therein and being movable between a first position blocking the set of cover apertures and a second position not blocking the set of cover apertures, wherein when an object probes at least one and fewer than all of the set of cover apertures, the slider is constrained in the first position. When a set of prongs is inserted simultaneously through the set of cover apertures, the prongs contact a slider surface that is oriented substantially orthogonal to a longitudinal axis of the set of prongs such that the slider is urged from the first to the second position. When in the second position the slider aperture aligns with at least one of the set of cover apertures to enable the set of prongs to contact the receptacle contacts. | 2011-02-03 |
| 20110028012 | SPARKLESS ELECTRICAL CONNECTOR - Methods and apparatuses supporting an electrical connection in a manner that eliminates or reduces a danger of electrical sparking are disclosed. A sparkless electrical connector has a conductor, configured to provide flow of electricity between an electrical source and a load, and a resistive element, operatively coupled to the conductor, to resist flow of electricity during a state of partial connection with the electrical source or the load. The resistive element may be not in contact with a terminal of the source or load during a state of full connection. The resistive element may be a coating of an anodized material on a pin of the conductor. The coating provides a resistance sufficient to prevent sparking during connection of the conductor and at least one of the electrical source and the load. Techniques disclosed herein benefit users and manufacturers in the areas of safety, cost, simplicity, and reliability. | 2011-02-03 |
| 20110028013 | ELECTRICITY DISTRIBUTION CIRCUIT - Disclosed are methods and devices for the use of electricity. The methods and devices generally relate to receptacles and plugs in which two electrical sockets share a circuit forming aperture | 2011-02-03 |
| 20110028014 | POWER CONNECTION APPARATUS - There is disclosed a power connection apparatus which can secure connection between a power socket and a power plug with a simple constitution and which can simplify the connecting operation properties thereof. A handle rotatably attached to the power plug having terminals includes engaging claw disengageably engaged with engagement portion of the power socket having an electrode portion, an abutment portion which abuts on the power socket, and a grip portion. In a state where the handle is rotated to such an angle that the handle is at substantially right angles to the power socket, the abutment portion abuts on the power socket, thereby releasing connection between the electrode portion and the terminals or the like. | 2011-02-03 |
| 20110028015 | QUICK INSERTION LAMP ASSEMBLY - A lamp assembly includes a light source, a contact base, a center contact and an outer contact. The contact base extends from a lower end to an upper end along a center axis. The upper end is interconnected with the light source and the lower end is configured to be received in a socket to mate the contact base with the socket. The center contact is disposed proximate the lower end of the contact base and is electronically coupled with the light source. The outer contact includes a ring body and an elongated contact line. The ring body encircles the center contact proximate the lower end of the contact base. The center contact and the outer contact are mechanically and electrically coupled with the socket and electrically join the light source with an electric ground reference. | 2011-02-03 |
