| 05th week of 2011 patent applcation highlights part 18 |
| Patent application number | Title | Published |
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| 20110025312 | MAGNETIC ENCODER AND METHOD OF DETECTING ABSOLUTE ROTATIONAL POSITION - A magnetic encoder includes a multi-pole magnetic detecting unit having a multi-pole magnet. In the multi-pole magnetic detecting unit, first and second magnetic detecting elements that output sinusoidal signals having a 90° phase difference are arranged apart from third and fourth magnetic detecting elements at a mechanical angle of 180°. The first and third magnetic detecting elements are disposed at the same position represented by an electrical angle and output sinusoidal signals of a same phase. The second and fourth magnetic detecting elements are arranged at the same position represented by an electrical angle and output sinusoidal signals of a same phase. A sum signal of the output signals of the first and third magnetic detecting elements and that of the output signals of the second and fourth magnetic detecting elements are obtained, thereby eliminating or remarkably reducing error components of detection signals of the first to fourth magnetic detecting elements caused by the magnetic flux of a two-pole magnet and those of the detection signals caused by rotational run out of the multi-pole magnet. A rotational angle can be detected with high accuracy. | 2011-02-03 |
| 20110025313 | Measurement Method, Sensor Arrangement and Measurement System - In a measurement method, an array of magnetic field sensors (MS | 2011-02-03 |
| 20110025314 | ANGLE DETECTOR - An angle detector includes a rotating member, a housing, a detector and an urging member. The rotating member is rotatable with a shaft inserted therethrough. The housing rotatably supports the rotating member. The detector detects a rotating angle of the rotating member with respect to the housing. The urging member urges the rotating member in a rotating direction of the rotating member. An engagement portion is provided on the housing. An engaged portion is provided on the rotating member. The engaged portion is adapted to be brought into engagement with the engagement portion by urged by the urging member. | 2011-02-03 |
| 20110025315 | DETECTING METHOD AND DIELECTRIC PARTICLES CONTAINING MAGNETIC MATERIAL EMPLOYED IN THE DETECTING METHOD - A magnetic binding substance, which is a first binding substance that specifically binds with a target substance, having magnet enveloping dielectric particles, which have magnetic particles enveloped therein and surfaces modified with functional groups that exhibit polarity within a liquid sample, attached thereto, and a labeling binding substance, which is a second binding substance that specifically binds with the target substance having photoresponsive labels attached thereto, are mixed with the liquid sample such that binding reactions occur. A magnetic field is generated within a sample cell, to draw the magnetic binding substance to a local region. Excitation light is irradiated only onto a predetermined region including the local region while the magnetic binding substance is drawn to the local region, causing the photoresponsive labels present therein to generate optical signals. The optical signals are detected. | 2011-02-03 |
| 20110025316 | EDDY CURRENT PROBE ASSEMBLY ADJUSTABLE FOR INSPECTING TEST OBJECTS OF DIFFERENT SIZES - An eddy current probe assembly suitable for inspecting a test object with longitudinal shape, being passed through the assembly in the object's axial direction during an inspection session, the probe assembly comprising multiple probe modules being disposed in a radial plane and with the modules partially overlaying on each other forming an iris structure encircling an inspection zone, wherein a movement in unison of each of the probe modules closer to or further away from the center of the inspection zone makes the inspection zone enlarged or contracted. Spring tension is applied on each of the probe modules so that constant life-off in maintained between the probe modules and the test surface. Array of eddy current elements for each probe module and multiple layers of probe modules can be employed to achieve complete coverage of the test surface. The radial cross-sectional shapes of the test objects can be of round or polygonal. | 2011-02-03 |
| 20110025317 | MsS PROBE FOR GUIDED-WAVE INSPECTION OF FUEL RODS - The present application discloses a magnetostrictive sensor (MsS) probe for guided-wave inspection of the entire length of a fuel rod. The probe includes a waveguide adapted to be clamped to a fuel rod, and an MsS adapted to generate guided waves into the waveguide such that the guided waves propagate down the waveguide into the fuel rod and back to the waveguide for detection by the MsS. | 2011-02-03 |
| 20110025318 | MAGNETIC SENSOR WITH BRIDGE CIRCUIT INCLUDING MAGNETORESISTANCE EFFECT ELEMENTS - A magnetic sensor for detecting a direction of an external magnetic field comprises: a bridge circuit configured to provide an output that changes in accordance with the direction of the external magnetic field, the bridge circuit including four resistance element sections, each of which comprises at least one magnetoresistance effect element; and two resistors connected to respective output terminals of the bridge circuit. The ratio of the resistance of each of the resistors to that of the bridge circuit is at least 2 when the resistance of each of the resistance element sections is at a minimum corresponding to a change in magnetoresistance. | 2011-02-03 |
| 20110025319 | MAGNETIC SENSOR INCLUDING A BRIDGE CIRCUIT - A magnetic sensor includes a bridge circuit with a first, a second, a third, and a fourth resistor annularly and electrically connected together in this order, and a compensation resistor. The compensation resistor is connected to a first point between the fourth resistor and the first resistor. The first to fourth resistors include a first to fourth tunnel magneto-resistance element, respectively. Each of the magnetization directions in the magnetization fixed layers in the second and fourth magneto resistance elements is opposite to the magnetization direction in the magnetization fixed layer in the first magneto resistance element. The magnetization direction in the magnetization fixed layer in the third magneto resistance element is the same as the magnetization direction in the magnetization fixed layer in the first magneto resistance element. The resistance of the compensation resistor varies with a period of 180 degrees with respect to a rotation angle of the external field. | 2011-02-03 |
| 20110025320 | MAGNETIC SENSOR - A magnetoresistive element includes magnetoresistive films each having an upper surface and a lower surface, and conductors combining the magnetoresistive films in series and including top electrodes and bottom electrodes. Each one of the top electrodes and corresponding one of the bottom electrodes oppose each other to sandwich corresponding one of the magnetoresistive films. Each electrode of the top electrodes and the bottom electrodes includes a stem section and a branch section, the stem section extending in a direction along a series alignment direction of the magnetoresistive films, and the branch section extending along the lamination plane in a direction intersecting a direction in which the stem section extends. The branch section in the top electrode is in contact with an upper surface of the corresponding magnetoresistive film, and the branch section in the bottom electrode is in contact with a lower surface of the corresponding magnetoresistive film. | 2011-02-03 |
| 20110025321 | MAGNETIC SENSOR - A magnetic sensor includes first to fourth MR elements. The first and second MR elements are connected at respective ends thereof through a first connecting portion in a central region. The third and fourth MR elements are connected at respective ends thereof through a second connecting portion that crosses the first connecting portion with a distance in a thickness direction in the central region. The first and fourth MR elements are connected at respective other ends thereof through a third connecting portion, and the second and third MR elements are connected at respective other ends thereof through a fourth connecting portion. Resistance values of the first and third MR elements change in a same increasing/decreasing direction, whereas resistance values of the second and fourth MR elements change in an increasing/decreasing direction opposite to the first and third MR elements, depending on an external signal magnetic field. | 2011-02-03 |
| 20110025322 | MAGNETO-RESISTANCE EFFECT ELEMENT AND SENSOR - A magneto-resistance effect element for a sensor to sense a variation in externally applied magnetism includes a pinned layer having a fixed magnetization direction, a free layer having a magnetization direction which varies in response to an external magnetic field, and an intermediate layer provided between the pinned layer and the free layer. The pinned layer has a planar shape which is long in the fixed magnetization direction and which is short in a direction orthogonal to the fixed magnetization direction. Moreover, the pinned layer preferably has a planar shape in which the pinned layer is divided into a plurality of sections. | 2011-02-03 |
| 20110025323 | OPTICAL ATOMIC MAGNETOMETER - An optical atomic magnetometers is provided operating on the principles of nonlinear magneto-optical rotation. An atomic vapor is optically pumped using linearly polarized modulated light. The vapor is then probed using a non-modulated linearly polarized light beam. The resulting modulation in polarization angle of the probe light is detected and used in a feedback loop to induce self-oscillation at the resonant frequency. | 2011-02-03 |
| 20110025324 | SIMULTANEOUS RELAXATION TIME INVERSION - In some embodiments, apparatus and systems, as well as methods, may operate to acquire fluid signature data representing a plurality of nuclear magnetic resonance echo trains associated with fluids in a material, to simultaneously invert a plurality of relaxation time models to provide inverted results, and to determine fluid properties using the inverted results. The relaxation time models may be associated with the fluids using the fluid signature data after constraining ratios of T | 2011-02-03 |
| 20110025325 | APPARATUS AND METHOD FOR ACQUISITION AND RECONSTRUCTION OF NON-CPMG PROPELLER SEQUENCES - An apparatus and method of MR imaging is disclosed. The apparatus and method comprises segmenting acquisition of an echo train into separate odd and even acquisition blades in k-space, wherein the odd and even acquisition blades extend orthogonally through a common reference point in a central region of k-space. A segment of MR data is acquired using a quadratic phase modulation scheme, wherein a first set of MR echo signals occurring after odd-numbered RF refocusing pulses are stored in the odd acquisition blade, and a second set of MR echo signals occurring after even-numbered RF refocusing pulses are stored in the even acquisition blade. This acquisition and segmentation is repeated until a sufficient number of blades are acquired to fill k-space. Finally, an image is reconstructed from the acquisition blades. | 2011-02-03 |
| 20110025326 | DUAL-USE NMR PROBE - An NMR probe comprising an RF resonator | 2011-02-03 |
| 20110025327 | METHOD FOR RADIOFREQUENCY MAPPING IN MAGNETIC RESONANCE IMAGING - A method of mapping a radio frequency magnetic field transmitted to a magnetic resonance imaging specimen. The method comprises the steps of: applying a first radio frequency pulse having a first excitation angle to the specimen and at a first time period after applying the first pulse applying one or more second radio frequency pulses each having a second excitation angle to the specimen, with a second time period between second pulses, to obtain a first data set defining a first sample of an image space; applying one or more third radio frequency pulses each having a third excitation angle to the specimen, with a third time period between third pulses, to obtain a second data set defining a second sample of the image space; applying one or more fourth radio frequency pulses each having a fourth excitation angle to the specimen, with a fourth time period between fourth pulses, to obtain a third data set defining a third sample of the image space; wherein the fourth excitation angle is different to the third excitation angle and/or the fourth time period is different to the third time period; calculating a magnetic field map data from at the three data sets; and outputting the magnetic field map data. | 2011-02-03 |
| 20110025328 | METHOD OF AND APPARATUS FOR ANALYSIS OF THE COMPOSITION OF A SAMPLE BY ELECTRON SPIN RESONANCE (ESR) SPECTROMETRY EMPLOYING CARRIER SUPPRESSION - Described is an electron spin resonance (ESR) spectrometer comprising a miniaturized radio-frequency (RF) microwave cavity resonator. The miniaturized RF microwave cavity resonator receives a carrier signal from a circulator, modulates the signal path signal, and reflects the carrier signal back to the circulator to amplify the carrier signal prior to demodulation. A mixer receives and demodulates the carrier signal and outputs an audio signal to generate an ESR spectrum for analyzing a chemical composition of a fluid sample. The ESR spectrum represents a magnetic susceptibility of the fluid sample to a magnetic resonance cause variation in a resonant frequency of the miniaturized RF microwave cavity resonator. In a desired aspect, the carrier signal is split into two paths prior to demodulation. The two paths are demodulated by different mixers to produce two separate outputs, an absorption spectrum and a dispersion spectrum. | 2011-02-03 |
| 20110025329 | SYSTEM AND METHOD FOR THERMO-ELECTRIC COOLING OF RF COILS IN AN MR IMAGING SYSTEM - A cooling system for reducing the thermal energy transfer from the heated spots of an RF coil assembly to a patient bore of an MRI system is disclosed. The MRI system includes a plurality of gradient coils positioned about a bore of a magnet, an RF shield formed about an RF space, and an RF coil assembly positioned within the RF space and about the patient bore. The cooling system is positioned within the RF space and includes a plurality of cooling modules configured to reduce an operating temperature of the MRI system. Each of the plurality of cooling modules further includes a thermoelectric cooler thermally coupled to the RF coil and a heat sink thermally coupled to the thermoelectric cooler opposite from the RF coil. The thermoelectric cooler is configured to extract heat from the RF coil when a current is applied to the thermoelectric cooler. | 2011-02-03 |
| 20110025330 | NUCLEAR MAGNETIC RESONANCE GYROSCOPE MECHANIZATION - One embodiment of the invention includes a nuclear magnetic resonance (NMR) gyroscope system. The system includes a gyro cell that is sealed to enclose an alkali metal vapor, a first gyromagnetic isotope, a second gyromagnetic isotope, and a third gyromagnetic isotope. The system also includes a magnetic field generator configured to generate a substantially uniform magnetic field that is provided through the gyro cell to cause the first, second, and third gyromagnetic isotopes to precess. The system further includes an angular rotation sensor configured to measure a rotation angle about a sensitive axis of the NMR gyroscope system based on measured precession angles of the first, second, and third gyromagnetic isotopes. | 2011-02-03 |
| 20110025331 | BODY COIL ASSEMBLY AND METHOD FOR GENERATING RADIO-FREQUENCY FIELD USING THE BODY COIL ASSEMBLY - A body coil assembly for a magnetic resonance apparatus has a first coil and a second coil for generating a radio-frequency field in space, and a power control apparatus connected to the first coil and the second coil for controlling the transmitting power of the first coil and the second coil. In a method for generating a radio-frequency field using such a body coil assembly, the transmitting powers of the first coil and the second coil are controlled, to provide unequal transmitting powers to the first coil and the second coil when needed to generate a required radio-frequency field distribution, so as to form a stronger field strength at a certain position, thus improving the signal to noise ratio at that position during the receiving process. | 2011-02-03 |
| 20110025332 | MRI APPARATUS - An MRI apparatus comprising a magnet structure which delimits a cavity for receiving a body under examination or a part thereof, and which includes means for generating a magnetic field in said cavity, as well as means for causing the body under examination or the part thereof to emit nuclear magnetic resonance signals, a region being defined in the cavity, known as imaging volume, and means for receiving the nuclear magnetic resonance signals. The MRI apparatus also comprises an electronic processing unit with which the means for receiving the nuclear magnetic resonance signals are electrically connected; the cavity has an access opening for receiving a body under examination or part thereof. | 2011-02-03 |
| 20110025333 | SHEAR MODE PRESSURE-ACTIVATED DRIVER FOR MAGNETIC RESONANCE ELASTOGRAPHY - A magnetic resonance elastography (“MRE”) driver that can produce shear waves in a subject without relying on mode conversion of longitudinal waves is disclosed. More specifically, the MRE driver includes a pneumatic driver located remotely from a magnetic resonance imaging (“MRI”) system which is operable in response to an applied electrical current to oscillate, a pressure-activated driver that is positioned on a subject in the MRI system, and a tube that is in fluid communication, at one end, with the pneumatic driver. The pressure-activated driver includes a base plate and a driver plate having a region between them that receives the tube. Oscillations of the pneumatic driver produce a pressure wave in the tube that causes the driver plate to vibrate. The driver plate rests against the subject of interest to apply a corresponding shear oscillatory force to the subject during the MRE examination. | 2011-02-03 |
| 20110025334 | Locating Arrangement and Method Using Boring Tool and Cable Locating Signals - An arrangement and an associated method are described in which a boring tool is moved through the ground within a given region along a path in which region a cable is buried. The boring tool and the cable transmit a boring tool locating signal and a cable locating signal, respectively. Intensities of the boring tool locating signal and the cable locating signal are measured along with a pitch orientation of the boring tool. Using the measured intensities and established pitch orientation, a positional relationship is determined to relative scale including at least the boring tool and the cable in the region. The positional relationship is displayed to scale in one view. The positional relationship may be determined and displayed including the forward locate point in scaled relation to the boring tool and the cable. Cable depth determination techniques are described including a two-point ground depth determination method. | 2011-02-03 |
| 20110025335 | METHOD AND APPARATUS FOR GALVANIC MULTI-FREQUENCY FORMATION RESISTIVITY IMAGING - A formation measurement and processing technique which reduces the effects of standoff between a resistivity tool and a borehole wall where the resistivity tool utilizes capacitive coupling between the tool and the formation to obtain resistivity data useful to generate a resistivity image of the formation. Reduction of standoff effects is achieved through the use of multi-frequency, phase sensitive measurements to identify a measured resonance frequency that may be used to produce an image that utilizes measurements least affected by the tool standoff and unknown or unspecified inductance of the tool. Reduction of standoff effects are the most pronounced in the case of the low resistivity formations and oil-based, low-conductive drilling fluids. | 2011-02-03 |
| 20110025336 | Method and apparatus for well logging resistivity image tomography - A method and apparatus for evaluating an earth formation penetrated by a borehole comprises taking resistivity measurements using a plurality of resistivity arrays or pads positioned within the borehole proximal the borehole wall. In one embodiment, pads are spaced apart azimuthally around the perimeter of a tool body, each pad carrying at least one electrode thereon. A sequence of resistivity measurement operations are performed involving sequentially operating each pad, in turn, as a transmitter, with remaining pads and electrodes operated as return electrodes. The sequence preferably involves a succession of adjacent pads around the perimeter of the tool body, resulting in a full rotational (360°) imaging of the formation penetrated by the borehole. In one embodiment, the pads include at least two electrodes spaced vertically apart from one another, such that helical current paths are defined between transmitting electrodes and return electrodes. | 2011-02-03 |
| 20110025337 | SYSTEM AND METHOD OF TESTING HIGH BRIGHTNESS LED (HBLED) - A system and method of testing High Brightness LED (HBLED) is provided, and more particularly, a system and method of Controlled Energy Testing of HBLED with improved accuracy and repeatability is provided. In one embodiment, the system includes a programmable constant power source for providing a constant power to a Device Under Test (DUT), in this case, an HBLED, wherein the programmable constant power source adjusts an output voltage or an output current to ensure that a given amount of power is supplied to the HBLED for a predetermined amount of time and to provide precise control of a junction temperature of the HBLED for the duration of the test sequences; a Parametric Measurement Unit (PMU) including a processor for executing a plurality of HBLED test sequences, and a spectrometer for measuring a set of HBLED parameters including power and color (wavelength) of an optical output of the HBLED; and a controller for coordinating timing of acquiring the set of measured HBLED parameters. In another embodiment, a photodetector is implemented to measure the integrated power of the optical output of the HBLED. | 2011-02-03 |
| 20110025338 | Monitoring of electroplating additives - The working electrode in the flow channel of a flow-through electrolytic detection cell is preconditioned by flowing a preconditioning electroplating solution with preconditioner species through the flow channel while applying a negative potential. Flow of liquid through the flow channel is rapidly switched from preconditioning solution to a target solution containing an organic target solute to be measured. The transient response of the system resulting from exposure of the working electrode to organic target solute is detected by measuring current density during an initial transient time period. An unknown concentration of target solute is determined by comparing the transient response with one or more transient responses characteristic of known concentrations. A preferred measuring system is operable to switch flow from preconditioning solution to target solution in about 200 milliseconds or less. | 2011-02-03 |
| 20110025339 | MAGNETORESISTIVE ELELCTROSTATIC DISCHARGE (ESD) DETECTOR - A magnetoresistive electrostatic discharge (ESD) event detector includes at least one magnetoresistive device. The at least one magnetoresistive device detects an ESD event in an ESD sensitive device based on magnetoresistive properties of the at least one magnetoresistive device. The at least one magnetoresistive device comprises an ESD failure level that is lower than the ESD failure level of said ESD sensitive device. | 2011-02-03 |
| 20110025340 | SEMICONDUCTOR DEVICE ANALYZER AND SEMICONDUCTOR DEVICE ANALYSIS METHOD - A semiconductor device analyzer comprises a function of radiating a charged particle beam on a sample and displaying a detected secondary electron image according to detected secondary electron intensity. A charged particle beam is radiated according to a first radiation pattern onto a semiconductor device that is to be analyzed, and a charge is injected. Next, a charge accumulation state of the semiconductor device that is to be analyzed is observed. A location where the charge accumulation state is abnormal can be detected as a defect location in the semiconductor device. A defect location is identified easily. | 2011-02-03 |
| 20110025341 | GROUND FAULT DETECTION - A ground fault detection system detects an earth fault or ground fault in a network device. The network device may be used in a fire alarm network. The ground fault detection system includes a power device that electrically isolates the ground fault detection system. A controller sequences a series of switches or relays to charge an energy storing element, such as a capacitor, with the isolated power supply. The capacitor is placed in communication with each port of the network device one at a time. If the connected port includes an inadvertent connection to ground, a detection circuit will detect the bias on the earth ground. The detection circuit may then output an indication of the inadvertent connection to ground to either a workstation or a fire alarm control panel. | 2011-02-03 |
| 20110025342 | REMOTE TEST POINT FOR ELECTRICAL CONNECTOR - A voltage indicating assembly for medium and high voltage systems includes a semiconductive cap configured for mounting on a test point, the test point including a test point terminal element configured to capacitively receive a voltage associated with a electrical component, where the electrical component is mounted in a first location. The semiconductive cap includes a contact element mounted therein configured to electrically communicate with the test point terminal element when the semiconductive cap is mounted on the test point. A cable is electrically coupled to the contact element. A remote test point assembly is electrically coupled to the cable in a second location remote from the first location, and the remote test point assembly includes a remote test point terminal element. | 2011-02-03 |
| 20110025343 | Line Testing - Embodiments related to line testing are described and depicted. | 2011-02-03 |
| 20110025344 | HOLDING MEMBER FOR USE IN TEST AND METHOD FOR MANUFACTURING SAME - A holding member for use in a test includes a base made of silicon or glass and chips in which devices are formed is mountable thereon. Positioning members made of resist sheets are formed on the top surface of the base. A resist film is formed on the bottom surface of the base, and suction grooves (intersection portions, connection portions) and support members are formed in the resist film. Suction holes are formed in regions of the top surface of the base where the chips are mounted, wherein the suction holes are formed through the base and communicate with the suction groove. | 2011-02-03 |
| 20110025345 | ELECTRODE SYSTEM FOR PROXIMITY DETECTION AND HAND-HELD DEVICE WITH ELECTRODE SYSTEM - An electrical hand-held device is provided with improved proximity detection, which can be placed on a surface and has at least one transmission electrode, at least one reception electrode and at least one compensation electrode arranged between transmission electrode and reception electrode. The transmission electrode and the compensation electrode can be supplied with an electric switching signal of predetermined signal frequency and predetermined signal amplitude. Switching electric signal at the compensation electrode is phase-delayed with respect to the switching electric signal at the transmission electrode. Alternating electric fields radiated at the transmission electrode and the compensation electrode generate a current in the reception electrode, which is representative of an approach of a hand to the hand-held device. The transmission electrode and the reception electrode are arranged in such a way, that the impedance between the transmission electrode and the reception electrode exceeds a predetermined value, which is suitable to keep the current generated in the reception electrode under a predetermined value. | 2011-02-03 |
| 20110025346 | POWER SUPPLY NOISE MEASURING CIRCUIT AND POWER SUPPLY NOISE MEASURING METHOD - A power-supply noise measuring circuit includes a voltage fluctuation detecting circuit, a unit time generating circuit: a current measuring circuit, and a sampling circuit. The voltage fluctuation detecting circuit generates a detection current in accordance with a voltage fluctuation of a power supply. The unit time generating circuit generates a unit time in accordance with a clock signal. The current measuring circuit treasures an amount of the detection current per unit time. The sampling circuit samples the amount of the detection current measured by the current measuring circuit, every unit time. The present invention provides the power-supply noise measuring circuit that has a small circuit area and enough accuracy. | 2011-02-03 |
| 20110025347 | Guided wave cutoff spectroscopy using a cylindrical measurement cell - A cylindrical waveguide ( | 2011-02-03 |
| 20110025348 | IMPEDANCE DETERMINATION - Apparatus for use in performing impedance measurements on a subject. The apparatus includes a processing system for causing a first signal to be applied to the subject, determining an indication of a second signal measured across the subject, using the indication of the second signal to determine any imbalance and if an imbalance exists, determining a modified first signal in accordance with the imbalance and causing the modified first signal to be applied to the subject to thereby allow at least one impedance measurement to be performed. | 2011-02-03 |
| 20110025349 | INDUCTIVE POSITION DETECTOR - An inductive detector arranged to measure position along a axis comprising: a transmit winding; a receive winding; a passive circuit comprising a winding in electrical series with a capacitor; wherein: the mutual inductance between the transmit winding and the receive winding is a function of the relative displacement of the passive circuit along the measurement axis; a first portion of one of the windings is wound on a first pitch and a second portion of the same winding is wound on a second pitch whose extent is greater than the first pitch. | 2011-02-03 |
| 20110025350 | Method of measuring micro- and nano-scale properties - This invention is a novel methodology for precision metrology, sensing, and actuation at the micro- and nano-scale. It is well-suited for tiny technology because it leverages off the electromechanical benefits of the scale. The invention makes use of electrical measurands of micro- or nano-scale devices to measure and characterize themselves, other devices, and whatever the devices subsequently interact with. By electronically measuring the change in capacitance, change in voltage, and/or resonant frequency of just a few simple test structures, a multitude of geometric, dynamic, and material properties may be extracted with a much higher precision than conventional methods. | 2011-02-03 |
| 20110025351 | COMBINED ELECTRICAL AND OPTICAL SENSOR FOR FLUIDS - The present invention relates to a sensor for the detection of an analyte, comprising a fluid holder ( | 2011-02-03 |
| 20110025352 | TOUCH DEVICE AND CONTROL METHOD - A touch device includes a first conductive film, a plurality of first electrodes, a first auxiliary electrode, a plurality of second electrodes, a second auxiliary electrode, and a second conductive film. The first conductive film has a first side, a second side, a first area, and a second area. The first electrodes are disposed at the portion of the first side located at a side of the first area. The first auxiliary electrode is disposed at the portion of the first side located at a side of the second area. The second electrodes are disposed at the portion of the second side located at another side of the second area. The second auxiliary electrode is disposed at the portion of the second side located at another side of the first area. The second conductive film is disposed beside the first conductive film. | 2011-02-03 |
| 20110025353 | METHOD FOR INCREASING THE AVAILABILITY OF DISPLACEMENT/POSITION MEASURING SYSTEMS ON THE BASIS OF POTENTIOMETERS WITH A SLIDER TAP - The disclosure relates to a method for increasing the availability of displacement/position measuring systems on the basis of potentiometers with a slider tap in a closed control loop, the controller of which is formed by a microcontroller which is supplied with the position of the slider via an analog/digital converter. The position of a defective slider position of the potentiometer is determined within the active process task by evaluating an available control loop variable, and the reference variable of the control loop is overloaded in a defined manner such that the defective slider position is passed over during the displacement/position measurement and an intact slider position is reached. | 2011-02-03 |
| 20110025354 | INSPECTION APPARATUS FOR PHOTOVOLTAIC DEVICES - The present invention provides an inspection apparatus for photovoltaic devices which electrifies the photovoltaic devices in a forward direction thereof to make the photovoltaic devices emit electro-luminescence light and which has a simple-structured and cheap darkroom. The inspecting apparatus of the present invention includes a darkroom ( | 2011-02-03 |
| 20110025355 | APPARATUS FOR ADJUSTING DIFFERENTIAL PROBE - An apparatus for adjusting a differential probe includes a regulator arranged therein capable of adjusting a distance between two tips of the probe. The probe is supported on the apparatus. The apparatus includes a rotatable shaft and a rotatable disk. The rotatable shaft engages with the regulator of the probe. The rotatable disk is mounted surrounding the rotatable shaft and rotatable together with the rotatable shaft. An angular ruler or a radian ruler is described on an outer surface of the rotatable disk to indicate a rotation angle or a rotation radian of the rotatable shaft, therefore the distance between the two tips of the probe are accurately adjusted. | 2011-02-03 |
| 20110025356 | METHOD FOR MAKING ELECTRICAL TEST PROBE CONTACTS - A method of testing an electrical component includes coupling the electrical component to at least a first probe, a second probe, and a third probe. The probes are in communication with a test control module. Furthermore, the method includes confirming that the probes are in sufficient electrical connection with the electrical component by allowing the test control module to supply a current through the electrical component via the first probe and the third probe, and simultaneously detecting a potential difference across the electrical component by the second probe and the third probe. Furthermore, the method includes testing a performance characteristic of the electrical component by supplying a redundant signal to the electrical component via at least two of the first probe, the second probe, and the third probe. | 2011-02-03 |
| 20110025357 | IC Test Substrate for Testing Various Signals - The present invention provides on IC test substrate for testing various signals, a combined flexible and rigid PCB included in the structure is applicable to perform a mission including for example: stabilizing power input/output, signal transfer by a connector; general, power, and high frequency signal transmission in preserved integrity state. | 2011-02-03 |
| 20110025358 | PROBE UNIT - A probe unit includes: large diameter probes; a small diameter probes; a large-diameter probe holder having large hole portions which individually hold the large diameter probes, and hole portions which have diameters smaller than those of the large hole portions, communicate with the large hole portions, and receive end portions of the small diameter probes so that the end portions come into contact with the large diameter; and a small-diameter probe holder probes having small hole portions which individually hold the small diameter probes The central axes of the large hole portion and the small hole portion that communicate with each other are separated from each other, and the small hole portions include two small hole portions which are adjacent to each other and of which central axes are separated from each other by a distance shorter than a distance between the central axes of two large hole portions that are corresponding to the two small hole portions. | 2011-02-03 |
| 20110025359 | BOND AND PROBE PAD DISTRIBUTION - An integrated circuit (IC) that includes a plurality of bond pads disposed on a surface of the IC and a plurality of probe pads disposed on the surface of the IC is provided. Each of the plurality of probe pads is in electrical communication with corresponding bond pads. The plurality of probe pads are linearly configured across the surface. In one embodiment, the probe pads are disposed along a diagonal of the surface of the die defined between opposing vertices of the die surface. In another embodiment, multiple rows of linearly disposed probe pads are provided on the surface. | 2011-02-03 |
| 20110025360 | SEMICONDUCTOR INTEGRATED CIRCUIT TEST DEVICE - A semiconductor IC test device includes: an IC tester providing first and second control signals (CS | 2011-02-03 |
| 20110025361 | HIGH PERFORMANCE PROBE SYSTEM - A probe system for providing signal paths between an integrated circuit (IC) tester and input/output, power and ground pads on the surfaces of ICs to be tested includes a probe board assembly, a flex cable and a set of probes arranged to contact the IC's I/O pads. The probe board assembly includes one or more rigid substrate layers with traces and vias formed on or within the substrate layers providing relatively low bandwidth signal paths linking the tester to probes accessing some of the IC's pads. The flex cable provides relatively high bandwidth signal paths linking the tester to probes accessing others of the IC's pads. | 2011-02-03 |
| 20110025362 | APPARATUS AND METHOD FOR MEASURING PHASE NOISE/JITTER IN DEVICES UNDER TEST - A system for testing integrated circuit products and other devices under test (DUT) includes a DUT tester, which stimulates the devices under test and analyzes signals from the devices under test. A device interface board transports signals between the DUT tester and the devices under test. A test board is coupled to the device interface board and used to generate measurements associated with the devices under test, such as phase noise or phase jitter measurements. The test board could, for example, include a phase detector for detecting a phase difference between two signals and a control loop for adjusting at least one of the two signals to maintain an average of zero DC volts at an output of the phase detector. A customization module could also be used to customize the test board. The customization module could include a phase shifter, a phase-locked loop synthesizer, and/or an oscillator. | 2011-02-03 |
| 20110025363 | METHOD AND DEVICE FOR DETECTING FOREIGN PARTICLE IN LIQUID CRYSTAL DISPLAY PANEL - A method for detecting a foreign particle trapped between substrates of a liquid crystal display panel, by which a potential short caused by the particle can be made into a short with reliability, and thus it is possible to make a display defect manifest itself that is caused by the particle. The method is for detecting the presence of a foreign particle trapped between flexible substrates ( | 2011-02-03 |
| 20110025364 | Test Mode Signal Generating Device - Various embodiments of a test mode signal generating device are disclosed. The device includes first and second test mode signal generating units. The first test mode signal generating unit is configured to receive test address signals to generate a first test mode signal when a first mode conversion signal is enabled. The first test mode signal generating unit is also configured to enable a second mode conversion signal when the test address signals correspond to a first predetermined combination. The second test mode signal generating unit is configured to receive the test address signals to generate a second test mode signal when the second mode conversion signal is enabled. The second test mode signal generating unit is also configured to enable the first mode conversion signal when the test address signals correspond to a second predetermined combination. | 2011-02-03 |
| 20110025365 | Circuit Arrangement and Method for Testing a Reset Circuit - A circuit arrangement ( | 2011-02-03 |
| 20110025366 | TEST DEVICE FOR TESTING TRANSISTOR CHARACTERISTICS IN SEMICONDUCTOR INTEGRATED CIRCUIT - A test device of a semiconductor integrated circuit includes: an oscillation unit including a plurality of oscillation circuits and configured to activate the respective oscillation circuits in response to a test mode signal and output a plurality of oscillation signals; a switching unit configured to extract only an activated signal among the plurality of oscillation signals; a frequency division unit configured to divide a signal outputted from the switching unit at a predetermined division ratio and generate a divided oscillation signal; and a data buffer unit configured to buffer the divided oscillation signal to output through a data pad. | 2011-02-03 |
| 20110025367 | ENERGY FEEDBACK DEVICE FOR THE WARM-UP TEST OF A POWER SUPPLY - This invention relates to an energy feedback device for the warm-up test of a power supply, which includes a power supply, a current limiter, a transformer and a selector. Moreover, the power supply is a target load tested by a warm-up procedure; external input power enters the selector, and the other end of the selector is electrically connected to the power supply. The current limiter is used to adjust the warm-up power consumed by the load of the power supply under testing. One end of the current limiter is electrically connected to another end of the power supply, and another end of current limiter is electrically connected with the voltage adapter; and another end of the voltage adapter is electrically connected to another end of the selector. Therefore, the device of this invention can effectively provide enhancing the efficiency of power is consumption, over-current protection and multiple application of energy feedback. | 2011-02-03 |
| 20110025368 | POWER SOURCE DEVICE AND IMAGE FORMING APPARATUS HAVING THE SAME - A power source device includes a main power source for outputting a direct current voltage with a specific value; a monitoring unit connected to the main power source for comparing the direct current voltage with a reference voltage to monitor whether a malfunction occurs in the main power source; and a monitoring display unit connected to the monitoring unit. The monitoring unit includes a comparison unit for comparing the direct current voltage with the reference voltage, and a monitoring control unit for detecting a signal of the comparison unit and for storing and displaying the direct current voltage on the monitoring display unit when the malfunction occurs in the main power source. | 2011-02-03 |
| 20110025369 | METHOD AND SYSTEM FOR TESTING ELECTRIC AUTOMOTIVE DRIVE SYSTEMS - Various methods and systems for testing electric automotive drive systems are provided. The methods may be implemented with components with components that are used during normal operation of the automobile, such an inverter, an electric motor, and an electronic control system. One such method includes adjusting the frequency of a current pulsed input provided to an electric motor while monitoring the winding currents. Another method includes monitoring current flow during and after a direct current (DC) pulse is generated by switches within an inverter. A further method includes monitoring current flow while a deactivation signal is provided to the switches and during individual activation of the switches. | 2011-02-03 |
| 20110025370 | Method and System for Testing Yawing System for Wind Turbine - A system and method is provided for ground testing of a yaw system of a nacelle ( | 2011-02-03 |
| 20110025371 | METHOD FOR DETECTING A FAULT IN AN INDUCTION MACHINE - The invention concerns a method for detecting a fault in a rotating field machine, in which current components are analysed in a flux-based, particularly rotor-flux-based, coordinate system a flux-forming current component being subjected to a frequency analysis in the flux-based, particularly rotor-flux-based, coordinate system. It is endeavoured to provide a simple method for an early detection of faults. For this purpose, a current operating point is detected for at least one predetermined supply frequency (f | 2011-02-03 |
| 20110025372 | METHOD AND APPARATUS FOR REDUCING RADIATION AND CROSS-TALK INDUCED DATA ERRORS - The different advantageous embodiments provide an integrated circuit comprising a number of latches and a number of filters. Each latch in the number of latches has a plurality of inputs and a plurality of storage nodes. The plurality of storage nodes includes a number of pairs of circuit nodes that form a number of upsettable circuit node pairs. Each input of the plurality of inputs is connected to a corresponding storage node in the plurality of storage nodes. Each filter in the number of filters has an input and a plurality of outputs. Each of the plurality of outputs is connected to a corresponding input of the plurality of inputs of a latch in the number of latches. Each filter in the number of filters is located between two circuit nodes forming an upsettable circuit node pair of the latch in the number of latches to increase critical node spacing. | 2011-02-03 |
| 20110025373 | Semiconductor devices having ZQ calibration circuits and calibration methods thereof - Provided is a semiconductor device for performing a calibration operation without an external ZQ calibration command and a calibration method thereof. The semiconductor device includes a calibration circuit for performing a pull-down calibration operation in response to a pull-down calibration enable signal and a command control unit for generating the pull-down calibration enable signal in response to a DLL reset signal. The calibration method includes adjusting an impedance of a first pull-up resistance structure in response to pull-up calibration codes having a default value. A pull-down calibration enable signal may be generated in response to a DLL reset signal. A voltage of the first node and a reference voltage are compared by a comparator. The comparator outputs pull-down calibration codes based on the comparison. An impedance of a pull-down resistance structure is adjusted, so a resistance of the pull-down resistance structure is equal to a resistance of the first pull-up resistance structure. | 2011-02-03 |
| 20110025374 | Multi-Drop Bus System - A multi-drop bus system and a method for operating such a system. The system includes a multi-drop bus having at least one bus line, each bus line being made up of a multiple of line segments. Each of the line segments terminates at a drop point and each drop point is coupled to a load impedance. The characteristic impedance of a line segment is matched to the equivalent impedance presented by the load impedance in combination with the characteristic impedance of a following segment, or is matched to the load impedance if there is no following segment. | 2011-02-03 |
| 20110025375 | CMOS CIRCUITRY WITH MIXED TRANSISTOR PARAMETERS - CMOS circuitry having mixed threshold voltages is disclosed. Circuits may be implemented using PMOS transistors, NMOS transistors, or both. For at least one given type of transistor (PMOS or NMOS), a circuit includes at least one transistor configured to switch at a first nominal threshold voltage and at least one transistor configured to switch at a second nominal threshold voltage. The different threshold voltages among a given transistor type are realized by varying the thickness of the transistor gate oxides and/or the channel dopant density, for example. | 2011-02-03 |
| 20110025376 | System for the flexible configuration of functional modules - A system for the flexible configuration of function modules. The system includes the following components a plurality of logic cells in a fixedly wired FPGA/standard ASIC structure, wherein the logic cells are so configurable by means of configuration registers, that they execute basic logic functions; a switch matrix having a plurality of memory cells, via which different logical connections of the logic cells in defined complex connections are configurable by means of the configuration registers; and a control unit, which partially dynamically so configures the logic cells and the switch matrix via an internal bus and via the configuration registers by means of a configuration bit stream, that the fixedly wired FPGA/ASIC structure behaves functionally as a partially dynamically reconfigurable logic chip. | 2011-02-03 |
| 20110025377 | Circuit Arrangement and Method for Evaluating a Data Signal - A circuit arrangement ( | 2011-02-03 |
| 20110025378 | SEMICONDUCTOR INTEGRATED CIRCUIT AND LAYOUT METHOD THEREOF - A layout method for a semiconductor integrated circuit includes, generating logic cell layout data by arranging logic cells and signal lines connected to said logic cells, by using an automatic place and root tool, generating variable capacitor cell layout data by arranging variable capacitor cells and control lines for controlling capacitance value of the variable capacitor cells, by using the automatic place and root tool, and generating layout data of the semiconductor integrated circuit, based on the logic cell layout data and the variable capacitor cell layout data. The generating variable capacitor cell layout data includes, arranging the control lines so as to be same as said signal lines in a resistance of a unit length in one wiring layer. | 2011-02-03 |
| 20110025379 | LATCHED COMPARATOR AND METHODS THEREFOR - A compare cycle of a comparator includes a precharge phase and a compare phase. During the precharge phase, a node of the comparator is precharged to a defined voltage. In addition, during the precharge phase an input transistor of the comparator is decoupled from the node. During the compare phase, an input voltage is coupled to the node via the input transistor. The input transistor is maintained in saturation during both the precharge phase and the compare phase, reducing switching noise. | 2011-02-03 |
| 20110025380 | OUTPUT DRIVER OPERABLE OVER WIDE RANGE OF VOLTAGES - An output driver includes a pull-up circuit and a pull-down circuit coupled to an output terminal and a capacitor having a first terminal coupled to a gate terminal of a P-channel transistor of the pull-up circuit and a second terminal configured to receive a drive signal. The output driver further includes a drive circuit coupled to the first terminal of the capacitor and configured to transfer charge from a power supply node to the first terminal of the capacitor when the drive signal is at a signal ground voltage and to decouple the first terminal of the capacitor from the power supply node when the drive signal is at a voltage level greater than the signal ground voltage such that a voltage swing of a signal generated at the gate terminal of the P-channel transistor is constrained to be less than a voltage of the power supply node with respect to the signal ground voltage. | 2011-02-03 |
| 20110025381 | MULTI-PHASE CLOCK DIVIDER CIRCUIT - A divider circuit for dividing the frequency of a multi-phase clock signal, which can ensure a sufficient data latch time even if the multi-phase clock signal has a high frequency, includes a main latch circuit which generates an inverted data signal using, for example, two of eight clock signals of an eight-phase clock signal, and a sub-latch circuit which uses the eight clock signals as a trigger to receive the inverted data signal as a common data signal. | 2011-02-03 |
| 20110025382 | FREQUENCY DIVIDER - A frequency divider ( | 2011-02-03 |
| 20110025383 | METHOD OF ENHANCING POWER SAVING IN AN INTEGRATED ELECTRONIC SYSTEM WITH DISTINCTLY POWERED ISLANDS OF FUNCTIONAL CIRCUITRIES AND RELATED DEVICE ARCHITECTURE - A method for power saving in an integrated circuit device may include defining an off-switchable analog circuit island including an internal clock generating circuit, and at power-on of the integrated circuit device, supplying to clocked digital circuits of the integrated circuit device an auxiliary clock from the external controller. The auxiliary clock has a frequency determined by the external controller and being lower than the root clock signal. The method includes supplying external reset commands to the integrated circuit device until an active functioning condition of the integrated circuit device is asserted, and interrupting the supply of the auxiliary clock and enabling supply of the root clock signal to the clocked digital circuits when the active functioning condition of the integrated circuit device is asserted. | 2011-02-03 |
| 20110025384 | DEVICE FOR GENERATING CLOCK IN SEMICONDUCTOR INTEGRATED CIRCUIT - Various embodiments of a semiconductor integrated circuit. According to one exemplary embodiment, a semiconductor integrated circuit includes a multi-phase clock generator that is configured to generate a multi-phase internal clock; a first edge combining unit that is configured to generate a first output clock having a first frequency by combining rising edges of clocks included in the internal clock, and transmit the first output clock to a first port; and a second edge combining unit that is configured to generate a second output clock having a second frequency by combining rising edges of clocks included in the internal clock, and transmit the output clock to a second port. | 2011-02-03 |
| 20110025385 | Power Supply Noise Rejection in PLL or DLL Circuits - A phase controller can be part of a phase-locked loop (PLL) or a delay-locked loop (DLL). The phase controller includes first and second regulators. The first regulator provides power supply noise rejection while the second regulator provides phase and frequency lock. | 2011-02-03 |
| 20110025386 | Phase-Locked Loop - A loop filter for a phase-locked loop that generates an output signal having a predetermined phase relationship with a reference signal, the loop filter being arranged to control a signal generator that forms the output signal in dependence on a phase error between the output signal and the reference signal by outputting a control signal for controlling the signal generator in dependence thereon, the loop filter being arranged to form the control signal to comprise a proportional component representative of an instantaneous magnitude of the phase difference and an integral component representative of an integral of the phase difference, the loop filter comprising a proportional path arranged to receive a signal representative of the instantaneous magnitude of the phase difference and form the proportional component of the control signal in dependence thereon and an integral path arranged to receive a signal representative of the instantaneous magnitude of the phase difference and form the integral component of the control signal in dependence thereon, the proportional and integral paths being decoupled in the loop filter such that each has a transfer function relating its received signal to its respective component of the control signal that is independent of the other path. | 2011-02-03 |
| 20110025387 | Charge Transfer in a Phase-Locked Loop - A phase-locked loop arranged to generate an output signal having a first frequency that is a static value times the frequency of a reference signal, the phase-locked loop comprising a signal generator arranged to generate the output signal, a divider arranged to receive the output signal and divide the output signal to form a feedback signal, the divider being arranged to vary the divisor by which the output signal is divided to cause the output signal to have a frequency that is said static value times the frequency of the reference signal, a comparison unit arranged to compare the feedback signal with the reference signal, one or more current generators arranged to output current pulses in dependence on said comparison, a summation unit arranged to receive the current pulses output by the current generator(s) and form a single current pulse therefrom and a loop filter arranged to filter the single current pulse to form a control signal for controlling the signal generator, the phase-locked loop being arranged such that the current generator(s) generate(s) a first current pulse dependent on a phase-difference between the feedback signal and the reference signal and a second current pulse whose magnitude and sign are dependent on an error in the feedback signal that is caused by the variation of the divisor, and the summation unit receives the first and second current pulses and stores an electrical charge representative of those current pulses and the summation unit outputs a single current pulse dependent on the electrical charge stored by the summation unit, said single current pulse being representative of a phase-difference that would have existed between the reference signal and the feedback signal if the feedback signal had been formed by dividing the output signal by said static value and not by the varied divisor. | 2011-02-03 |
| 20110025388 | Charge Pump For Phase-Locked Loop - A current generator for a phase-locked loop arranged to generate an output signal having predetermined frequency-relationship with a reference signal, the phase-locked loop comprising a signal generator arranged to generate the output signal, a divider arranged to receive the output signal and divide the output signal to form a feedback signal, the divider being arranged to vary the divisor by which the output signal is divided, a comparison unit arranged to compare the feedback signal with the reference signal and output a first error signal indicative of the phase-difference between the feedback signal and the reference signal to the current generator and a loop filter arranged to filter a current signal output by the current generator to form a control signal for controlling the signal generator, the current generator being capable of receiving the first error signal and generating a current in dependence thereon, receiving a second error signal indicative of an error in the feedback signal caused by the variation of the divisor by which the output signal is divided and generating a current having a magnitude and sign that is dependent on that error and combining the currents generated in dependence on the first error signal and the second error signal to form a current signal output to the loop filter that is representative of an overall error in the output signal of the phase-locked loop relative to the reference signal. | 2011-02-03 |
| 20110025389 | CLOCK JITTER COMPENSATED CLOCK CIRCUITS AND METHODS FOR GENERATING JITTER COMPENSATED CLOCK SIGNALS - Clock circuits, memories and methods for generating a clock signal are described. One such clock circuit includes a delay locked loop (DLL) configured to receive a reference clock signal and generate an output clock signal having an adjustable phase relationship relative to the reference clock signal, and further includes a clock jitter feedback circuit coupled to a clock tree and the DLL. The clock jitter feedback circuit is configured to synchronize a clock jitter feedback signal and a DLL feedback signal that is based on the output clock signal. The clock jitter feedback circuit is further configured to provide the clock jitter feedback signal to the DLL for synchronization with a buffered reference clock signal. The clock jitter feedback signal is based on and generated in response to receiving a distributed output clock signal from the clock tree circuit and the buffered reference signal is based on the reference clock signal. | 2011-02-03 |
| 20110025390 | UPDATE CONTROL APPARATUS IN DLL CIRCUIT - An update control apparatus in a DLL circuit is provided. The update control apparatus includes a logic value determination, a phase information collection unit, and an update control unit. The logic value determination unit is configured to determine a logic value of a phase detection signal for a first period interval of a reference clock signal to generate a phase information signal, and configured to extend the first period interval into a second period interval when an extension instruction signal is enabled. The phase information collection unit is configured to determine consecutive logic values of an update possible signal to generate the extension instruction signal, and configured to collect the phase information signal to generate an update information signal. The update control unit is configured to generate the update possible signal, a valid interval signal, and an update control signal in response to the update information signal. | 2011-02-03 |
| 20110025391 | Methods and Systems for Measuring and Reducing Clock Skew - A technique for a delay measurement system to measure the skews in a clock distribution network is presented. It uses the principle of sub-sampling to measure and amplify small clock skews and determine an estimate of clock skew by further manipulation if these sampled measurements. The technique can be applied to measure clock skew on a computer chip, between bit-line of a communication bus, or between elements connected by an electronic or optical interconnect. | 2011-02-03 |
| 20110025392 | Duty cycle correction method and its implementing circuit - A duty cycle correction method comprises detecting independently a relative delay time of two input differential signals; equating the sum of two relative delay time with the cycle of the input differential signals; and adjusting the two delay time to the same value. A corresponding implementation circuit comprises two time delay units; two correlation phase detectors connecting simultaneously with each of the two time delay units; a charge pump connecting with the output of each of the two correlation phase detectors, with its output connecting to the two time delay units in order to form a loop; and a synthesis output unit connecting with both the time delay units, thereby generating output signals. The adjusting range of duty cycle becomes much wider. The implementation circuit is absolutely symmetrical, so a duty cycle with high accuracy can be obtain. | 2011-02-03 |
| 20110025393 | Leakage Power Optimized Structure - A digital latch circuit substantially reduces leakage current in output stages of edge-triggered digital switching devices. The circuit comprises first and second NAND gates for receiving first and second input signals and providing first and second output signals. The first NAND gate includes a first A input for receiving the first input signal, a first B input connected to a second NAND gate output, a first leakage current control input connected to a second A input of the second NAND gate, and a first NAND gate output for providing the first output signal. The second NAND gate includes the second A input for receiving the second input signal, a second B input connected to the first NAND gate output, a second leakage current control input connected to the first A input of the first NAND gate, and the second NAND gate output for providing the second output signal. The leakage current through the first NAND gate is substantially reduced based on application of the second input signal to the first leakage current control input. Similarly, the leakage current through the second NAND gate is substantially reduced based on application of the first input signal to the second leakage current control input. This circuit may comprise a set-reset latch in an output stage of an edge-triggered sequential switching device, such as a D flip-flop or a JK master-slave flip-flop. | 2011-02-03 |
| 20110025394 | LOW LATENCY SYNCHRONIZER CIRCUIT - A synchronizer circuit includes a master stage and a slave stage. The master stage may include a first master latch coupled to receive a data input signal, and a clock signal. The master stage may also include a second master latch coupled to receive the data input signal, and a delayed version of the clock signal. The master stage may further include a pull-up circuit that may drive an output line of the master stage depending upon an output of each of the first master latch and the second master latch. The slave stage may include a slave latch having an input coupled to the output line of the master stage. The slave stage may provide an output data signal that corresponds to the captured input data signal and is synchronized to the receiving clock signal. | 2011-02-03 |
| 20110025395 | SYSTEM AND METHOD FOR COMPENSATING PULSE GENERATOR FOR PROCESS AND TEMPERATURE VARIATIONS - An apparatus for generating a pulse having a pulse width substantially independent of process variation in resistive and capacitive values. The apparatus includes a PTAT current source to generate a first current to charge a capacitor to produce a first voltage; a ΔVGS current source to generate a second current through a resistor to produce a second voltage V | 2011-02-03 |
| 20110025396 | Digital Attenuator Circuits and Methods for Use thereof - An attenuator system includes a first adjustable impedance component on a first current path between a input component and a output component, and a second adjustable impedance component between the first current path and ground, wherein each of the first and second adjustable impedance components include a plurality of selectable, discrete legs, each leg having an impedance. | 2011-02-03 |
| 20110025397 | DRIVER CIRCUIT FOR GALLIUM NITRIDE (GaN) HETEROJUNCTION FIELD EFFECT TRANSISTORS (HFETs) - A driver circuit and integrated circuit implementation of a driver circuit for driving a GaN HFET device is disclosed. The driver circuit includes a resonant drive circuit having an LC circuit with an inductance and a capacitance. The capacitance of the LC circuit includes the gate-source capacitance of the GaN HFET device. The driver circuit further includes a level shifter circuit configured to receive a first signal and to amplify the first signal to a second signal suitable for driving a GaN HFET device. The resonant drive circuit is controlled based at least in part on the second signal such that the resonant drive circuit provides a first voltage to the GaN HFET device to control the GaN HFET device to operate in a conducting state and to provide a second voltage to the GaN HFET device to control the GaN HFET device to operate in a non-conducting state. | 2011-02-03 |
| 20110025398 | Level Shifting Circuit - A level shifting circuit including a driving circuit, a reset circuit, a coupling circuit and an output-stage circuit is provided. The driving circuit, controlled by the input signal, controls the first driving signal having a high voltage level in the first period and controls the first driving signal having a low reference level in the second period. The reset circuit, controlled by the first driving signal in the first period, resets the second driving signal having the low reference level. The coupling circuit, controlled by the falling edge of the input-inversed signal, controls the second driving signal having a low voltage coupling level in the second period. The output-stage circuit, controlled by the first and the second driving signal, controls the output signal having a high voltage level in the second period and controls the output signal having a low voltage level in the first period. | 2011-02-03 |
| 20110025399 | AMPLITUDE CONVERSION CIRCUIT - In an amplitude conversion circuit that converts an input signal having a small amplitude into an output signal having a large amplitude, the input signal is supplied to a gate of a transistor that discharges an output terminal through a capacitance element. A charging/discharging circuit causes a gate voltage of the transistor to be substantially equal to a threshold voltage during an inactive period of the input signal. | 2011-02-03 |
| 20110025400 | ELECTRONIC DC CIRCUIT BREAKER - The present invention relates to a device for connecting and breaking DC power comprising an input DC power (DC-In) arranged to be connected to a circuit board ( | 2011-02-03 |
| 20110025401 | SWITCH CONTROLLING CIRCUIT, SWITCH CIRCUIT UTILIZING THE SWITCH CONTROLLING CIRCUIT AND METHODS THEREOF - A switch controlling circuit, which comprises: a frequency programmable clock signal generator and a plurality of registers. The frequency programmable clock signal generator serves to generate a frequency controllable clock signal. The registers comprises: a first stage register, for receiving an input signal and the frequency controllable clock signal, and for outputting a first output signal, which is utilized to control a first switch device, according to the input signal and the frequency controllable clock signal; and a second stage register, for receiving the first output signal and the frequency controllable clock signal, and for outputting a second output signal, which is utilized to control a second switch device, according to the first output signal and the frequency controllable clock signal. | 2011-02-03 |
| 20110025402 | CHOPPING TECHNIQUE FOR CONTINUOUS TIME SIGMA-DELTA ADCS WITHOUT Q-NOISE FOLDING - A chopping transconductor includes an transconductor input stage coupled with input signals of the chopping transconductor; a chopping switch coupled with an output of the transconductor input stage, the chopping switch having a switch output; and a cascode transistor, wherein the switch output is coupled to an output of the chopping transconductor through the cascode transistor. The chopping transconductor may be used in an analog-to-digital converter to isolate chopping switches from junctions with quantization noise. | 2011-02-03 |
| 20110025403 | SWITCH WITH IMPROVED BIASING - Switches with improved biasing and having better isolation and reliability are described. In an exemplary design, a switch is implemented with a set of transistors, a set of resistors, and an additional resistor. The set of transistors is coupled in a stacked configuration, receives an input signal, and provides an output signal. The set of resistors is coupled to the gates of the set of transistors. The additional resistor is coupled to the set of resistors and receives a control signal for the set of transistors. The resistors reduce signal loss through parasitic capacitances of the transistors when they are turned on. The resistors also help split the signal swing of the input signal approximately evenly across the transistors when they are turned off, which may improve reliability of the transistors. The switch may be used in a switchplexer, a power amplifier (PA) module, etc. | 2011-02-03 |
| 20110025404 | SWITCHES WITH VARIABLE CONTROL VOLTAGES - Switches with variable control voltages and having improved reliability and performance are described. In an exemplary design, an apparatus includes a switch, a peak voltage detector, and a control voltage generator. The switch may be implemented with stacked transistors. The peak voltage detector detects a peak voltage of an input signal provided to the switch. In an exemplary design, the control voltage generator generates a variable control voltage to turn off the switch based on the detected peak voltage. In another exemplary design, the control voltage generator generates a variable control voltage to turn on the switch based on the detected peak voltage. In yet another exemplary design, the control voltage generator generates a control voltage to turn on the switch and attenuate the input signal when the peak voltage exceeds a high threshold. | 2011-02-03 |
| 20110025405 | SWITCHING CIRCUIT - A switching circuit includes a first switching module, a second switching module, a first relay module, a second relay module, and a processing module. The first switching module includes a switch and a first transistor. The base of the first transistor functions as a first reset terminal. The second switching module includes a second transistor. An output terminal of the second relay module functions as a second reset terminal. Two input terminals of the processing module are connected to the first and second reset terminals respectively. The processing module resets a system with a first type or a second type according to voltages of the first and second reset terminals. | 2011-02-03 |
| 20110025406 | Power Semiconductor Component Including a Potential Probe - A power semiconductor component including a semiconductor body and two load terminals is provided. Provided furthermore is a potential probe positioned to tap an electric intermediate potential of the semiconductor body at a tap location of the semiconductor body for an electric voltage applied across the two load terminals, the intermediate potential being intermediate to the electric potentials of the two load terminals, but differing from each of the two electric potentials of the two load terminals. | 2011-02-03 |
| 20110025407 | DYNAMICALLY DRIVEN DEEP N-WELL CIRCUIT - A circuit can include an NMOS transistor having a drain and a source, a p-well containing the drain and the source, an n-well under the p-well, a circuit node, and a connection element connecting the n-well to the circuit node. The connection element can include a diode having an anode terminal connected to the circuit node and a cathode terminal connected to the n-well, a resistor having a first terminal connected to the circuit node and a second terminal connected to the n-well, a conductor directly connecting the n-well to the circuit node, or a well switch configured to connect the n-well to the circuit node during an enable phase of a switching signal and to electrically float the n-well during a non-enable phase of the switching signal. The diode can include a diode-connected transistor. The circuit node can be configured to receive a predetermined voltage having a magnitude equal to or greater than an upper supply voltage. | 2011-02-03 |
| 20110025408 | SWITCHES WITH BIAS RESISTORS FOR EVEN VOLTAGE DISTRIBUTION - Switches with connected bulk for improved switching performance and bias resistors for even voltage distribution to improve reliability are described. In an exemplary design, a switch may include a plurality of transistors coupled in a stack and at least one resistor coupled to at least one intermediate node in the stack. The transistors may have (i) a first voltage applied to a first transistor in the stack and (ii) a second voltage that is lower than the first voltage applied to bulk nodes of the transistors. The resistor(s) may maintain matching bias conditions for the transistors when they are turned off. In one exemplary design, one resistor may be coupled between the source and drain of each transistor. In another exemplary design, one resistor may be coupled between each intermediate node and the first voltage. The resistor(s) may maintain the source of each transistor at the first voltage. | 2011-02-03 |
| 20110025409 | Semiconductor integrated circuit device - A semiconductor integrated circuit device for fast and low power operations, comprising a plurality of circuit blocks of a chip, each of which has a plurality of states with different power consumption values. A power management circuit determines the state of each of the circuit blocks so as not to exceed a maximum power consumption value of the semiconductor integrated circuit device by considering the power consumption of each circuit block and by each state transition in each circuit block. The maximum power consumption value may be preset or adjustable after fabrication. | 2011-02-03 |
| 20110025410 | Resonant Circuits - Embodiments of the invention relate to resonant circuits; particularly but not exclusively the embodiments relate to resonant circuits in RPID (radio frequency identification) responsive to a wide frequency range. A controllable electric resonator comprising an inductor coupled to a first capacitor to form a resonant circuit, the resonator further comprising a controllable element, a second capacitor controllable coupled across said first capacitor by said controllable element, and a control device to control said controllable element such that a total effective capacitance of said first and second capacitor varies over a duty cycle of an oscillatory signal on said resonator. | 2011-02-03 |
| 20110025411 | Apparatus and Method for Tuning a GM-C Filter - An apparatus to control a tuneable Gm-C filter, including and a filter that can be reconfigured as a free running oscillator by toggling the feedback sign of an output amplifier ( | 2011-02-03 |
