05th week of 2011 patent applcation highlights part 12 |
Patent application number | Title | Published |
20110024711 | APPARATUS FOR REDUCING PHOTODIODE THERMAL GAIN COEFFICIENT AND METHOD OF MAKING SAME - An apparatus for reducing photodiode thermal gain coefficient includes a bulk semiconductor material having a light-illumination side. The bulk semiconductor material includes a minority charge carrier diffusion length property configured to substantially match a predetermined hole diffusion length value and a thickness configured to substantially match a predetermined photodiode layer thickness. The apparatus also includes a dead layer coupled to the light-illumination side of the bulk semiconductor material, the dead layer having a thickness configured to substantially match a predetermined thickness value and wherein an absolute value of a thermal coefficient of gain due to the minority carrier diffusion length property of the bulk semiconductor material is configured to substantially match an absolute value of a thermal coefficient of gain due to the thickness of the dead layer. | 2011-02-03 |
20110024712 | PCM With Poly-Emitter BJT Access Devices - A phase change memory (PCM) includes an array comprising a plurality of memory cells, a memory cell comprising a phase change element (PCE); and a PCE access device comprising a bipolar junction transistor (BJT), the BJT comprising an emitter region comprising a polycrystalline semiconductor. A memory cell for a phase change memory (PCM) includes a phase change element (PCE); and a PCE access device comprising a bipolar junction transistor (BJT), the BJT comprising an emitter region comprising a polycrystalline semiconductor. | 2011-02-03 |
20110024713 | NONVOLATILE MEMORY DEVICE AND METHOD FOR MANUFACTURING SAME - According to one embodiment, a nonvolatile memory device includes a stacked body including a first layer, a second layer and a recording layer. The recording layer is provided between the first layer and the second layer. The recording layer is capable of reversibly changing between a first state and a second state having a resistance higher than a resistance in the first state by a current supplied via the first layer and the second layer. The recording layer includes a first portion and a second portion provided in a plane of a major surface of the recording layer. The second portion has a nitrogen amount higher than a nitrogen amount in the first portion. | 2011-02-03 |
20110024714 | Nanoscale Three-Terminal Switching Device - A nanoscale three-terminal switching device has a bottom electrode, a top electrode, and a side electrode, each of which may be a nanowire. The top electrode extends at an angle with respect to the bottom electrode and has an end section going over and overlapping the bottom electrode. An active region is disposed between the top electrode and bottom electrode and contains a switching material. The side electrode is disposed opposite from the top electrode and in electrical contact with the active region. A self-aligned fabrication process may be used to automatically align the formation of the top and side electrodes with respect to the bottom electrode. | 2011-02-03 |
20110024715 | METHOD OF FABRICATING AG-DOPED TE-BASED NANO-MATERIAL AND MEMORY DEVICE USING THE SAME - A nano-ionic memory device is provided. The memory device includes a substrate, a chemically inactive lower electrode provided on the substrate, a solid electrolyte layer provided on the lower electrode and including a silver (Ag)-doped telluride (Te)-based nano-material, and an oxidizable upper electrode provided on the electrolyte layer. | 2011-02-03 |
20110024716 | MEMRISTOR HAVING A NANOSTRUCTURE IN THE SWITCHING MATERIAL - A memristor includes a first electrode having a first surface, at least one electrically conductive nanostructure provided on the first surface, in which the at least one electrically conductive nanostructure is relatively smaller than a width of the first electrode, a switching material positioned upon said first surface, in which the switching material covers the at least one electrically conductive nanostructure, and a second electrode positioned upon the switching material substantially in line with the at least one electrically conductive nanostructure, in which an active region in the switching material is formed substantially between the at least one electrically conductive nanostructure and the first electrode. | 2011-02-03 |
20110024717 | METHOD FOR PREFERENTIAL GROWTH OF SEMICONDUCTING VERTICALLY ALIGNED SINGLE WALLED CARBON NANOTUBES - A method and system for the preferential growth of semiconducting vertically-aligned single-walled carbon nanotubes (VA-SWNTs) is provided. The method combines the use of plasma-enhanced chemical vapor deposition at low pressure with rapid heating. The method provides a high yield of up to approximately 96% semiconducting SWNTs in the VA-SWNT array. The as-synthesized semiconducting SWNTs can be used directly for fabricating field effect transistor (FET) devices without the need for any post-synthesis purification or separation. | 2011-02-03 |
20110024718 | Nanowire Synthesis - A noble metal nanoparticle can be grown on a semiconductor substrate by contacting a predetermined region of the substrate with a solution including noble metal ions. The predetermined region of the semiconductor substrate can be exposed by applying a polymeric layer over the substrate selectively removing a portion of the polymeric layer. The nanoparticles can be prepared in a predetermined pattern. Nanowires having a predetermined diameter and a predetermined position can be grown from the nanoparticles. | 2011-02-03 |
20110024719 | LARGE SCALE NANOELEMENT ASSEMBLY METHOD FOR MAKING NANOSCALE CIRCUIT INTERCONNECTS AND DIODES - Nanoelements such as single walled carbon nanotubes are assembled in three dimensions into a nanoscale template on a substrate by means of electrophoresis and dielectrophoresis at ambient temperature. The current-voltage relation indicates that strong substrate-nanotube interconnects carrying mA currents are established inside the template pores. The method is suitable for large-scale, rapid, three-dimensional assembly of 1,000,000 nanotubes per square centimeter area using mild conditions. Circuit interconnects made by the method can be used for nanoscale electronics applications. | 2011-02-03 |
20110024720 | High-efficiency LED - A high-efficiency LED includes: a substrate, an epitaxial layer structure, a cathode, an anode, a transparent sealing compound and a polyimide layer. The polyimide layer covers surfaces of the epitaxial layer structure and the substrate. The transparent sealing compound covers the polyimide layer, the substrate, the epitaxial layer structure, the cathode and the anode. The polyimide layer of the present invention has a refractive index higher than that of packaging materials in prior art, so as to reduce total internal reflection and optical consumption caused by light scattered from the epitaxial layer structure and the transparent sealing compound. | 2011-02-03 |
20110024721 | SEMICONDUCTOR LIGHT EMITTING DEVICE - A semiconductor light emitting device including a semiconductor substrate and an active layer which is formed on the substrate and has a cascade structure formed by multistage-laminating unit laminate structures | 2011-02-03 |
20110024722 | OPTICAL DEVICES FEATURING NONPOLAR TEXTURED SEMICONDUCTOR LAYERS - A semiconductor emitter, or a precursor therefor, has a substrate and one or more textured semiconductor layers deposited onto the substrate in a nonpolar orientation. The textured layers enhance light extraction, and the use of nonpolar orientation greatly enhances internal quantum efficiency compared to conventional devices. Both the internal and external quantum efficiencies of emitters of the invention can be 70-80% or higher. The invention provides highly efficient light emitting diodes suitable for solid state lighting. | 2011-02-03 |
20110024723 | Nanoparticle synthesis - A noble metal nanoparticle can be grown on a semiconductor substrate by contacting a predetermined region of the substrate with a solution including noble metal ions. The predetermined region of the semiconductor substrate can be exposed by applying a polymeric layer over the substrate selectively removing a portion of the polymeric layer. The nanoparticles can be prepared in a predetermined pattern. The nanoparticle can be formed with a barrier separating it from another nanoparticle on the substrate; for example, nanoparticle can be located in a pit etched in the substrate. The size and location of the nanoparticle can be stable at elevated temperatures. | 2011-02-03 |
20110024724 | MULTI-LAYERED ELECTRO-OPTIC DEVICES - A laminate film includes a plurality of planar photovoltaic semi-transparent modules disposed one on top of another and laminated to each other. Each of the modules includes a substrate, first and second conductive layers and at least first and second semiconductor layers disposed between the conductive layers. The first and second semiconductor layers define a junction at an interface therebetween. At least one of the junctions is configured to convert a first spectral portion of optical energy into an electrical voltage and transmit a second spectral portion of optical energy to another of the junctions that is configured to convert at least a portion of the second spectral portion of optical energy into an electrical voltage. | 2011-02-03 |
20110024725 | ANTHRACENE DERIVATIVES AND ORGANIC ELECTRONIC DEVICE USING THE SAME - The present invention relates to a novel anthracene derivative and an organic electronic device using the same. The organic electronic device according to the present invention shows excellent characteristics in efficiency, driving voltage, and life time. | 2011-02-03 |
20110024726 | ORGANIC LIGHT EMITTING DISPLAY DEVICE - An organic light emitting display device includes: a substrate; a first electrode located on the substrate; an organic light emitting layer located on the first electrode; and a second electrode located on the organic light emitting layer, wherein the organic emitting layer comprises an interface buffer layer located on the first electrode and formed from a mixture of an inorganic material and an organic material. | 2011-02-03 |
20110024727 | LOW-VOLTAGE, N-CHANNEL HYBRID TRANSISTORS - Hybrid semiconducting-dielectric materials and electronic or electro-optic devices using the hybrid semiconducting-dielectric materials. Hybrid semiconducting-dielectric materials comprise molecules that have a core section that provides an n-type semiconducting property and side chains that provide a dielectric property to a layer of hybrid semiconducting-dielectric material. Specific hybrid semiconducting-dielectric materials include tetracarboxylic diimide compounds having sidechains comprising fluorine substituted aliphatic or aromatic moieties linked to the tetracarboxylic diimide structure by an alkylene or heteroalkylene linking group. | 2011-02-03 |
20110024728 | Organic Thin Film Transistors and Methods of Making the Same - An organic thin film transistor, and a method of making the same, comprising a source and drain electrode and organic semi-conductive material disposed therebetween in a channel region, in which the source and drain electrodes have disposed on them a thin self-assembled layer of a material comprising a dopant moiety for chemically doping the organic semi-conductive material by accepting electrons, the dopant moiety having a redox potential of at least 0.3 eV relative to a saturated calomel electrode in acetonitrile. | 2011-02-03 |
20110024729 | Crosslinked Polymeric Dielectric Materials And Electronic Devices Incorporating Same - Solution-processable dielectric materials are provided, along with precursor compositions and processes for preparing the same. Composites and electronic devices including the dielectric materials also are provided. | 2011-02-03 |
20110024730 | POLYMER, ORGANIC THIN FILM USING THE SAME, AND ORGANIC THIN FILM DEVICE - A polymer according to the present invention comprises a repeating structure represented by the following formula (1), wherein L and X each independently have a configuration in which are linked a plurality of conjugation forming structures each conjugated by itself, and each have at least one thienylene structure as the conjugation forming structure: | 2011-02-03 |
20110024731 | NOVEL CONDENSED POLYCYCLIC AROMATIC COMPOUND AND USE THEREOF - The object of the present invention to provide an organic semiconductor device comprising an organic semiconductor material satisfying both the requirement of high electron field-effect mobility and high on/off current ratio. The present invention provides a novel condensed polycyclic aromatic compound satisfying both the high electron field-effect mobility and high on/off current ratio required for organic semiconductor materials. | 2011-02-03 |
20110024732 | LIGHT EMITTING ELEMENT AND LIGHT EMITTING - It is an object of the present invention to obtain an organometallic complex that is capable of converting an excited triplet state into luminescence, a light-emitting element that can be driven for a long time, is high in luminous efficiency, and has a favorable long lifetime, and a light-emitting device using the light-emitting element. The present invention provides a light-emitting element that has a pair of electrodes (an anode and a cathode) and a light-emitting layer between a pair of electrodes, where the light-emitting layer includes an organometallic complex represented by the following general formula (5) and one of a compound that has a larger energy gap than the organometallic complex and a compound that has a larger ionization potential and a smaller electron affinity than the organometallic complex, and provides a light-emitting device using the light-emitting device. | 2011-02-03 |
20110024733 | POLYMERISABLE COMPOSITIONS AND ORGANIC LIGHT-EMITTING DEVICES CONTAINING THEM - Compositions of a mixture of a thiol material and a material that contains a reactive unsaturated carbon-carbon bond that can be polymerised to form a charge-transporting or luminescent film are described, as is an organic light-emitting diode (OLED) device comprising at least one such charge-transporting or emissive layer that has been formed by polymerising a thiol material and an ene material. The process for forming such an OLED, including the deposition of a layer of material comprising the polymerisable composition, from solution, exposing said layer to actinic radiation through a mask, and then optionally developing said film to form a photopatterned film, is also disclosed. | 2011-02-03 |
20110024734 | DEVICE FOR SPRAYING, METHOD THEREFOR AND ORGANIC ELECTRONIC CONSTRUCTION ELEMENT - The embodiments relate to a device and a method for spraying coatings of organic construction elements. The embodiments relate, in particular, to the spraying of coatings made up of components that do not dissolve in the same solvent, for example, and/or the spraying of a plurality of coatings one after the other. A plurality of spray heads is used, for example one after the other and/or next to one another. | 2011-02-03 |
20110024735 | COMPOUND FOR ORGANIC ELECTROLUMINESCENT DEVICE AND ORGANIC ELECTROLUMINESCENT DEVICE USING THE SAME - Disclosed is an organic electroluminescent device (organic EL device) that is improved in luminous efficiency, fully secured of driving stability, and of simple structure. The organic EL device comprises a light-emitting layer between an anode and a cathode piled one upon another on a substrate and the light-emitting layer comprises a phosphorescent dopant and a compound containing carbazolyl groups at both ends represented by the following formula (1) as a host material. In formula (1), X is independently CH optionally containing a substituent or N and L is a direct bond, an ethylene group, or an acetylene group. | 2011-02-03 |
20110024736 | ORGANIC ELECTROLUMINESCENT ELEMENT AND DISPLAY - An organic electroluminescent includes an organic layer with a total thickness of 150 nm or over is included between an anode and a cathode. The organic layer includes a light-emitting layer containing a host material of a polycyclic aromatic hydrocarbon compound with a basic skeleton having three to seven ring members, and hole supply layers arranged between the anode and the light-emitting layer and having a smaller thickness than a thickness of the light-emitting layer. | 2011-02-03 |
20110024737 | FUSED POLYCYCLIC COMPOUND AND ORGANIC LIGHT EMITTING DEVICE HAVING THE COMPOUND - Provided are a fused polycyclic compound obtained by expanding the conjugated system of a chrysene skeleton, and an organic light emitting device using the compound. The organic light emitting device has an optical output with high efficiency and high luminance, and is extremely durable. | 2011-02-03 |
20110024738 | SUBSTRATE HAVING IMPRINTED STRUCTURE - In a substrate with a hydrophilic surface and a structure made of a conductive and/or light-emitting organic polymer imprinted on the hydrophilic surface, the hydrophilic surface is formed from a layer arranged on the substrate of an oxide ceramic and/or metallic material. | 2011-02-03 |
20110024739 | Digital X-Ray Detecting Panel and Method for Manufacturing the same - A digital X-ray detecting panel includes a wavelength transforming layer and a photoelectric detecting plate. The wavelength transforming layer is configured for transforming X-ray into visible light. The photoelectric detecting plate is disposed under the wavelength transforming layer. The photoelectric detecting plate includes a substrate and a number of photoelectric detecting units disposed on the substrate and arranged in an array. Each of the photoelectric detecting units includes a thin film transistor and a photodiode electrically connected to the thin film transistor. The thin film transistor has an oxide semiconductor layer. The digital X-ray detecting panel can avoid a photocurrent in the thin film transistor, and thereby improving detecting accuracy of the digital X-ray detecting panel. A method for manufacturing the digital X-ray detecting panel is also provided. | 2011-02-03 |
20110024740 | SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD THEREOF - A semiconductor device having a structure which enables sufficient reduction in parasitic capacitance is provided. In addition, the operation speed of thin film transistors in a driver circuit is improved. In a bottom-gate thin film transistor in which an oxide insulating layer is in contact with a channel formation region in an oxide semiconductor layer, a source electrode layer and a drain electrode layer are formed in such a manner that they do not overlap with a gate electrode layer. Thus, the distance between the gate electrode layer and the source electrode layer and between the gate electrode layer and the drain electrode layer are increased; accordingly, parasitic capacitance can be reduced. | 2011-02-03 |
20110024741 | INTEGRATED CIRCUITS UTILIZING AMORPHOUS OXIDES - Semiconductor devices and circuits with use of transparent oxide film are provided. The semiconductor device having a P-type region and an N-type region, wherein amorphous oxides with electron carrier concentration less than 10 | 2011-02-03 |
20110024742 | PROCESS FOR PRODUCING ZnO SINGLE CRYSTAL, SELF-SUPPORTING ZnO SINGLE-CRYSTAL WAFER OBTAINED BY THE SAME, SELF-SUPPORTING WAFER OF Mg-CONTAINING ZnO MIXED SINGLE CRYSTAL, AND PROCESS FOR PRODUCING Mg-CONTAINING ZnO MIXED SINGLE CRYSTAL FOR USE IN THE SAME - A ZnO single crystal can be grown on a seed crystal substrate using a liquid phase epitaxial growth method by mixing and melting ZnO as a solute and a solvent, bringing the crystal substrate into direct contact with the resultant melt, and pulling up the seed crystal substrate continuously or intermittently. A self-supporting Mg-containing ZnO mixed single crystal wafer can be obtained as follows. A Mg-containing ZnO mixed single crystal is grown using a liquid phase epitaxial growth method by mixing and melting ZnO and MgO forming a solute and a solvent, then bringing a seed crystal substrate into direct contact with the resultant melt, and pulling up the seed crystal substrate continuously or intermittently. Then, the self-supporting Mg-containing ZnO mixed single crystal wafer is obtained by removing the substrate by polishing or etching, and polishing or etching a surface, on the side of −c plane, of the single crystal grown by the liquid phase epitaxial growth method. | 2011-02-03 |
20110024743 | SEMICONDUCTOR INTEGRATED CIRCUIT - A semiconductor integrated circuit includes a multi-chip package having a plurality of semiconductor chips. The semiconductor integrated circuit includes a signal line; and a signal loading compensation section in a semiconductor chip among the plurality of semiconductor chips, configured to apply a designed signal loading to the signal line in response to activation of a test signal. Here, the designed signal loading has a value corresponding to a signal loading component of another semiconductor chip among the plurality of semiconductor chips to the signal line. | 2011-02-03 |
20110024744 | CONNECTION PAD STRUCTURE FOR AN ELECTRONIC COMPONENT - The invention relates to electronic components on thinned substrates, for example image sensors. Preferably, connection pads are connected through the thinned substrate to underlying layers and notably to a test pad by way of openings through which the metal of the pad passes. The openings are elongate openings extending along one edge of the pad of rectangular shape and a circular area of at least 50% (and preferably 65 to 75%) of the area of the pad contains no opening for connection with the underlying layers. This circular area is intended for bonding an external connection wire. The connection pads are testable from the back side by test probes and the front side may be tested (before bonding and thinning) by test probes with the same geometric configuration. | 2011-02-03 |
20110024745 | System With Semiconductor Components Having Encapsulated Through Wire Interconnects (TWI) - A method for fabricating a semiconductor component with an encapsulated through wire interconnect includes the steps of providing a substrate having a first side, a second side and a substrate contact; forming a via in the substrate contact and the substrate to the second side; placing a wire in the via; forming a first contact on the wire proximate to the first side and a second contact on the wire proximate to the second side; and forming a polymer layer on the first side leaving the first contact exposed. The polymer layer can be formed using a film assisted molding process including the steps of: forming a mold film on tip portions of the bonding members, molding the polymer layer, and then removing the mold film to expose the tip portions of the bonding members. The through wire interconnect provides a multi level interconnect having contacts on opposing sides of the semiconductor substrate. | 2011-02-03 |
20110024746 | Semiconductor Device with Test Pads and Pad Connection Unit - A semiconductor device includes at least one first type of pad and at least one second type of pad having a different area from the first type of pad. A pad connection unit electrically couples the at least one second type of pad to an integrated circuit of the semiconductor device during a test mode, and disconnects the at least one second type of pad from the integrated circuit during a normal operating mode. | 2011-02-03 |
20110024747 | METHODS FOR IMPROVING THE QUALITY OF GROUP III-NITRIDE MATERIALS AND STRUCTURES PRODUCED BY THE METHODS - The invention provides methods which can be applied during the epitaxial growth of two or more layers of Group III-nitride semiconductor materials so that the qualities of successive layer are successively improved. In preferred embodiments, surface defects interact with a protective layer of a protective material to form amorphous complex regions capable of preventing the further propagation of defects and dislocations. The invention also includes semiconductor structures fabricated by these methods. | 2011-02-03 |
20110024748 | RADIATION IMAGE DETECTOR - An intermediate layer is located between a recording photoconductive layer and an electrode, which is either one of a bias electrode and a reference electrode, and which is located on the side at positive electric potential with respect to a charge accumulating section at the time of readout of electric charges of the charge accumulating section. The intermediate layer is an a-Se layer containing, as a specific substance, at least one kind of substance selected from the group consisting of an alkali metal fluoride, an alkaline earth metal fluoride, an alkali metal oxide, an alkaline earth metal oxide, SiO | 2011-02-03 |
20110024749 | RADIATION DETECTOR - A radiation detector of this invention has an insulating, non-amine barrier layer disposed between exposed surfaces of a radiation sensitive semiconductor layer, a carrier selective high resistance film and a common electrode, and a curable synthetic resin film. | 2011-02-03 |
20110024750 | SEMICONDUCTOR DEVICE AND METHOD FOR MANUFACTURING THE SAME - An object is to provide a semiconductor device having a structure with which parasitic capacitance between wirings can be sufficiently reduced. An oxide insulating layer serving as a channel protective layer is formed over part of an oxide semiconductor layer overlapping with a gate electrode layer. In the same step as formation of the oxide insulating layer, an oxide insulating layer covering a peripheral portion of the oxide semiconductor layer is formed. The oxide insulating layer which covers the peripheral portion of the oxide semiconductor layer is provided to increase the distance between the gate electrode layer and a wiring layer formed above or in the periphery of the gate electrode layer, whereby parasitic capacitance is reduced. | 2011-02-03 |
20110024751 | SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD THEREOF - In a bottom-gate thin film transistor using the stack of the first oxide semiconductor layer and the second oxide semiconductor layer, an oxide insulating layer serving as a channel protective layer is formed over and in contact with part of the oxide semiconductor layer overlapping with a gate electrode layer. In the same step as formation of the insulating layer, an oxide insulating layer covering a peripheral portion (including a side surface) of the stack of the oxide semiconductor layers is formed. | 2011-02-03 |
20110024752 | THIN FILM TRANSISTOR, METHOD OF FABRICATING THE SAME, AND DISPLAY APPARATUS HAVING THE SAME - A method of fabricating a thin film transistor includes forming a gate electrode on a substrate, forming a semiconductor layer on the gate electrode, forming a source electrode on the semiconductor layer, forming a drain electrode on the semiconductor layer spaced apart from the source electrode, forming a copper layer pattern on the source electrode and the drain electrode, exposing the copper layer pattern on the source electrode and the drain electrode to a fluorine-containing process gas to form a copper fluoride layer pattern thereon, and patterning the semiconductor layer. | 2011-02-03 |
20110024753 | PIXEL STRUCTURE AND FABRICATING METHOD THEREOF - A fabricating method of a pixel structure is provided. First, a substrate with a plurality of pixel areas is provided. A common electrode is formed on the substrate to surround each pixel area. Then, a capacitance storage electrode is formed on the common electrode, and a first passivation layer is formed to cover the capacitance storage electrode and the common electrode. Following that, a scan line and a gate electrode are formed within each pixel area. Next, a gate insulation layer and a semiconductor layer are formed. A data line, a source, and a drain are formed within each pixel area. After that, a second passivation layer is formed on the substrate, and a contact window is formed in the second passivation layer above the drain. Moreover, a pixel electrode is formed within each pixel area, and the pixel electrode is electrically connected with the drain through the contact window. | 2011-02-03 |
20110024754 | ACTIVE MATRIX SUBSTRATE, ELECTRO-OPTICAL DEVICE, AND ELECTRONIC APPARATUS - An active matrix substrate including: a substrate; a display section having a pixel circuit formed on the substrate; and a protection circuit connected to an interconnection of the display section. The protection circuit has a diode-connected transistor, an insulating layer provided so as to cover the transistor, and a light-shielding layer provided in a region above the insulating layer so as to face at least a channel region in the transistor and electrically connected to at least any one of a gate electrode and a source electrode of the transistor. | 2011-02-03 |
20110024755 | THIN FILM TRANSISTOR SUBSTRATE AND THIN FILM TRANSISTOR USED FOR THE SAME - A thin film transistor (TFT) substrate includes first and second TFTs on the same substrate. The first TFT has a feature that a lower conductive layer or a bottom gate electrode layer is provided between the substrate and a first insulating layer while an upper conductive layer or a top gate electrode layer is disposed on a second insulating layer formed on a semiconductor layer which is formed on the first insulating layer. The first conductive layer has first and second areas such that the first area overlaps with the first conductive layer without overlapping with the semiconductor layer while the second area overlaps with the semiconductor layer, and the first area is larger than the second area while the second insulating layer is thinner than the first insulating layer. The second TFT has the same configuration as the first TFT except that the gate electrode layer is eliminated. | 2011-02-03 |
20110024756 | ORGANIC LIGHT EMITTING DISPLAY - The general inventive concept relates to an organic light emitting display that has the same area where the upper and lower electrodes of a capacitor are overlapped for adjacent pixels, for respective pixels that constitute the organic light emitting display but implements the sizes of the upper and lower electrodes to be different. This thereby prevents the display quality of horizontal line shaped spot generated due to the effects of a critical dimension (CD) distribution from being degraded. | 2011-02-03 |
20110024757 | Semiconductor Device and Fabrication Method Thereof - For forming a gate electrode, a conductive film with low resistance including Al or a material containing Al as its main component and a conductive film with low contact resistance for preventing diffusion of Al into a semiconductor layer are laminated, and the gate electrode is fabricated by using an apparatus which is capable of performing etching treatment at high speed. | 2011-02-03 |
20110024758 | LIQUID CRYSTAL DISPLAY DEVICE AND SEMICONDUCTOR DEVICE - By increasing an interval between electrodes which drives liquid crystals, a gradient of an electric field applied between the electrodes can be controlled and an optimal electric field can be applied between the electrodes. The invention includes a first electrode formed over a substrate, an insulating film formed over the substrate and the first electrode, a thin film transistor including a semiconductor film in which a source, a channel region, and a drain are formed over the insulating film, a second electrode located over the semiconductor film and the first electrode and including first opening patterns, and liquid crystals provided over the second electrode. | 2011-02-03 |
20110024759 | THIN FILM TRANSISTOR SUBSTRATE AND METHOD FOR FORMING METAL WIRE THEREOF - The present invention relates to a thin film transistor substrate and a metal wiring method thereof, more particularly to a thin film transistor substrate comprising self-assembled monolayers between the substrate and the metal wiring, and a metal wiring thereof. Since a thin film transistor substrate of the present invention comprises three-dimensionally cross-linked self-assembled monolayers between the Si surface and the metal wiring, it has good adhesion ability and anti-diffusion ability. | 2011-02-03 |
20110024760 | SEMICONDUCTOR DEVICE, DISPLAY DEVICE, AND ELECTRONIC DEVICE - A pixel includes a load, a transistor which controls a current supplied to the load, a storage capacitor, and first to fourth switches. By inputting a potential in accordance with a video signal into the pixel after the threshold voltage of the transistor is held in the storage capacitor, and holding a voltage of the sum of the threshold voltage and the potential, variations of a current value caused by variations of threshold voltage of a transistor can be suppressed. Consequently, a predetermined current can be supplied to the load such as a light-emitting element. Further, by changing the potential of a power supply line, a display device with a high duty ratio can be provided. | 2011-02-03 |
20110024761 | INTERCONNECTION STRUCTURE, A THIN FILM TRANSISTOR SUBSTRATE, AND A MANUFACTURING METHOD THEREOF, AS WELL AS A DISPLAY DEVICE - Provided is a direct contact technology by which a barrier metal layer between an Al alloy interconnection composed of pure Al or an Al alloy and a semiconductor layer can be eliminated and the Al alloy interconnection can be directly and surely connected to the semiconductor layer within a wide process margin. In an interconnection structure, the semiconductor layer, and the Al alloy film composed of the pure Al or the Al alloy are provided on the substrate in this order from the substrate side. A multilayer structure of an (N, C, F) layer containing at least one type of an element selected from among a group composed of nitrogen, carbon and fluorine, and an Al—Si diffusion layer containing Al and Si is included in this order from the substrate side, between the semiconductor layer and the Al alloy film. At least the one type of the element, i.e., nitrogen, carbon or fluorine contained in the (N, C, F) layer is bonded with Si contained in the semiconductor layer. | 2011-02-03 |
20110024762 | Method of Forming a Thin Film Transistor - A method of forming a thin film transistor relative to a substrate includes, a) providing a thin film transistor layer of polycrystalline material on a substrate, the polycrystalline material comprising grain boundaries; b) providing a fluorine containing layer adjacent the polycrystalline thin film layer; c) annealing the fluorine containing layer at a temperature and for a time period which in combination are effective to drive fluorine from the fluorine containing layer into the polycrystalline thin film layer and incorporate fluorine within the grain boundaries to passivate said grain boundaries; and d) providing a transistor gate operatively adjacent the thin film transistor layer. The thin film transistor can be fabricated to be bottom gated or top gated. A buffering layer can be provided intermediate the thin film transistor layer and the fluorine containing layer, with the buffering layer being transmissive of fluorine from the fluorine containing layer during the annealing. Preferably, the annealing temperature is both sufficiently high to drive fluorine from the fluorine containing layer into the polycrystalline thin film layer and incorporate fluorine within the grain boundaries to passivate said grain boundaries, but sufficiently low to prevent chemical reaction of the fluorine containing layer with the polycrystalline thin film layer. | 2011-02-03 |
20110024763 | DISPLAY DEVICE AND MANUFACTURING METHOD THEREOF - A display device which has thin film transistors, wherein a semiconductor layer includes a first layer, second layers and third layers, the first layer has a channel region, the second layers are an impurity layer, the third layers are a low-concentration impurity layer, the second layers have connection portions connected with an electrodes, the third layers are formed to annularly surround the second layers, a channel-region-side edge portion out of edge portions of the third layer is in contact with the first layer, the edge portions of the third layer but the channel-region-side edge portion are in contact with an interlayer insulation film, the second layers have a first region where the second layer overlaps with a gate electrode and a second region where the second layer does not overlap with the gate electrode, and the connection portion is in the second region. | 2011-02-03 |
20110024764 | SEMICONDUCTOR DEVICE, METHOD FOR PRODUCING THE SAME, AND DISPLAY DEVICE - The present invention provides a semiconductor device which can reduce I | 2011-02-03 |
20110024765 | SILICON CARBIDE SEMICONDUCTOR STRUCTURES, DEVICES AND METHODS FOR MAKING THE SAME - There are provided semiconductor structures and devices comprising silicon carbide (SiC) and methods for making the same. The structures and devices comprise a base or shielding layer, channel and surface layer, all desirably formed via ion implantation. As a result, the structures and devices provided herein are hard, “normally off” devices, i.e., exhibiting threshold voltages of greater than about 3 volts. | 2011-02-03 |
20110024766 | ONE HUNDRED MILLIMETER SINGLE CRYSTAL SILICON CARBIDE WAFER - A method is disclosed for producing a high quality bulk single crystal of silicon carbide in a seeded growth system by reducing the separation between a silicon carbide seed crystal and a seed holder until the conductive heat transfer between the seed crystal and the seed holder dominates the radiative heat transfer between the seed crystal and the seed holder over substantially the entire seed crystal surface that is adjacent the seed holder. | 2011-02-03 |
20110024767 | Semiconductor Substrates, Devices and Associated Methods - Semiconductor substrates and devices having improved performance and cooling, as well as associated methods, are provided. In one aspect, for example, a semiconductor device can include a matrix layer and a plurality of single crystal semiconductor tiles disposed in the matrix layer. The plurality of semiconductor tiles are positioned such that an exposed surface of each of substantially all of the plurality of diamond tiles aligns along a common plane to form a substrate surface. In one aspect, a semiconductor layer is disposed on the substrate surface. In another aspect, the semiconductor layer is a doped diamond layer. In yet another aspect, the semiconductor tiles are doped. In a further aspect, the exposed surface of each of the plurality of semiconductor tiles has a common crystallographic orientation. | 2011-02-03 |
20110024768 | SiC AVALANCHE PHOTODIODE WITH IMPROVED EDGE TERMINATION - An avalanche photodiode semiconductor device ( | 2011-02-03 |
20110024769 | SEMICONDUCTOR DEVICE AND METHOD FOR FABRICATING THE SAME - A method for fabricating a semiconductor device includes the steps of forming a SiC film, forming trenches at a surface of the SiC film, heat-treating the SiC film with silicon supplied to the surface of the SiC film, and obtaining a plurality of macrosteps to constitute channels, at the surface of the SiC film by the step of heat-treating. Taking the length of one cycle of the trenches as L and the height of the trenches as h, a relation L=h(cot α+cot β) (where α and β are variables that satisfy the relations 0.5≦α, β≦45) holds between the length L and the height h. Consequently, the semiconductor device can be improved in property. | 2011-02-03 |
20110024770 | Inverted Bottom-Emitting OLED Device - A method of making an inverted bottom-emitting OLED device, comprising: providing a substrate; providing one or more first electrodes driven by n-type transistors on the substrate; providing an electron-transporting layer over the substrate and first electrode(s), wherein the electron-transporting layer comprises an n-type inorganic semiconductive material with a resistivity in the range of 1 to 10 | 2011-02-03 |
20110024771 | Optically Interrogated Solid State Biosensors Incorporating Porous Materials - Devices and Methods of Fabrication - Quantitative understanding of neural and biological activity at a sub-millimeter scale requires an integrated probe platform that combines biomarker sensors together with electrical stimulus/recording sites. Optically addressed biomarker sensors within such an integrated probe platform allows remote interrogation from the activity being measured. Monolithic or hybrid integrated silicon probe platforms would beneficially allow for accurate control of neural prosthetics, brain machine interfaces, etc as well as helping with complex brain diseases and disorders. According to the invention a silicon probe platform is provided employing ultra-thin silicon in conjunction with optical waveguides, optoelectronic interfaces, porous filter elements, and integrated CMOS circuitry. Such probes allowing simultaneously analysis of both neural electrical activities along with chemical activity derived from multiple biomolecular sensors with porous membrane filters. Such porous silicon and polymer filters providing biomolecular filtering and optical filtering being compatible with post-processing wafers with integrated CMOS electronics. | 2011-02-03 |
20110024772 | ELECTRICAL CONNECTION FOR SEMICONDUCTOR STRUCTURES, METHOD FOR THE PRODUCTION THEREOF, AND USE OF SUCH A CONNECTION IN A LUMINOUS ELEMENT - The invention relates to a method for electrically contacting an arrangement of a plurality of semiconductor structures comprising contact regions therefor and emitting electromagnetic radiation when a voltage is applied thereto. According to said method, a viscous, hardenable material is applied to the arrangement of a plurality of semiconductor structures and hardened to form a material web. The invention also relates to a luminous element comprising a plurality of semiconductor structures ( | 2011-02-03 |
20110024773 | LIGHT EMITTING DIODE PACKAGE STRUCTURE AND LEAD FRAME STRUCTURE THEREOF - An LED package structure includes a frame, at least a first LED, and at least a second LED. The frame includes a base having a first cavity and a second cavity, where the second cavity is disposed under the first cavity and the second cavity is smaller than the first cavity. The first LED is disposed in the bottom of the first cavity, and the second LED is disposed in the bottom of the second cavity. | 2011-02-03 |
20110024774 | DIGITAL RADIOGRAPHIC FLAT-PANEL IMAGING ARRAY WITH DUAL HEIGHT SEMICONDUCTOR AND METHOD OF MAKING SAME - A method of manufacturing an imaging array includes providing a silicon tile having a first surface and a second, opposite surface. A buried dielectric layer is formed in the silicon tile between the first and second surfaces to define a bottom silicon layer between the first surface and the dielectric layer. A separation boundary is formed in the silicon tile between the second surface and the dielectric layer to define a top silicon layer between the dielectric layer and the separation boundary and a removable silicon layer between the separation boundary and the second surface. An oxide layer is formed on the first surface of the silicon tile and the silicon tile is bonded to a glass substrate at the oxide layer. The silicon tile is separated at the separation boundary to remove the removable silicon layer, exposing the top silicon layer. Semiconductive elements are formed using the exposed top silicon layer. | 2011-02-03 |
20110024775 | Methods for and devices made using multiple stage growths - Surface modification of individual nitride semiconductor layers occurs between growth stages to enhance the performance of the resulting multiple layer semiconductor structure device formed from multiple growth stages. Surface modifications may include, but are not limited, to laser patterning, lithographic patterning (with the scale ranging from 10 microns to a few angstroms), actinic radiation modifications, implantation, diffusional doping and combinations of these methods. The semiconductor structure device has enhanced crystal quality, reduced phonon reflections, improved light extraction, and an increased emission area. The ability to create these modifications is enabled by the thickness of the HVPE growth of the GaN semiconductor layer. | 2011-02-03 |
20110024776 | LIGHT EMITTING DEVICE - A light emitting device according to the embodiment includes a first conductive semiconductor layer; an active layer under the first conductive semiconductor layer; a second conductive semiconductor layer under the active layer; a current blocking region under the second conductive semiconductor layer; a second electrode layer under the second conductive semiconductor layer and the current blocking region; and a first electrode layer including a protrusion protruding toward the first conductive semiconductor layer arranged, on the first conductive semiconductor layer. | 2011-02-03 |
20110024777 | NITRIDE SEMICONDUCTOR LIGHT-EMITTING DEVICE AND METHOD FOR MANUFACTURING THE SAME - There are provided a nitride semiconductor light-emitting device and a method for manufacturing the same. The nitride semiconductor light-emitting device includes a buffer layer on a sapphire substrate, wherein the buffer layer includes a plurality of layers having different lattice constants, a first n-type nitride semiconductor layer on the buffer layer, an active layer on the first n-type nitride semiconductor layer, and a p-type nitride semiconductor layer on the active layer. | 2011-02-03 |
20110024778 | Optoelectronic device - This invention relates to optoelectronic devices of improved efficiency. In particular it relates to light emitting diodes, photodiodes and photovoltaics. By careful design of periodic microstructures, e.g. gratings, associated with such devices more efficient light generation or detection is achieved. | 2011-02-03 |
20110024779 | ORGANIC EL DEVICE - An organic EL device in the present invention comprises a light-transmissive substrate | 2011-02-03 |
20110024780 | ORGANIC LIGHT EMITTING DIODE DISPLAY - An organic light emitting diode includes a display substrate assembly including an organic light emitting element; an encapsulation substrate assembly disposed on the display substrate assembly with a space therebetween and sealed with the display substrate assembly in a vacuum-tight manner; and a filling agent filling the space between the display substrate assembly and the encapsulation substrate assembly. The filling agent is adapted to selectively absorb external light entering through the encapsulation substrate assembly and incident on the organic light emitting element as a function of wavelength in a wavelength band of the external light to control transmittance. | 2011-02-03 |
20110024781 | Light emitting device - A light emitting device has a light emitting layer having a first semiconductor layer of a first conductivity type, a second semiconductor layer of a second conductivity type different from the first conductivity type, and an active layer sandwiched between the first semiconductor layer and the second semiconductor layer, a reflecting layer provided on a side of one surface of the light emitting layer, which reflects a light emitted from the active layer, a supporting substrate provided on an opposite side of the reflecting layer with respect to the light emitting layer, which supports the light emitting layer via an adhesion layer, an ohmic contact portion provided on a part of the reflecting layer, which electrically connects between the reflecting layer and the light emitting layer, and convexo-concave portions formed on other surface of the light emitting layer and side surfaces of the light emitting layer, respectively, and an insulating film configured to cover the convexo-concave portions. | 2011-02-03 |
20110024782 | LOW OPTICAL LOSS ELECTRODE STRUCTURES FOR LEDS - An electrode structure is disclosed for enhancing the brightness and/or efficiency of an LED. The electrode structure can have a metal electrode and an dielectric material formed intermediate the electrode and a light emitting semiconductor material. Electrical continuity between the semiconductor material and the metal electrode is provided by an optically transmissive ohmic contact layer, such as a layer of Indium Tin Oxide. The metal electrode thus can be physically separated from the semiconductor material by one or more of the dielectric material and the ohmic contact layer. The dielectric layer can increase total internal reflection of light at the interface between the semiconductor and the dielectric layer, which can reduce absorption of light by the electrode. Such LED can have enhanced utility and can be suitable for uses such as general illumination. | 2011-02-03 |
20110024783 | LIGHT EMITTING DIODE - A light emitting diode includes: an electrically conductive permanent substrate having a reflective top surface; an epitaxial film disposed on the reflective top surface of the permanent substrate and having an upper surface and a roughened lower surface that is opposite to the upper surface, the roughened lower surface having a roughness with a height of not less than 300 nm and a plurality of peaks which are in ohmic contact with the reflective top surface; an optical adhesive filled in a gap between the lower surface and the reflective top surface and connecting the epitaxial film to the permanent substrate; and a top electrode disposed on the upper surface and in ohmic contact with the epitaxial film. | 2011-02-03 |
20110024784 | LIGHT-EMITTING ELEMENT - Disclosed is a light emitting device. The light emitting device includes a first conductive semiconductor layer, an active layer on the first conductive semiconductor layer, a second conductive semiconductor layer on the active layer, a passivation layer surrounding the first conductive semiconductor layer, the active layer, and the second conductive semiconductor layer, a first light extracting structure layer having a concave-convex structure on the passivation layer, a first electrode layer electrically connected to the first conductive semiconductor layer through the passivation layer and the first light extracting structure layer, and a second electrode layer electrically connected to the second conductive semiconductor layer through the passivation layer and the light extracting structure layer. | 2011-02-03 |
20110024785 | Light Emitting Diode Device - An electronic assembly includes a Light Emitting Diode (LED) and a substrate. The LED has a solderable surface other than the contacts. The substrate has an opening. The solderable surface is mounted substantially over the opening. When the opening is filled with solder, the solderable surface is metallically bonded with the solder in the opening. | 2011-02-03 |
20110024786 | LIGHT EMITTING DEVICE AND METHOD OF MANUFACTURING THE LIGHT EMITTING DEVICE - A method of manufacturing a light emitting device includes: a first step of forming on a supporting substrate made of a stainless steel, a plurality of conductive members each including a first region containing Au and a second region containing a metallic member having a diffusion coefficient with respect to a metal in the stainless steel smaller than a diffusion coefficient of Au with respect to the metal in the stainless steel, a second step of forming a base member made of a light-blocking resin on the supporting substrate between the conductive members, a third step of bonding a light emitting element on an upper surface of a conductive member through an adhesive member, a fourth step of covering the light emitting element with an optically transmissive sealing member, and a fifth step of removing the supporting substrate and individually separating the light emitting devices. | 2011-02-03 |
20110024787 | LIGHT EMITTING DEVICE AND METHOD OF MANUFACTURING THE SAME - A high-quality light emitting device is provided which has a long-lasting light emitting element free from the problems of conventional ones because of a structure that allows less degradation, and a method of manufacturing the light emitting device is provided. After a bank is formed, an exposed anode surface is wiped using a PVA (polyvinyl alcohol)-based porous substance or the like to level the surface and remove dusts from the surface. An insulating film is formed between an interlayer insulating film on a TFT and the anode. Alternatively, plasma treatment is performed on the surface of the interlayer insulating film on the TFT for surface modification. | 2011-02-03 |
20110024788 | SEMICONDUCTOR COMPOSITE APPARATUS, LED, LED PRINTHEAD, AND IMAGE FORMING APPARATUS - A semiconductor composite apparatus includes a substrate and a planarizing layer, and a semiconductor thin film. The planarizing layer is formed on the substrate either directly or indirectly. The planarizing layer includes a first surface that faces the substrate, and a second surface that is on the side of the planarizing layer remote from the substrate. The semiconductor thin film formed on the planarizing layer. The second surface has a roughness of not more than 5 nm. | 2011-02-03 |
20110024789 | LIGHT-EMITTING DEVICE HAVING A ROUGHENED SURFACE WITH DIFFERENT TOPOGRAPHIES - This invention provides an optoelectronic semiconductor device having a rough surface and the manufacturing method thereof. The optoelectronic semiconductor device comprises a semiconductor stack having a rough surface and an electrode layer overlaying the semiconductor stack. The rough surface comprises a first region having a first topography and a second region having a second topography. The method comprises the steps of forming a semiconductor stack on a substrate, forming an electrode layer on the semiconductor stack, thermal treating the semiconductor stack, and wet etching the surface of the semiconductor stack to form a rough surface. | 2011-02-03 |
20110024790 | OPTOELECTRONIC SEMICONDUCTOR COMPONENT AND METHOD OF PRODUCING AN OPTOELECTRONIC SEMICONDUCTOR COMPONENT - An optoelectronic semiconductor component includes a connection support with a connection side, at least one optoelectronic semiconductor chip mounted on the connection side and electrically connected to the connection support, an adhesion-promoting intermediate film applied to the connection side and covering the latter at least in selected places, and at least one radiation-transmissive cast body which at least partially surrounds the semiconductor chip, the cast body being connected mechanically to the connection support by the intermediate film. | 2011-02-03 |
20110024791 | BIPOLAR SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD - A bipolar semiconductor device and method are provided. One embodiment provides a bipolar semiconductor device including a first semiconductor region of a first conductivity type having a first doping concentration, a second semiconductor region of a second conductivity type forming a pn-junction with the first semiconductor region, and a plurality of third semiconductor regions of the first conductivity type at least partially arranged in the first semiconductor region and having a doping concentration which is higher than the first doping concentration. Each of the third semiconductor regions is provided with at least one respective junction termination structure. | 2011-02-03 |
20110024792 | Photovoltaic Device Using Single Wall Carbon Nanotubes and Method of Fabricating the Same - A photovoltaic device and methods for forming the same. In one embodiment, the photovoltaic device has a silicon substrate, and a film comprising a plurality of single wall carbon nanotubes disposed on the silicon substrate, wherein the plurality of single wall carbon nanotubes forms a plurality of heterojunctions with the silicon in the substrate. | 2011-02-03 |
20110024793 | BULK HETEROJUNCTION SOLAR CELL AND METHOD OF MANUFACTURING THE SAME - Provided are a bulk heterojunction solar cell, including: a substrate; a rear electrode formed on a top surface of the substrate; a core layer comprising a copper indium gallium diselenide (CIGS) layer in which a CIGS powder is formed on a top surface of the rear electrode to be porous, an n-type buffer layer coated on the CIGS powder, and an n-type ZnO layer coated on the n-type buffer layer; and a grid electrode formed on a top surface of the core layer, and a method of manufacturing the same. A porous p-type semiconductor layer is formed by sintering CIGS powders, and then, the n-type semiconductor is coated on the surface of the CIGS powders by using a wet method such that a much larger junction area than a physical size of the solar cell is formed and a power output of the solar cell can be greatly increased. | 2011-02-03 |
20110024794 | FIN STRUCTURE FOR HIGH MOBILITY MULTIPLE-GATE TRANSISTOR - A vertical fin structure for a semiconductor transistor includes a semiconductor substrate, a fin layer on top of the substrate, a capping layer overlaying the fin layer, wherein the substrate comprises group IV semiconductor material, the fin layer comprises group IV semiconductor material, the capping layer comprises semiconductor compound from group III-V. The fin layer can comprise Ge, SiGe, SiC, or any combinations thereof. The semiconductor substrate can comprise Si, Ge, SiGe, or SiC. The capping layer can comprise GaAs, InGaAs, InAs, InSb, GaSb, GaN, InP, or any combinations thereof. The capping layer can provide more than a 4 percent lattice mismatch with the semiconductor substrate. The fin layer can be located in between shallow trench insulation (STI) layers that provide isolation from adjacent devices. The vertical fin structure can further include a high-k dielectric layer overlaying the capping layer and a metal gate layer overlaying the high-k dielectric layer. | 2011-02-03 |
20110024795 | EPITAXIAL SUBSTRATE FOR SEMICONDUCTOR DEVICE, SEMICONDUCTOR DEVICE, AND PROCESS FOR PRODUCING EPITAXIAL SUBSTRATE FOR SEMICONDUCTOR DEVICE - Provided is an epitaxial substrate capable of manufacturing a HEMT device that has excellent two-dimensional electron gas characteristics and is capable of performing normally-off operation. A channel layer is formed of a first group III nitride represented by In | 2011-02-03 |
20110024796 | EPITAXIAL SUBSTRATE FOR SEMICONDUCTOR DEVICE, SEMICONDUCTOR DEVICE, AND PROCESS FOR PRODUCING EPITAXIAL SUBSTRATE FOR SEMICONDUCTOR DEVICE - Provided is an epitaxial substrate having excellent two-dimensional electron gas characteristics and reduced internal stress due to strains. A channel layer is formed of a first group III nitride represented by In | 2011-02-03 |
20110024797 | NITRIDE-BASED SEMICONDUCTOR DEVICE WITH CONCAVE GATE REGION - In FET, a second nitride semiconductor layer is provided on a first nitride semiconductor layer, and a source electrode and a drain electrode are each provided to have at least a portion thereof in contact with the second nitride semiconductor layer. A concave portion is formed in the upper surface of the second nitride semiconductor layer to be located between the source electrode and the drain electrode. A gate electrode is provided over the concave portion to cover the opening of the concave portion. | 2011-02-03 |
20110024798 | Semiconductor device and method for manufacturing same - A semiconductor device includes: a compound semiconductor substrate; an n-channel field-effect transistor region formed on the compound semiconductor substrate, and that includes a first channel layer; an n-type first barrier layer that forms a heterojunction with the first channel layer, and supplies an n-type charge to the first channel layer; and a p-type gate region that has a pn junction-type potential barrier against the n-type first barrier layer; and a p-channel field-effect transistor region formed on the compound semiconductor substrate, and that includes a p-type second channel layer, and an n-type gate region that has a pn junction-type potential barrier against the p-type second channel layer. | 2011-02-03 |
20110024799 | COMPOUND SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING SAME - A method for manufacturing a compound semiconductor device includes forming a first compound semiconductor layer over a first substrate, the first compound semiconductor layer containing Al | 2011-02-03 |
20110024800 | Shared Resources in a Chip Multiprocessor - In one embodiment, a node comprises a plurality of processor cores and a node controller configured to receive a first read operation addressing a first register. The node controller is configured to return a first value in response to the first read operation, dependent on which processor core transmitted the first read operation. In another embodiment, the node comprises the processor cores and the node controller. The node controller comprises a queue shared by the processor cores. The processor cores are configured to transmit communications at a maximum rate of one every N clock cycles, where N is an integer equal to a number of the processor cores. In still another embodiment, a node comprises the processor cores and a plurality of fuses shared by the processor cores. In some embodiments, the node components are integrated onto a single integrated circuit chip (e.g. a chip multiprocessor). | 2011-02-03 |
20110024801 | TRANSISTORS HAVING A COMPOSITE STRAIN STRUCTURE, INTEGRATED CIRCUITS, AND FABRICATION METHODS THEREOF - A transistor includes a gate electrode disposed over a substrate. At least one composite strain structure is disposed adjacent to a channel below the gate electrode. The at least one composite strain structure includes a first strain region within the substrate. A second strain region is disposed over the first strain region. At least a portion of the second strain region is disposed within the substrate. | 2011-02-03 |
20110024802 | SEMICONDUCTOR DEVICE - To attain reduction in size of a semiconductor device having a power transistor and an SBD, a semiconductor device according to the present invention comprises a first region and a second region formed on a main surface of a semiconductor substrate; plural first conductors and plural second conductors formed in the first and second regions respectively; a first semiconductor region and a second semiconductor region formed between adjacent first conductors in the first region, the second semiconductor region lying in the first semiconductor region and having a conductivity type opposite to that of the first semiconductor region; a third semiconductor region formed between adjacent second conductors in the second region, the third semiconductor region having the same conductivity type as that of the second semiconductor region and being lower in density than the second semiconductor region; a metal formed on the semiconductor substrate in the second region, the third semiconductor region having a metal contact region for contact with the metal, the metal being electrically connected to the second semiconductor region, and a center-to-center distance between adjacent first conductors in the first region being smaller than that between adjacent second conductors in the second region. | 2011-02-03 |
20110024803 | SEMICONDUCTOR DEVICE WITH INTEGRATED CHANNEL STOP AND BODY CONTACT - A channel stop is provided for a semiconductor device that includes at least one active region. The channel stop is configured to surround the semiconductor device, to abut the at least one active region at a periphery of the semiconductor device, and to share an electrical connection with the at least one active region. | 2011-02-03 |
20110024804 | METHOD FOR FORMING HIGH GERMANIUM CONCENTRATION SIGE STRESSOR - A method for producing a SiGe stressor with high Ge concentration is provided. The method includes providing a semiconductor substrate with a source area, a drain area, and a channel in between; depositing the first SiGe film layer on the source area and/or the drain area; performing a low temperature thermal oxidation, e.g., a high water vapor pressure wet oxidation, to form an oxide layer at the top of the first SiGe layer and to form the second SiGe film layer with high Ge percentage at the bottom of the first SiGe film layer without Ge diffusion into the semiconductor substrate; performing a thermal diffusion to form the SiGe stressor from the second SiGe film layer, wherein the SiGe stressor provides uniaxial compressive strain on the channel; and removing the oxide layer. A Si cap layer can be deposited on the first SiGe film layer prior to performing oxidation. | 2011-02-03 |
20110024805 | USING HIGH-K DIELECTRICS AS HIGHLY SELECTIVE ETCH STOP MATERIALS IN SEMICONDUCTOR DEVICES - A spacer structure in sophisticated semiconductor devices is formed on the basis of a high-k dielectric material, which provides superior etch resistivity compared to conventionally used silicon dioxide liners. Consequently, a reduced thickness of the etch stop material may nevertheless provide superior etch resistivity, thereby reducing negative effects, such as dopant loss in the drain and source extension regions, creating a pronounced surface topography and the like, as are typically associated with conventional spacer material systems. | 2011-02-03 |
20110024806 | SEMICONDUCTOR DEVICES WITH ENCLOSED VOID CAVITIES - Field effect devices and ICs with very low gate-drain capacitance Cgd are provided by forming a substantially empty void between the gate and the drain regions. For vertical FETS a cavity is etched in the semiconductor (SC) and provided with a gate dielectric liner. A poly-SC gate deposited in the cavity has a central fissure (empty pipe) extending through to the underlying SC. This fissure is used to etch the void in the SC beneath the poly-gate. The fissure is then closed by a dielectric plug formed by deposition or oxidation without significantly filling the etched void. Conventional process steps are used to provide the source and body regions around the cavity containing the gate, and to provide a drift space and drain region below the body region. The etched void between the gate and drain provides lower Cgd and Ron*Qg than can be achieved using low k dielectrics. | 2011-02-03 |
20110024807 | SEMICONDUCTOR DEVICE AND METHOD FOR PRODUCING SAME - A semiconductor device includes a semiconductor substrate having at least one surface provided with a semiconductor element, wherein the semiconductor substrate includes a region of a first conductivity type, the region being formed in a surface layer portion of the semiconductor substrate; a first diffusion region of a second conductivity type, the first diffusion region having a first impurity concentration and being formed in the surface layer portion, and a pn junction being formed between the first diffusion region and the region of the first conductivity type; and a first metal silicide film formed on part of a portion of the surface corresponding to the first diffusion region. | 2011-02-03 |
20110024808 | SUBSTRATE BIAS FOR CMOS IMAGERS - A CMOS image sensor is disclosed. The CMOS imager includes a lightly doped semiconductor substrate of a first conductivity type. At least one CMOS pixel of a second conductivity type is formed in the semiconductor substrate. The semiconductor substrate is configured to receive a bias voltage applied for substantially depleting the semiconductor substrate and for forming a depletion edge within the semiconductor substrate. A well of the second conductivity type substantially surrounds the at least one CMOS pixel to form a depletion region about the at least one CMOS pixel operable to form a minimum predetermined barrier to the depletion edge within the semiconductor substrate to pinch off substrate bias in proximity to the return contact. | 2011-02-03 |
20110024809 | RING PIXEL FOR CMOS IMAGERS - A CMOS pixel is disclosed. The CMOS pixel includes a semiconductor substrate; a sense node formed in the semiconductor substrate and positioned substantially in the center of the CMOS pixel; a transfer gate formed about the sense node; and at least one photodiode formed about the transfer gate. A reset transistor, a source follower transistor, and a row select transistor are located substantially to one side of the CMOS pixel substantially adjacent to the photodiode. The sense node is operable to be floating. An implant may be formed about the photodiode configured to step potential in a direction toward the sense node. | 2011-02-03 |
20110024810 | SOI-BASED CMOS IMAGERS EMPLOYING FLASH GATE/CHEMISORPTION PROCESSING - A method of manufacturing a CMOS image sensor is disclosed. A silicon-on-insulator substrate is provided, which includes providing a silicon-on-insulator substrate including a mechanical substrate, an insulator layer substantially overlying the mechanical substrate, and a seed layer substantially overlying the insulator layer. A semiconductor substrate is epitaxially grown substantially overlying the seed layer. The mechanical substrate and at least a portion of the insulator layer are removed. An ultrathin oxide layer is formed substantially underlying the semiconductor substrate. A mono layer of metal is formed substantially underlying the ultrathin oxide layer. | 2011-02-03 |