05th week of 2014 patent applcation highlights part 31 |
Patent application number | Title | Published |
20140029281 | LIGHT SOURCE FOR AN AUTOMOTIVE HEADLIGHT WITH ADAPTIVE FUNCTION - A light source system operable in at least first and second modes to provide at least and first and second different far field illumination patterns, the system comprising: a photoluminescent material; and a light beam generator for generating, in the first mode, a first set of light beams for illuminating respective first regions of the photoluminescent material and for generating, in the second mode, a second set of light beams for illuminating respective second regions of the photoluminescent material, the first and second sets of light beams being independently controllable. In the first mode, the light beam generator generates the first set of light beams such that a first beam of the first set of light beams illuminates a first illumination region of the photoluminescent material having one side that is inclined with respect to another side of the illumination region. | 2014-01-30 |
20140029282 | ADAPTIVE LIGHTING SYSTEM FOR AN AUTOMOBILE VEHICLE - An adaptive lighting system for an automotive vehicle. The adaptive lighting system has a wavelength conversion device for receiving the light radiation (L) from the primary source and re-emitting white light radiation (B). An optical imaging system receives the white light (B) re-emitted by the wavelength conversion device and projects this light (B) in front of the vehicle to form a lighting beam, the wavelength conversion device being situated close to a focal plane of the optical imaging system, and the scanning system and the optical system being situated on the same side of the wavelength conversion device. An intensity of the white light radiation (B) emitted by the wavelength conversion device is capable of being modulated between a minimum value and a maximum value, and the scanning is performed at variable speed. | 2014-01-30 |
20140029283 | LED Retrofit Vehicle Tail Lamp - A replacement vehicular lamp assembly ( | 2014-01-30 |
20140029284 | LIGHT GUIDE FOR AN AUTOMOBILE LIGHTING AND/OR SIGNALING DEVICE - The light guide for an automobile lighting and/or signaling device comprises at least one coupler having at least two input faces arranged so that, when a light source is positioned at a predetermined point in relation to the coupler, for each of the input faces, all the rays from the source passing geometrically through the point and penetrating into the guide through the input face are refracted there in mutually parallel planes. | 2014-01-30 |
20140029285 | SEMICONDUCTOR INCANDESCENT LAMP RETROFIT LAMP - A semiconductor incandescent lamp retrofit lamp may include: at least one semiconductor light source, at least one light scattering body, and at least one optical waveguide, into which light of the at least one semiconductor light source can be coupled, wherein the at least one light scattering body is configured and arranged for the purpose of diffusely emitting light supplied thereto from the at least one semiconductor light source by way of the at least one optical waveguide. | 2014-01-30 |
20140029286 | INTERIOR LAMP FOR VEHICLE - An interior lamp includes a design portion and a function portion. A circuit board is attached to the function portion. A light source is mounted on the circuit board. Terminals are mounted on a side portion of the circuit board. A connector is disposed on a side portion of the function portion. Connector terminals are provided on the connector. A switch has a switch knob and a switch body. The switch knob is attached to a side portion of the design portion. The switch body is attached to the side portion of the function portion. The switch knob and the switch body are operated in an interlocked manner to perform electrical connection between the terminals and the connector terminals selectively so as to perform a tuning on or off of the light source. | 2014-01-30 |
20140029287 | PROJECTOR TYPE HEADLIGHT - A projector type headlight can include a projection lens arranged on an optical axis extending in a longitudinal direction of a vehicle, and a light source unit arranged on a more rear side than a back side focal plane of the projection lens, the projection lens including resin lenses which are arranged on the optical axis. A resin lens out of the resin lenses arranged closer to the light source unit includes a diffraction grating provided on a lens face in a side opposite to a light source, the resin lens out of the resin lenses arranged closer to the light source unit has a lens face having a positive power, which is arranged in a light source side, and the diffraction grating is designed so as to cancel chromatic aberration of light emitted from the light source unit and emitted forward through the resin lenses. | 2014-01-30 |
20140029288 | Multiple Lamp Element Adjuster for a Vehicle - A vehicular lighting adjustment system ( | 2014-01-30 |
20140029289 | VEHICLE HEADLAMP - A vehicle headlamp includes a first lamp unit having a first irradiation range, the first lamp unit being configured such that the first irradiation range is adjustable in a horizontal direction, and a second lamp unit having a second irradiation range, the second lamp unit being configured such that the second irradiation range is adjustable in a vertical direction. A resolution of the second lamp unit with respect to the second irradiation range is higher than a resolution of the first lamp unit with respect to the first irradiation range. | 2014-01-30 |
20140029290 | SOLID-STATE LIGHT SOURCE - A solid-state light source includes a semiconductor light source for emitting light and an optical system having a fiber optic element. The fiber optic element has an input for receiving emitted light from the semiconductor light source. The fiber optic element also has an output for emitting light received from the solid-state light source. The semiconductor light source and the fiber optic element in aggregate form an illumination path. | 2014-01-30 |
20140029291 | LIGHTING DEVICE - The lighting device includes a rod and two or more lighting units superimposing each other. Each of the lighting units includes a housing and a lighting element. The housing has a through hole, a first conductive element, a second conductive element and a positioning mechanism. The through hole is penetrated by the rod so that the housing can turn about the rod. The positioning mechanism limits the lighting units to turn between a first position and a second position. The first conductive elements and second conductive elements of the lighting units make contact at the second position, respectively. | 2014-01-30 |
20140029292 | LINEAR LIGHTING DEVICE - The present invention provides a linear lighting device which includes an elongated light guide, a light source disposed at an end in a longitudinal direction of the light guide, and a case accommodating the light guide and the light source. In the linear lighting device, the light guide has a plurality of grooves arranged in the longitudinal direction of the light guide, and has a stepped cutout at the other end on an opposite side from the end, and a protruding portion protruding into the cutout is formed on an inner surface of the case which faces the cutout. | 2014-01-30 |
20140029293 | LCD SHOWER - An LCD shower includes a body part with waterway, an information acquisition module, a transparent or semitransparent display module, a CPU connected to the information acquisition module and the display module and a power module to supply power to the information acquisition module, the display module and the CPU; the body part is disposed with a through hole, the display module is assembled in the through hole, wherein the display module includes a LCD screen, a first light guiding panel and a second light guiding panel, the LCD screen is sealed and disposed between the first light guiding panel and the second light guiding panel. User can see the display information of the LCD screen from one side of the first light guiding panel or the second light guiding panel; at the same time, as the display module is transparent or semi-transparent. | 2014-01-30 |
20140029294 | BACKLIGHT MODULE - The present invention provides a backlight module, which includes a backplane, a backlight source arranged inside the backplane, a light guide plate arranged inside the backplane to correspond to the backlight source, a reflector plate arranged between the light guide plate and the backplane, an optic film disposed on the light guide plate, a mold frame arranged on the backplane, and a block wall arranged between the light guide plate and the mold frame and opposing the backlight module. The block wall forms a slope face close to the backlight source. A reflective layer is formed on the slope face. Being provided between the mold frame and the light guide plate, the block wall reflects light that gets incident thereon back into the light guide plate in order to eliminate leak through a gap between an optic film assembly and the light guide plate. | 2014-01-30 |
20140029295 | HYBRID LIGHT GUIDE PLATE AND DISPLAY DEVICE - A display device includes a housing, a frame bonded to the housing, and a display module. The display module includes a back cover bonded to the frame, a light guide plate (LGP), a support element, a display panel, and an optical film set. The LGP is supported on the back cover and has a light exiting surface and an opposite back surface. At least two sides of the LGP's back surface are adhered on the back cover, and the LGP is made of glass. The support element and display panel are supported respectively on the LGP and support element. The optical film set is between the display panel and LGP. A hybrid LGP includes a first light guide sub-plates and a second light guide sub-plate. The second light guide sub-plate is stacked on and bonded to the first light guide sub-plate. | 2014-01-30 |
20140029296 | ILLUMINATION DEVICE AND DISPLAY DEVICE - A backlight device (illumination device) | 2014-01-30 |
20140029297 | DISPLAY DEVICE - A display device includes a side light type backlight for white color display by single color LEDs, an LED set is placed in a concave portion of a light guide plate, in which a first color LED is located in the center and a second or third color LED is located on the side of the first color LED. An incident slit with an arc shaped convex portion is formed facing the first color LED, and a saw tooth slit with a right-angled triangular concave portion is formed facing the second or third color LED. This allows directing the distribution axes of the lights from the second and third color LEDs to the center side, and adjusting orientation angles to allow effective mixing of the three color lights, in order to increase the white color area and effective display area. | 2014-01-30 |
20140029298 | OPTICAL MEMBER AND DISPLAY DEVICE INCLUDING THE SAME - Disclosed are an optical member and a display device including the same. The optical member includes a receiving member; a host in the receiving member; and a plurality of wavelength conversion particles distributed in the host. The receiving member includes a light incident part having a first refractive index; and a light exit part having a second refractive index different from the first refractive index. The optical member improves the optical characteristics by adjusting the refractive indexes of the light incident part and the light exit part. | 2014-01-30 |
20140029299 | OPTICAL MEMBER, DISPLAY DEVICE INCLUDING THE SAME, AND METHOD FOR MANUFACTURING THE SAME - Disclosed are an optical member, a display device having the same and a method of fabricating the same. The optical member includes a host; a plurality of light conversion particles dispersed in the host to convert a wavelength of light generated from a light source; and a protective layer surrounding the host and including plastic. | 2014-01-30 |
20140029300 | LIGHTING SYSTEM AND DISPLAY DEVICE - A plurality of prisms | 2014-01-30 |
20140029301 | Backlight Module and Liquid Crystal Display Device - The present invention discloses a backlight module which can be incorporated within the liquid crystal display device, and which includes a waveguide, a heat dissipating frame, a light source and a backframe. The heat dissipating frame includes a carrying portion and a sidewalk The carrying portion abuts against a bottom surface of the waveguide. The carrying portion is defined with openings in an area adjacent to the sidewalk. The light source is mounted onto the sidewall and offset to the opening. The backframe includes a bottom board and erections which extend and pass through the opening. The bottom board abuts the carrying portion. The thickness of the erection is larger than the thickness of the light source such that expansion of the waveguide exposed under heat will not in contacting with the light source. Accordingly, the light source will not be damaged by the expansion of the waveguide, and therefore prolong the service of the light source. | 2014-01-30 |
20140029302 | BACKLIGHT MODULE AND ASSEMBLY METHOD THEREOF - A backlight module includes a light guide plate with at least one light incident surface, and a light source structure arranged at a side of the light guide plate. The light source structure includes a reflection cover and at least one light emitting module. At least one positioning pin is arranged on the reflection cover. The at least one light emitting module is installed on the reflection cover and corresponding to the at least one light incident surface. The at least one light emitting module is fixed on the positioning pin in a rotatable manner, such that the at least one light emitting module can rotate around the positioning pin as an axis when the reflection cover is combined with the light guide plate, so as to allow the at least one light emitting module facing the at least one light incident surface. | 2014-01-30 |
20140029303 | Backlight Module and Liquid Display Devices with the Same - A backlight module including a back frame, a light guiding plate received in the back frame, and a position piece is disclosed. The position piece is arranged between the back frame and the light guiding plate, and the position piece is detachably fixed on sidewalls of the back frame to firmly press the light guiding plate within the back frame. In addition, a liquid crystal display with the backlight module is also disclosed. The light guiding plate is reliably positioned by adopting the above position piece. | 2014-01-30 |
20140029304 | SIDE-EDGE BACKLIGHT MODULE HAVING NON-UNIFORMLY SIZED BACKLIGHT SECTIONS AND DESIGN METHOD THEREOF - The present invention relates to a side-edge backlight module having non-uniformly sized backlight sections and a design method thereof. The backlight module includes backlight sections that have relative sizes satisfying the condition that the backlight sections have higher ranks are of greater sizes. Ranking the backlight sections is made by conducting an simulation operation for a process of sectionalized lighting of backlight to display liquid crystal panel signals on the basis of uniformly sized backlight sections and conducting analysis of the number of zones where an interference signal appears and distance of the interference signal when each of backlight sections is lit in the simulation operation on the basis of uniformly sized backlight sections and ranking the backlight sections according to strength of cross-talking caused by the interference signal so that a backlight section having less strong cross-talking is set with a higher rank. | 2014-01-30 |
20140029305 | LIGHT SOURCE MODULE - A light source module including a light emitting element and a light guiding element is provided. The light guiding element has a light incident surface, a light emitting surface, a first surface, a second surface, a first reflective layer, and a second reflective layer. The light emitting element faces to the light incident surface. The light incident surface is connected to the light emitting surface. The first surface is connected to the light emitting surface and opposite to the light incident surface. The first surface is non-parallel to the light incident surface. The second surface is connected to the first surface and opposite to the light emitting surface. The first reflective layer is disposed on the first surface. The second reflective layer is disposed on the second surface. | 2014-01-30 |
20140029306 | LIGHT GUIDE PLATE, LIGHT GUIDE PLATE MANUFACTURING METHOD, AND LIGHT GUIDE PLATE MANUFACTURING APPARATUS - A light guide pate includes: a light guide member with a light incident surface and first and second principal surfaces; and first and second protrusions formed on at least one of the first and second principal surfaces. When the first principal surface is viewed in a normal direction, a distance between the light incident surface and the second protrusion is larger than a distance between the light incident surface and the first protrusion; each of the first and second protrusions has a shape, a length of which in an orthogonal direction orthogonal to a propagation direction of light incident from the light incident surface increases monotonously in the propagation direction; and a minimum value of the length of the second protrusion in the orthogonal direction is larger than a maximum value of the length of the first protrusion in the orthogonal direction. | 2014-01-30 |
20140029307 | THIN LIGHT GUIDE DEVICE UTILIZING LED FLASH ON A PORTABLE ELECTRONIC APPARATUS - A thin light guide device applying LED flash on a portable electronic apparatus is to utilize a reflection unit such as a mirror to change forward direction of the light emitting from a LED flash, thereby making the LED flash capable of providing illumination, decoration and light source projecting to the display for enhancing functions of the LED flash. | 2014-01-30 |
20140029308 | INVERTER HAVING EXTENDED LIFETIME DC-LINK CAPACITORS - An inverter having extended lifetime DC-link capacitors for use with a DC power source such as a photovoltaic panel is described. The inverter uses a plurality of switchable capacitors to control the voltage across the capacitors. The expected lifetime of the capacitors can be extended by disconnecting unnecessary capacitors from a voltage. The capacitors may be periodically connected to a voltage in order to maintain an oxide dielectric layer of the capacitor. | 2014-01-30 |
20140029309 | POWER CONVERTER WITH LOW RIPPLE OUTPUT - A power supply includes two or more input waveforms being shaped or selected so that after being separately level-shifted and rectified, their additive combination results in a DC output waveform with substantially no ripple. The power supply may comprise a waveform generator, a level conversion stage for step up or down conversion, a rectification stage, and a combiner. The waveform generator may generate complementary waveforms, preferably identical but phase offset from each other, such that after the complementary waveforms are level-converted, rectified and additively combined their sum will be constant, thus requiring no or minimal smoothing for generation of a DC output waveform. The level conversion may be carried out using transformers or switched capacitor circuits. Feedback from the DC output waveform may be used to adjust the characteristics of the input waveforms. | 2014-01-30 |
20140029310 | POWER CONVERSION APPARATUS - A power conversion apparatus is disclosed. The power conversion apparatus includes a power transistor, a thermal resistor and a temperature detection circuit. A control terminal of the power transistor receives a control signal. The power transistor converts an input voltage into an output voltage according to the control signal. The thermal resistor has a negative temperature coefficient. The temperature detection circuit generates the control signal and provides a driving current to the control terminal of the power transistor according to the control signal. The temperature detection circuit further generates an over temperature protection signal according to the driving current. | 2014-01-30 |
20140029311 | SYNCHRONOUS RECTIFYING APPARATUS AND CONTROLLING METHOD THEREOF - The present application provides a synchronous rectifying apparatus and a control method thereof, the apparatus comprising: a transformer, a primary circuit, a rectifying circuit, a self-driving circuit, a PWM control circuit and an auxiliary control module including at least one auxiliary control circuit and at least one auxiliary winding, wherein the auxiliary control circuit includes at least one auxiliary switch and is electrically coupled to the Pulse Width Modulation control circuit and the auxiliary winding via the auxiliary switch, and the auxiliary winding is electrically coupled to the transformer; wherein before the transfer switch of the primary circuit is controlled to be turned on by the switching control signal, the auxiliary switch is controlled to be turned on by the auxiliary control signal, and the synchronous rectifier of the rectifying circuit is controlled to be turned off through the self-driving signal. | 2014-01-30 |
20140029312 | HIGH POWER CONVERTER ARCHITECTURE - The power converter is an integration of three topologies which include a forward converter topology, a flyback converter topology, and a resonant circuit topology. The combination of these three topologies functions to transfer energy using three different modes. A first mode, or forward mode, is a forward energy transfer that forwards energy from the input supply to the output load in a manner similar to a forward converter. A second mode, or flyback mode, stores and releases energy in a manner similar to a flyback converter. A third mode, or resonant mode, stores and releases energy from the resonant tank using a resonant circuit and a secondary side forward-type converter topologies. An output circuit of the power converter is configured as a forward-type converter including two diodes and an inductor. The output circuit is coupled to a secondary winding of a converter transformer. | 2014-01-30 |
20140029313 | HIGH POWER CONVERTER ARCHITECTURE - The power converter is an integration of three topologies which include a forward converter topology, a flyback converter topology, and a resonant circuit topology. The combination of these three topologies functions to transfer energy using three different modes. A first mode, or forward mode, is a forward energy transfer that forwards energy from the input supply to the output load in a manner similar to a forward converter. A second mode, or flyback mode, stores and releases energy in a manner similar to a flyback converter. A third mode, or resonant mode, stores and releases energy from the resonant tank using a resonant circuit and a secondary side forward-type converter topologies. | 2014-01-30 |
20140029314 | TRANSFORMER-COUPLED GATE-DRIVE POWER REGULATOR SYSTEM - A transformer-coupled gate-drive power regulator system is provided that includes a feedback stage that generates a PWM signal having a duty-cycle that is based on a magnitude of an output voltage in an output stage. A switch driver stage configured to provide each of a first control signal and a second control signal based on the PWM signal. A switching stage comprising a first transformer input stage, a second transformer input stage, and a control switch. The first transformer input stage activates the control switch via the first control signal while the second transformer input stage is deactivated, and the second transformer input stage activates the control switch via the second control signal while the first transformer input stage is deactivated. The control switch can be configured to provide current through an output inductor in the output stage to generate the output voltage in response to being activated. | 2014-01-30 |
20140029315 | SYSTEMS AND METHODS FOR CURRENT CONTROL OF POWER CONVERSION SYSTEMS - System and method for regulating an output current of a power conversion system. An example system controller for regulating an output current of a power conversion system includes a driving component, a demagnetization detector, a current-regulation component, and a signal processing component. The driving component is configured to output a drive signal to a switch in order to affect a primary current flowing through a primary winding of the power conversion system. The demagnetization detector is configured to receive a feedback signal associated with an output voltage of the power conversion system and generate a detection signal based on at least information associated with the feedback signal. The current-regulation component is configured to receive the drive signal, the detection signal and a current-sensing signal and output a current-regulation signal based on at least information associated with the drive signal, the detection signal, and the current sensing signal. | 2014-01-30 |
20140029316 | METHOD AND CIRCUIT FOR CONTROLLING A SWITCHING REGULATOR - A method for controlling a switching regulator includes defining a waiting time during which a trigger signal corresponding to a recirculation signal of the switching regulator is ignored holding a control switch in an open condition, and detecting a number of local valleys of the recirculation signal during the waiting time. In particular, defining the waiting time is performed for each switching cycle by adding a first value, which is determined on the basis of a load on the regulator, to a second variable value, which is proportional to the number valleys detected during the waiting time of the preceding switching cycle. | 2014-01-30 |
20140029317 | Non-Contact Transformer - A non-contact transformer assembly comprises an iron core having a pole with a length longer than the total height of the transmitting coil and the receiving coil to improve the induced voltage and magnetic field of the receiving coil and achieve the high effect of flux conversion. | 2014-01-30 |
20140029318 | PASSIVE POWER FACTOR CORRECTION CIRCUIT - The disclosure relates to a passive power factor correction circuit. The passive power factor correction circuit comprises: a filtering device being used for decreasing high order harmonic of an input current; a resonance device being coupled to the filtering device for controlling operation time of the input current; and a suppression device being coupled to the resonance device for suppressing ripple of the input current. | 2014-01-30 |
20140029319 | RECTIFIER MODULE FOR POWER CONVERSION CIRCUITS - A rectifier module comprises a conductive housing made of injection molded aluminum or aluminum alloy. Diodes are inserted into recesses formed in the housing. The housing is placed at an alternating input potential during operation, and transmits alternating current input power to the diode modules for conversion to direct current power. Multiple recesses may be provided for high and low side diodes, of which there may be one or many. Multiple such modules may be provided for converting multiple phases of input power to direct current power. | 2014-01-30 |
20140029320 | Power Conversion with Added Pseudo-Phase - Methods and systems for power conversion. An energy storage capacitor is contained within an H-bridge subcircuit which allows the capacitor to be connected to the link inductor of a Universal Power Converter with reversible polarity. This provides a “pseudo-phase” drive capability which expands the capabilities of the converter to compensate for zero-crossings in a single-phase power supply. | 2014-01-30 |
20140029321 | RECTIFICATION CIRCUIT - A rectification circuit includes a first input terminal, a first switch, an energy storage circuit, a first diode, a filtering circuit connected in series and in order to ground, a second diode, and a controller. Two opposite terminals of the second diode are connected to a first node between the first diode and the filtering circuit and a second node between the first switch and the energy storage circuit. The controller transmits control signals to the first switch and the second switch to control conductivities of the first switch and the second switch. | 2014-01-30 |
20140029322 | ELECTRIC POWER CONVERTER AND METHOD FOR OPERATING THE SAME - A power converter includes a plurality of semiconductor switching devices coupled in a parallel configuration and positioned proximate each other in an interlaced configuration with respect to a plurality of electrical phases. The interlaced configuration facilitates inducing an electric current flow through each semiconductor switching device of the plurality of semiconductor switching devices that cancels at least a portion of current imbalances between at least a portion of the plurality of semiconductor switching devices. | 2014-01-30 |
20140029323 | POWER CONVERTER IN WHICH SWITCHING ELEMENTS ARE DRIVEN IN PARALLEL - A power converter for converting DC power to AC power by switching operation of a switching element includes: a bridge circuit configured by at least two series circuits using, as power input terminals, terminals on both sides of two switching elements connected to each other in series and using, as a power output terminal, a connection point of the two switching elements are connected in parallel via the power output terminal; a gate drive circuit for outputting a driving signal which controls to turn on/off the switching elements; and signal lines using a driving signal output terminal in the gate drive circuit as a starting point of wiring, individually hard-wired to each of the switching elements in each of series circuits to which the same driving signal is supplied from the driving signal output terminal, and having inductances which are configured equal to each other. | 2014-01-30 |
20140029324 | POWER SUPPLY DEVICE - Provided is a power supply device that can suitably release heat with a small number of parts. In an AC-DC converter that is a power supply device according to an embodiment of the present invention, a heat conductive member thermally connected to a base plate is thermally connected to an upper surface of a stacked coil board including a main circuit board and circuit boards. This configuration causes heat generated in the stacked coil board to be transferred to the base plate also from the upper surface of the stacked coil board via the heat conducting member, whereby the heat release effect can be increased. In addition, since the heat conducting member is the only member used for releasing heat, the heat release effect can be increased while the number of parts is kept from increasing. | 2014-01-30 |
20140029325 | APPARATUS AND METHODS FOR A PHYSICAL LAYOUT OF SIMULTANEOUSLY SUB-ACCESSIBLE MEMORY MODULES - A layout for simultaneously sub-accessible memory modules is disclosed. In one embodiment, a memory module includes a printed circuit board having a plurality of sectors, each sector being electrically isolated from the other sectors and having a multi-layer structure. At least one memory device is attached to each sector, the memory devices being organized into a plurality of memory ranks. A driver is attached to the printed circuit board and is operatively coupled to the memory ranks. The driver is adapted to be coupled to a memory interface of the computer system. Because the sectors are electrically-isolated from adjacent sectors, the memory ranks are either individually or simultaneously, or both individually and simultaneously accessible by the driver so that one or more memory devices on a particular sector may be accessed at one time. In an alternate embodiment, the printed circuit board includes a driver sector electrically isolated from the other sectors and having a multi-layer structure, the driver being attached to the driver sector. | 2014-01-30 |
20140029326 | FERROELECTRIC RANDOM ACCESS MEMORY WITH A NON-DESTRUCTIVE READ - An embodiment of the invention provides a ferroelectric random access memory with a non-destructive read cycle. During the non-destructive read cycle, a plate of the ferroelectric capacitor in a selected one-capacitor, one-transistor memory cell and a bit line electrically connected to the selected one-capacitor, one-transistor memory cell are grounded. A word line electrically connected to a pass transistor in the one-capacitor, one-transistor selected memory cell is charged to a logical high value. The pass-transistor connects the bit line and the ferroelectric capacitor. The bit line is charged to a voltage less than the disturb voltage of the ferroelectric capacitor. The sense amplifier senses the voltage difference between the voltage on the bit line and a reference voltage. After the sensing occurs, the word line is grounded. | 2014-01-30 |
20140029327 | BIPOLAR RESISTIVE SWITCH HEAT MITIGATION - A heat mitigated bipolar resistive switch includes a BRS matrix sandwiched between first and second electrodes and a heat mitigator. The BRS matrix is to support bipolar switching of a conduction channel formed between the first and second electrodes through BRS matrix. The heat mitigator is to reduce heat in the BRS matrix generated during bipolar switching. The heat mitigator includes one or both of a parallel-connected NDR element to limit current flowing in the BRS matrix and a high thermal conductivity material to conduct the generated heat away from the BRS matrix above a predetermined elevated temperature. | 2014-01-30 |
20140029328 | Storing Data in a Non-volatile Latch - Storing data in a non-volatile latch may include applying a bias voltage to a memristor pair in electrical communication with at least one logic gate and applying a gate voltage to a transmission gate to allow an input voltage to be applied to the at least one logic gate where the input voltage is greater than the bias voltage and the input voltage determines a resistance state of the memristor pair. | 2014-01-30 |
20140029329 | WORD LINE SELECTION CIRCUIT AND ROW DECODER - A first exemplary aspect of the present invention is a word line selection circuit where address decode signals composed of a power supply voltage and a first voltage lower than a ground voltage are input, and that a word line selection signal composed of the first voltage and a second voltage higher than the power supply voltage is output not via a level shift circuit according to the address decode signals. | 2014-01-30 |
20140029330 | METHOD FOR DRIVING NONVOLATILE MEMORY ELEMENT, AND NONVOLATILE MEMORY DEVICE - A method for driving a nonvolatile memory element includes: a writing step of changing a variable resistance layer to a low resistance state, by applying a writing voltage pulse having a first polarity; and an erasing step of changing the variable resistance layer to a high resistance state, by applying an erasing voltage pulse having a second polarity different from the first polarity, wherein in the writing step, a first input and output terminal of a field effect transistor is a source terminal of the transistor, and when a pulse width of the writing voltage pulse is PWLR and a pulse width of the erasing voltage pulse is PWHR, PWLR and PWHR satisfy a relationship of PWLR2014-01-30 | |
20140029331 | MEMORY DEVICE WITH MULTI-MODE DESERIALIZER - An integrated circuit memory device is disclosed. The memory device includes a memory core having a timing input to receive a clock signal. An interface couples to the memory core. The interface includes a receiver to receive a serial stream of write data bits and a sampler clocked by a strobe signal to generate serialized write data. The interface also includes a deserializer and control logic. The deserializer includes an input to receive the serialized write data and an output to generate parallel data responsive to a control signal generated by the control logic. In a first mode of operation, the control logic generates the control signal with respect to the clock signal. In a second mode of operation, the control logic generates the control signal with respect to the strobe signal. | 2014-01-30 |
20140029332 | USE OF HYDROCARBON NANORINGS FOR DATA STORAGE - Hydro-carbon nanorings may be used in storage. Sufficiently cooled, an externally hydrogen doped carbon nanoring may be used to create a radial dipole field to contain streams of electrons. Similarly, an internally hydrogen doped carbon nanoring may be used to create a radial dipole field to contain streams of positrons. When matched streams of positrons and electrons are sufficiently compressed they may form Cooper pairs with magnetic moments aligned to the movement of the stream. Matched adjacent Cooper pairs of electrons and positrons may contain information within their magnetic moments, and as such, may transmit and store information with little or no energy loss. | 2014-01-30 |
20140029333 | FIVE TRANSISTOR SRAM CELL - A five transistor static random-access-memory (SRAM) cell is disclosed which can be made part of an SRAM array to provide an improved reduction in size. The cell includes two cross-coupled inverters, each having two complementary transistors, and an n-channel transistor switch connected to a bit line (BL) and a word line (WL). The p-channel element of one of the inverters is connected to a power supply, and the p-channel transistor of the other inverter is coupled to a write bit line (WBL). By varying the voltage levels on the BL and WBL lines the biasing of the individual n-channel transistors of each of the inverters can be changed based on the data to be written to the cell. Various biasing systems are presented such that the SRAM cell memory state can be changed without requiring larger transistor elements to overpower the cell state. | 2014-01-30 |
20140029334 | MAGNETIC FIELD SENSING USING MAGNETORESISTIVE RANDOM ACCESS MEMORY (MRAM) CELLS - A magnetic field sensing system includes one or more magnetoresistive random access memory (MRAM) cells, and may be configured to determine one or more of a presence, a magnitude, and a polarity of an external magnetic field incident upon an MRAM cell. In some examples, a control module of the system controls a write current source, or another device, to provide a write current through a write line associated with the MRAM cell to induce a magnetic field proximate to the MRAM cell. The magnetic field may be less than a magnetic switching threshold of the MRAM cell. After initiating the provision of the write current through the write line, the control module may determine a magnetic state of the MRAM cell, and determine a presence of an external magnetic field incident upon the MRAM cell based at least in part on the magnetic state of the MRAM cell. | 2014-01-30 |
20140029335 | METHODS AND SYSTEMS FOR ADJUSTING NVM CELL BIAS CONDITIONS BASED UPON OPERATING TEMPERATURE TO REDUCE PERFORMANCE DEGRADATION - Methods and systems are disclosed for making temperature-based adjustments to bias conditions for non-volatile memory (NVM) cells to improve performance and product lifetime of NVM systems. System embodiments include integrated NVM systems having an NVM controller, a bias voltage generator, and an NVM cell array. Further, the NVM systems can store temperature-based bias condition information in storage circuitry. The disclosed embodiments select and apply bias conditions for the NVM cells based upon temperature measurements. | 2014-01-30 |
20140029336 | SYSTEMS AND METHODS OF UPDATING READ VOLTAGES - A method includes, in a data storage device that includes a non-volatile memory, selecting an updated reference voltage as one of a reference voltage, a first alternate reference voltage and a second alternate reference voltage. The first alternate reference voltage and the second alternate reference voltage are calculated based on the reference voltage and based on a voltage increment. Selection of the updated reference voltage is based on a comparison of error counts, each error count associated with a unique one of the reference voltage, the first alternate reference voltage, and the second alternate reference voltage. The method includes resetting the reference voltage to the updated reference voltage, resetting the voltage increment to a reset voltage increment that is smaller than the voltage increment, and selecting an additional updated reference voltage based on the reset reference voltage and based on the reset voltage increment. | 2014-01-30 |
20140029337 | SEMICONDUCTOR MEMORY DEVICE WHICH STORES PLURAL DATA IN A CELL - A memory cell array is configured to have a plurality of memory cells arranged in a matrix, each of the memory cells being connected to a word line and a bit line and being capable of storing n values (n is a natural number equal to or larger than 3). A control circuit controls the potentials of the word line and bit line according to input data and writes data into a memory cell. The control circuit writes data into the memory cell to a k-valued threshold voltage (k<=n) in a write operation, precharges the bit line once, and then changes the potential of the word line an i number of times to verify whether the memory cell has reached an i-valued (i<=k) threshold voltage. | 2014-01-30 |
20140029338 | STORAGE AT M BITS/CELL DENSITY IN N BITS/CELL ANALOG MEMORY CELL DEVICES, M>N - A method for data storage includes accepting data for storage in a memory that includes multiple analog memory cells and supports a set of built-in programming commands. Each of the programming commands programs a respective page, selected from a group of N pages, in a subset of the memory cells. The subset of the memory cells is programmed to store M pages of the data, M>N, by performing a sequence of the programming commands drawn only from the set. | 2014-01-30 |
20140029339 | NONVOLATILE SEMICONDUCTOR MEMORY DEVICE AND METHOD FOR ITS USE - A nonvolatile semiconductor memory device comprises multiple cell units that are arranged in the form of a matrix in the memory cell region, a bit line that is connected to the drain of one side of the selector gate transistor of each of the cell units and that is arranged in an extending direction of the multiple cell units, a source line that is connected to the source of the other side of the selector gate transistor of each of the cell units and that is arranged at right angle to the multiple cell units, and a bit line charge-discharge transistor that charges and discharges the bit line and that is arranged adjacent to the contact connected to the bit line on the region of drain side of at least one of the selector gate transistors of the multiple cell units. | 2014-01-30 |
20140029340 | STRUCTURES AND OPERATIONAL METHODS OF NON-VOLATILE DYNAMIC RANDOM ACCESS MEMORY DEVICES - A Dynamic Random Access Memory (DRAM) cell and a semiconductor Non-Volatile Memory (NVM) cell are incorporated into a single Non-Volatile Dynamic Random Access Memory (NVDRAM) cell. The NVDRAM cell is operated as the conventional DRAM cell for read, write, and refreshment on dynamic memory applications. Meanwhile the datum in the NVM cells can be directly loaded into the correspondent DRAM cells in the NVDRAM cell array without applying intermediate data amplification and buffering leading to high speed non-volatile data access. The datum in DRAM cells can be also stored back to the correspondent semiconductor NVM cells in the NVDRAM cells for the datum required for non-volatile data storage. The NVDRAM of the invention can provide both fast read/write function for dynamic memory and non-volatile memory storage in one unit memory cell. | 2014-01-30 |
20140029341 | NON-VOLATILE SOLID STATE MEMORY-BASED MASS STORAGE DEVICE AND METHODS THEREOF - Non-volatile solid state mass storage device and methods for improving write performance thereof. The storage device includes a NAND flash controller, an array of NAND flash memory integrated circuits, and means for determining a lowest unused page number of each write target block in a group of the NAND flash memory integrated circuits that are simultaneously accessible at any given time by a write command. The storage device has further means for programming a dummy write to at least a first write target block in a first NAND flash memory integrated circuit within the group of NAND flash memory integrated circuits if the lowest unused page number within the first write target block is lower than the lowest unused page number of a second write target block in a second NAND flash memory integrated circuit in the group of NAND flash memory integrated circuits. | 2014-01-30 |
20140029342 | EXPERIENCE COUNT DEPENDENT PROGRAM ALGORITHM FOR FLASH MEMORY - In a non-volatile memory device, the parameters used in write and erase operation are varied based upon device age. For example, in a programming operation using a staircase waveform, the amplitude of the initial pulse can be adjusted based upon the number of erase-program cycles (hot count) of the block containing the selected physical page for the write. This arrangement can preserve performance for relatively fresh devices, while extending life as a devices ages by using gentler waveforms as the device ages. | 2014-01-30 |
20140029343 | NONVOLATILE SEMICONDUCTOR MEMORY DEVICE - According to one embodiment, a nonvolatile semiconductor memory device comprises a memory cell array including memory cell transistors configured to store information in accordance with n (n is an integer larger than 2) threshold voltage levels, and a control circuit configured to control the memory cell array. In a write operation, the control circuit shifts a threshold voltage level of a write target memory cell transistor to a base threshold level of the n threshold levels, except for a threshold level having a highest voltage and a threshold level having a lowest voltage. Then the control circuit shifts the threshold voltage level of the write target memory cell transistor from the base threshold level to one of the n threshold levels. | 2014-01-30 |
20140029344 | NONVOLATILE MEMORY DEVICE, PROGRAMMING METHOD THEREOF AND MEMORY SYSTEM INCLUDING THE SAME - Provided is a programming method of a nonvolatile memory device. The nonvolatile memory device includes a substrate and a plurality of memory cells which are stacked in the direction perpendicular to the substrate. The programming method applies a first voltage to a selected bit line connected to at least two memory strings in same column including a memory cell of the plurality of memory cell to be programmed, applies a second voltage to an unselected bit line connected to at least two memory strings in same column including a memory cell of the plurality of memory cell to be program-prohibited, applies a third voltage to a selected string selection line connected to at least two memory strings in same row, applies a fourth voltage to an unselected string selection line connected to at least two memory strings in same row, and applies a program operation voltage to a plurality of word lines, each word line connected to each corresponding memory cell in the memory string, wherein the first to third voltages are positive voltages. | 2014-01-30 |
20140029345 | MEMORY DEVICES AND PROGRAMMING MEMORY ARRAYS THEREOF - An embodiment of a method includes decreasing a difference of a voltage applied to a first select gate minus a voltage applied to a source while the first select gate is off, decreasing a difference of a voltage applied to a second select gate minus a voltage applied to a data line while the second select gate is off, and increasing a voltage of a signal applied to a selected access line that is coupled to an untargeted memory cell in a string of memory cells coupled to the first and second select gates to a program voltage after or substantially concurrently with decreasing the difference of the voltage applied to the first select gate minus the voltage applied to the source and with decreasing the difference of the voltage applied to the second select gate minus the voltage applied to the data line. | 2014-01-30 |
20140029346 | CHARGE PUMP REDUNDANCY IN A MEMORY - An integrated circuit includes a circuit block to utilize a load current at a load voltage from a power input and two or more charge pump arrays. The outputs of the charge pump arrays are coupled to the power input of the circuit block. The integrated circuit includes one or more modifiable elements to disable one or more of the two or more charge pump arrays. | 2014-01-30 |
20140029347 | MEMORY SYSTEM HAVING A PLURALITY OF SERIALLY CONNECTED DEVICES - A semiconductor memory device and system are disclosed. The memory device includes a memory, a plurality of inputs, and a device identification register for storing register bits that distinguish the memory device from other possible memory devices. Circuitry for comparing identification bits in the information signal with the register bits provides positive or negative indication as to whether the identification bits match the register bits. If the indication is positive, then the memory device is configured to respond as having been selected by a controller. If the indication is negative, then the memory device is configured to respond as having not been selected by the controller. A plurality of outputs release a set of output signals towards a next device. | 2014-01-30 |
20140029348 | DYNAMIC PROGRAMMING FOR FLASH MEMORY - A method is for operating a memory having a group of non-volatile memory cells. A first programming pulse is applied to a subset of the group of non-volatile memory cells. The subset needs additional programming. A portion of the subset still needing additional programming is identified. A ratio of the number of memory cells in the subset and the number of memory cells in the portion is determined. A size of a second programming pulse based on the ratio is selected. The second programming pulse is applied to the portion. | 2014-01-30 |
20140029349 | VOLTAGE GENERATION AND ADJUSTMENT IN A MEMORY DEVICE - Voltage generation devices and methods are useful in determining a data state of a selected memory cell in a memory device. Voltages can be generated in response to a first current and a second current. The first current is responsive to a memory device operation and a memory cell data state associated with the memory device operation, while the second current is responsive to a temperature associated with the memory device and to the memory cell data state associated with the memory device operation. | 2014-01-30 |
20140029350 | METHODS AND SYSTEMS FOR ADJUSTING NVM CELL BIAS CONDITIONS FOR READ/VERIFY OPERATIONS TO COMPENSATE FOR PERFORMANCE DEGRADATION - Methods and systems are disclosed for adjusting read/verify bias conditions for non-volatile memory (NVM) cells to improve performance and product lifetime of NVM systems. System embodiments include integrated NVM systems having a NVM controller, a bias voltage generator, and an NVM cell array. Further, the NVM systems can store performance degradation information and read/verify bias condition information within storage circuitry. The disclosed embodiments adjust read/verify bias conditions for the NVM cells based upon performance degradation determinations, for example, temperature-based performance degradation determinations. | 2014-01-30 |
20140029351 | METHODS AND SYSTEMS FOR ADJUSTING NVM CELL BIAS CONDITIONS FOR PROGRAM/ERASE OPERATIONS TO REDUCE PERFORMANCE DEGRADATION - Methods and systems are disclosed for adjusting program/erase bias conditions for non-volatile memory (NVM) cells to improve performance and product lifetime of NVM systems. System embodiments include integrated NVM systems having an NVM controller, a bias voltage generator, and an NVM cell array. Further, the NVM systems can store performance degradation information and program/erase bias condition information within storage circuitry. The disclosed embodiments adjust program/erase bias conditions for the NVM cells based upon performance degradation determinations, for example, temperature-based performance degradation determinations and interim verify based performance degradation determinations. | 2014-01-30 |
20140029352 | VERTICAL MEMORY WITH BODY CONNECTION - An embodiment of an apparatus includes a substrate, a body semiconductor, a vertical memory access line stack over the body semiconductor, and a body connection to the body semiconductor. | 2014-01-30 |
20140029353 | METHODS AND DEVICES FOR MEMORY READS WITH PRECHARGED DATA LINES - Methods of operating memory devices including precharging an adjacent pair of data lines to a particular voltage, isolating one data line of the adjacent pair of data lines from the particular voltage while maintaining the other data line of the adjacent pair of data lines at the particular voltage, and selectively discharging the one data line depending upon a data value of a selected memory cell of a string of memory cells associated with the one data line. | 2014-01-30 |
20140029354 | NON-VOLATILE MEMORY CELL WITH HIGH BIT DENSITY - A non-volatile memory cell with high bit density is disclosed. Embodiments include: providing a transistor having a wordline gate structure over a substrate, first and second floating gate structures proximate opposite sides of the wordline gate structure, and first and second diffusion regions in the substrate, wherein the wordline gate structure, the first floating gate structure, and the second floating gate structure are laterally between the first and second diffusion regions; and providing a capacitor having first, second, and third control gate structures over the substrate, a third floating gate structure between the first and second control gate structures, a fourth floating gate structure between the second and third control gate structures, and third and fourth diffusion regions in the substrate, wherein the first, second, and third control gate structures are laterally between the third and fourth diffusion regions. | 2014-01-30 |
20140029355 | MEMORY DEVICE AND METHOD OF DETERMINING READ VOLTAGE OF MEMORY DEVICE - A method of operating a memory device comprises applying an initial read voltage to a selected wordline to perform a read operation on memory cells connected to the selected wordline, determining whether a read failure occurs with respect to one or more of the memory cells, upon determining that a read failure has occurred with respect to some of the memory cells, determining threshold voltage distribution information for distinct groups of the memory cells, and determining a new read voltage to be applied to the selected wordline based on the threshold voltage distribution information. | 2014-01-30 |
20140029356 | TEMPERATURE COMPENSATION OF CONDUCTIVE BRIDGE MEMORY ARRAYS - Methods for operating a semiconductor memory array including dynamically adjusting control line voltages (e.g., unselected word line or unselected bit line voltages) based on one or more array conditions associated with the semiconductor memory array are described. The one or more array conditions may include a temperature associated with the semiconductor memory array or a particular number of write cycles associated with the semiconductor memory array. In some embodiments, an intermediate voltage is generated based on the one or more array conditions and applied to the unselected word lines and the unselected bit lines of the semiconductor memory array. The one or more intermediate voltages may be generated such that a first voltage difference across unselected memory cells sharing a selected word line is different from a second voltage difference across other unselected memory cells sharing a selected bit line based on the one or more array conditions. | 2014-01-30 |
20140029357 | Non-Volatile Memory and Method with Peak Current Control - A non-volatile memory with multiple memory dice manages simultaneous operations so as to not exceed a system power capacity. A load signal bus is pulled up with a strength proportional to the system power capacity. Each die has a driver to pull down the bus by an amount corresponding to its degree of power need as estimated by a state machine of the die. The bus therefore provides a load signal that serves as arbitration between the system power capacity and the cumulative loads of the individual dice. The load signal is therefore at a high state when the system power capacity is not exceeded; otherwise it is at a low state. When a die wishes to perform an operation and requests a certain amount of power, it drives the bus accordingly and its state machine either proceeds with the operation or not, depending on the load signal. | 2014-01-30 |
20140029358 | MEMORY DEVICE AND METHOD FOR WRITING THEREFOR - A method for writing a memory cell in a specific write cycle is provided. The method includes the following steps: providing a first signal having a first transition edge in the specific write cycle; providing a second signal having a second transition edge in the specific write cycle, wherein the second transition edge lags behind the first transition edge; providing a first voltage level to the memory cell; and lowering the first voltage level to a second voltage level in the specific write cycle for writing the memory cell in response to the second transition edge. A memory device is also provided. | 2014-01-30 |
20140029359 | SENSE AMPLIFIER CIRCUIT AND MEMORY DEVICE INCLUDING THE SAME - A sense amplifier circuit includes a first pull-up transistor configured to pull-up drive a data bar line in response to a voltage of a data line, a first pull-down transistor configured to pull-down drive the data bar line in response to the voltage of the data line, and to receive the voltage of the data line through a back gate of the first pull-down transistor, a second pull-up transistor configured to pull-up drive the data line in response to a voltage of the data bar line, and a second pull-down transistor configured to pull-down drive the data line in response to the voltage of the data bar line, and to receive the voltage of the data bar line through a back gate of the second pull-down transistor. | 2014-01-30 |
20140029360 | TECHNIQUES FOR PROVIDING A SEMICONDUCTOR MEMORY DEVICE - Techniques for providing a semiconductor memory device are disclosed. In one particular exemplary embodiment, the techniques may be realized as a semiconductor memory device including a plurality of memory cells arranged in an array of rows and columns. Each memory cell including a first region, a second region, and a body region capacitively coupled to at least one word line and disposed between the first region and the second region. Each memory cell also including a third region, wherein the third region may be doped differently than the first region, the second region, and the body region. | 2014-01-30 |
20140029361 | BUFFER, METHOD FOR CONTROLLING BUFFER, SYNCHRONIZATION CONTROL DEVICE, SYNCHRONIZATION CONTROL METHOD, IMAGE PROCESSING APPARATUS, AND IMAGE PROCESSING METHOD - In a storage device including a plurality of storage regions, in order to synchronize input/output control of data into/from the storage region, a writing sequence or a reading sequence of the data into or from the storage region is stored, one of the storage regions to be accessed is selected in accordance with the stored sequence, and the synchronization control of input/output processing into/from an intermediate buffer is carried out, which allows an intermediate buffer control mechanism to be applied to various intermediate buffers. | 2014-01-30 |
20140029362 | MECHANISMS FOR BULIT-IN SELF TEST AND REPAIR FOR MEMORY DEVICES - This description relates to a system for storing repair data of a random access memory (RAM) array in a one-time programming memory (OTPM). The system includes the RAM array, wherein the RAM array includes a main memory, redundant rows and columns, and a first repair register memory. The system further includes a built-in self-test-and-repair (BISTR) module having a second repair register memory, wherein the BISTR module is used to test and repair the RAM array. The system further includes the one-time programming memory (OTPM) for storing repair data from more than one test and repair stages for the RAM array, wherein the repair data from different test and repair stages are stored in a same data segment. | 2014-01-30 |
20140029363 | FAIL ADDRESS DETECTOR,SEMICONDUCTOR MEMORY DEVICE INCLUDING THE SAME AND METHOD OF DETECTING FAIL ADDRESS - A fail address detector includes cam latch groups configured to store fail addresses and a comparing section connected to the cam latch groups in common and configured to detect whether or not a fail address corresponding to a comparison address exists among the fail addresses received from the cam latch groups. The cam latch groups share the comparing section in time division. | 2014-01-30 |
20140029364 | BIT ERROR TESTING AND TRAINING IN DOUBLE DATA RATE (DDR) MEMORY SYSTEM - DDR PHY interface bit error testing and training is provided for Double Data Rate memory systems. An integrated circuit comprises a bit error test (BERT) controller that provides a bit pattern; and a physical interface having a plurality of byte lanes. A first byte lane is connected by a loopback path to a second byte lane and the BERT controller writes the bit pattern that is obtained using the loopback path to evaluate the physical interface. The evaluation comprises (i) a verification that the bit pattern was properly written and read; (ii) a gate training process to position an internal gate signal; (iii) a read leveling training process to position both edges of a strobe signal; and/or (iv) a write bit de-skew training process to align a plurality of bits within a given byte lane. | 2014-01-30 |
20140029365 | PRECHARGE OPERATIONS AND CIRCUITRY THERE FOR - Examples described include precharge operations and circuitry for performing precharge operations. Digit lines may be driven to ground during a portion of example precharge operations. By driving the digit lines to ground, charge accumulating in bodies of vertical access devices may be discharged to the digit lines in some examples. To drive the digit lines to ground, a dynamic reference may be used where the reference is ground during one portion of the precharge operation and another value, which may be between two supply voltages (e.g. V | 2014-01-30 |
20140029366 | MEMORY DEVICE WITH SEPARATELY CONTROLLED SENSE AMPLIFIERS - A memory device includes a memory array comprising memory cells, sense amplifiers configured to sense data stored in the memory cells of the memory array, and control circuitry configured to generate a plurality of separate sense amplifier control signals for application to respective control inputs of respective ones of the sense amplifiers. For example, the memory device may comprise a row of dummy memory cells each coupled to a dummy wordline. In such an arrangement, the control circuitry may comprise a plurality of logic gates coupled to respective ones of the dummy memory cells, with each such logic gate configured to generate a corresponding one of the separate sense amplifier control signals for a corresponding one of the sense amplifiers as a function of a data transition at a bitline of the corresponding dummy memory cell. The separate sense amplifier control signals may comprise respective sense amplifier enable signals. | 2014-01-30 |
20140029367 | REFRESH ADDRESS GENERATOR, VOLATILE MEMORY DEVICE INCLUDING THE SAME AND METHOD OF REFRESHING THE VOLATILE MEMORY DEVICE - A refresh address generator includes a refresh sequence buffer and a refresh address generating unit. The refresh sequence buffer stores a sequence of memory groups, each memory group including a plurality of memory cell rows. The refresh address generating unit generates a plurality of refresh row addresses according to the sequence of memory groups stored in the refresh sequence buffer, in response to a refresh signal. | 2014-01-30 |
20140029368 | METHOD AND APPARATUS FOR INCREASING YIELD - Aspects of the disclosure provide an integrated circuit (IC) that is configured to have an increased yield. The IC includes a memory element configured to store a specific value determined based on a characteristic of the IC, and a controller configured to control an input regulator based on the specific value of the IC. The input regulator is operative to provide a regulated input to the IC during operation, such that the IC performance satisfies performance requirement. | 2014-01-30 |
20140029369 | MEMORY DEVICE, CONTROLLER, AND WRITE CONTROL METHOD - According to one embodiment, a storage device includes a buffer memory, a write controller, a nonvolatile memory, and bank writing modules. Data buffer areas are set in the buffer memory. The write controller sequentially writes data transmitted from a host to the data buffer areas. Banks are set in the nonvolatile memory. The write controller writes data transmitted from the host to a data buffer area in the data buffer areas from which first data written to the data buffer area is read when one of the bank writing modules reads the first data. Each bank writing module reads second data from one of the data buffer areas independently of data write processing statuses of another bank writing module, and writes the second data to a corresponding bank. | 2014-01-30 |
20140029370 | SEMICONDUCTOR MEMORY DEVICE, METHOD OF CONTROLLING READ PREAMBLE SIGNAL THEREOF, AND DATA TRANSMISSION METHOD - A system, includes a controller including a plurality of first external terminals configured to supply a command, a clock signal and an address, and communicate a data, and communicate a strobe signal related to the data, and a semiconductor memory device including a plurality of second external terminals corresponding to the plurality of first external terminals, one of the plurality of first external terminals and one of the plurality of second external terminals transferring an information specifying a length of a preamble of the strobe signal before the semiconductor memory device communicates the data, | 2014-01-30 |
20140029371 | Foam Production System and Method - A foam production system for producing a foam suitable for combining with a concrete mix comprises an air actuator for providing pressurized air to an aerator assembly and a water actuator arranged to provide pressurized water. A foaming agent is added to the water in a mixing chamber. The mixture of water and foaming agent is pumped out of the mixing chamber to the aerator, which is arranged to mix pressurized air into the mixture of a water and foaming agent to produce a foam output that is suitable for being combined with concrete mix to produce foamed concrete. | 2014-01-30 |
20140029372 | Auto Stucco Trowel - An apparatus for mixing and delivering a liquefied masonry mix such as grout, mortar, stucco, and the like is presented. The apparatus comprises a frame element, a hopper element, and a dispensing element. A bag of masonry mix may be loaded into the hopper element, mixed with water, and dispensed as a liquid mix through a hose with an attachable dispensing tool such as a trowel to a point of application such as a wall surface. | 2014-01-30 |
20140029373 | Bowl Assembly - The present invention relates generally to a bowl assembly and in particular, a mixing bowl assembly. | 2014-01-30 |
20140029374 | CHEMICAL PRECURSOR BUBBLER - One or more techniques and/or systems are disclosed for saturating a gas with a liquid-borne compound. A bubbler container may be configured to contain a carrier liquid, which comprises a desired compound. The container may comprise at least one channeling plane, disposed between the top and bottom of the container, which may be configured to allow gas bubbles to travel through a circuitous, channeling route. The gas can be introduced to the container at a bottom portion of the container, into the carrier liquid comprising the compound. Carrier gas bubbles formed in the liquid may be forced to travel the channeling route to a top portion of the container, where gas saturated with the compound may be collected. | 2014-01-30 |
20140029375 | FEED DELIVERY DEVICE - The invention relates to a feed delivery device with at least two feed containers and a device for delivering, mixing and distributing feed. According to the invention the mixing device and the distributing device are formed separately from each other and are movable relative to each other for assuming a transfer position in a transfer station, where the mixing device has a movement | 2014-01-30 |
20140029376 | METHOD FOR ESTIMATING THE WATER SPEED OF AN ACOUSTIC NODE - A method and apparatus are provided for estimating the water speed of a first acoustic node D belonging to a network of acoustic nodes, at least some of the acoustic nodes being arranged along towed acoustic linear antennas (S). The method includes steps of: a) defining a N-dimensional base, the center of which is the first acoustic node and comprising a single axis, when N=1, or N non-collinear axes, when N=2 or N=3, each axis being associated with a base vector extending from the first acoustic node to another acoustic node; and b) estimating an amplitude of the water speed, as a function of: for each given other acoustic node defining the base vector: an acoustic propagation duration of an acoustic signal transmitted from the first acoustic node to the given other acoustic node, and an acoustic propagation duration of an acoustic signal transmitted from the given other acoustic nodes to the first acoustic node; and a value c of the underwater acoustic sound velocity. | 2014-01-30 |
20140029377 | STREAMER FOR SEISMIC PROSPECTION COMPRISING TILT COMPENSATION OF DIRECTIONAL SENSORS - A streamer for seismic prospection comprising directional sensors ( | 2014-01-30 |
20140029378 | RECONSTRUCTING SEISMIC WAVEFIELDS - A technique includes receiving seismic data acquired in a seismic survey in the vicinity of a reflecting interface. The survey has an associated undersampled direction. The technique includes providing second data indicative of discrete samples of incident and reflected components of a continuous seismic wavefield along the undersampled direction and relating the discrete samples to a linear combination of the continuous incident and reflected seismic wavefields using at least one linear filter. Based on the relationship, an unaliased representation of the linear combination of the continuous incident and reflected seismic wavefields is constructed. | 2014-01-30 |
20140029379 | METHOD FOR STEERING A TOWED ACOUSTIC LINEAR ANTENNA - A method and apparatus are provided for steering a first acoustic linear antenna belonging to a plurality of acoustic linear antennas towed by a vessel. A plurality of navigation control devices are arranged along the plurality of linear antennas in order to act at least laterally on the position of the linear antennas. At least one of the navigation control devices arranged along the first acoustic linear antenna performs steps of: obtaining a local measurement of a feather angle or of a parameter linked to the feather angle, the local measurement being associated with the at least one of the navigation control devices arranged along the first acoustic linear antenna; computing a lateral force, as a function of the obtained local measurement; and applying the computed lateral force. | 2014-01-30 |
20140029380 | ACTIVE STEERING FOR MARINE SEISMIC SOURCES - A seismic survey system having a source array ( | 2014-01-30 |