05th week of 2009 patent applcation highlights part 60 |
Patent application number | Title | Published |
20090031024 | Method and System for Monitoring Server Events in a Node Configuration by Using Direct Communication Between Servers - In a method and system for monitoring events occurring at respective servers of a configuration of nodes, a first server located at a first node receives information from a messaging system pertaining to events at servers located at other nodes. The messaging system usefully comprises a highly available (HA) bulletin board or the like. When the first server receives a start event notification pertaining to a second server located at a second node, a direct communication path is established between the first and second servers. The first server identifies events in the second server that affect or are of interest to services of the first server. The first server then registers with the second server, to receive notification through the direct communication path when respective identified events occur. | 2009-01-29 |
20090031025 | Load optimization - Methods, computer code, and means are described that can control load in a network. In some applications, the monetary cost of operating the network can be reduced. Utilization of links in the network can be monitored. A degree of suboptimality with respect to some criteria can be assessed. In some instances, the criteria could be based at least partly one or more monetary billing structures of some subset of two or more links. A subset of the forwarding decisions of one or more forwarding nodes in the network can be adjusted automatically, based at least partly on the assessing. The adjustment can attempt to reduce the degree of suboptimality. | 2009-01-29 |
20090031026 | System and method for cross-authoritative configuration management - A system and method for cross-authoritative, user-based network configuration management is provided. Users log-in to a network using any device coupled to the network, and an identity manager may provide the user with a custom computing environment by verifying the user's identity and identifying content, assignments, and other configuration information associated with the user. For instance, the identity manager may retrieve a unique identifier assigned to the user, query one or more authoritative source domains based on the unique identifier, and deliver a computing environment assigned to the user. By seamlessly integrating multiple authoritative sources, administrators can make assignments to users across multiple authoritative source domains, and queries to the sources will always be up-to-date without having to perform synchronization processes. | 2009-01-29 |
20090031027 | Relationship-Centric Portals for Communication Sessions - Relationship-centric resources are provided to users during a communication session. After establishing a communication session between a first communication device and a second communication device, content that meets a content descriptor is retrieved. This content descriptor describes a nature of a relationship between users of the first and second communication devices. The retrieved content, which meets the content descriptor, is then simultaneously displaying on both the first communication device and the second communication device. | 2009-01-29 |
20090031028 | Secure tunnel domain name management - Apparatus, systems, and methods may operate to establish a virtual private network (VPN) connection between a server in a private network and a client in a public network. Additional activities include intercepting a socket call from the client requesting resolution of a network address associated with a domain name in the private network, searching a local linked list for the network address, returning the network address to the client if the network address is found in the local linked list, and, if the network address is not found in the local linked list, sending a request to resolve the network address to a domain name system (DNS) server in the private network. Additional apparatus, systems, and methods are disclosed. | 2009-01-29 |
20090031029 | SYSTEM AND METHOD FOR REESTABLISHING, WITH A CLIENT DEVICE, A SIGNALING SESSION ASSOCIATED WITH A CALL IN PROGRESS - The subject matter described herein includes methods, systems, and computer readable media for re-establishing, with a client device, a signaling session associated with a call in progress. One method for reestablishing, with a client device, a signaling session associated with a call in progress includes monitoring an Internet protocol (IP) address of media packets received from the client device during a call in progress having an associated signaling session and detecting a change in the IP address for the device from the media packets, and wherein the signaling session is terminated. The method further includes, in response to detecting a change in the IP address for the device from the media packets, sending a notification message to the client device. The method further includes receiving a registration message from the client device to re-establish the signaling session. | 2009-01-29 |
20090031030 | PEER-BASED NETWORKING ENVIRONMENT - A solution for providing a networking environment is provided, in which data for a plurality of members is managed. Each member includes profile data and may include one or more peers. A peer can comprise another member that is a friend of the member. The member can provide invitee credentials, such as an identifier (e.g., user name) and password, which another member can use to view some or all of the profile data of the member. Additionally, peers of the other member can also view some or all of the profile data of the member and both the other member and his/her peers can view some or all of the profile data of the peer(s) of the member. In this manner, a networking environment is provided that enables an individual and his/her peers to learn about another individual in the context of the other individual's peers. | 2009-01-29 |
20090031031 | METHOD AND SYSTEM FOR MAINTAINING A CONFIGURATION STATE - A system for configuring configurable products includes a stateless configuration engine. A user and a server are coupled to a network for transmitting and receiving information. The user includes a web browser, memory and a display. The user receives web pages from the server and enters information into the fields on the page. The user sends the web page and the entered information to the server. The server decodes the information on the web page and sends a next page to the user including hidden form fields that include the decoded information. The information is stored in the source code of the page displayed by the web browser located at the user. | 2009-01-29 |
20090031032 | REGISTER CLUSTERING IN A SIP-BASED NETWORK - In one embodiment, a method can include: receiving a request for service in a first edge proxy; applying a hash function to a source address of an endpoint; and forwarding the request to a second edge proxy in response to a first result of the hash function, or servicing the request in the first edge proxy in response to a second result of the hash function. | 2009-01-29 |
20090031033 | System and Method for User to Verify a Network Resource Address is Trusted - A system, method and computer program product for a user to verify that a network resource address is trusted. At least one entity registration is stored at a server. Each entity registration comprises an identity of an entity and entity addressing information associated with the identity of the entity. The existence of at least one entity whose identity is included in the at least one entity registration is confirmed. A query comprising a target addressing information is received from a client. If the target addressing information matches the entity addressing information, the identity of the entity associated with the entity addressing information is determined and a result comprising the identity of the entity associated with the entity addressing information matching the target addressing information is transmitted to the client. If no entity addressing information matches the target addressing information, an indication of such is transmitted to the client. | 2009-01-29 |
20090031034 | Methods and systems for proofing ldentities using a certificate authority - A digital certificate is provided to a customer having an electronic account linked to the customer's physical address. Using the digital certificate, the customer performs electronic transactions with a third party. A proofing workstation receives a request from a third party to validate the digital certificate. The proofing workstation communicates with a proofing server that maintains a list of valid certificates and a list of revoked certificates. The proofing server sends a response to the proofing workstation, where it is received by the third party. | 2009-01-29 |
20090031035 | WIRELESS ARCHITECTURE FOR TRADITIONAL WIRE BASED PROTOCOL - Aspects describe service discovery of wireless MDDI client-capable devices though interaction with an underlying bearer protocol. Service discovery can be performed when the underlying layer supports multicasting, when the underlying layer is wiMedia UWB MAC and/or UDP/IP. Service discovery can be initiated by a w-MDDI sender and/or a w-MDDI receiver. An optional mutual security association procedure can be conducted if both devices support security and security is necessary. | 2009-01-29 |
20090031036 | ENVIRONMENT INFORMATION PROVIDING METHOD, VIDEO APPARATUS AND VIDEO SYSTEM USING THE SAME - An environment information providing method, a video apparatus and a video system using the same are provided. The environment information is generated and inserted in between packets of a video stream. Accordingly, a user can watch the video in an environment similar to the reproduced video. | 2009-01-29 |
20090031037 | METHOD OF STREAMING MEDIA AND INSERTING ADDITIONAL CONTENT THEREIN USING BUFFERING - A method and system of streaming media content is disclosed. The method and system includes a process step and structures for inputting the live feed into a first audio card having an output. Another process step and structures are provided for inputting the output of the first audio card into a FIFO buffer having an output. Another process step and structures are provided for inputting the output of the FIFO buffer into a virtual audio card having an output. Another process step and structures are provided for inserting additional content into a second audio card by replacing content to be substituted where the additional content and the content to be replaced do not have to be of the same duration. Another process step and structures are provided for mixing the output from the first audio card and the additional content by the second audio card to provide a mixed output. Another process step and structures are provided for inputting the mixed output of the second audio card into an encoder having an output. Another process step and structures are provided for streaming the output of the encoder over a network. | 2009-01-29 |
20090031038 | ADAPTIVE VARIABLE FIDELITY MEDIA DISTRIBUTION SYSTEM AND METHOD - An adaptive variable fidelity media provision system and method are provided herein. | 2009-01-29 |
20090031039 | IMAGE FORMING METHOD, IMAGE FORMING APPARATUS, AND HOST - An image forming method, an image forming apparatus, and a host include determining if a disorder is generated in a network set to perform an operation among networks between an image forming apparatus including at least two network interfaces and a host, and if a disorder is generated in the set network, networking the image forming apparatus with the host via a non-disordered network interface. | 2009-01-29 |
20090031040 | Distributed denial-of-service attack mitigation by selective black-holing in IP networks - In an IP network during a DDoS attack on a website or other internet entity having an IP address, selective black-holing of attack traffic is performed such that some of the traffic destined for the IP address under attack continues to go to the IP address under attack while other traffic, destined for the same IP address is, rerouted via BGP sessions to a black-hole router. Such a selective black-holing scheme can be used to allow some traffic to continue in route to the IP address under attack, while other traffic is diverted. | 2009-01-29 |
20090031041 | Forwarding system with multiple logical sub-system functionality - Generation of a mapping for use by a data forwarding entity having communication interfaces and instantiating multiple logical forwarding sub-systems associated with respective mappings including a first mapping and a second mapping. The first mapping specifies a next hop interface for data elements received at the interfaces, at least one next hop interface belonging to a set of logical interfaces. The second mapping specifies a second next hop interface for certain data elements for which the next hop interface specified by the first mapping belongs to the set of logical interfaces, at least one second next hop interface belonging to the plurality of communication interfaces. A consolidated mapping is created by replacing each portion of the first mapping that specifies a next hop interface belonging to the set of logical interfaces by a corresponding portion of the second mapping that specifies a second next hop interface. Efficiency arises when the same data is processed by more than one logical forwarding sub-system in the same physical forwarding system. | 2009-01-29 |
20090031042 | SPREAD IDENTITY COMMUNICATIONS ARCHITECTURE - Real routable external addresses may be pooled rather than assigned to nodes and may be dynamically bound to connections by a proxy or gateway device in ways that spread apparent identity of individual nodes across multiple of the external addresses. In general, these spread identity techniques may be employed at one end or the other of a connection, as well as at both ends. In a typical double-ended configuration, the architecture and associated techniques provide “double-blindfolding,” wherein true identities (addresses) of communicating peers are always hidden from each other. In some double-ended configurations, dynamic binding may be employed at a fine level of granularity, for instance allowing individual packets associated with given connection to bear different apparent source addresses and/or different apparent destination addresses. In some single-ended configurations, a spread identity proxy is interposed between an information server and a plurality of requesters. The proxy redirects individual inbound connection requests for information from the information server to distinct addresses of a pool and establishes corresponding network address translations thereby dynamically spreading identity of the information server across multiple distinct addresses of the pool. | 2009-01-29 |
20090031043 | Method, Communication System, and Communication Terminal for the Transmission of Data - Disclosed is a method, a communication system, and a communication device for transmitting data to a first subscriber, within the framework of a connection signaling from a first primary service communication device of the first subscriber to a second primary service communication device, a primary address information message associated with the first primary service communication device and a secondary address information message associated with a first secondary service communication device of the first subscriber is transmitted to the second primary service communication device. The transmitted address information messages are identified and stored via the primary service communication device. For the transmission of data to be transmitted to the first subscriber, the stored secondary address information message is transferred from the second primary service communication device to a second secondary service communication device, and is transmitted based on the transferred secondary address information message during transmission to the first secondary service communication device. | 2009-01-29 |
20090031044 | High-Speed MAC Address Search Engine - Disclosed is an apparatus and method for storing and searching computer node addresses in a computer network system. In one embodiment, the apparatus comprises a frame forwarding device such as a switch. The switch includes two MAC address tables including a primary MAC address table and secondary MAC address table both for storing and searching MAC addresses. The primary table stores records that contain compressed values of MAC addresses. The records are contained in storage locations that are referenced using the compressed value of the MAC address as a search index. In order to account for searching collisions that may result from different MAC addresses compressing to the same value, each record in the primary address table is linked to a chain of records in the secondary table. The records in the secondary table store the full value of the MAC address. Each chain of records in the secondary address table contains MAC addresses the present invention. | 2009-01-29 |
20090031045 | INFORMATION RELAY DEVICE, INFORMATION RELAY METHOD, INFORMATION RELAY PROGRAM AND INFORMATION RECORDING MEDIUM - A network connection control device is provided that is capable of quickly and accurately executing the process for connection when connecting together networks that both comply to the IEEE 1394 standard. After networks that both comply to the IEEE 1394 standard are connected together and a bus reset occurs, as the contents of the route maps M | 2009-01-29 |
20090031046 | Hardware control interface for IEEE standard 802.11 - A standardized 802.11 hardware control interface may be provided such that a driver may communicate with any one or more of a variety of network adapters. | 2009-01-29 |
20090031047 | COMPUTER SYSTEM AND MONITOR WITH PERIPHERAL INTERFACES - The present invention relates to a computer system and a monitor with peripheral interfaces. The computer system includes a monitor, a host, and a transmission cable. The monitor includes a plurality of peripheral interfaces and an integrated interface. The peripheral interfaces are utilized to connect corresponding peripheral devices, and the peripheral interfaces are connected with the integrated interface. The transmission cable is configured for connecting the integrated interface and the host, and transmitting peripheral signals from the peripheral devices to the host. | 2009-01-29 |
20090031048 | Configuring Multi-Bit Slave Addressing on a Serial Bus Using a Single External Connection - Unique addresses for a plurality of devices may be programmed through a single external connection (pin) on each device by using a one of a plurality of different analog voltage or current values on the single external pin in combination with a serial clock of a serial data bus for each device requiring a unique binary address. The unique binary address is stored in the device after detection of certain number of clocks on the serial data bus. Once the unique binary address has been stored in the device, the single external connection may be used for another purpose such as a multifunction external connection. This unique binary address may be retained by the device until a power-on-reset (POR) or general reset condition occurs. Address detection and address load commands on the serial bus may also perform the same address definition and storage functions. | 2009-01-29 |
20090031049 | RESOURCE SHARING APPARATUS - A method for controlling a resource sharing apparatus coupling least one input device to a first host is disclosed. A first input signal is acquired from the input device, and whether the first input signal comprises standby indication of a switching command is determined. The input device is disconnected from the first host when the first input signal comprises the standby indication, and the input device is emulated to the first host. | 2009-01-29 |
20090031050 | System for Dual Use of an I/O Circuit - A system provides dual use of a general purpose input/output (I/O) line. In an embodiment, the system comprises a controlling circuit having a dual purpose I/O line that is selectively operable in a serial transmit mode or an I/O mode. A first circuit that receives a serial data stream when the controlling circuit operates in the serial transmit mode is coupled to the I/O line. A second circuit that generates and transmits a signal when the controlling circuit operates in the I/O mode is also coupled to the I/O line. Finally, a third circuit is disposed between the second circuit and the I/O line. In an embodiment, when the controlling circuit operates in the serial transmit mode, the third circuit maintains the second circuit in an idle state, and when the controlling circuit operates in the I/O mode, the third circuit permits the second circuit to transmit the signal to the controlling circuit. | 2009-01-29 |
20090031051 | CENTRALIZED SERVER RACK MANAGEMENT USING USB - A multi-server computing system includes a plurality of server modules mounted in an enclosure; each server has a universal serial bus (USB) interface. An enclosure onboard administration (OA) module is also mounted in the enclosure and has an addressable communication interface for connection to a remote management system and a USB interface connected to each of the plurality of servers. The USB interface of the enclosure OA operates as a master and the USB interface of each of the plurality of servers acts as a slave to the enclosure OA, such that each of the server modules can be managed by the remote management system using a single communication address. | 2009-01-29 |
20090031052 | PRINT DEVICE DIAGNOSIS METHOD AND SYSTEM - A system and method include a printing device having an embedded server that generates an electronic document. The content of the electronic document may he data representative of operational elements of the device. An application server may contain program instructions that request the electronic document from the printing device. A firewall may separate the printing device and the application server from an external hosted server. The application server may include program instructions to periodically poll the hosted server to determine whether the hosted server has issued an electronic document request. If the hosted server has issued an electronic document request, the application server may return content of the electronic document from the printing device to the hosted server. | 2009-01-29 |
20090031053 | SEMICONDUCTOR INTEGRATED CIRCUIT AND SEMICONDUCTOR DEVICE WITH THE SAME - An interconnect configuration technology of making an access from an IP mounted on a semiconductor chip to an IP mounted on another semiconductor chip by transmitting and receiving a packet transferred through an interconnect built in a semiconductor chip among the chips using the 3D coupling technology. The device according to the technology has an initiator for transmitting an access request, a target for receiving the access request and transmitting an access response, a router for relaying the access request and the access response, and a 3D coupling circuit (three-dimensional transceiver) for performing communication with the outside, wherein the 3D coupling circuit is disposed adjacent to the router. | 2009-01-29 |
20090031054 | DATA PROCESSING APPARATUS AND DATA TRANSFER METHOD - A data processing apparatus which can copy necessary data without imposing a burden on a CPU when broadcasting specific data is realized. A data processing apparatus includes a reception FIFO memory which temporarily stores received data sequentially; a buffer management unit which reads out the received data stored in the reception FIFO memory, discriminates whether or not a plurality of the same data are required for transferring the received data, and searches a plurality of buffer memory areas that are different from each other when the plurality of the same data are required; and a DMA (Direct Memory Access) control circuit which writes the received data read from the reception FIFO memory into each of buffer memory areas designated by the buffer management unit. | 2009-01-29 |
20090031055 | Chaining Direct Memory Access Data Transfer Operations for Compute Nodes in a Parallel Computer - Methods, systems, and products are disclosed for chaining DMA data transfer operations for compute nodes in a parallel computer that include: receiving, by an origin DMA engine on an origin node in an origin injection FIFO buffer for the origin DMA engine, a RGET data descriptor specifying a DMA transfer operation data descriptor on the origin node and a second RGET data descriptor on the origin node, the second RGET data descriptor specifying a target RGET data descriptor on the target node, the target RGET data descriptor specifying an additional DMA transfer operation data descriptor on the origin node; creating, by the origin DMA engine, an RGET packet in dependence upon the RGET data descriptor, the RGET packet containing the DMA transfer operation data descriptor and the second RGET data descriptor; and transferring, by the origin DMA engine to a target DMA engine on the target node, the RGET packet. | 2009-01-29 |
20090031056 | USB integrated bidirectional digital isolator - An interface between USB devices employs isolation techniques to provide electrical isolation of a USB signal for transmission of the USB signal between the devices. Unidirectional isolator channels are utilized to transmit the USB signals, and a selection of an isolator channel operating in an intended direction is performed by either direction control logic or a USB hub function. Logic may be employed to detect a device attempting to initiate a USB signal. The logic operates to enable a transmitter on a receiving side and isolate the USB signal through an isolator channel operating in a transmission direction. | 2009-01-29 |
20090031057 | METHODS, SYSTEMS AND COMPUTER PRODUCTS FOR USER-MANAGED MULTI-PATH PERFORMANCE IN BALANCED OR UNBALANCED FABRIC CONFIGURATIONS - Methods, system and computer products for user-managed multi-path performance in balanced or unbalanced fabric configurations. Exemplary embodiments include a path priority selection method, including selecting a first I/O data path to be a highest priority path in a storage area network system, selecting a second I/O data path to be a low priority path, selecting an I/O threshold value, the I/O threshold value indicating that I/O data load is excessive, directing the load balance of I/O traffic to the first I/O data path, thereby placing the second I/O data path in a standby state, monitoring the first I/O data path, determining if the first I/O data path has reached the threshold value and performing a controlled failover of the first I/O data path to the second I/O data path when an I/O data load on the first data path has reached the threshold value. | 2009-01-29 |
20090031058 | Methods and Apparatuses for Flushing Write-Combined Data From A Buffer - Methods and apparatuses for flushing write-combined data from a buffer within a memory to an input/output (I/O) device. | 2009-01-29 |
20090031059 | Method, System, and Computer Program Product for Dynamically Selecting Software Buffers for Aggregation According to Current System Characteristics - A method, system, and computer program product in a data processing system are disclosed for dynamically selecting software butters for aggregation in order to optimize system performance. Data to be transferred to a device is received. The data is stored in a chain of software buffers. Current characteristics of the system are determined. Software buffers to be combined are then dynamically selected. This selection is made according to the characteristics of the system in order to maximize performance of the system. | 2009-01-29 |
20090031060 | BUS CONVERTER, SEMICONDUCTOR DEVICE, AND NOISE REDUCTION METHOD OF BUS CONVERTER AND SEMICONDUCTOR DEVICE - A bus converter is disclosed that converts a signal of a synchronous bus into a signal of an asynchronous bus. The bus converter includes a control signal generation unit that generates n control signals synchronized at different timings of a predetermined synchronization signal, where n is an integer of two or more; and an output unit that outputs the signal of the synchronous bus divided into n signal groups based on a control using the n control signals. | 2009-01-29 |
20090031061 | HOST APPARATUS CAPABLE OF CONNECTING WITH AT LEAST ONE DEVICE USING WUSB AND METHOD OF CONNECTING HOST APPARATUS TO DEVICE - A host apparatus capable of connecting with one or more devices using a wireless universal serial bus (WUSB) and a method of connecting the host apparatus to one or more devices. The method includes receiving a connection request signal for connecting to the host apparatus from one of the devices; and selectively responding to the connection request signal of the device according to preset device information. Accordingly, the host can be selectively connected with the device according to the preset connection option of the device. Hence the device can be connected with the host apparatus only when a user wants, and thus user convenience increases in using and managing the device through the host apparatus in the USB environment. | 2009-01-29 |
20090031062 | MODULARIZED MOTHERBOARD - A modularized motherboard is provided. The modularized motherboard includes a first circuit board, a second circuit board and a connecting device. The first circuit board includes a north bridge chip, a central processing unit (CPU) slot and a first connecting port. The CPU slot is coupled to the north bridge chip and is used for installing a CPU. The second circuit board is independent of the first circuit board. The second circuit board includes a second connecting port and a south bridge chip. The south bridge chip is coupled to the north bridge chip via the second connecting port the first connecting port. The connecting device is coupled between the first connecting port and the second connecting port. | 2009-01-29 |
20090031063 | Data Processing System And Method - Embodiments of the present invention relate a data processing method comprising executing a first application on a first processor of a multiprocessor system and implementing, on the first processor, a first protocol stack supporting a first communication channel, bearing first communication data, associated with the first application; and executing a second application on a second processor of the multiprocessor system and implementing, on the second processor, a second protocol stack supporting a second communication channel, bearing second communication data, associated with the second application. | 2009-01-29 |
20090031064 | Information processing apparatus including transfer device for transferring requests - According to an aspect of an embodiment, an apparatus has a pair of first system boards, each of the first system boards including a processor and being adapted for sending duplicate requests, in parallel, respectively, a second system board including a processor and being adapted for sending requests, a first transfer device for transferring requests, having a first arbiter for selecting and outputting one of the duplicate requests sent from each of the first system boards, and a second arbiter for selecting and outputting one of the requests sent from the second system board and a second transfer device for transferring requests, having a third arbiter for selecting one of the duplicate requests sent from each of the first system boards and outputting the selected request in synchronization with the selected request outputted by the first arbiter, the second transfer device having a forth arbiter. | 2009-01-29 |
20090031065 | Repeater for a bidirectional serial bus - A digital bit-level repeater for joining two wired-AND buses such as the I | 2009-01-29 |
20090031066 | CAPACITY PLANNING BY TRANSACTION TYPE - Capacity planning is performed based on expected transaction load and the resource utilization for each expected transaction. Resource usage is determined for one or more transactions or URLs based on transaction specific and non-transaction specific resource usage. Once the resource usage for each transaction is known, the expected resource usage may be determined for an expected quantity of each transaction. The actual resources needed to meet the expected resource usage are then determined. Resources may include hardware or software, such as a central processing unit, memory, hard disk bandwidth, network bandwidth, and other computing system components. The expected resource usage for a transaction may based on the usage directly related to the transaction and usage not directly related to the transaction but part of a process associated with the performed transactions. | 2009-01-29 |
20090031067 | Spider Web Interconnect Topology Utilizing Multiple Port Connection - A data communications apparatus includes a central device and a plurality of communication devices. The central device includes a plurality of central port pairs, in which each central port pair includes an input port and an output port. The plurality of communication devices is arranged in a spoke and ring configuration, in which each communication device is part of a communication spoke. Each communication spoke is in communication with a different central port pair. Each communication device is also a part of a communication ring, so that each communication device in a selected communication ring belongs to a different communication spoke. | 2009-01-29 |
20090031068 | SYSTEM BOARD WITH EDGE CONNECTOR - A system comprises a chassis and a system board contained within the chassis. The system board has an edge connector adapted to receive an add-in card in a configuration in which the system board and add-in card are substantially co-planar. | 2009-01-29 |
20090031069 | DATA COMMUNICATION SYSTEM, CRADLE APPARATUS, SERVER APPARATUS AND DATA COMMUNICATION METHOD - A data communication system includes a server apparatus and a cradle apparatus. The cradle apparatus includes a first communication section, a second communication section, a connection detection section, a notification control section, and a relay control section. The server apparatus includes a communication section, a data preparation section, and a communication control section. | 2009-01-29 |
20090031070 | Systems And Methods For Improving Performance Of A Routable Fabric - Systems and methods for improving performance of a rentable fabric are disclosed. In an exemplary embodiment a system may comprise a plurality of compute nodes, a routable fabric, and a plurality of chipsets connected by the routable fabric to the plurality of compute nodes. The chipsets have range registers dynamically directing traffic from any device to any of the plurality of compute nodes over the routable fabric. | 2009-01-29 |
20090031071 | METHOD FOR ACQUIRING RELEVENT INFORMATION TO AN OBJECT USING AN INFORMATION ACCESS TAG - A method for retrieving relevant information about an object is disclosed. An information access tag is associated with the object. Relevant information or data about the object are store on a server. The information access tag comprises a link pointing to the address of the server. When a user uses a mobile electronic device to read the information access tag the link is decoded and the electronic device connects to the server via a network. The relevant information is downloaded and displayed on the electronic device for the user to interact with the information or data. | 2009-01-29 |
20090031072 | Hybrid nonvolatile RAM - A memory subsystem includes a volatile memory, a nonvolatile memory, and a controller including logic to interface the volatile memory to an external system. The volatile memory is addressable for reading and writing by the external system. The memory subsystem includes a power controller with logic to detect when power from the external system to at least one of the volatile and nonvolatile memories and to the controller fails. When external system power fails, backup power is provided to at least one of the volatile and nonvolatile memories and to the controller for long enough to enable the controller to back up data from the volatile memory to the nonvolatile memory. | 2009-01-29 |
20090031073 | MULTI-INTERFACE AND MULTI-BUS STRUCTURED SOLID-STATE STORAGE SUBSYSTEM - A solid-state storage subsystem, such as a non-volatile memory card or drive, includes multiple interfaces and a memory area storing information used by a data arbiter to prioritize data commands received through the interfaces. As one example, the information may store a priority ranking of multiple host systems that are connected to the solid-state storage subsystem, such that the data arbiter may process concurrently received data transfer commands serially according to their priority ranking. A host software component may be configured to store and modify the priority control information in solid-state storage subsystem's memory area. | 2009-01-29 |
20090031074 | Multi-level Cell Flash Memory and Method of Programming the Same - Provided is a flash memory having a multi-level cell (MLC) and a method of programming the same. The method includes identifying a set of first patterns from input data, determining whether there is a set of second patterns stored within the flash memory that is of a number substantially similar to the number of the first patterns, and programming the input data as a most significant bit (MSB) in a location of the flash memory where the identified set of second patterns is stored when it is determined that there is a set of second patterns stored within the flash memory that is of a number substantially similar to the number of first patterns. | 2009-01-29 |
20090031075 | Non-volatile memory device and a method of programming the same - Provided are a non-volatile memory device and a method of programming the same. The method includes: performing a program operation; performing a program verify read operation; and performing a pass/fail determine operation simultaneously with one of a verify recovery operation and a bit line setup operation, after the performing of the program verify read operation. | 2009-01-29 |
20090031076 | Method for Managing Flash Memory - A method for managing a flash memory, a method for leveling the wear of blocks in a flash memory, and a method for managing a file system for a flash memory are provided. The method for managing a flash memory includes: if changing of data of a data block recorded in a data area is requested, recording the data block having changed data in an alternative area and recording mapping information of the data block recorded in the alternative area in a mapping area; and if changing of data of the data block recorded in the alternative area is requested, recording a data block having changed data in the data area and deleting the mapping information recorded in the alternative area from the mapping area. | 2009-01-29 |
20090031077 | INTEGRATED CIRCUIT INCLUDING MULTIPLE MEMORY DEVICES - An integrated circuit includes a data bus and a first memory device coupled to the data bus. The first memory device is configured to provide a first signal in response to completing a power-up sequence of the first memory device. The integrated circuit includes a second memory device coupled to the data bus. The second memory device is configured to provide a second signal in response to completing a power-up sequence of the second memory device. The integrated circuit includes a controller configured to access the first memory device and the second memory device based on the first signal and the second signal. | 2009-01-29 |
20090031078 | Rank sparing system and method - A system, and a corresponding method, are used to implement rank sparing. The system includes a memory controller and one or more DIMM channels coupled to the memory controller, where each DIMM channel includes one or more DIMMS, and where each of the one or more DIMMs includes at least one rank of DRAM devices. The memory controller is loaded with programming to test the DIMMs to designate at least one specific rank of DRAM devices as a spare rank. | 2009-01-29 |
20090031079 | LOGGING LATENCY REDUCTION - A disk is divided into K angular regions. A log write request is replicated K times and K number of identical log writes are issued to the disk to be written to each of the angular regions of the log. Upon completion of the first write, the application requesting the log write is informed of its completion resulting in a reduction of rotational latency by a factor of K. | 2009-01-29 |
20090031080 | FLASH MEMORY DEVICE AND PROGRAM METHOD THEREOF - A flash memory device includes a memory cell array, a peri circuit unit, an I/O controller, and a controller. The memory cell array includes a plurality of memory cells respectively connected to a plurality of bit line pairs and a plurality word lines. The peri circuit unit is configured to program data into the memory cell array or read data stored in the memory cell array in response to a command input through a control bus. The I/O controller is configured to receive data for programming and supply the data to the peri circuit unit in response to a command provided through a data input/output (I/O) bus. The controller is configured to control the I/O controller to perform a voltage setup operation for a program while the data for program is received. | 2009-01-29 |
20090031081 | SYSTEM AND MODULE FOR MERGING ELECTRONIC AND PRINTED DATA - A system for merging electronic and printed information is provided. The system includes a computing device having a visual display. Additionally, the system includes a handheld electronic memory device containing at least one information file with information corresponding to printed information that is presented on a separate physical medium. The memory device also includes a processing file comprising stored computer-readable instructions. The system further includes an electrical connector that is attached to the handheld electronic memory device. The electrical connector connects to the computing device having the visual display so that the at least one information file and the processing file are conveyed via the electrical connector to the computing device when the electrical connector is connected to the computing device. | 2009-01-29 |
20090031082 | Accessing a Cache in a Data Processing Apparatus - A data processing apparatus is provided having processing logic for performing a sequence of operations, and a cache having a plurality of segments for storing data values for access by the processing logic. The processing logic is arranged, when access to a data value is required, to issue an access request specifying an address in memory associated with that data value, and the cache is responsive to the address to perform a lookup procedure during which it is determined whether the data value is stored in the cache. Indication logic is provided which, in response to an address portion of the address, provides for each of at least a subject of the segments an indication as to whether the data value is stored in that segment. The indication logic has guardian storage for storing guarding data, and hash logic for performing a hash operation on the address portion in order to reference the guarding data to determine each indication. Each indication indicates whether the data value is either definitely not stored in the associated segment or is potentially stored with the associated segment, and the cache is then operable to use the indications produced by the indication logic to affect the lookup procedure performed in respect of any segment whose associated indication indicates that the data value is definitely not stored in that segment. This technique has been found to provide a particularly power efficient mechanism for accessing the cache. | 2009-01-29 |
20090031083 | Storage control unit with memory cash protection via recorded log - A “Logging” method and apparatus is provided to protect control unit cached data not yet written to backing storage disk drives. This recording mechanism will copy “WRITE DATA” to a log at a target logically or physically external (to the storage controllers) location equally common to all members of the set of distributed storage control units managing a common storage pool. Upon the failure of one the members of the set of control units, the “Log” information is available to insure that pending “write” data is written to the proper location on the disk drives upon a recovery action. One of the surviving members of the set assumes control of the storage managed by the failing unit by utilizing the recorded information to insure that data not written to backing storage (disks) up to the point of failure is then written to the disk backing storage. The surviving member of the set recovering the failing control unit storage (disk set) ownership will thereby “flush” (WRITE) the Journaled WRITE DATA to the backing storage disk drives before allowing normal operations to proceed. | 2009-01-29 |
20090031084 | CACHE LINE REPLACEMENT TECHNIQUES ALLOWING CHOICE OF LFU OR MFU CACHE LINE REPLACEMENT - Methods and apparatus allowing a choice of Least Frequently Used (LFU) or Most Frequently Used (MFU) cache line replacement are disclosed. The methods and apparatus determine new state information for at least two given cache lines of a number of cache lines in a cache, the new state information based at least in part on prior state information for the at least two given cache lines. Additionally, when an access miss occurs in one of the at least two given lines, the methods and apparatus (1) select either LFU or MFU replacement criteria, and (2) replace one of the at least two given cache lines based on the new state information and the selected replacement criteria. Additionally, a cache for replacing MFU cache lines is disclosed. The cache additionally comprises MFU circuitry (1) adapted to produce new state information for the at least two given cache lines in response to an access to one of the at least two given cache lines, and (2) when a cache miss occurs in one of the at least two given cache lines, adapted to determine, based on the new state information, which of the at least two given cache lines is the most frequently used cache line. | 2009-01-29 |
20090031085 | Directory for Multi-Node Coherent Bus - A method for maintaining cache coherency for a multi-node system using a specialized bridge which allows for fewer forward progress dependencies. A look-up of a local node directory is performed if a request received at a multi-node bridge of the local node is a system request. If a directory entry indicates that data specified in the request has a local owner or local destination, the request is forwarded to the local node. If the local node determines that the request is a local request, a look-up of the local node directory is performed. If the directory entry indicates that data specified in the request has a local owner and local destination, the coherency of the data on the local node is resolved and a transfer of the request data is performed if required. Otherwise, the request is forwarded to all remote nodes in the multi-node system. | 2009-01-29 |
20090031086 | Directory For Multi-Node Coherent Bus - A method for maintaining cache coherency for a multi-node system using a specialized bridge which allows for fewer forward progress dependencies. A local node makes a determination whether a request is a local or system request. If the request is a local request, a look-up of a directory in the local node is performed. If an entry in the directory of the local node indicates that data in the request does not have a remote owner and that the request does not have a remote destination, the coherency of the data is resolved on the local node, and a transfer of the data specified in the request is performed if required and if the request is a local request. If the entry indicates that the data has a remote owner or that the request has a remote destination, the request is forwarded to all remote nodes in the multi-node system. | 2009-01-29 |
20090031087 | MASK USABLE FOR SNOOP REQUESTS - A system comprises a plurality of cache agents, a computing entity coupled to the cache agents, and a programmable mask accessible to the computing entity. The programmable mask is indicative of, for at least one memory address, those cache agents that can receive a snoop request associated with a memory address. Based on the mask, the computing entity transmits snoop requests, associated with the memory address, to only those cache agents identified by the mask as cache agents that can receive a snoop request associated with the memory address. | 2009-01-29 |
20090031088 | METHOD AND APPARATUS FOR HANDLING EXCESS DATA DURING MEMORY ACCESS - A computer system includes a system memory and a processor having one or more processor cores and a memory controller. The memory controller may control data transfer to the system memory. The processor further includes a cache memory such as an L3 cache, for example, that includes a data storage array for storing blocks of data. In response to a request for data by a given processor core, the system memory may provide a first data block that corresponds to the requested data, and an additional data block that is associated with the first data block and that was not requested by the given processor core. In addition, the memory controller may provide the first data block to the given processor core and store the additional data block in the cache memory. | 2009-01-29 |
20090031089 | Transpose Memory And Method Thereof - A transpose memory circuit is provided which comprises a number of dual port memory blocks each having a plurality of storage cells each configured for storing one or more data word. The dual port memory blocks form a storage array for storing at least one input matrix and outputting the at least one input matrix in transposed form. A data input is provided to receive a plurality data words on each cycle and a data output is provided to output a plurality of data words on each cycle. A read address logic is provided to generate read addresses such that one cell of each dual port memory block can be read out on each cycle. A write address logic is provided to generate write addresses such that one cell k of each dual port memory block can be written on each cycle. In each cycle, one storage cell of each dual port memory block is addressed by the read address logic. The data words stored in the addressed storage cells are read out from one dual port memory block and outputted through the data output. In each cycle, one storage cell of each dual port memory block is addressed by the write address logic, where the addressed storage cells have been read out in a preceding cycle and into which storage cells data words received through the data input are written. The transpose memory circuit is provided to receive an input matrix in cycles and to output the transposed input matrix in next cycles without any dead cycles interposed between them. | 2009-01-29 |
20090031090 | APPARATUS AND METHOD FOR FAST ONE-TO-MANY MICROCODE PATCH - A microcode patch apparatus including a patch array, a mux, and a RAM. The patch array receives a microcode ROM address and determines that the microcode ROM address matches one of a plurality of entries within the patch array. The patch array outputs a corresponding branch instruction and asserts a hit signal. The branch instruction prescribes a microcode branch target address. The mux receives the branch instruction from the patch array and a micro instruction corresponding to the microcode ROM address from a microcode ROM. The mux provides the micro instruction or the corresponding branch instruction to an instruction register based upon the state of the hit signal. The RAM stores a plurality of patch instructions that are to be executed in place of the micro instruction. The first one of the plurality of patch instructions is stored at a location in the RAM corresponding to the microcode branch target address. | 2009-01-29 |
20090031091 | CONTINUOUS TIMING CALIBRATED MEMORY INTERFACE - A system that adjusts the timing of write operations at a memory controller is described. This system operates by observing timing drift for read data at the memory controller, and then adjusting the timing of write operations at the memory controller based on the observed timing drift for the read data. | 2009-01-29 |
20090031092 | Data reception system - A data reception system includes a data acquisition unit acquiring data from a predetermined transmission path, an access control unit storing the data acquired by the data acquisition unit in a predetermined storage area, and a plurality of storage areas. The plurality of storage areas includes a first storage area and a second storage area having a greater storable capacity and a lower storing speed compared to the first storage area. The access control unit further includes a transfer unit. The access control unit determines whether the total amount of data stored in the first storage area is in the excess of a predetermined threshold or not and causes a transfer unit to transfer the data acquired by the data acquisition unit to the second storage area to store the data in the second storage area when the total amount is in the excess of the threshold. | 2009-01-29 |
20090031093 | Memory System and Method for Two Step Memory Write Operations - A method of operating a memory component that includes a memory core includes receiving, from external control lines, a write command that specifies a write operation. The write command is stored for a first time period after receiving the write command. After the first time period, the write operation is initiated in response to the write command. During the write operation, unmasked portions of received data are written to the memory core, where the unmasked portions of the data are bits of the data that are identified by received mask information as not being masked. | 2009-01-29 |
20090031094 | Method and device for interleaving data - A data interleaving device is provided that includes an input, an output, and a data interleaver coupled to the input and the output. The input receives data originating from a plurality of processing blocks. The output transfers interleaved data to the plurality of processing blocks. The data interleaver includes a controller, at least one interconnection module, and a plurality of memories. The controller prepares a data-to-memory assignment data structure. The at least one interconnection module switches data in parallel according to the data-to-memory assignment data structure and acts identically on all data switched simultaneously in parallel. The plurality of memories store the switched data. The data interleaver interleaves data received from the input and provides the interleaved data at the output. | 2009-01-29 |
20090031095 | PURGE OPERATIONS FOR SOLID-STATE STORAGE DEVICES - A storage system that comprises multiple solid-state storage devices includes a command set that enables a host system to initiate one or more types of purge operations. The supported purge operations may include an erase operation in which the storage devices are erased, a sanitization operation in which a pattern is written to the storage devices, and/or a destroy operation in which the storage devices are physically damaged via application of a high voltage. The command set preferably enables the host system to specify how many of the storage devices are to be purged at a time during a purge operation. The host system can thereby control the amount of time, and the current level, needed to complete the purge operation. In some embodiments, the number of storage devices that are purged at a time may additionally or alternatively be selectable by a controller of the storage system. | 2009-01-29 |
20090031096 | STORAGE SYSTEM AND METHOD FOR RECOVERING FROM A SYSTEM FAILURE - An apparatus and method for rapidly resuming the processing of client requests after a system failure event are disclosed. Accordingly, a surviving storage system, upon detecting a system failure event at a partner storage system, executes a takeover routine and conditions its system memory to reflect the state of the system memory of the failed storage system by processing client requests or commands stored in an operations log mirror. Then, the storage system converts the unused portion of the log mirror for use as an operations log, and resumes processing client requests prior to flushing any data to storage devices. | 2009-01-29 |
20090031097 | Creating Backups in Storage Systems - Embodiments include methods, apparatus, and systems for creating backups in storage systems. One embodiment includes a method that uses a background process to asynchronously copy data from a production virtual disk (vdisk) to a two-tier mirrorclone on a backup disk in a storage system. | 2009-01-29 |
20090031098 | Variable partitioning in a hybrid memory subsystem - A memory subsystem may include logic to make available to the device into which it is installed at least one portion of the volatile memory that will be backed up to the nonvolatile memory in the event of device power failure. The logic may make available to the device at least one portion of the volatile memory that will not be backed up to the nonvolatile memory in the event of device power failure, and make available to the device at least one portion of the nonvolatile memory that is not reserved for backups from the volatile memory. | 2009-01-29 |
20090031099 | Power interrupt recovery in a hybrid memory subsystem - A memory subsystem includes volatile memory and nonvolatile memory, and logic to interrupt a power down save operation of the memory subsystem upon detection of a restoration of system power, and to enable use of the memory subsystem by the system if sufficient nonvolatile memory capacity of the memory subsystem is available to backup an amount of the volatile memory capacity of the memory subsystem. | 2009-01-29 |
20090031100 | MEMORY REALLOCATION IN A COMPUTING ENVIRONMENT - Systems and methods for reallocating memory in a computing environment are provided. The method comprises deallocating first memory space allocated to a first software application in a first execution context, in response to determining that a first page size associated with the first memory space allocation is inappropriate for said first software application within a second execution context; and reallocating second memory space to the first software application responsive to the second execution context, such that a second page size associated with the second memory space allocation is appropriate for the first software application in the second execution context. | 2009-01-29 |
20090031101 | DATA PROCESSING SYSTEM - Before arbitration is performed in an arbitration section, an access from a master is kept in a waiting state until update of a conversion table buffer is performed, and an address conversion section is provided in a subsequent stage of the arbitration section. Without waiting for the completion of buffer update, an access is issued in advance at a time when it is assured that update is completed at the completion of address conversion. Thus, influences of waiting buffer update on another master can be eliminated and access latency can be reduced. | 2009-01-29 |
20090031102 | MAPPING AN N-BIT APPLICATION PORTED FROM AN M-BIT APPLICATION TO AN N-BIT ARCHITECTURE - Embodiments of the present invention provide a system that maps an N-bit application to virtual memory. The N-bit application may be obtained by porting an M-bit application to an N-bit architecture where N is greater than M. During operation, the system receives a request to map an N-bit application to a computer's virtual memory. The system then maps the N-bit application to a section of virtual memory which begins at a memory address that is greater than or equal to 2 | 2009-01-29 |
20090031103 | MECHANISM FOR IMPLEMENTING A MICROCODE PATCH DURING FABRICATION - A patch apparatus in a microprocessor is provided. The patch apparatus includes a plurality of fuse banks and an array controller. The plurality of fuse banks is configured to store associated patch records that are employed to patch microcode or circuits in the microprocessor. The array controller is coupled to the plurality of fuse banks, and is configured to read the associated patch records, and is configured to provide the associated patch records to a patch loader, where the patch loader provides patches corresponding to the associated patch records, as prescribed, to designated target patch mechanisms in the microprocessor. The patch loader provides the patches to the designated target patch mechanisms following transition of a microprocessor reset signal and prior to execution of instructions stored in a BIOS ROM. | 2009-01-29 |
20090031104 | Low Latency Massive Parallel Data Processing Device - Data processing device comprising a multidimensional array of ALUs, having at least two dimensions where the number of ALUs in the dimension is greater or equal to 2, adapted to process data without register caused latency between at least some of the ALUs in the corresponding array. | 2009-01-29 |
20090031105 | Processor for executing group instructions requiring wide operands - A programmable processor and method for improving the performance of processors by expanding at least two source operands, or a source and a result operand, to a width greater than the width of either the general purpose register or the data path width. The present invention provides operands which are substantially larger than the data path width of the processor by using the contents of a general purpose register to specify a memory address at which a plurality of data path widths of data can be read or written, as well as the size and shape of the operand. In addition, several instructions and apparatus for implementing these instructions are described which obtain performance advantages if the operands are not limited to the width and accessible number of general purpose registers. | 2009-01-29 |
20090031106 | RECONFIGURABLE DEVICE - There is provided a reconfigurable device that includes a plurality of processing blocks ( | 2009-01-29 |
20090031107 | ON-CHIP MEMORY PROVIDING FOR MICROCODE PATCH OVERLAY AND CONSTANT UPDATE FUNCTIONS - A patch mechanism in a microprocessor is provided. The patch mechanism includes an expansion RAM and a patch loader. The expansion RAM stores a plurality of patches, where a first one or more of the plurality of patches are to be executed by the microprocessor in place of a corresponding one or more micro instructions which are stored in a microcode ROM, and where a second one or more of the plurality of patches are employed to patch a corresponding one or more machine states in the microprocessor. The patch loader is coupled to the expansion RAM, and is configured to retrieve the plurality of patches from a source external to the microprocessor, and is configured to load the plurality of patches into the expansion RAM. | 2009-01-29 |
20090031108 | CONFIGURABLE FUSE MECHANISM FOR IMPLEMENTING MICROCODE PATCHES - A patch apparatus includes fuse banks, one or more configuration fuse banks, and an array controller. The fuse banks are configured to store associated patch records that are employed to patch microcode or machine state circuits in the microprocessor or to store associated control data entities that are employed to program control circuits in the microprocessor. The configuration fuse banks are encoded to indicate whether each of the plurality of fuse banks is programmed with one of the associated patch records or with one of the associated control data entities. The array controller reads the fuse banks, and provides the associated patch records to a patch loader or the associated control data entities to control circuits in the microprocessor. The patch loader provides patches corresponding to the associated patch records, as prescribed, to designated target patch mechanisms in the microprocessor. The patch loader provides the patches to the designated target patch mechanisms following transition of a microprocessor reset signal and prior to execution of instructions stored in a BIOS ROM. | 2009-01-29 |
20090031109 | APPARATUS AND METHOD FOR FAST MICROCODE PATCH FROM MEMORY - A microcode patch apparatus including a patch array, a mux, and a RAM. The patch array receives a microcode ROM address and determines that the microcode ROM address matches one of a plurality of entries within the patch array. The patch array outputs a corresponding branch instruction and asserts a hit signal. The branch instruction prescribes a microcode branch target address. The mux receives the branch instruction from the patch array and a micro instruction corresponding to the microcode ROM address from a microcode ROM. The mux provides the micro instruction or the corresponding branch instruction to an instruction register based upon the state of the hit signal. The RAM stores a plurality of patch instructions that are to be executed in place of the micro instruction. The first one of the plurality of patch instructions is stored at a location in the RAM corresponding to the microcode branch target address. | 2009-01-29 |
20090031110 | MICROCODE PATCH EXPANSION MECHANISM - A microcode patch expansion mechanism includes a patch RAM, an expansion RAM, and a controller. The patch RAM stores a first plurality of patch instructions. The first plurality is to be executed by the microprocessor in place of one or more micro instructions which are stored in a microcode ROM. The expansion RAM stores a second plurality of patch instructions. The number of the second plurality is greater than the number of the first plurality. The second plurality is to be executed by the microprocessor in place of a second one or more micro instructions which are stored in the microcode ROM. The controller executes an EXPRAM micro instruction directing that one or more of the second plurality of patch instructions be loaded into the patch RAM, and loads the one or more of the second plurality of patch instructions into the patch RAM. | 2009-01-29 |
20090031111 | METHOD, APPARATUS AND COMPUTER PROGRAM PRODUCT FOR DYNAMICALLY SELECTING COMPILED INSTRUCTIONS - A method, apparatus, and computer program product dynamically select compiled instructions for execution. Static instructions for execution on a first execution and dynamic instructions for execution on a second execution unit are received. The throughput performance of the static instructions and the dynamic instructions is evaluated based on current states of the execution units. The static instructions or the dynamic instructions are selected for execution at runtime on the first execution unit or the second execution unit, respectively, based on the throughput performance of the instructions. | 2009-01-29 |
20090031112 | SYSTEM AND METHOD FOR PROVIDING GLOBAL VARIABLES WITHIN A HUMAN CAPITAL MANAGEMENT SYSTEM - A system and method are provided for stacking global variables associated with a plurality of tools. The method includes loading a first tool global variable into a memory and executing a first tool of a computer application, the computer application configured to automate human resource processes. The method includes responsive to a call to execute a second tool of the computer application, pushing the first tool global variable onto a stack. The method includes loading a second tool global variable into the memory and executing the second tool. The method includes responsive to completing execution of the second tool, popping the first tool global variable off the stack and loading the first tool global variable back into the memory. | 2009-01-29 |
20090031113 | Processor Array, Processor Element Complex, Microinstruction Control Appraratus, and Microinstruction Control Method - A processor array including area-saving microprogram memories is provided. In the processor array, microprogram memories of a plurality of adjacent processor arrays are shared. Effective data and position information | 2009-01-29 |
20090031114 | MULTITHREAD PROCESSOR - To guarantee response time while strictly maintaining the priority specified by software, a processor ( | 2009-01-29 |
20090031115 | METHOD FOR HIGH INTEGRITY AND HIGH AVAILABILITY COMPUTER PROCESSING - A method of providing high integrity checking for an N-lane computer processing module (Module), N being an integer greater than equal to two. The method comprises the steps of: detecting, by a data Output Management unit (OM), when any of the N processing lanes sends different output data; configuring each Hosted Application as either normal or high integrity; for the Hosted Applications configured as high integrity, running an identical version of the software source code targeted for similar or dissimilar microprocessors on all N processing lanes, and activating a Time Management Unit, Critical Regions Management Unit, data Input Management Unit and data Output Management Unit for each of the N processing lanes; and for the Hosted Applications configured as normal integrity, running a copy of the software on one of the N processing lanes, and not activating the Time Management Unit, Critical Regions Management Unit, Input Management Unit and Output Management Unit for the one activated processing lane while that Hosted Application is running. | 2009-01-29 |
20090031116 | THREE OPERAND INSTRUCTION EXTENSION FOR X86 ARCHITECTURE - A method and apparatus are contemplated for increasing the number of available instructions in an instruction set architecture. The new instructions extend the number of general-purpose registers and include three or more operands. A combination of an escape code field, an opcode field, an operation configuration field and an operation size field determines a unique new instruction operation. A source operand extension field includes bits to be combined with other fields in order to extend the number of source operand values for general-purpose registers. | 2009-01-29 |
20090031117 | SAME INSTRUCTION DIFFERENT OPERATION (SIDO) COMPUTER WITH SHORT INSTRUCTION AND PROVISION OF SENDING INSTRUCTION CODE THROUGH DATA - A same instruction different operation (SIDO) processor is disclosed in which the instruction control word is supplied using data bus as one operand and the data to be operated is supplied through another operand. Also disclosed is a method for the provision of operation-code along with data/operands using a short instruction word. With all the execution units working in parallel on multiple data operands, a variety of operations can be performed in parallel. This allows short instruction format and flexibility to dynamically program the processor on the fly by changing data/operand words, and supports basic integer operations using very simple and efficient hardware execution units. | 2009-01-29 |
20090031118 | Apparatus and method for controlling order of instruction - An apparatus includes an instruction generator which generates a load instruction and a first store instruction from a program, a processor which executes said load and store instruction, wherein said instruction generator analyzes a relevancy between said load instruction and said first store instruction with respect to memory addresses accessed by said instructions, specifies a second store instruction irrelevant to said load instruction with respect to said memory address, and notifies said second store instruction to said processor, wherein said processor executes said load instruction in advance of said second store instruction during said processor prepares to execute said second store instruction. | 2009-01-29 |
20090031119 | Method for the operation of a multiprocessor system in conjunction with a medical imaging system - The invention relates to a method for operating a multiprocessor system, especially in conjunction with a medical imaging system. The invention also relates to a medical imaging device which is designed to perform this method. The multiprocessor system in this case has at least two processing units, at least one control unit and operations which can be allocated to the processing units. Data provided from an input is processed by the processing unit and made available at an output. The at least one control unit enhances the named data with control data, which defines an allocation of the data to the respective operations for the purposes of processing. | 2009-01-29 |
20090031120 | Method and Apparatus for Dynamically Fusing Instructions at Execution Time in a Processor of an Information Handling System - One embodiment of a processor includes a fetch stage, decoder stage, execution stage and completion stage. The execution stage includes a primary execution stage for handling low latency instructions and a secondary execution stage for handling higher latency instructions. A detector determines if an instruction is a high latency instruction or a low latency instruction. If the detector also finds that a particular low latency instruction is dependent on, and destructive of, a corresponding high latency instruction, then the secondary execution stage dynamically fuses the execution of the low latency instruction together with the execution of the high latency instruction. Otherwise, the primary execution stage handles the execution of the low latency instruction. | 2009-01-29 |
20090031121 | APPARATUS AND METHOD FOR REAL-TIME MICROCODE PATCH - An apparatus for performing microcode patches that is both fast and flexible. In one embodiment, an apparatus for performing a real-time microcode patch is provided. The apparatus includes a patch array and a mux. The patch array receives a microcode ROM address and determines that the microcode ROM address matches one of a plurality of entries within the patch array. When the microcode ROM address matches, the patch array outputs a corresponding patch instruction and to assert a hit signal. The mux receives the patch instruction from the patch array and a micro instruction corresponding to the microcode ROM address from a microcode ROM. The mux provides the micro instruction or the corresponding patch instruction to an instruction register based upon the state of the hit signal. | 2009-01-29 |
20090031122 | Mechanism for restoring an apparatus to factory default - A mechanism for restoring an apparatus to factory default is disclosed. A reset mechanism is provided in an electronic apparatus and can be activated or pressed when the electronic apparatus is powered off. A detection circuit, when the apparatus is powered on, is configured to detect whether the reset mechanism has been activated when the apparatus was powered off. If it is determined that the reset mechanism was activated, the detection circuit activates a resetting process that sets the apparatus back to the factory default status. | 2009-01-29 |
20090031123 | Secure Remote Configuration of Device Capabilities - In one embodiment, the present invention is a method for providing a secure remote configuration. The method includes obtaining a signed configuration file (S-CF) from a storage using a device identity of the device, wherein the device identity of the device is linked with a location of the device. A validated configuration file (V-CF) is then generated using the S-CF. At least one device parameter is then configured using the V-CF. In another embodiment, the present invention is a method for providing a signed configuration file (S-CF) to the device. The method includes processing a request for an S-CF from the device, wherein the request comprises a device identity of the device. A location of the device is then determined using a location database and the device identity of the device. A configuration file (CF) for the location of the device is then obtained from a storage. An S-CF is then generated using the CF. The S-CF is then provided to the device. | 2009-01-29 |