05th week of 2009 patent applcation highlights part 14 |
Patent application number | Title | Published |
20090026412 | Preparation of a hydrogen source for fuel cells - A method for preparing a hydrogen source for a fuel cell by adding an ammonium salt to a slurry of sodium borohydride and a sodium alkoxide in a liquid hydrocarbon. | 2009-01-29 |
20090026413 | Compound Based on Titanium Diphosphate and Carbon, Preparation Process, and Use as an Active Material of an Electrode for a Lithium Storage Battery - A compound containing titanium diphosphate TiP | 2009-01-29 |
20090026414 | Process for the production of an aqueous stream comprising melamine and aldehyde - Process for the production of an aqueous stream comprising melamine and aldehyde in which a melamine comprising aqueous stream is contacted with an aldehyde comprising stream, the melamine comprising aqueous stream originating from a melamine plant, and process for the production of an aqueous stream comprising melamine, urea and aldehyde in which a melamine comprising aqueous stream and a urea comprising stream are being contacted with an aldehyde comprising stream, the melamine comprising aqueous stream originating from a melamine plant. | 2009-01-29 |
20090026415 | Process to Produce an Enriched Composition - A process is provided for producing an enriched carboxylic acid compositions produced by contacting composition comprising a carboxylic acid with an enrichment feed in an enrichment zone to form an enriched carboxylic acid composition. This invention also relates to a process and the resulting compositions for removing catalyst from a carboxylic acid composition to produce a post catalyst removal composition. | 2009-01-29 |
20090026416 | PROCESS FOR SYNTHESIZING METAL BOROHYDRIDES - A process for synthesizing metal borohydride especially sodium borohydride directly from borax by the use of proton H at room temperature and pressure. Said process comprising the steps of:
| 2009-01-29 |
20090026417 | Gallium Nitride Crystal Growth Method, Gallium Nitride Crystal Substrate, Epi-Wafer Manufacturing Method, and Epi-Wafer - Affords gallium nitride crystal growth methods, gallium nitride crystal substrates, epi-wafers, and methods of manufacturing the epi-wafers, that make it possible to curb cracking that occurs during thickness reduction operations on the crystal, and to grow gallium nitride crystal having considerable thickness. A gallium nitride crystal growth method in one aspect of the present invention is a method of employing a carrier gas, a gallium nitride precursor, and a gas containing silicon as a dopant, and by hydride vapor phase epitaxy (HVPE) growing gallium nitride crystal onto an undersubstrate. The gallium nitride crystal growth method is characterized in that the carrier-gas dew point during the gallium nitride crystal growth is −60° C. or less. | 2009-01-29 |
20090026418 | Replacement Solvents Having Improved Properties and Methods of Using the Same - CFC replacement solvent compositions, methods of using the same and methods of making the same. These compositions meet or exceed the solvency, flammability, and compatibility requirements for CFC's while providing similar or improved environmental and toxicological properties. These solvent compositions have applications including, but not limited to, oxygen handling, refrigeration or heat pumps, electronics, implantable prosthetic devices, and optical equipment. | 2009-01-29 |
20090026419 | Partial oxidation of hydrocarbons - A process of catalytic partial oxidation of hydrocarbons, particularly methane and/or natural gas to form a product containing hydrogen and carbon monoxide where the first catalyst at the inlet has a lower surface area than that of a second catalyst closer to the outlet. | 2009-01-29 |
20090026420 | Partial oxidation of hydrocarbons - A process of catalytic partial oxidation of hydrocarbons, particularly methane and/or natural gas to form a product containing hydrogen and carbon monoxide where the first catalyst at the inlet has a higher thermal conductivity than that of a second catalyst closer to the outlet. The second catalyst closer to the outlet has a higher surface area than that of the first catalyst at the inlet. | 2009-01-29 |
20090026421 | OPTIMIZED LASER PYROLYSIS REACTOR AND METHODS THEREFOR - An apparatus for making a set of Group IV nanoparticles is disclosed. The apparatus includes a top plate, the top plate further including an outlet port; a bottom plate; and a casing extending between the top plate and the bottom plate. The apparatus also includes a particle collector assembly configured to be in fluid communication with the outlet port; and a primary precursor tubing assembly passing through the bottom plate into the casing, the primary precursor tubing assembly including a primary precursor tubing assembly nozzle. The apparatus further includes a set of secondary precursor tubing assemblies passing through the bottom plate into the casing, wherein each secondary precursor tubing assembly of the set of secondary precursor tubing assemblies further includes a set of secondary precursor tubing assembly nozzles positioned orthogonally to the primary precursor tubing assembly nozzle, the set of secondary precursor tubing assembly nozzles further configured to be adjusted to a first height above primary precursor tubing assembly nozzle. The apparatus also includes a laser configured to generate a laser beam, the laser beam being substantially perpendicular to the primary precursor tubing assembly nozzle in the reaction zone, wherein the laser may be adjusted to a second height above primary precursor tubing assembly nozzle. | 2009-01-29 |
20090026422 | Electrode Material for Electric Double Layer Capacitor and Process for Producing the Same, Electrode for Electric Double Layer Capacitor, and Electric Double Layer Capacitor - The present invention provides an electrode material for an electric double layer capacitor which can provide an electric double layer capacitor having a low internal resistance and a large capacitance, a process for producing the same, and an electrode for an electric double layer capacitor and an electric double layer capacitor using the same. The electrode material of the present invention is characterized by comprising a carbonaceous material and an activated carbon, the carbonaceous material obtained by thermal-treating or activating a fullerene-containing soot or an extracted residue obtained by substantially extracting at least a part of fullerene from a fullerene-containing soot using a solvent. The electrode for an electric double layer capacitor and the electric double layer capacitor of the present invention is characterized by using the electrode material. | 2009-01-29 |
20090026423 | METHOD AND SYSTEM FOR CONTROLLING RESISTIVITY IN INGOTS MADE OF COMPENSATED FEEDSTOCK SILICON - Techniques for controlling resistivity in the formation of a silicon ingot from compensated feedstock silicon material prepares a compensated, upgraded metallurgical silicon feedstock for being melted to form a silicon melt. The compensated, upgraded metallurgical silicon feedstock provides a predominantly p-type semiconductor for which the process assesses the concentrations of boron and phosphorus and adds a predetermined amount of aluminum or/and gallium. The process further melts the silicon feedstock together with a predetermined amount of aluminum or/and gallium to form a molten silicon solution from which to perform directional solidification and, by virtue of adding aluminum or/and gallium, maintains the homogeneity the resistivity of the silicon ingot throughout the silicon ingot. In the case of feedstock silicon leading to low resistivity in respective ingots, typically below 0.4Ω cm, a balanced amount of phosphorus can be optionally added to aluminum or/and gallium. Adding phosphorus becomes mandatory at very low resistivity, typically close to 0.2Ω cm and slightly below. | 2009-01-29 |
20090026424 | HYBRID COMPOSITE INCLUDING CARBON NANOTUBE AND CARBIDE-DERIVED CARBON, ELECTRON EMITTER INCLUDING THE HYBRID COMPOSITE, METHOD OF PREPARING THE ELECTRON EMITTER, AND ELECTRON EMISSION DEVICE INCLUDING THE ELECTRON EMITTER - Hybrid composites including carbon nanotubes and a carbide-derived carbon material, electron emitters including the hybrid composites, methods of preparing the electron emitters, and electron emission devices including the electron emitters are provided. Specifically, a hybrid composite includes at least one carbon nanotube and a carbide-derived carbon material. The carbide-derived carbon material is prepared by thermochemically reacting a carbide compound with a halogen-containing gas to extract substantially all of the elements except for the carbon in the carbide compound. Since the carbon nanotubes and the carbide-derived carbon material are hybridized and composited, a screen effect that may occur when large amounts of carbon nanotubes are used can be prevented, and an electron emitter including the hybrid composite has excellent electron emission capabilities, excellent uniformity, and a long lifetime. | 2009-01-29 |
20090026425 | COMPOSITION COMPRISING POLYESTER AMIDE ACID AND THE LIKE AND INK-JET INK COMPOSITION USING THE SAME - The invention provides a composition comprising a polyester amide acid (A) obtained by reacting a tetracarboxylic dianhydride (a1), a diamine (a2) and a multivalent hydroxy compound (a3); a pigment (B); and an epoxy resin (C), which is most suitable for an ink-jet ink composition for a color filter. | 2009-01-29 |
20090026426 | Truck crane - The present invention relates to a truck crane with a winch, in particular a hoisting winch, which is mounted on the uppercarriage, wherein the truck crane includes means for raising and/or lowering the winch. | 2009-01-29 |
20090026427 | CRIBBING APPARATUS - A cribbing apparatus for stabilizing a post-accident vehicle against unwanted movement of the vehicle during a rescue operation in which a victim trapped in the vehicle is to be extricated from the vehicle including a cribbing block having a two cribbing block portions, one of which is vertically movable with respect to the second in order to fill a space between the vehicle and the ground. The cribbing block includes a stair-stepped upper surface to facilitate the placement of the cribbing beneath vehicles of various ground clearances. The first cribbing block portion is raised to further fill space between the vehicle and the ground on high clearance vehicles, such as SUVs, Trucks and Buses. The structure and operation of the cribbing apparatus eliminates the need to forcefully jam cribbing into place between the vehicle and the ground and eliminates the need to stack cribbing. | 2009-01-29 |
20090026428 | EXTENSION ROD USED FOR A JACK ARM - An extension rod for a jack arm comprises a connecting rod having a first joint and a second joint formed at the respective ends of the connecting rod. A first locking hole and a second locking hole are formed in the first and second joints, respectively. The extension rod also comprises a lockup mechanism comprising an elastic body configured to connect to either the first joint or the connecting rod and a lockup bolt formed on the elastic body, and configured to engage the first locking hole. | 2009-01-29 |
20090026429 | Optical Fibre Installation Apparatus - A blowing head for installing blown cable, comprising a low-inertia motor using electrical current, operable to obtain the advance of the cable within the blowing head, adjusting means operable to vary the level of current of the motor, and low-inertia sensing means to sense movement and changes in the level of movement of the cable within the blowing head, wherein in use the adjusting means varies the level of current used by the motor in response to changes in the level of movement sensed by the sensing means, and wherein the varying level of current does not exceed a maximum current level. | 2009-01-29 |
20090026430 | LIFTING AND CRIBBING SYSTEMS - Underlying surface lift systems and methods are disclosed that facilitate the lifting and moving of constructions, including but not limited to structures, and machines, implements, building materials, earth, rock, and other massive massively weighted and/or large dimensioned objects or materials. The underlying surface lift systems and methods may be used or performed in combination with one or more support elements to the construction or other item to be lifted, such as steel I-beams or wooden beams or other supportive elements. The invention comprises in some embodiments underlying surface lift systems and methods, alone or in combination with or performed with supportive elements generally, such as beams and other devices or elements. Further embodiments may include an underlying surface lift apparatus having a support plate and a lift device in adjustable connection with the support plate. In some embodiments a pivot saddle is the adjustable connection of the support plate and the lift device. The invention may comprise technology that facilitates the lifting and moving of constructions such as structures or other objects, particularly those having support elements, while reducing the costs and hazards of traditional jack systems and without the added costs and risks associated with complex crane operations. Other disclosed embodiments are methods of lifting from an underlying surface, business methods of lifting and moving constructions objects, or materials, and methods of cribbing constructions, objects or materials are further disclosed. Still other methods such as those corresponding to each apparatus and assemblies are also disclosed, as well as methods of doing business. Applications may include the lifting and relocating of structures such as temporary or extension buildings to new locations and other lifting and moving solutions and may be provided in combination with other relocating technologies. | 2009-01-29 |
20090026431 | PICKET AND RAIL FENCE - A picket and rail fence is provided. In one embodiment, the invention relates to a fence including a rail including a tube having a rectangular cross section including a top, a bottom, two sides, and at least one cutout, a picket including a bar configured to fit within the at least one cutout of the rail, a retaining bar having a lengthwise rectangular shape, the retaining bar including a first substantially flat longitudinal portion, a second substantially flat longitudinal portion, wherein the first portion and the second portion are separated by a middle portion having a cross section forming a protrusion extending away from the first portion and the second portion, wherein the retaining bar is configured to slide within the rail such that a bottom of the retaining bar abuts one of the two sides of the rail, and wherein the picket bar includes a notch configured to receive at least a portion of the protrusion of the retaining bar. | 2009-01-29 |
20090026432 | METHOD AND STRUCTURE FOR UNIFORM CONTACT AREA BETWEEN HEATER AND PHASE CHANGE MATERIAL IN PCRAM DEVICE - A PCM (phase change memory) cell in a PCRAM (phase change random access memory) semiconductor device includes a phase change material subjacently contacted by a heater film. The phase change material is formed over a surface that is a generally planar surface with at least a downwardly extending recess. The phase change material fills the recess and contacts the upper edge of the heater film that forms the bottom of the recess. After a planar surface is initially formed, a selective etching process is used to recede the top edge of the heater film below the planar surface using a selective and isotropic etching process. | 2009-01-29 |
20090026433 | MULTISTATE NONVOLATILE MEMORY ELEMENTS - Multistate nonvolatile memory elements are provided. The multistate nonvolatile memory elements contain multiple layers. Each layer may be based on a different bistable material. The bistable materials may be resistive switching materials such as resistive switching metal oxides. Optional conductor layers and current steering elements may be connected in series with the bistable resistive switching metal oxide layers. | 2009-01-29 |
20090026434 | NONVOLATILE MEMORY ELEMENTS - Nonvolatile memory elements that are based on resistive switching memory element layers are provided. A nonvolatile memory element may have a resistive switching metal oxide layer. The resistive switching metal oxide layer may have one or more layers of oxide. A resistive switching metal oxide may be doped with a dopant that increases its melting temperature and enhances its thermal stability. Layers may be formed to enhance the thermal stability of the nonvolatile memory element. An electrode for a nonvolatile memory element may contain a conductive layer and a buffer layer. | 2009-01-29 |
20090026435 | Phase change random access meomory and semiconductor device - A phase change random access memory comprises an under electrode; an interlayer insulating layer which is formed on the under electrode; an impurity diffusion layer which is embedded into a pore through the interlayer insulating layer; a phase change recording layer which is formed on the interlayer insulating layer; an upper electrode which is formed on the phase change recording layer; a side gate electrode which is located on an inner wall of the pore into which the impurity diffusion layer is embedded; and a side gate insulating layer which is located between the side gate electrode and the impurity diffusion layer, wherein the side gate electrode applies an electric field to the impurity diffusion layer via the side gate insulating lay, the impurity diffusion layer is depleted, and so that an effective diameter of the impurity diffusion layer can become smaller than the pore diameter. | 2009-01-29 |
20090026436 | Phase change memory devices and methods of forming the same - A method of forming a phase change memory device includes forming a core pattern on a substrate, conformally forming a heat conductive layer on the substrate including the core pattern, anisotropically etching the heat conductive layer down to a top surface of the core pattern to form a heat electrode surrounding a sidewall of the core pattern, and forming a phase change memory pattern connected to a top surface of the heat electrode. | 2009-01-29 |
20090026437 | Copper compatible chalcogenide phase change memory with adjustable threshold voltage - A phase change memory cell may include two or more stacked or unstacked series connected memory elements. The cell has a higher, adjustable threshold voltage. A copper diffusion plug may be provided within a pore over a copper line. By positioning the plug below the subsequent chalcogenide layer, the plug may be effective to block copper diffusion upwardly into the pore and into the chalcogenide material. Such diffusion may adversely affect the electrical characteristics of the chalcogenide layer. | 2009-01-29 |
20090026438 | SOLID STATE ELECTROLYTE MEMORY DEVICE AND METHOD OF FABRICATING THE SAME - A method of fabricating a solid state electrolytes memory device is provided. An insulator layer is formed on a substrate. A conductive layer is formed on the insulator layer. At least two openings partially overlapped and capable of communicating with each other are formed in the conductive layer, so that the conductive layer forms at least a pair of tip electrodes. Thereafter, solid state electrolytes are filled in the openings. | 2009-01-29 |
20090026439 | Phase Change Memory Cells Having a Cell Diode and a Bottom Electrode Self-Aligned with Each Other - Integrated circuit devices are provide having a vertical diode therein. The devices include an integrated circuit substrate and an insulating layer on the integrated circuit substrate. A contact hole penetrates the insulating layer. A vertical diode is in lower region of the contact hole and a bottom electrode in the contact hole has a bottom surface on a top surface of the vertical diode. The bottom electrode is self-aligned with the vertical diode. A top surface area of the bottom electrode is less than a horizontal section area of the contact hole. Methods of forming the integrated circuit devices and phase change memory cells are also provided. | 2009-01-29 |
20090026440 | Nitride semiconductor light-emitting element - A nitride semiconductor light-emitting element | 2009-01-29 |
20090026441 | Continuous plane of thin-film materials for a two-terminal cross-point memory - A structure for a memory device including a plurality of substantially planar thin-film layers or a plurality of conformal thin-film layers is disclosed. The thin-film layers form a memory element that is electrically in series with first and second cladded conductors and operative to store data as a plurality of conductivity profiles. A select voltage applied across the first and second cladded conductors is operative to perform data operations on the memory device. The memory device may optionally include a non-ohmic device electrically in series with the memory element and the first and second cladded conductors. Fabrication of the memory device does not require the plurality of thin-film layers be etched in order to form the memory element. The memory element can include a CMO layer having a selectively crystallized polycrystalline portion and an amorphous portion. The cladded conductors can include a core material made from copper. | 2009-01-29 |
20090026442 | Continuous plane of thin-film materials for a two-terminal cross-point memory - A structure for a memory device including a plurality of substantially planar thin-film layers or a plurality of conformal thin-film layers is disclosed. The thin-film layers form a memory element that is electrically in series with first and second cladded conductors and operative to store data as a plurality of conductivity profiles. A select voltage applied across the first and second cladded conductors is operative to perform data operations on the memory device. The memory device may optionally include a non-ohmic device electrically in series with the memory element and the first and second cladded conductors. Fabrication of the memory device does not require the plurality of thin-film layers be etched in order to form the memory element. The memory element can include a CMO layer having a selectively crystallized polycrystalline portion and an amorphous portion. The cladded conductors can include a core material made from copper. | 2009-01-29 |
20090026443 | ORGANIC THIN-FILM TRANSISTOR AND METHOD OF MANUFACTURE THEREOF - A durable organic thin-film transistor and a method of manufacture thereof, the organic thin-film transistor having: a source electrode and a drain electrode arranged mutually separated; an organic semiconductor layer interposed between the source electrode and the drain electrode; and a gate electrode arranged to face said organic semiconductor layer which is between said source electrode and said drain electrode, with a gate insulating film being provided between said gate electrode and said organic semiconductor layer, wherein the gate insulating film includes an organic compound and particles of an inorganic compound dispersed in the organic compound, and a flattened film is provided between the source electrode and the drain electrode, or the gate electrode and the gate insulating film. | 2009-01-29 |
20090026444 | Organic thin film transistor array panel and manufacturing method of the same - An organic thin film transistor array panel includes a substrate, a gate line formed on the substrate and including a gate electrode. A gate insulating layer is formed on the gate electrode and a data line is formed on the gate insulating layer, intersecting the gate line, and including a drain electrode. A source electrode is formed on the gate insulating layer and is spaced apart from the drain electrode, enclosed by the drain electrode. A bank insulating layer includes a first opening exposing the drain electrode and the source electrode and a second opening which exposes at least a portion of the source electrode. An organic semiconductor is formed in the first opening and contacts the drain electrode and the source electrode. A pixel electrode contacts the source electrode through the second opening. | 2009-01-29 |
20090026445 | Organic thin film transistor array panel and method for manufacturing the same - A method for manufacturing an organic thin film transistor array panel includes forming a data line including a source electrode and a drain electrode apart from the data line on a substrate and forming a bank insulating layer including a first opening and a second opening on the data line and the drain electrode. An organic semiconductor is formed in the first opening, sequential deposition is performed of an insulating material layer and a metal layer on the bank insulating layer and the organic semiconductor. A first passivation layer is formed on the metal layer which is etched using the first passivation layer as an etch mask to form a gate line including a gate electrode. The insulating material layer is etched using the first passivation layer as an etch mask to form a gate insulating layer. A second passivation layer is formed on the first passivation layer and a pixel electrode is formed on the second passivation layer. | 2009-01-29 |
20090026446 | Organic light emitting device and manufacturing method thereof - An organic light emitting device according to an embodiment includes a thin film transistor substrate including a plurality of thin film transistors and an over-coating film formed on the thin film transistors. The over-coating film includes a curved surface on at least two pixels among pixels of different colors and the slope angles of depressed portions forming the curved surface are respectively different from each other depending on the colors of the pixels. A plurality of first electrodes formed on the over-coating film includes a surface formed according to the curved surface, an organic light emitting member formed on the first electrodes includes a surface formed according to the curved surface, and a second electrode formed on the organic light emitting member includes a surface formed according to the curved surface. Slope angles of the depressed portions increase according to a decrease of wavelengths of the colors of the pixels. | 2009-01-29 |
20090026447 | Light emitting device - An organic EL display device having a long lifetime is provided. The light emitting device includes at least one organic compound layer between a pair of electrodes, and the content of an impurity generated from an organic compound in the at least one organic compound layer is 10 ng/cm | 2009-01-29 |
20090026448 | ELECTRONIC COMPONENT, METHOD FOR ITS PRODUCTION AND ITS USE - The present invention relates to an electronic component having at least one anode, at least one cathode, at least one charge injection layer, at least one layer of an organic semiconductor and at least one layer situated between the charge injection layer and the organic semiconductor layer, which component is characterized in that the layer situated between the charge injection layer and the organic semiconductor layer and the organic semiconductor layer are obtainable by coating the charge injection layer with a mixture composing at least one material which can be made insoluble by means of chemical reaction, and at least one organic semiconductor, method for producing said component and use of said component. | 2009-01-29 |
20090026449 | PIXEL STRUCTURE AND METHOD OF FABRICATING THE SAME - A method for fabricating pixel structures is disclosed. Specifically, the present invention deposits a conductive layer, a gate dielectric layer, and an aluminum layer on a gate dielectric layer, and performs an isotropic etching process to evenly etch a portion of the aluminum layer in the horizontal and vertical direction. By following this process, the number of photomasks used before the formation of the source/drain region can be reduced, and the conductive layer and the aluminum layer disposed on the capacitor electrode in the capacitor region can be used to increase the capacitance of the capacitor. | 2009-01-29 |
20090026450 | THIN FILM TRANSISTOR SUBSTRATE AND METHOD OF MANUFACTURING THE SAME - A thin film transistor array substrate comprising a base substrate, a first wire on the base substrate, a first insulating layer on the base substrate to cover the first wire, a semiconductor layer on the first insulating layer, a second insulating layer on the first insulating layer on which the semiconductor layer is formed, and a second wire on the second insulating layer on the second insulating layer is provided, and a portion of the second wire makes contact with the semiconductor layer through the contact hole. | 2009-01-29 |
20090026451 | THIN FILM TRANSISTOR ARRAY SUBSTRATE AND METHOD FOR MANUFACTURING THE SAME - A thin film transistor array substrate and a method for manufacturing the same are disclosed. The thin film transistor array substrate includes a plurality of gate lines and a plurality of data lines on a substrate, to define pixel regions crossing each other, thin film transistors, each formed at the intersection of the gate lines and the data lines, and including a gate electrode, a source electrode and a drain electrode, common lines, each including a first pattern formed across the data lines, a second pattern formed adjacent to the data lines on both sides in the pixel region and parallel to the data lines, and a third pattern formed adjacent to the gate lines to connect the second pattern disposed on both the sides in the associated one of the pixel regions, and passing below the drain electrode of the thin film transistors and pixel electrodes formed in the pixel regions. | 2009-01-29 |
20090026452 | Liquid crystal display device and electronic device provided with the same - A liquid crystal display device provided with a thin film transistor with excellent electrical characteristics and reduced off current, for which increase in manufacturing costs can be suppressed while suppressing reduction in yield. A thin film transistor includes a gate electrode provided over a substrate; a gate insulating film provided to cover the substrate and the gate electrode; a first island-shaped semiconductor layer and a second island-shaped semiconductor layer each formed as a stack of a microcrystalline semiconductor layer and a buffer layer with a depression on an upper surface thereof, over the gate electrode with the gate insulating film interposed therebetween; a conductive semiconductor layer; and a conductive layer provided on the conductive semiconductor layer. The conductive semiconductor layer is provided between the first island-shaped semiconductor layer and the second island-shaped semiconductor layer in contact with the gate insulating film. | 2009-01-29 |
20090026453 | Display device and manufacturing method thereof - A gate insulating film is formed over a gate electrode; a microcrystalline semiconductor is formed over the gate insulating film; an impurity element for controlling the threshold value is added into the microcrystalline semiconductor film by an ion implantation method; the microcrystalline semiconductor film is irradiated with a laser beam so that the crystallinity of the microcrystalline semiconductor film is improved; and then, a buffer layer is formed over the microcrystalline semiconductor film, whereby a channel-etched thin film transistor is formed. Further, a display device including the thin film transistor is manufactured. | 2009-01-29 |
20090026454 | Display device - To provide a display device including a protection circuit having a thin film transistor which has small size and high withstand voltage. In the protection circuit of the display device, a thin film transistor is used in which an amorphous semiconductor layer, a microcrystalline semiconductor layer, a gate insulating layer which is in contact with the microcrystalline semiconductor layer, and a gate electrode layer overlap with each other. Since current drive capability of the microcrystalline semiconductor layer is high, the size of the transistor can be made small. In addition, the amorphous semiconductor layer is included, so that the withstand voltage can be improved. Here, the display device is a liquid crystal display device or a light-emitting device. | 2009-01-29 |
20090026455 | LIQUID CRYSTAL DISPLAY DEVICE AND ITS MANUFACTURING METHOD - The occurrence of the poor electric connection between the outer circuit and the liquid crystal display device can be reduced in the manufacturing method of the outer circuit and liquid display device of this invention. The liquid crystal display device has the pixel region | 2009-01-29 |
20090026456 | TRANSISTOR ARRAY PANEL, LIQUID CRYSTAL DISPLAY PANEL, AND METHOD OF MANUFACTURING LIQUID CRYSTAL DISPLAY PANEL - A transistor array panel includes switching elements provided in intersecting portions between gate and data lines, and display electrodes connected to the switching elements. A conductive film pattern is provided to be electrically insulated from the gate and data lines, and display electrodes, and to be overlapped on the display electrodes, thereby forming a storage capacitance between each of the display electrodes and the conductive film pattern. A protection circuit is electrically connected to the gate and data lines, and disposed in an outer peripheral portion of a display region in which the switching elements and the display electrodes are formed on the one side of the substrate. A common line is insulated from the protection circuit, connected to the conductive film pattern, and provided to be insulated from the protection circuit and to be at least partially overlapped on the protection circuit, in the outer peripheral portion of the display region. | 2009-01-29 |
20090026457 | Active matrix substrate, method of making the substrate, and display device - An active matrix substrate includes base substrate, gate lines, data lines, thin-film transistors and pixel electrodes. The gate lines are formed on the base substrate. The data lines are formed over the gate lines. Each of the data lines crosses all of the gate lines with an insulating film interposed therebetween. The thin-film transistors are formed over the base substrate. Each of the thin-film transistors is associated with one of the gate lines and operates responsive to a signal on the associated gate line. Each of the pixel electrodes is associated with one of the data lines and one of the thin-film transistors and is electrically connectable to the associated data line by way of the associated thin-film transistor. Each of the pixel electrodes and the associated thin-film transistor are connected together by way of a conductive member. Each of the pixel electrodes crosses one of the gate lines, while the conductive member for the pixel electrode crosses another one of the gate lines that is adjacent to the former gate line. | 2009-01-29 |
20090026458 | POROUS SEMICONDUCTIVE FILM AND PROCESS FOR ITS PRODUCTION - The present invention provides a porous semiconductive structure, characterized in that the structure has an electrical conductivity of 5·10 | 2009-01-29 |
20090026459 | EPITAXIAL AND POLYCRYSTALLINE GROWTH OF SI1-X-YGEXCY AND SI1-YCY ALLOY LAYERS ON SI BY UHV-CVD - A method and apparatus for depositing single crystal, epitaxial films of silicon carbon and silicon germanium carbon on a plurality of substrates in a hot wall, isothermal UHV-CVD system is described. In particular, a multiple wafer low temperature growth technique in the range from 350° C. to 750° C. is described for incorporating carbon epitaxially in Si and SiGe films with very abrupt and well defined junctions, but without any associated oxygen background contamination. Preferably, these epitaxial SiC and SiGeC films are in-situ doped p- or n-type and with the presence of low concentration of carbon <10 | 2009-01-29 |
20090026460 | VERTICAL NON-VOLATILE MEMORY AND MANUFACTURING METHOD THEREOF - A manufacturing method of a vertical non-volatile memory is provided. A first semiconductor layer, a first barrier, a second semiconductor layer, a second barrier and a third semiconductor layer are formed on a substrate sequentially. The first and the third semiconductor layers have a first conductive state, while the second semiconductor layer has a second conductive state. Several strips of active stacked structures are formed by removing portions of the first, second and third semiconductor layers, and portions of the first and second barrier on the substrate. After forming a storage structure on the substrate, the storage structure is covered with a conductive layer filling spaces among the active stacked structures. A portion of the conductive layer is removed to form word lines across the active stacked structures. | 2009-01-29 |
20090026461 | Semiconductor device including semiconductor circuit made from semiconductor element and manufacturing method thereof - In the present invention, a semiconductor film is formed through a sputtering method, and then, the semiconductor film is crystallized. After the crystallization, a patterning step is carried out to form an active layer with a desired shape. The present invention is also characterized by forming a semiconductor film through a sputtering method, subsequently forming an insulating film. Next, the semiconductor film is crystallized through the insulating film, so that a crystalline semiconductor film is formed. According this structure, it is possible to obtain a thin film transistor with a good electronic property and a high reliability in a safe processing environment. | 2009-01-29 |
20090026462 | WIRING SUBSTRATE AND METHOD OF MANUFACTURING SAME, AND DISPLAY DEVICE - A wiring substrate includes a plurality of lines provided on the substrate, and a plurality of mounting terminals each for respective one of the plurality of lines, the plurality of mounting terminals being arranged in several rows in a staggered pattern, wherein the mounting terminal includes a first conductive film formed in the same layer as the lines, an insulating film covering the lines and the first conductive film, the insulating film having an opening above the first conductive film, and an upper layer conducive film electrically connected to the first conductive film through the opening, and wherein the insulating film includes a thick film portion located on the outside of the area where the plurality of mounting terminals are arranged in several rows in the staggered pattern, and a thin film portion located in the area adjacent to the opening in the row direction of the staggered pattern with a thickness thinner than the thick film portion. | 2009-01-29 |
20090026463 | ARRAY SUBSTRATE FOR A DISPLAY DEVICE AND METHOD OF MANUFACTURING THE SAME - An array substrate includes a thin-film transistor (TFT), a first insulation layer and a second insulation layer. The TFT is formed on the substrate. The TFT includes an active pattern, a gate metal pattern and a data metal pattern. The first insulation layer insulates the active pattern from the gate metal pattern. The second insulation layer is formed spaced apart by a predetermined width from at least one edge of the substrate. The second insulation layer insulates the gate metal pattern from the data metal pattern. Therefore, the second insulation layer is formed so that stress that is inflicted on a substrate may be decreased, thereby preventing deformation during a manufacturing process of the substrate. | 2009-01-29 |
20090026464 | Semiconductor device and manufacturing method thereof - A TFT is manufactured using at least five photomasks in a conventional liquid crystal display device, and therefore the manufacturing cost is high. | 2009-01-29 |
20090026465 | POLYSILICON FILM HAVING SMOOTH SURFACE AND METHOD OF FORMING THE SAME - A method of forming a polysilicon film having smooth surface using a lateral growth and a step-and-repeat laser process. Amorphous silicon formed in a first irradiation region of a substrate is crystallized to form a first polysilicon region by a first laser shot. Then, the substrate is moved a predetermined distance, and irradiated by a second laser shot. The polysilicon region is then recrystallized and locally planarized by subsequent laser shots. After multiple repetitions of the irradiation procedure, the amorphous silicon film formed on a substrate is completely transformed into a polysilicon film. The polysilicon film includes lateral growth crystal grains and nano-trenches formed in parallel on the surface of the polysilicon film. A longitudinal direction of the nano-trenches is substantially perpendicular to a lateral growth direction of the crystal grains. | 2009-01-29 |
20090026466 | QUASI SINGLE CRYSTAL NITRIDE SEMICONDUCTOR LAYER GROWN OVER POLYCRYSTALLINE SiC SUBSTRATE - A compound semiconductor device is manufactured by using a polycrystalline SiC substrate, the compound semiconductor device having a buffer layer being formed on the substrate and having a high thermal conductivity of SiC and aligned orientations of crystal axes. The method for manufacturing the compound semiconductor device includes: forming a mask pattern on a polycrystalline SiC substrate, the mask pattern having an opening of a stripe shape defined by opposing parallel sides or a hexagonal shape having an apex angle of 120 degrees and exposing the surface of the polycrystalline SiC substrate in the opening; growing a nitride semiconductor buffer layer, starting growing on the polycrystalline SiC substrate exposed in the opening of the mask pattern, burying the mask pattern, and having a flat surface; and growing a GaN series compound semiconductor layer on the nitride semiconductor buffer layer. | 2009-01-29 |
20090026467 | ELECTROOPTICAL DEVICE, ELECTRONIC APPARATUS, AND METHOD FOR PRODUCING ELECTROOPTICAL DEVICE - An electrooptical device having a plurality of light-emitting regions includes a substrate, a bank disposed in a region other than the light-emitting regions on the substrate so as to surround the light-emitting regions, and a functional layer disposed in openings surrounded by the bank. The bank includes an upper bank segment and a plurality of lower bank segments having a higher wettability than the upper bank segment. The number of the lower bank segments exposed is smaller in second regions of the openings than in first regions of the openings. | 2009-01-29 |
20090026468 | Semiconductor Light Emitting Element - In a semiconductor light emitting element, a p-type layer ( | 2009-01-29 |
20090026469 | LIGHT-EMITTING DEVICE AND METHOD FOR MANUFACTURING SAME - The light-emitting device of the present invention is a light-emitting device having a plurality of pixels that comprises a light-emitting function layer of at least one layer that emits light in accordance with a supplied current, a first electrode layer of a conductive material provided at one surface of the light-emitting function layer, and being transparent to at least part of a wavelength range of light emitted from the light-emitting function layer, a second electrode layer provided facing the first electrode layer on the other surface of the light-emitting function layer, including conductive material, and being transparent to at least part of the wavelength range of light emitted from the light-emitting function layer, and a reflecting layer provided on the second electrode layer, and being reflective to at least part of the wavelength range of light emitted from the light-emitting function layer. | 2009-01-29 |
20090026470 | SUPER THIN SIDE-VIEW LIGHT-EMITTING DIODE (LED) PACKAGE AND FABRICATION METHOD THEREOF - A fabrication method of a side-view LED package is provided. A chip carrier is provided. An opaque housing is bonded with the chip carrier. An LED chip electrically connects the chip carrier by performing a chip-bonding process and the opaque housing has a cavity for accommodating the LED chip. A transparent encapsulant is disposed in the cavity wherein the transparent encapsulant has a side-view light output surface uncovered by the opaque housing and light emitted from the LED chip is output via the side-view light output surface. A portion of the opaque housing and a portion of the transparent encapsulant are removed for reducing an overall thickness of the opaque housing such that a top surface of the transparent encapsulant is uncovered by the opaque housing beside the side-view light output surface. An opaque protective layer is formed on the top surface of the transparent encapsulant and the opaque housing. | 2009-01-29 |
20090026471 | LIGHT-SCATTERING STRUCTURE, LIGHT EMITTING DEVICE COMPRISING THE SAME AND METHOD OF FORMING THE SAME - A light-scattering structure with micron-scale or submicron-scale protruding portions is provided to improve the light extraction efficiency of light emitting devices. The protruding portions function as scattering sites and can be assembled closely. A method of forming a light-scattering structure is also provided, wherein all the conventional substrate materials can be used for the substrate of the light-scattering structure, and scattering sites of submicron-scale, micron-scale or larger size can be fabricated. | 2009-01-29 |
20090026472 | Silicon LED package having horn and contact edge with (111) planes | 2009-01-29 |
20090026473 | InGaAlN LIGHT-EMITTING DEVICE AND MANUFACTURING METHOD THEREOF - There is provided an InGaAlN light-emitting device and a manufacturing method thereof. The light emitting device includes a conductive substrate having a main surface and a back surface, a metal bonding layer formed on the main surface of the substrate, a light reflecting layer formed on the bonding layer, a semiconductor multilayer structure including at least a p-type and an n-type InGaAlN layer disposed on the reflecting layer, the p-type InGaAlN layer directly contacting the reflecting layer, and ohmic electrodes disposed on said n-type InGaAlN layer and on the back surface of the conductive substrate, respectively. | 2009-01-29 |
20090026474 | RADIATION-EMITTING ELEMENT AND METHOD FOR PRODUCING A RADIATION-EMITTING ELEMENT - A radiation-emitting component comprises an optical element and a housing body that has a fastening device that engages with or wraps around the optical element, wherein the fastening device is bent or is provided with projections in such a way that the optical element is irreversibly fixed on the housing body. | 2009-01-29 |
20090026475 | Semiconductor Light Emitting Device and Method for Manufacturing the Same - Concaves and convexes are formed in a light transmitting conductive layer provided on a surface of a light emitting device made of nitride semiconductor, thereby light emitted from a light emitting layer is totally reflected repeatedly in a semiconductor lamination portion and a substrate and can be effectively taken out without attenuation, and external quantum efficiency can be improved. A semiconductor lamination portion ( | 2009-01-29 |
20090026476 | SEMICONDUCTOR LIGHT-EMITTING ELEMENT AND SEMICONDUCTOR LIGHT-EMITTING ELEMENT MANUFACTURING METHOD - An aspect of the present invention inheres in a semiconductor light-emitting element includes a light-emitting functional stacked body including a light-emitting region having a light-emitting function, and including a light extraction surface for extracting light emitted from the light-emitting region, and an upward convex lens disposed on the light extraction surface. | 2009-01-29 |
20090026477 | NOVEL PHOSPHOR AND FABRICATION OF THE SAME - The present invention provides a novel phosphor represent by the following general formula: | 2009-01-29 |
20090026478 | SEMICONDUCTOR LIGHT EMITTING DEVICE - There is provided a semiconductor light emitting device having excellent light extraction efficiency to efficiently reflect light moving into the device by increasing the total reflectivity of a reflective layer. A semiconductor light emitting device according to an aspect of the invention includes: a substrate, a reflective electrode, a first conductivity semiconductor layer, an active layer, and a second conductivity type semiconductor layer that are sequentially stacked. Here, the reflective electrode includes; a first reflective layer provided on the substrate and including a conductive reflective material reflecting light generated from the active layer; and a second reflective layer provided on the first reflective layer, including one or more dielectric portions reflecting light generated from the active layer, and one or more contact holes filled with a conductive filler to electrically connect the first conductivity type semiconductor layer and the first reflective layer, and having a greater thickness than a wavelength of the generated light. | 2009-01-29 |
20090026479 | OPTICAL WAVEGUIDE DEVICE AND MANUFACTURING METHOD THEREOF - An optical waveguide device including a substrate; a light emitting element provided on a light emitting element provision region of an upper surface of the substrate; an under-cladding layer provided on a portion of the upper surface of the substrate except for the light emitting element provision region; and a core covering the light emitting element and the under-cladding layer on the substrate, and serving as a path of light emitted from the light emitting element. An optical waveguide device manufacturing method including the steps of: forming an under-cladding layer on a portion of an upper surface of a substrate except for the light emitting element provision region; placing a light emitting element on the light emitting element provision region; and forming a core on the resultant substrate to cover the light emitting element and the under-cladding layer. | 2009-01-29 |
20090026480 | LIGHT EMITTING DEVICE AND METHOD OF MANUFACTURING THE SAME - Provided is a light emitting device with high extraction efficiency, in which absorption of light by a conductive wire is prevented effectively. The light emitting device includes a conductive wire electrically connecting an electrode of a light emitting element and an electrically conductive member. The surface of the bonding portion of the conductive wire between the conductive wire and at least one of the electrode of the light emitting element and the electrically conductive member is covered with a metal film. The reflectivity of the metal film is higher than that of the conductive wire at the emission peak wavelength of the light emitting element. | 2009-01-29 |
20090026481 | Nitride semiconductor light-emitting device and method of manufacturing nitride semiconductor light-emitting device - A nitride semiconductor light-emitting device including a coating film and a reflectance control film successively formed on a light-emitting portion, in which the light-emitting portion is formed of a nitride semiconductor, the coating film is formed of an aluminum oxynitride film or an aluminum nitride film, and the reflectance control film is formed of an oxide film, as well as a method of manufacturing the nitride semiconductor light-emitting device are provided. | 2009-01-29 |
20090026482 | Optoelectronic Component - An optoelectronic component having a basic housing or frame and at least one semiconductor chip, specifically a radiation-emitting or-receiving semiconductor chip, in a cavity of the basic housing. In order to increase the efficiency of the optoelectronic component, reflectors are provided in the cavity in the region around the semiconductor chip. These reflectors are formed by virtue of the fact that a filling compound filled at least partly into the cavity is provided, the material and the quantity of the filling compound being chosen in such a way that the filling compound, on account of the adhesion force between the filling compound and the basic housing, assumes a form which widens essentially conically from bottom to top in the cavity, and the conical inner areas of the filling compound serve as reflector. | 2009-01-29 |
20090026483 | HIGH-POWER LED PACKAGE - A high-power LED package includes a thermally conductive substrate, a plurality of electric contact pins, and at least one high-power LED. The thermally conductive substrate has a circuit board, a metal plate, and a connecting member connected between the circuit board and the metal plate. The substrate is provided with a plurality of through holes running through the circuit board and the metal plate. The electric contact pins are received in the respective through holes and partially extending out of the through holes. The high-power LED is mounted on the metal plate and electrically connected to the circuit board by means of a plurality of metal wires. Therefore, the metal plate having preferable thermal conductivity can effectively dissipate the heat generated by the high-power LED. | 2009-01-29 |
20090026484 | LIGHT EMITTING DIODE DEVICE - A light emitting diode device is disclosed, and the light emitting diode device includes a base, a substrate, a lead frame, a chip, a first mixed layer and a second mixed layer. The first mixed layer and the second mixed layer respectively contain a glue and a thermal conductance insulating material, such as diamond carbon, diamond-like carbon or ceramic. The substrate and the lead frame are set on the base. The first mixed layer is formed between the chip and the substrate to fix the chip and strengthen heat dissipation. The second mixed layer is covered on the substrate and the chip to reduce the difference of the refraction index such that the total internal reflection angle is wider and the emitting efficiency is enhanced. | 2009-01-29 |
20090026485 | LIGHT-EMITTING DEVICE - A light-emitting device of the present invention includes: a LED chip | 2009-01-29 |
20090026486 | Nitride based compound semiconductor light emitting device and method of manufacturing the same - A nitride based compound semiconductor light emitting device having a first substrate and a nitride based compound semiconductor part including a p-type nitride based compound semiconductor layer, an active layer, and an n-type nitride based compound semiconductor layer in this order from the first substrate side, in which the first substrate has a through hole penetrating through the first substrate in up and down directions and a metal film is buried in the through hole, and its method of manufacturing. The heat dissipation property is improved in the nitride based compound semiconductor light emitting device. | 2009-01-29 |
20090026487 | LIGHT-EMITTING DEVICES HAVING AN ACTIVE REGION WITH ELECTRICAL CONTACTS COUPLED TO OPPOSING SURFACES THEREOF AND METHODS OF FORMING THE SAME - A light-emitting device includes a substrate having first and second opposing surfaces, an active region on the first surface of the substrate, a via in the substrate between the first and second opposing surfaces, a contact plug in the via, a first electrical contact on the active region, and a second electrical contact adjacent to the second surface that is coupled to the active region by the contact plug. The via and the first electrical contact are offset with respect to each other relative to an axis that is substantially perpendicular to the first and second surfaces of the substrate. | 2009-01-29 |
20090026488 | NITRIDE SEMICONDUCTOR MATERIAL AND PRODUCTION PROCESS OF NITRIDE SEMICONDUCTOR CRYSTAL - A nitride semiconductor material comprising a semiconductor or dielectric substrate having thereon a first nitride semiconductor layer group, wherein the surface of the first nitride semiconductor layer group has an RMS of 5 nm or less, a variation of X-ray half-width within ±30%, a light reflectance of the surface of 15% or more, and a variation thereof of ±10% or less, and the thickness of said first nitride semiconductor layer group is 25 μm or more. This nitride semiconductor material is excellent in uniformity and stability, assured of a low production cost, and useful as a substrate for a nitride semiconductor-type device. | 2009-01-29 |
20090026489 | SEMICONDUCTOR LIGHT EMITTING DEVICE - A semiconductor light emitting device has an active layer of a gallium nitride compound semiconductor material, a first semiconductor layer of In | 2009-01-29 |
20090026490 | LIGHT EMITTING DEVICE AND MANUFACTURING METHOD THEREOF - Provided is a light emitting device. The light emitting device comprises a second electrode layer, a second conduction type semiconductor layer, an active layer, a first conduction type semiconductor layer, a first electrode layer, and an insulating layer. The second conduction type semiconductor layer is formed on the second electrode layer. The active layer is formed on the second conduction type semiconductor layer. The first conduction type semiconductor layer is formed on the active layer. The first electrode layer is formed on the first conduction type semiconductor layer. The insulating layer is disposed between the second electrode layer and the second conduction type semiconductor layer. | 2009-01-29 |
20090026491 | TUNNELING EFFECT TRANSISTOR WITH SELF-ALIGNED GATE - In one embodiment, a mandrel and an outer dummy spacer may be employed to form a first conductivity type region. The mandrel is removed to form a recessed region wherein a second conductivity type region is formed. In another embodiment, a mandrel is removed from within shallow trench isolation to form a recessed region, in which an inner dummy spacer is formed. A first conductivity type region and a second conductivity region are formed within the remainder of the recessed region. An anneal is performed so that the first conductivity type region and the second conductivity type region abut each other by diffusion. A gate electrode is formed in self-alignment to the p-n junction between the first and second conductivity regions. The p-n junction controlled by the gate electrode, which may be sublithographic, constitutes an inventive tunneling effect transistor. | 2009-01-29 |
20090026492 | LATERAL JUNCTION BREAKDOWN TRIGGERED SILICON CONTROLLED RECTIFIER BASED ELECTROSTATIC DISCHARGE PROTECTION DEVICE - The components of a silicon controlled rectifier, which are a p-doped anode, an n-well middle region, a p-well middle region, and an n-doped cathode, are formed along sidewalls and a bottom surface of a shallow trench isolation structure. The p-doped anode and the n-doped cathode are formed directly underneath a top surface of a silicon substrate. A trigger mechanism that provides an instantaneous turn-on current to latch the silicon controlled rectifier to an on-state is also provided. The trigger mechanism provides a temporary surge in the voltage of the p-doped middle region, causing the instantaneous turn-on current to flow from the p-doped middle region to the n-doped cathode. Combined with the proximity of the p-doped anode to the n-doped cathode, the trigger mechanism provides a fast turn on and a short low resistance current path for the electrostatic discharge protection circuit. | 2009-01-29 |
20090026493 | Electrostatic Protection Circuit - An electrostatic protection circuit includes a thyristor that discharges an excess charge generated between a first power supply terminal and a second power supply terminal having a lower voltage than the first power supply terminal, a trigger device that supplies a current turning on the thyristor, and an electrostatic discharge element placed between the first power supply terminal and the second power supply terminal in parallel with thyristor and having a higher current supply capability than the trigger device at the same inter-power-terminal voltage, the electrostatic element changing to an on state in a time shorter than a turn-on time of the thyristor connected to the trigger device and at a voltage lower than a turn-on voltage of the thyristor. | 2009-01-29 |
20090026494 | Avalanche Photodiode Having Controlled Breakdown Voltage - Avalanche photodiodes and methods for forming them are disclosed. The breakdown voltage of an avalanche photodiode is controlled through the inclusion of a diffusion sink that is formed at the same time as the device region of the photodiode. The device region and diffusion sink are formed by diffusing a dopant into a semiconductor to form a p-n junction in the device region. The dopant is diffused through a first diffusion window to form the device region and a second diffusion window to form the diffusion sink. The depth of the p-n junction is based on an attribute of the second diffusion window. | 2009-01-29 |
20090026495 | LAYER TRANSFER OF LOW DEFECT SiGe USING AN ETCH-BACK PROCESS - A method for forming strained Si or SiGe on relaxed SiGe on insulator (SGOI) or a SiGe on Si heterostructure is described incorporating growing epitaxial Si | 2009-01-29 |
20090026496 | METHODS OF MAKING SUBSTITUTIONALLY CARBON-DOPED CRYSTALLINE SI-CONTAINING MATERIALS BY CHEMICAL VAPOR DEPOSITION - Methods of making Si-containing films that contain relatively high levels of substitutional dopants involve chemical vapor deposition using trisilane and a dopant precursor. Extremely high levels of substitutional incorporation may be obtained, including crystalline silicon films that contain 2.4 atomic % or greater substitutional carbon. Substitutionally doped Si-containing films may be selectively deposited onto the crystalline surfaces of mixed substrates by introducing an etchant gas during deposition. | 2009-01-29 |
20090026497 | Method for Producing Semiconductor Device - A method for producing a semiconductor device ( | 2009-01-29 |
20090026498 | FIELD EFFECT TRANSISTOR AND METHOD FOR FABRICATING THE SAME - A field effect transistor includes: a nitride semiconductor layer having a channel layer; a gate electrode including a Schottky electrode that contacts the nitride semiconductor layer and includes a gallium doped zinc oxide (GZO) layer annealed in an inactive gas atmosphere; and ohmic electrodes connecting with the channel layer. | 2009-01-29 |
20090026499 | SEMICONDUCTOR INTEGRATED CIRCUIT DEVICE AND SEMICONDUCTOR SWITCHING DEVICE USING THEREOF - A semiconductor integrated circuit device having a plurality of semiconductor electronic members including a field effect transistor, intended for suppressing a sidegating effect on the field effect transistor, wherein accumulation of majority carriers of the field effect transistor is suppressed at the interface of heterojunction in the buffering compound semiconductor layer and the interface between the substrate and the buffering compound semiconductor layer in the device isolation region so that the discontinuity of energy forbidden bands of the semiconductors caused at the interfaces does not form a potential barrier upon conduction of the carriers into the substrate, whereby the sidegating effect from the resistor element, etc. placed adjacently to the field effect transistor can be decreased drastically. | 2009-01-29 |
20090026500 | Semiconductor Device and Method of Manufacturing Such a Device - A semiconductor device includes a substrate of a first conductivity type, and a first semiconductor region that includes a plurality of sub-regions of the first conductivity type that have a first doping concentration and a further semiconductor region of a second conductivity type opposite to the first conductivity type. The further semiconductor region separates the sub-regions from each other and the first semiconductor region is located on the substrate. The semiconductor device further includes a second semiconductor region of the first conductivity type located on the first semiconductor region, a third semiconductor region of the second conductivity type located on the second semiconductor region, and a fourth semiconductor region of the first conductivity type located on the third semiconductor region. The sub regions extend from the second semiconductor region into the substrate, and the thickness and the doping concentration of the second and the third semiconductor region are such that these regions are completely depleted during operation of the device. | 2009-01-29 |
20090026501 | ENHANCEMENT - DEPLETION SEMICONDUCTOR STRUCTURE AND METHOD FOR MAKING IT - A ED-HEMT structure includes a buffer layer ( | 2009-01-29 |
20090026502 | VIA ANTENNA FIX IN DEEP SUB-MICRON CIRCUIT DESIGNS - A filler cell for use in fabricating an integrated circuit. The filler cell couples a power supply rail of an adjacent logic cell to a power supply rail of another adjacent logic cell. The filler cell also has a diode to bleed charge accumulated on the power rails of the adjacent logic cells to the substrate. The diode is reverse biased during normal integrated circuit operation. A method for fabricating an integrated circuit with a power grid. At least one filler cell is placed on the integrated circuit to bleed away charge accumulated on the power grid during the fabrication of the integrated circuit. The filler cell is connected to a supply rail of an adjacent logic cell. | 2009-01-29 |
20090026503 | SEMICONDUCTOR DEVICE - CMOS inverters are included in a standard cell. Power supply lines are electrically connected to CMOS inverters, and include lower layer interconnects and upper layer interconnect. Lower layer interconnects extend along a boundary of standard cells adjacent to each other and on the boundary. Upper layer interconnects are positioned more inside in standard cell than lower layer interconnects, as viewed from a plane. CMOS inverters are electrically connected through upper layer interconnects to lower layer interconnects. Thus, a semiconductor device is obtained that can achieve both higher speeds and higher integration. | 2009-01-29 |
20090026504 | Semiconductor Device and Method of Manufacturing Semiconductor Device - The present invention provides a semiconductor device and a method of manufacturing a semiconductor device in which a driving force can be increased by increasing a strain amount given by a stressed film in a MOS transistor including an elevated region. | 2009-01-29 |
20090026505 | SEMICONDUCTOR DEVICE AND METHOD OF FABRICATING THE SAME - A semiconductor device according to an embodiment includes: a semiconductor substrate; a fin formed on the semiconductor substrate; a gate electrode formed so as to sandwich both side faces of the fin between its opposite portions via a gate insulating film; an extension layer formed on a region of a side face of the fin, the region being on the both sides of the gate electrode, the extension layer having a plane faced to a surface of the semiconductor substrate at an acute angle; and a silicide layer formed on a surface of the plane faced to the surface of the semiconductor substrate at an acute angle. | 2009-01-29 |
20090026506 | SEMICONDUCTOR DEVICE - In the semiconductor device, a gate region is formed in a mesh pattern having first polygonal shapes and second polygonal shapes the area of which is smaller than that of the first polygonal shapes, and drain regions and source regions are disposed within the first polygonal shapes and the second polygonal shapes, respectively. With this configuration, the forward transfer admittance gm can be increased as compared with a structure in which gate regions are disposed in a stripe pattern. Furthermore, compared with a case in which a gate region is disposed in a grid pattern, deterioration in forward transfer characteristics (amplification characteristics) due to an increase in input capacitance Ciss can be minimized while a predetermined withstand voltage is maintained. | 2009-01-29 |
20090026507 | Semiconductor device and method of fabricating same - There are disclosed TFTs that have excellent characteristics and can be fabricated with a high yield. The TFTs are fabricated, using an active layer crystallized by making use of nickel. Gate electrodes are comprising tantalum. Phosphorus is introduced into source/drain regions. Then, a heat treatment is performed to getter nickel element in the active layer and to drive it into the source/drain regions. At the same time, the source/drain regions can be annealed out. The gate electrodes of tantalum can withstand this heat treatment. | 2009-01-29 |
20090026508 | Solid-state photosensor with electronic aperture control - The effective photosensitive area of a solid-state photosensor is controlled with a multitude of electrodes (E | 2009-01-29 |
20090026509 | PHOTOSENSOR - For a photosensor, an array substrate is provided, wherein the edge of a photodiode is enclosed by the opening edge of a contact hole formed on a drain electrode. | 2009-01-29 |
20090026510 | Image sensor and method for fabricating the same - An image sensor includes an epi-layer of a first conductivity type formed in a substrate, a photodiode formed in the epi-layer, and a first doping region of a second conductivity type formed under the photodiode to separate the first doping region from the photodiode. | 2009-01-29 |
20090026511 | Isolation process and structure for CMOS imagers - A barrier implanted region of a first conductivity type formed in lieu of an isolation region of a pixel sensor cell that provides physical and electrical isolation of photosensitive elements of adjacent pixel sensor cells of a CMOS imager. The barrier implanted region comprises a first region having a first width and a second region having a second width greater than the first width, the second region being located below the first region. The first region is laterally spaced from doped regions of a second conductivity type of adjacent photodiodes of pixel sensor cells of a CMOS imager. | 2009-01-29 |