04th week of 2016 patent applcation highlights part 57 |
Patent application number | Title | Published |
20160027423 | Encephalophone - A novel musical instrument was created using electroencephalogram (EEG) motor imagery to control a synthesized piano, and is herein named the Encephalophone. Alpha-frequency (8-12 Hz) signal power, originating from either posterior dominant rhythm (PDR) in the occipital cortex or from mu rhythm in the motor cortex, was used to create a power scale which was then converted into a musical scale which could be manipulated by the individual. Subjects could then generate different notes of the scale by activation (event-related synchronization) or de-activation (event-related desynchronization) of the PDR or mu rhythms in occipital or motor cortex, respectively. | 2016-01-28 |
20160027424 | ULTRASONIC WAVE GENERATION APPARATUS - An ultrasonic wave generation apparatus that includes an ultrasonic wave generation element having an inner space formed by bonding first and second vibrators so as to close off a through-hole or a groove provided in a frame body, and a connecting member that is bonded to the second vibrator supports the ultrasonic wave generation element and is electrically connected to at least one of the first and second vibrators. A ventilation hole that opens into a first side surface of the frame body and that allows the inner space to communicate with the exterior is provided in the frame body. When a direction parallel to the first main surface or the second main surface is a lengthwise direction, an outer side end portion of the ventilation hole in the lengthwise direction and an inner side end portion in the lengthwise direction of the connecting member do not match. | 2016-01-28 |
20160027425 | LATTICE STRUCTURES - A unit cell for a lattice structure includes eight unit trusses disposed at vertices of the unit cell. A single unit truss is disposed at a centroid of the unit cell. Each of the nine unit trusses includes fourteen struts. Lattice structures are commonly used to connect various loads within a volume of space. Most such structures, however, have a rigid definition for their topology, and are unable to conform to shape or load directions. Additionally, conventional lattice structures are homogeneous, having dimensions and properties that are consistent throughout. These constraints, generally imposed for ease of manufacturing and assembly, prevent the development of highly robust and efficient structures, and limit the potential for multi-functional applications. | 2016-01-28 |
20160027426 | SOUND DAMPING COMPOSITION - A sound damping material composition for use as a bake-on free layer cladding in automotive applications, in particular to dampen acoustic vibrations coming from 3D shaped metal body panels of vehicles, based on flaky mica filled bitumen is disclosed. | 2016-01-28 |
20160027427 | Sound Attenuating Structures - A sound attenuation panel is configured with a substantially acoustically transparent planar, rigid frame divided into a plurality of individual, substantially two-dimensional cells. A sheet of a flexible material is fixed to the rigid frame, and a plurality of platelets fixed to the sheet of flexible material such that each individual cell of the plurality of cells is provided with a respective platelet to establish a resonant frequency, the resonant frequency defined by the planar geometry of the individual cells, the flexibility of the flexible material and the platelets. The cells are divided into at least two different types of the individual cells, configured so that sound waves emitted by a first type of said different types of individual cells establishes a sound cancellation pattern with sound waves emitted by a second type of said different individual cells or an aggregation of different types of the individual cells. | 2016-01-28 |
20160027428 | NOISE CANCELLATION SYSTEM - Active noise cancellation may be provided by a variety of systems, methods and techniques. General aspects, for example, include an active noise cancellation system, a controller for an active noise cancellation system, and/or a method of generating an anti-noise signal. In one example aspect, an active noise cancellation system for an aircraft In-flight entertainment system may include at least one input device, a processing means, and an output. The input device may be associated with a seat on the aircraft and adapted to receive an input representative of an ambient noise in the vicinity of the seat. The processing means may be adapted to process the input to produce an output signal adapted to reduce the ambient noise in volume associated with the seat. The output may be adapted to transmit an output signal to at least one driver, which is adapted to transmit the output signal to a user. | 2016-01-28 |
20160027429 | Integrated Acoustic Phase Array - A system includes a processor and a phased array, coupled to the processor, having an arrayed waveguide for acoustic waves to enable directional sound communication. | 2016-01-28 |
20160027430 | METHOD FOR FORMING THE EXCITATION SIGNAL FOR A GLOTTAL PULSE MODEL BASED PARAMETRIC SPEECH SYNTHESIS SYSTEM - A system and method are presented for forming the excitation signal for a glottal pulse model based parametric speech synthesis system. The excitation signal may be formed by using a plurality of sub-band templates instead of a single one. The plurality of sub-band templates may be combined to form the excitation signal wherein the proportion in which the templates are added is dynamically based on determined energy coefficients. These coefficients vary from frame to frame and are learned, along with the spectral parameters, during feature training. The coefficients are appended to the feature vector, which comprises spectral parameters and is modeled using HMMs, and the excitation signal is determined. | 2016-01-28 |
20160027431 | SYSTEMS AND METHODS FOR MULTIPLE VOICE DOCUMENT NARRATION - Disclosed are techniques and systems to provide a narration of a text in multiple different voices. In some aspects, systems and methods described herein can include receiving a user-based selection of a first portion of words in a document where the document has a pre-associated first voice model and overwriting the association of the first voice model, by the one or more computers, with a second voice model for the first portion of words. | 2016-01-28 |
20160027432 | Speaker Dependent Voiced Sound Pattern Template Mapping - Various implementations disclosed herein include a training module configured to produce a set of segment templates from a concurrent segmentation of a plurality of vocalization instances of a VSP vocalized by a particular speaker, who is identifiable by a corresponding set of vocal characteristics. Each segment template provides a stochastic characterization of how each of one or more portions of a VSP is vocalized by the particular speaker in accordance with the corresponding set of vocal characteristics. Additionally, in various implementations, the training module includes systems, methods and/or devices configured to produce a set of VSP segment maps that each provide a quantitative characterization of how respective segments of the plurality of vocalization instances vary in relation to a corresponding one of a set of segment templates. | 2016-01-28 |
20160027433 | METHOD OF SELECTING TRAINING TEXT FOR LANGUAGE MODEL, AND METHOD OF TRAINING LANGUAGE MODEL USING THE TRAINING TEXT, AND COMPUTER AND COMPUTER PROGRAM FOR EXECUTING THE METHODS - Method of selecting training text for language model, and method of training language model using the training text, and computer and computer program for executing the methods. The present invention provides for selecting training text for a language model that includes: generating a template for selecting training text from a corpus in a first domain according to generation techniques of: (i) replacing one or more words in a word string selected from the corpus in the first domain with a special symbol representing any word or word string, and adopting the word string after replacement as a template for selecting the training text; and/or (ii) adopting the word string selected from the corpus in the first domain as the template for selecting the training text; and selecting text covered by the template as the training text from a corpus in a second domain different from the first domain. | 2016-01-28 |
20160027434 | UNSUPERVISED AND ACTIVE LEARNING IN AUTOMATIC SPEECH RECOGNITION FOR CALL CLASSIFICATION - Utterance data that includes at least a small amount of manually transcribed data is provided. Automatic speech recognition is performed on ones of the utterance data not having a corresponding manual transcription to produce automatically transcribed utterances. A model is trained using all of the manually transcribed data and the automatically transcribed utterances. A predetermined number of utterances not having a corresponding manual transcription are intelligently selected and manually transcribed. Ones of the automatically transcribed data as well as ones having a corresponding manual transcription are labeled. In another aspect of the invention, audio data is mined from at least one source, and a language model is trained for call classification from the mined audio data to produce a language model. | 2016-01-28 |
20160027435 | METHOD FOR TRAINING AN AUTOMATIC SPEECH RECOGNITION SYSTEM - A system and method for speech recognition is provided. Embodiments may include receiving, at a first computing device, a far-talk signal from a far-talk computing device, the far-talk signal transmitted using a first channel and corresponding to an audible sound. Embodiments may further include receiving, at the first computing device, a near-talk signal from a near-talk computing device, the near-talk signal transmitted using a second channel and corresponding to the audible sound, wherein the far-talk signal and the near-talk signal are received during an enrollment phase of a far-talk speech recognition system. Embodiments may also include updating, at the first computing device, one or more models associated with a far-talk speech recognition system based upon, at least in part, one or more characteristics of the far-talk signal and one or more characteristics of the near-talk signal. | 2016-01-28 |
20160027436 | SPEECH RECOGNITION DEVICE, VEHICLE HAVING THE SAME, AND SPEECH RECOGNITION METHOD - A speech recognition device is configured to increase usability by retrying speech recognition without returning to a previous operation or a re-input of speech when a user's speech is misrecognized. The speech recognition device is further configured increase accuracy of recognition by changing a search environment when the user's speech is misrecognized or when re-recognition is performed since the recognized speech is rejected due to a low confidence. A vehicle includes a speech input device configured to receive speech; and a speech recognition device configured to recognize the received speech and output a recognition result of the received speech. The speech recognition device resets a recognition environment applied to speech recognition and re-recognizes the received speech when a re-recognition instruction is input by a user, and resets the reset recognition environment to an initial value when the re-recognition is completed. | 2016-01-28 |
20160027437 | METHOD AND APPARATUS FOR SPEECH RECOGNITION AND GENERATION OF SPEECH RECOGNITION ENGINE - A method and apparatus for speech recognition and for generation of speech recognition engine, and a speech recognition engine are provided. The method of speech recognition involves receiving a speech input, transmitting the speech input to a speech recognition engine, and receiving a speech recognition result from the speech recognition engine, in which the speech recognition engine obtains a phoneme sequence from the speech input and provides the speech recognition result based on a phonetic distance of the phoneme sequence. | 2016-01-28 |
20160027438 | Concurrent Segmentation of Multiple Similar Vocalizations - Various implementations disclosed herein include a training module configured to concurrently segment a plurality of vocalization instances of a voiced sound pattern (VSP) as vocalized by a particular speaker, who is identifiable by a corresponding set of vocal characteristics. Aspects of various implementations are used to determine a concurrent segmentation of multiple similar instances of a VSP using a modified hierarchical agglomerative clustering (HAC) process adapted to jointly and simultaneously segment multiple similar instances of the VSP. Information produced from multiple instances of a VSP vocalized by a particular speaker characterize how the particular speaker vocalizes the VSP and how those vocalizations may vary between instances. In turn, in some implementations, the information produced using the modified HAC process is sufficient to determine more a reliable detection (and/or matching) threshold metric(s) for detecting and matching the VSP as vocalized by the particular speaker. | 2016-01-28 |
20160027439 | PROVIDING PRE-COMPUTED HOTWORD MODELS - Methods, systems, and apparatus, including computer programs encoded on a computer storage medium, for obtaining, for each of multiple words or sub-words, audio data corresponding to multiple users speaking the word or sub-word; training, for each of the multiple words or sub-words, a pre-computed hotword model for the word or sub-word based on the audio data for the word or sub-word; receiving a candidate hotword from a computing device; identifying one or more pre-computed hotword models that correspond to the candidate hotword; and providing the identified, pre-computed hotword models to the computing device. | 2016-01-28 |
20160027440 | SELECTIVE SPEECH RECOGNITION FOR CHAT AND DIGITAL PERSONAL ASSISTANT SYSTEMS - Disclosed are computer-implemented methods and systems for dynamic selection of speech recognition systems for the use in Chat Information Systems (CIS) based on multiple criteria and context of human-machine interaction. Specifically, once a first user audio input is received, it is analyzed so as to locate specific triggers, determine the context of the interaction or predict the subsequent user audio inputs. Based on at least one of these criteria, one of a free-diction recognizer, pattern-based recognizer, address book based recognizer or dynamically created recognizer is selected for recognizing the subsequent user audio input. The methods described herein increase the accuracy of automatic recognition of user voice commands, thereby enhancing overall user experience of using CIS, chat agents and similar digital personal assistant systems. | 2016-01-28 |
20160027441 | SPEECH RECOGNITION SYSTEM, SPEECH RECOGNIZING DEVICE AND METHOD FOR SPEECH RECOGNITION - A speech recognition system is to be used on a human subject. The speech recognition system includes an image capturing device, an oral cavity detecting device and a speech recognition device. The image capturing device captures images of lips of the subject during a speech of the subject. The oral cavity detecting device detects contact with a tongue of the subject and distance from the tongue of the subject, and accordingly generates a contact signal and a distance signal. The speech recognition device processes the images of the lips and the contact and distance signals so as to obtain content of the speech of the subject. | 2016-01-28 |
20160027442 | SUMMARIZATION OF AUDIO DATA - Aspects of the present invention disclose a method, computer program product, a service, and a system for generating a summary of audio on one or more computing devices. The method includes one or more processors retrieving an audio recording. The method further includes one or more processors identifying supplemental information associated with the audio recording, wherein the supplemental information includes information associated with content in the audio recording and information associated with one or more speakers of the audio recording. The method further includes one or more processors converting the audio recording to a transcript of the audio recording. The method further includes one or more processors generating a summary of the transcript of the audio recording based at least in part on the identified supplemental information. | 2016-01-28 |
20160027443 | CONTINUOUS SPEECH TRANSCRIPTION PERFORMANCE INDICATION - A method of providing speech transcription performance indication includes receiving, at a user device data representing text transcribed from an audio stream by an ASR system, and data representing a metric associated with the audio stream; displaying, via the user device, said text; and via the user device, providing, in user-perceptible form, an indicator of said metric. Another method includes displaying, by a user device, text transcribed from an audio stream by an ASR system; and via the user device, providing, in user-perceptible form, an indicator of a level of background noise of the audio stream. Another method includes receiving data representing an audio stream; converting said data representing an audio stream to text via an ASR system; determining a metric associated with the audio stream; transmitting data representing said text to a user device; and transmitting data representing said metric to the user device. | 2016-01-28 |
20160027444 | METHOD AND APPARATUS FOR DETECTING SPLICING ATTACKS ON A SPEAKER VERIFICATION SYSTEM - A method of detecting an occurrence of splicing in a speech signal includes comparing one or more discontinuities in the test speech signal to one or more reference speech signals corresponding to the test speech signal. The method may further include calculating a frame-based spectral-like representation S | 2016-01-28 |
20160027445 | STEREO AUDIO SIGNAL ENCODER - An apparatus comprising a mapper configured to map an instance of a parameter according to a first mapping to generate a first mapped instance; a remapper configured to remap the first mapped instance dependent on the frequency distribution of mapped instances to generate a remapped instance with an associated order position; and an encoder configured to encode the remapped instance dependent on an order position of the remapped instance. | 2016-01-28 |
20160027446 | Stereo Audio Encoder and Decoder - The present disclosure provides methods, devices and computer program products for encoding and decoding a stereo audio signal based on an input signal. According to the disclosure, a hybrid approach of using both parametric stereo coding and a discrete representation of the stereo audio signal is used which may improve the quality of the encoded and decoded audio for certain bitrates. | 2016-01-28 |
20160027447 | SPATIAL COMFORT NOISE - A method, an apparatus, logic (e.g., executable instructions encoded in a non-transitory computer-readable medium to carry out a method), and a non-transitory computer-readable medium configured with such instructions. The method is to generate and spatially render spatial comfort noise at a receiving endpoint of a conference system, such that the comfort noise has target spectral characteristics typical of comfort noise, and at least one spatial property that at least substantially matches at least one target spatial property. On version includes receiving one or more or more audio signals from other endpoints, combining the received audio signals with the spatial comfort noise signals, and rendering the combination of the received audio signals and the spatial comfort noise signals to a set of output signals for loudspeakers, such that the spatial comfort noise signals are continually in the output signal sin addition to output from the received audio signals. | 2016-01-28 |
20160027448 | LOW-COMPLEXITY TONALITY-ADAPTIVE AUDIO SIGNAL QUANTIZATION - The invention provides an audio encoder for encoding an audio signal so as to produce therefrom an encoded signal, the audio encoder including: a framing device configured to extract frames from the audio signal; a quantizer configured to map spectral lines of a spectrum signal derived from the frame of the audio signal to quantization indices, wherein the quantizer has a dead-zone, in which the input spectral lines are mapped to quantization index zero; and a control device configured to modify the dead-zone; wherein the control device includes a tonality calculating device configured to calculate at least one tonality indicating value for at least one spectrum line or for at least one group of spectral lines, wherein the control device is configured to modify the dead-zone for the at least one spectrum line or the at least one group of spectrum lines depending on the respective tonality indicating value. | 2016-01-28 |
20160027449 | PYRAMID VECTOR QUANTIZER SHAPE SEARCH - An encoder and a method therein for Pyramid Vector Quantizer, PVQ, shape search, the PVQ taking a target vector x as input and deriving a vector y by iteratively adding unit pulses in an inner dimension search loop. The method comprises, before entering a next inner dimension search loop for unit pulse addition, determining, based on the maximum pulse amplitude, maxamp | 2016-01-28 |
20160027450 | Classification Between Time-Domain Coding and Frequency Domain Coding - A method for processing speech signals prior to encoding a digital signal comprising audio data includes selecting frequency domain coding or time domain coding based on a coding bit rate to be used for coding the digital signal and a short pitch lag detection of the digital signal. | 2016-01-28 |
20160027451 | System and Method for Providing Noise Suppression Utilizing Null Processing Noise Subtraction - Systems and methods for noise suppression using noise subtraction processing are provided. The noise subtraction processing comprises receiving at least a primary and a secondary acoustic signal. A desired signal component may be calculated and subtracted from the secondary acoustic signal to obtain a noise component signal. A determination may be made of a reference energy ratio and a prediction energy ratio. A determination may be made as to whether to adjust the noise component signal based partially on the reference energy ratio and partially on the prediction energy ratio. The noise component signal may be adjusted or frozen based on the determination. The noise component signal may then be removed from the primary acoustic signal to generate a noise subtracted signal which may be outputted. | 2016-01-28 |
20160027452 | EMOTIONAL SPEECH PROCESSING - A method for emotion or speaking style recognition and/or clustering comprises receiving one or more speech samples, generating a set of training data by extracting one or more acoustic features from every frame of the one or more speech samples, and generating a model from the set of training data, wherein the model identifies emotion or speaking style dependent information in the set of training data. The method may further comprise receiving one or more test speech samples, generating a set of test data by extracting one or more acoustic features from every frame of the one or more test speeches, and transforming the set of test data using the model to better represent emotion/speaking style dependent information, and use the transformed data for clustering and/or classification to discover speech with similar emotion or speaking style. It is emphasized that this abstract is provided to comply with the rules requiring an abstract that will allow a searcher or other reader to quickly ascertain the subject matter of the technical disclosure. It is submitted with the understanding that it will not be used to interpret or limit the scope or meaning of the claims. | 2016-01-28 |
20160027453 | SURFACE FORMING METHOD FOR ELECTRONIC COMPONENT - A surface forming method for electronic component includes: forming a body that has at least one waveguide, with two ends of the waveguide exposed on a front end surface and a back end surface of the body; forming a photoresist film to cover on the front end surface of the body; irradiating a light from the back end surface of the body to remove a part, of the photoresist film, that covers at least a part of an end surface of the waveguide, thereby forming an exposed area on the end surface of the waveguide; etching the exposed area of the waveguide to form a recess; and removing the photoresist film. The position and size of the pattern could be controlled accurately and efficiently, instead of inefficient complex procedures of alignment. | 2016-01-28 |
20160027454 | MAGNETIC MEDIA ACCESS HEAD WITH METAL COATING - Embodiments disclosed herein provide magnetic media access heads with metal coatings. In a particular embodiment, a magnetic media head for accessing magnetic media comprises a base substrate configured to support a magnetic head layer. The magnetic head layer is formed on the base substrate and configured to magnetically access the magnetic media. A metallic layer formed over the magnetic head layer and disposed between the magnetic head layer and the magnetic media when the magnetic media is positioned for access by the magnetic head layer. | 2016-01-28 |
20160027455 | MAGNETIC RECORDING HEAD AND MAGNETIC RECORDING APPARATUS - According to an embodiment, a magnetic recording head includes a main magnetic pole and a spin torque oscillator. The spin torque oscillator includes a first perpendicular free layer, a second perpendicular free layer, and a first spacer layer, each of the first perpendicular free layer and the second perpendicular free layer including a magnetic anisotropy axis in a direction perpendicular to a film plane of the spin torque oscillator. An effective perpendicular magnetic anisotropy magnetic field of the first perpendicular free layer is smaller than an effective perpendicular magnetic anisotropy magnetic field of the second perpendicular free layer, and a current is applied from the first perpendicular free layer side to the second perpendicular free layer side. | 2016-01-28 |
20160027456 | Data Storage Device with Phase Lock Spin-Torque Oscillation Stabilization - A data storage device can be configured at least with a first spin-torque oscillator disposed between and contacting a write pole and a shield on an air bearing surface. A second spin-torque oscillator can be disposed between and contact the write pole and shield with the second spin-torque oscillator separated from the air bearing surface by a first stabilization distance and from the first spin-torque oscillator by a second stabilization distance. The first and second spin-torque oscillators can be configured to magnetostatically couple and phase lock to produce a single microwave frequency in response to a bias field. | 2016-01-28 |
20160027457 | MAGNETORESISTANCE EFFECT ELEMENT, MAGNETIC HEAD, MAGNETIC HEAD ASSEMBLY, MAGNETIC RECORDING AND REPRODUCING DEVICE, AND METHOD FOR MANUFACTURING MAGNETORESISTANCE EFFECT ELEMENT - According to one embodiment, a magnetoresistance effect element includes first and second shields, first and second side magnetic units, a stacked body, and a hard bias unit. The first side magnetic unit includes a first soft magnetic layer, a first nonmagnetic intermediate layer, and a second soft magnetic layer. The second side magnetic unit includes a third soft magnetic layer, a second nonmagnetic intermediate layer, and a fourth soft magnetic layer. The stacked body includes a fifth ferromagnetic layer, a third nonmagnetic intermediate layer, and a sixth ferromagnetic layer. The hard bias unit is provided between the first and second shields. A first distance between the first and fifth magnetic layers is shorter than a second distance between the second and sixth magnetic layers. A third distance between the third and fifth magnetic layers is shorter than a fourth distance between the fourth and sixth magnetic layers. | 2016-01-28 |
20160027458 | CONFINEMENT MAGNETIC CAP - Embodiments disclosed herein generally relate to a TMR sensor for reading a recording from a magnetic recording medium using TMR, and in particular, to a magnetic capping structure of the TMR sensor. The sensor comprises a free layer and a magnetic capping structure. The magnetic capping structure comprises a ferromagnetic capping layer and an absorption layer formed on the ferromagnetic capping layer. The absorption layer is adapted to absorb molecules from the ferromagnetic capping layer and prevent the ferromagnetic capping layer from diffusing into the free layer. | 2016-01-28 |
20160027459 | SLIDER WITH HIGH FREQUENCY VOLTAGE GROUND AND LOW FREQUENCY DC VOLTAGE ISOLATION - In one embodiment, a slider includes a substrate, a magnetic head, and a coupling capacitor. In one embodiment, a slider includes a substrate, a magnetic head, and a coupling capacitor configured to AC couple an electronics ground of the slider to the substrate and DC decouple the electronics ground of the slider from the substrate, the coupling capacitor including: a first conductive layer, a gap layer positioned above the first conductive layer, a dielectric layer positioned above the gap layer and the first conductive layer, and a second conductive layer positioned above the dielectric layer. In another embodiment, a method for forming a capacitor includes forming a substrate, forming a first conductive layer above the substrate, forming a gap layer above the first conductive layer, forming a dielectric layer above the gap layer and the first conductive layer, and forming a second conductive layer above the dielectric layer. | 2016-01-28 |
20160027460 | CONDUCTIVE POLYMERS FOR USE IN MAGNETIC MEDIA - According to one embodiment, a magnetic recording medium includes a substrate, an underlayer positioned above the substrate, a magnetic recording layer positioned above the underlayer, and a plurality of conductive polymers dispersed within at least one of the substrate, the underlayer and the magnetic recording layer. | 2016-01-28 |
20160027461 | METHOD FOR FORMING PARTICLE LAYER AND METHOD FOR MANUFACTURING MAGNETIC RECORDING MEDIUM - A method for forming a particle layer includes covering surfaces of particles with a first polymer, covering a surface of a substrate with a second polymer having a same skeletal structure as the first polymer, and applying a liquid in which the particles covered with the first polymer are dispersed, onto the surface of the substrate covered with the second polymer. | 2016-01-28 |
20160027462 | MAGNETIC RECORDING MEDIUM MANUFACTURING METHOD - According to one embodiment, there is provided a magnetic recording medium manufacturing method including forming a bonding layer on a substrate, forming a holding layer containing silicon on the bonding layer, forming a single-particle layer on the holding layer using particles containing metal fusible on the bonding layer, etching SiO | 2016-01-28 |
20160027463 | Servo Processor Receiving Photodetector Signals - A digital servo method for an optical disk drive includes receiving low-pass filtered and gain-adjusted versions of photodetector output signals resulting from an illumination of an optical disk. Versions of the photodetector signals are digitized to produce digital signals. A focus control signal is determined through at least one servo algorithm in a digital signal processor based on a focus error determined from the digital signals. Alternatively, a tracking control signal is determined through at least one servo algorithm in the digital signal processor based on a tracking error determined from the digital signals. An optical disk drive includes an analog-to-digital converter configured to convert low-pass filtered and gain-adjusted versions of photodetector output signals into at least one digital signal and the digital signal processor. | 2016-01-28 |
20160027464 | RECORDING MEDIUM CHANGER AND CONTROL METHOD - A conveying block | 2016-01-28 |
20160027465 | GATE STRUCTURE AND ELECTRONIC DEVICE USING THE SAME - An electronic and a gate structure including a first door-leaf, a second door-leaf, and a latch are provided. The first door-leaf having three first locking portions is movably assembled to an entrance of an object. The second door-leaf having two second locking portions is movably disposed at the first door-leaf, such that the first door-leaf closes or opens the entrance. The latch having a third locking portion and a fourth locking portion is movably disposed on the first door-leaf and between the first and the second door-leaves. The first locking portions are located on a moving path of the third locking portion. The second door-leaf is locked to the object and the third locking portion is located at the middle one of the three first locking portions, the fourth locking portion is blocked with one second locking portion and the first door-leaf covers the entrance. | 2016-01-28 |
20160027466 | Systems and Methods for a Recorder User Interface - An incident recorder records original and supplemental incident information using a simplified user interface. | 2016-01-28 |
20160027467 | ROOM MONITORING DEVICE WITH CONTROLLED RECORDING - A system monitors a person in a dwelling. A detection device is in communication with the user monitoring device. The detection device includes at least one motion/movement gesture sensing device configured to detect at least one of a person's motion, movement and gesture. A user monitoring device includes at least two elements selected from: a proximity sensor; a temperature sensor/humidity sensor; a particulate sensor; a light sensor; a microphone; a speaker; two RF transmitters (BLE/ANT+WIFI); a memory card; and LED's. Recording of a sound of a person's motion, movement and gesture is not always preserved. | 2016-01-28 |
20160027468 | CHANNEL BITWORD PROSESSOR, PRML DECODER, AND OPTICAL INFORMATION RECORDING/REPRODUCING DEVICE - It is an objective of the present invention to provide a technique to balance DSV in channel bit word when using fixed-length run length limited code based on enumeration. A channel bit word processor according to the present invention: evaluates DSV of a channel bit word in NRZI format which is generated on the basis of enumeration; and selects a connection word which causes a minimum absolute value of DSV after connecting a plurality of channel bit words (refer to FIG. | 2016-01-28 |
20160027469 | MAGNETIC DISK APPARATUS, CONTROLLER AND DATA PROCESSING METHOD - According to one embodiment, a magnetic disk apparatus includes an RW channel with an internal memory for processing data to be read/written from/to a magnetic disk, a transfer controller for controlling data transfer between a host apparatus and the RW channel, and a processor for controlling the RW channel and transfer controller. The processor reads, from the magnetic disk, predetermined area data including to-be-rewritten data, subjects the read predetermined area data to error correction processing in the RW channel, and stores resultant data in the internal memory. The processor rewrites, with rewrite data from the host apparatus, the to-be-rewritten data of the predetermined area data stored in the internal memory to update the predetermined area data, adds an error correction code to the updated data in the RW channel module, and writes resultant data to the magnetic disk. | 2016-01-28 |
20160027470 | SCENE AND ACTIVITY IDENTIFICATION IN VIDEO SUMMARY GENERATION - Video and corresponding metadata is accessed. Events of interest within the video are identified based on the corresponding metadata, and best scenes are identified based on the identified events of interest. A video summary can be generated including one or more of the identified best scenes. The video summary can be generated using a video summary template with slots corresponding to video clips selected from among sets of candidate video clips. Best scenes can also be identified by receiving an indication of an event of interest within video from a user during the capture of the video. Metadata patterns representing activities identified within video clips can be identified within other videos, which can subsequently be associated with the identified activities. | 2016-01-28 |
20160027471 | SYSTEMS AND METHODS FOR CREATING, EDITING AND PUBLISHING RECORDED VIDEOS - Systems and methods for creating, editing and publishing recorded videos based on user selected edit points are described herein. The present invention transforms a recorded video and user selected edit points into a customized presentable video. A video editing tool analyzes a recorded video and flags occurrences of user selected edit points. The video editing tool then creates a customized video that can include video portions based on user selected edit points. The video can also include flags for a user to jump from edit point to edit point. | 2016-01-28 |
20160027472 | LOW BANDWIDTH CONSUMPTION ONLINE CONTENT EDITING - Various embodiments of the invention provide systems and methods for low bandwidth consumption online content editing, where user-created content comprising high definition/quality content is created or modified at an online content editing server according to instructions from an online content editor client, and where a proxy version of the resulting user-created content is provided to online content editor client to facilitate review or further editing of the user-created content from the online content editor client. In some embodiments, the online content editing server utilizes proxy content during creation and modification operations on the user-created content, and replaces such proxy content with corresponding higher definition/quality content, possibly when the user-created content is published for consumption, or when the user has paid for the higher quality content. | 2016-01-28 |
20160027473 | METHOD AND APPARATUS FOR CREATING A CUSTOM TRACK - A method and system for creating and editing video and/or audio tracks is described. The method includes providing at least one artist, venue, and track available for selection and providing at least one clip associated with the at least one artist, venue, and track. The method also includes allowing a user to create a custom track from the at least one clip. The system includes a plurality of video cameras for recording a live performance at a plurality of positions. The system also includes at least one server for storing a plurality of video clips created from the plurality of video cameras and an application stored on the at least one server for allowing a user to access the plurality of video clips via the Internet. | 2016-01-28 |
20160027474 | Systems and Methods of Detecting Significant Faces in Video Streams - Systems and methods of processing video streams are described. A face is detected in a video stream. The face is tracked to determine a video clip associated with one of a plurality of individuals. The video segment is assigned to a group of video clips based on the associated individual. A significant face is detected in the group of video clips when the detected face meets one or more significance criteria. The significance criteria describes a face-frame characteristic. A representation of the significant face is displayed in association with a representation of the group of video clips. The order of the significance criteria is adjusted through a user interface. | 2016-01-28 |
20160027475 | VIDEO SCENE CLASSIFICATION BY ACTIVITY - Video and corresponding metadata is accessed. Events of interest within the video are identified based on the corresponding metadata, and best scenes are identified based on the identified events of interest. A video summary can be generated including one or more of the identified best scenes. The video summary can be generated using a video summary template with slots corresponding to video clips selected from among sets of candidate video clips. Best scenes can also be identified by receiving an indication of an event of interest within video from a user during the capture of the video. Metadata patterns representing activities identified within video clips can be identified within other videos, which can subsequently be associated with the identified activities. | 2016-01-28 |
20160027476 | DIGITAL IMAGE PROCESSING APPARATUS AND METHOD OF CONTROLLING THE SAME - A digital image processing apparatus and a method of controlling the same. The digital image processing apparatus includes: a display controller for displaying first content on a display unit; and an image generator for generating second content based on a photographing signal input, which may be from a user, and third content related to the second content. | 2016-01-28 |
20160027477 | INTERLEAVED GROUPED WORD LINES FOR THREE DIMESIONAL NON-VOLATILE STORAGE - A three dimensional non-volatile storage system includes a substrate and a plurality of memory cells arranged in a monolithic three dimensional memory array (or other 3D structure) positioned above and not in the substrate. The system includes a plurality of vertical bit lines and a plurality of word lines. Each group of three neighboring word lines on a common level of the three dimensional memory array are electrically isolated from each other and at least a subset of the three neighboring word lines of each group are connected to other word lines. | 2016-01-28 |
20160027478 | STACK BANK TYPE SEMICONDUCTOR MEMORY APPARATUS CAPABLE OF IMPROVING ALIGNMENT MARGIN - A semiconductor memory apparatus is capable of improving the alignment margin for a bank and sufficiently ensuring a space for forming a global input/output line. The semiconductor memory apparatus includes a stack bank structure having at least two sub-banks continuously stacked without disconnection of data signal lines, and a control block arranged at one side of the stack bank structure to simultaneously control column-related signals of the sub-banks. | 2016-01-28 |
20160027479 | SEMICONDUCTOR MEMORY - Semiconductor memories are provided. The Semiconductor memory includes a plurality of sense amplifiers, plurality sets of master data line segments and a plurality of memory segments. The plurality sets of master data line segments are arranged in a column direction. Each memory segment includes a plurality of memory cells, and is coupled to a set of corresponding master data line segments via a corresponding sense amplifier. Adjacent sets of corresponding master data line segments are coupled together. When accessing memory data, the memory data are transferred by the adjacent sets of corresponding master data line segments which are coupled together. | 2016-01-28 |
20160027480 | Hardware-Accelerated Dynamic Voltage And Frequency Scaling - One or more values associated with a first configuration setting for a first circuit may be stored in a first set of one or more registers when an operation of the first circuit is based at least in part on one or more values associated with a second configuration setting stored in a second set of one or more registers. In response to receiving an indication of a change in an operating frequency or voltage of the first circuit, the one or more values stored in the second set of one or more registers may be changed by loading the one or more values associated with the first configuration setting stored in the first set of one or more registers into the second set of one or more registers in a parallel fashion. | 2016-01-28 |
20160027481 | STORAGE DEVICE AND OPERATING METHOD OF STORAGE DEVICE - The method of operating a storage device includes receiving a command, an address, and data, and comparing data previously stored at a storage space of the nonvolatile memory corresponding to the address with the received data in response to the command. The method includes writing the received data at a nonvolatile memory when the previously stored data is different from the received data. Writing of the received data is terminated when the previously stored data is equal to the received data. | 2016-01-28 |
20160027482 | Communication Interface Architecture Using Serializer/Deserializer - A memory interface architecture uses a serializer/deserializer (SerDes) to connect a memory array on one semiconductor die to a device on another semiconductor die, for example via a fast interposer. | 2016-01-28 |
20160027483 | SEMICONDUCTOR INTEGRATED CIRCUIT - A semiconductor integrated circuit may include: a memory block partitioned into a first region and a second region; a data latch unit configured to latch data outputted from the memory block in response to a control signal; and a control circuit configured to generate a source signal separated into an odd order and an even order in response to a column access signal consecutively inputted to access the first region or the second region, and to generate the control signal in response to the source signal. | 2016-01-28 |
20160027484 | DATA TRANSFER CIRCUIT AND DATA TRANSFER METHOD - A data transfer circuit includes: a first power domain; a nonvolatile memory configured to store first data; a holding circuit; a readout circuit configured to read the first data from the nonvolatile memory and write the first data into the holding circuit at a time of chip reset; and a first controller configured to transfer the first data written into the holding circuit to the first power domain and make the holding circuit keep the first data at the time of chip reset, wherein the readout circuit, at a time of reset of the first power domain after the chip reset, does not read the first data from the nonvolatile memory, and the first controller transfers the first data held in the holding circuit to the first power domain. | 2016-01-28 |
20160027485 | MEMORY DEVICES, MEMORY SYSTEMS, AND RELATED OPERATING METHODS - A method of operating a memory system including memory cells commonly connected to a first signal line in a memory cell array includes; dividing the memory cells according to cell regions, and independently performing read operations on memory cells disposed in each cell region using a read reference selected from a plurality of read references and respectively corresponding to each cell region. | 2016-01-28 |
20160027486 | APPARATUSES AND METHODS FOR PROVIDING STROBE SIGNALS TO MEMORIES - Apparatuses and methods for providing strobe signals to memories are described herein. An example apparatus may include a plurality of memories and a memory controller. The memory controller may be coupled to the plurality of memories and configured to receive an input clock signal. The memory controller may further be configured to provide a timing strobe signal having a delay relative to the input clock signal to a memory of the plurality of memories. The memory controller may further be configured to receive a return strobe signal from the plurality of memories. In some examples, the return strobe signal may be based at least in part on the timing strobe signal and the memory controller may be configured to adjust the delay based, at least in part, on a phase difference of the input clock signal and the return strobe signal. | 2016-01-28 |
20160027487 | SEMICONDUCTOR MEMORY APPARATUS - A semiconductor memory apparatus includes a bank; a temperature sensor configured to generate a temperature voltage of which voltage level is changed according to a temperature variation of the bank; and a timing control block configured to control a timing of a signal to be inputted to the bank, according to the voltage level of the temperature voltage. | 2016-01-28 |
20160027488 | RESISTIVE MEMORY DEVICE, MEMORY SYSTEM INCLUDING THE SAME AND METHOD OF READING DATA FROM THE SAME - A resistive memory device may include first and second resistive memory cells, a reference current generator, and first and second bitline sense amplifiers. The reference current generator may be configured to apply the first and second reference currents to a first common node. A total reference current of the first reference current and the second reference current provided to the first common node may be divided into a first sensing current and a second sensing current by the first common node. The first and second sensing currents may be provided to the first and second bitline sense amplifiers by the first common node, respectively. The first and second bitline sense amplifiers may be configured to sense first data of the first resistive memory cell and second data of the second resistive memory cell based on the first and second sensing currents, respectively. | 2016-01-28 |
20160027489 | HYBRID READ SCHEME FOR SPIN TORQUE MRAM - A method of reading data from a plurality of bits in a spin-torque magnetoresistive memory array includes performing one or more referenced read operations of the bits, and performing a self-referenced read operation, for example, a destructive self-referenced read operation, of any of the bits not successfully read by the referenced read operation. The referenced read operations can be initiated at the same time or prior to that of the destructive self-referenced read operation. | 2016-01-28 |
20160027490 | CHARGE STORAGE FERROELECTRIC MEMORY HYBRID AND ERASE SCHEME - A technique for erasing a ferroelectric field effect transistor (FeFET) memory circuit comprising a plurality memory cells comprising FeFETs is described. Each FeFET comprises a gate stack, a source, a drain, a channel and a bulk substrate region, where the gate stack comprises a gate and a ferroelectric layer disposed between the gate and the channel. A positive or a negative voltage is applied to the source and drain regions of at least one FeFET memory cell depending on the channel type. The gate and bulk substrate regions are held at a ground state during said applying of the positive voltage to the source and drain regions of the FeFET memory cell to cause erasure of the at least one FeFET memory cell. In addition, a FeFET is described with a charge storage layer disposed adjacently to the ferroelectric layer within the gate stack. | 2016-01-28 |
20160027491 | REFRESH CIRCUIT - A refresh circuit is configured to perform a first refresh operation for a plurality of memory banks. The first refresh operation may be performed within a first time period determined according to a first parameter. The refresh circuit may be configured to perform a second refresh operation for a partial number of memory banks among the plurality of memory banks. The second refresh operation may be performed for the partial number of memory banks that have completed the first refresh operation. The second refresh operation may be performed within the first time period. | 2016-01-28 |
20160027492 | SEMICONDUCTOR MEMORY DEVICE, METHOD OF PERFORMING A REFRESH FOR SEMICONDUCTOR MEMORY DEVICE AND REFRESH COUNTER IN SEMICONDUCTOR MEMORY DEVICE - A semiconductor memory device may include a memory cell array, a first decoder and a second decoder. The memory cell array includes a plurality of memory cell rows. The first decoder is configured to select a first number of memory cell rows of the plurality of memory cell rows based on a selected refresh row address of a set of row addresses. The second decoder is configured to select a second number of memory cell rows of the plurality of memory cell rows based on the selected refresh row address. A total number of the first number and the second number is varied in response to the selected refresh row address. | 2016-01-28 |
20160027493 | DYNAMIC RANDOM ACCESS MEMORY FOR COMMUNICATIONS SYSTEMS - An integrated circuit may comprise a digital logic circuit, a memory refresh circuit, a first one or more dynamic random access memory (DRAM) cells, and a second one or more DRAM cells. The first DRAM cell(s) may be refreshed by the memory refresh circuit whereas the second DRAM cell(s) is not refreshed by any memory refresh circuit. Each of the first DRAM cell(s) and the second DRAM cell(s) may be a one-transistor cell. The first DRAM cell(s) may be used for storage of data which is overwritten at less than a threshold frequency. The second DRAM cell(s) may be used for storage of data which is overwritten at greater than the threshold frequency. A rate at which the first DRAM cell(s) are refreshed may be adjusted during run-time of the integrated circuit. | 2016-01-28 |
20160027494 | PRIORITIZING REFRESHES IN A MEMORY DEVICE - A method and apparatus for refreshing a row of a memory device prior to a scheduled refresh. A memory array may include a plurality of memory cells. The memory array may be configured to be refreshed at a first refresh time interval. The memory device may also include an intermediate refresh circuit. The intermediate refresh circuit may be configured to detect a triggering event and request a refresh for a row of the memory array in response to detecting a triggering event. | 2016-01-28 |
20160027495 | METHOD OF OPERATING MEMORY DEVICE AND REFRESH METHOD OFTHE SAME - A method of operating a memory device may include: providing a first power supply voltage to a sense amplifier during a first time interval, the first time interval being between a first time at which a voltage is provided to a first bit line, and a second time at which a pre-charge command is received; and providing a second power supply voltage to the sense amplifier during a second time interval, during which the word line is enabled after the pre-charge command is received. The second power supply voltage may be greater than the first power supply voltage. | 2016-01-28 |
20160027496 | SEMICONDUCTOR DEVICE EMPLOYING DVFS FUNCTION - Disclosed herein is a device that includes: a memory cell array including a plurality of memory cells, the memory cell array operates on a first internal voltage; a peripheral circuit accessing selected one or ones of the memory cells, the peripheral circuit operates on a second internal voltage; a first internal voltage generation circuit that supplies the first internal voltage to the memory cell array; and a second internal voltage generation circuit that supplies the second internal voltage to the peripheral circuit. The second internal voltage generation circuit sets the second internal voltage to a first voltage value in a first mode, and to a second voltage value that is different from the first voltage value in a second mode. The first internal voltage generation circuit sets the first internal voltage to a third voltage value in both the first and second modes. | 2016-01-28 |
20160027497 | APPARATUSES AND METHODS FOR PERFORMING LOGICAL OPERATIONS USING SENSING CIRCUITRY - The present disclosure includes apparatuses and methods related to performing logical operations using sensing circuitry. An example apparatus comprises an array of memory cells and sensing circuitry coupled to the array. The sensing circuitry is configured to perform a logical operation using a data value stored in a first memory cell coupled to a sense line as a first input and a data value stored in a second memory cell coupled to the sense line as a second input. The sensing circuitry is configured to perform the logical operation without transferring data via a sense line address access. | 2016-01-28 |
20160027498 | REDUCED REFRESH POWER - N out of every M number of refresh commands are ignored (filtered out) by a buffer chip on a memory module. N and M are programmable. The buffer receives refresh commands (e.g., auto-refresh commands) from the command-address channel, but does not issue a proportion of these commands to the DRAMs on the module. This reduces the power consumed by refresh operations. The buffer may replace some auto-refresh (REF) commands with activate (ACT) and precharge (PRE) commands directed to specific rows. These rows may have known ‘weak’ cells that require refreshing more often than a majority of the other rows on the module (or component). By ignoring some auto-refresh commands, and directing some others to specific rows that have ‘weak’ cells, the power consumed by refresh operations can be reduced. | 2016-01-28 |
20160027499 | Dual-Port Static Random-Access Memory Cell - The present disclosure provides a static random access memory (SRAM) cell comprising a first inverter including a first pull-up (PU) device, a first pull-down (PD) device, and a second PD device; a second inverter cross-coupled to the first inverter, the second inverter including a second PU device, a third PD device, and a fourth PD device; first and second pass gate (PG) devices coupled to the first inverter to form a first port; and third and fourth PG devices coupled to the second inverter to form a second port. The first and second PG devices, the first PD device of the first inverter, and the third PD device of the second inverter are configured on a first active region. The third and fourth PG devices, the second PD device of the first inverter, and the fourth PD device of the second inverter are configured on a second active region. | 2016-01-28 |
20160027500 | CIRCUIT FOR MITIGATING WRITE DISTURBANCE OF DUAL-PORT SRAM - A circuit for mitigating write disturbance including a first and a second discharge control paths is provided and applied to the dual-port SRAM. The first discharge control path is connected to bit lines of the second port and the first port, and a first control line. The second discharge control path is connected to inverse bit lines of the second port and the first port, and the first control line. A first discharge current is generated when the bit line of the second and the first ports are respectively at a high level voltage, and a low level voltage, and the first control line operates. A second discharge current is generated when the inverse bit line of the second and the first ports are respectively at the high level voltage and the low level voltage, and the first control line operates. | 2016-01-28 |
20160027501 | THREE DIMENSIONAL DUAL-PORT BIT CELL AND METHOD OF USING SAME - A three dimensional dual-port bit cell generally comprises a first portion disposed on a first tier, wherein the first portion includes a plurality of port elements. The dual-port bit cell also includes a second portion disposed on a second tier that is vertically stacked with respect to the first tier using at least one via, wherein the second portion includes a latch. | 2016-01-28 |
20160027502 | SEMICONDUCTOR DEVICE INCLUDING NEGATIVE BIAS VOLTAGE GENERATION CIRCUIT - A semiconductor device includes a bit line connected to memory cells, a negative bias voltage generation circuit generating a negative bias voltage that is to be applied to the bit line during writing, and a negative bias reference voltage generation unit generating a negative bias reference voltage based on a resistance ratio between a first resistor and a second resistor. | 2016-01-28 |
20160027503 | Memory Architecture With Local And Global Control Circuitry - A system includes a memory block. The memory block includes a local control circuit that is operable to control a memory operation of the memory block. The local control circuit includes a local sense amplifier. The system also includes a global memory control circuit separate from the memory block, and the global memory control circuit is operable to communicate with the local control circuit. The global memory control circuit includes a global data latch operable to receive a sensed data state from the local sense amplifier. | 2016-01-28 |
20160027504 | YUKAI VSL-BASED Vt-COMPENSATION FOR NAND MEMORY - A YUKAI NAND array comprising multiple strings associated with hierarchical global/local bit lines (GBL/LBL) and each string being associated with one LBL and having adjacent LBL as a dedicated local source line (LSL) without a common source line to connect all strings. Each of the LBLs is interleavingly associated with either an Odd or Even string selected via one pair of dummy cells inserted in each string and is used as one on-chip PCACHE register with full BL-shielding without wasting extra silicon area to allow batch-based multiple concurrent MLC All-BL, All-Vtn-Program and Alternative-WL program, Odd/Even read and verify operations with options of providing individual and common V | 2016-01-28 |
20160027505 | 3D VARIABLE RESISTANCE MEMORY DEVICE AND METHOD OF MANUFACTURING THE SAME - A variable resistance memory device includes a plurality of cell gate electrodes extending in a first direction, wherein the plurality of cell gate electrodes are stacked in a second direction that is substantially perpendicular to the first direction, A gate insulating layer surrounds each cell gate electrode of the plurality of cell gate electrodes and a cell drain region is formed on two sides of the each cell gate electrode of the plurality of cell gate electrodes A channel layer extends in the second direction along the stack of the plurality of cell gate electrodes, and a variable resistance layer contacting the channel layer. | 2016-01-28 |
20160027506 | RESISTIVE MEMORY DEVICE CAPABLE OF INCREASING SENSING MARGIN BY CONTROLLING INTERFACE STATES OF CELL TRANSISTORS - Memory systems can include a memory device having an array of nonvolatile memory cells therein, which is electrically coupled to a plurality of bit lines and a plurality of word lines. The nonvolatile memory cells may include respective nonvolatile resistive devices electrically coupled in series with corresponding cell transistors. A controller is also provided, which may be coupled to the memory device. The controller can be configured to drive the memory device with signals that support dual programming of: (i) the nonvolatile resistive devices; and (ii) interface states within the cell transistors, during operations to write data into the memory device. | 2016-01-28 |
20160027507 | NONVOLTILE RESISTANCE MEMORY AND ITS OPERATION THEREOF - A memory cell and the associated array circuits are disclosed. The memory array circuit includes a plurality of memory units, in which each of the memory units includes a storage device and a field-effect transistor. The storage device includes a top electrode, a bottom electrode and an oxide-based dielectric layer. The top electrode is formed by metal or metallic oxide dielectrics and connected to a word line. The bottom electrode is formed by metal, and the oxide-based dielectric layer is placed between the top electrode and the bottom electrode. The field-effect transistor includes a gate terminal connected to the bottom electrode, a source terminal connected to a ground line, and a drain terminal connected to a bit line. The resistance of the storage device is configured to be adjusted according to a first voltage applied to the word line and a second voltage applied to the bit line. | 2016-01-28 |
20160027508 | RESISTIVE MEMORY DEVICE AND OPERATION - A method of operating a resistive memory device including a plurality of memory cells comprises determining whether to perform a refresh operation on memory cells in a memory cell array; determining a resistance state of each of at least some of the memory cells; and performing a re-writing operation on a first memory cell having a resistance state from among a plurality of resistance states that is equal to or less than a critical resistance level. | 2016-01-28 |
20160027509 | MEMOIRE NON VOLATILE A RESISTANCE PROGRAMMABLE - A non-volatile memory including a plurality of elementary cells, each cell including: a first programmable-resistance storage element connected between first and second nodes of the cell; a first access transistor coupling the second node to a third node of the cell; and a second access transistor coupling the second node to a fourth node of the cell. | 2016-01-28 |
20160027510 | MEMORY DEVICE AND METHOD OF OPERATING THE SAME - A method of operating a memory device, which includes of memory cells respectively arranged in regions where first signal lines and second lines cross each other, includes determining a plurality of pulses so that each of the plurality of pulses that are sequentially applied to a selected memory cell among the plurality of memory cells is changed according to a number of times of executing programming loops. In response to the change of the plurality of pulses, at least one of a first inhibit voltage and a second inhibit voltage is determined so that a voltage level of at least one of the first and second inhibit voltages that are respectively applied to unselected first and second signal lines connected to unselected memory cells among the plurality of memory cells is changed according to the number of times of executing the programming loops. | 2016-01-28 |
20160027511 | Computing Register with Non-Volatile-Logic Data Storage - A digital system includes a non-volatile calculating register having a set of latches configured to perform a calculation. A set of non-volatile storage cells is coupled to the set of latches. Access detection logic is coupled to the calculating register and is operable to initiate a calculation of a next value by the calculating register each time the calculating register is accessed by an accessing module. The access detection logic is operable to cause the next value to be stored in the set of non-volatile storage cells at the completion of the calculation as an atomic transaction. After a power loss or other restore event, the contents of the calculating register may be restored from the non-volatile storage cells. | 2016-01-28 |
20160027512 | NONVOLATILE SEMICONDUCTOR MEMORY DEVICE AND OPERATION METHOD OF THE SAME - A nonvolatile semiconductor memory device according to an embodiment includes a control unit, during the read sequence performed to an interested cell, performing a first read operation to detect that a threshold voltage of an adjacent cell is higher than a second reference voltage higher, performing a second read operation to detect that the threshold voltage of the interested cell is higher than a first reference voltage while applying a first bit line voltage to the adjacent bit line when threshold voltages of the adjacent cells are lower than the second reference voltage, and to detect that the threshold voltage of the interested cell is higher than the first reference voltage while applying a second bit line voltage higher than the first bit line voltage to the adjacent bit line when threshold voltages of the adjacent cells are higher than the second reference voltage, after the first read operation. | 2016-01-28 |
20160027513 | NONVOLATILE MEMORY DEVICE, PROGRAM METHOD THEREOF, AND STORAGE DEVICE INCLUDING THE SAME - A nonvolatile memory device includes memory cells stacked in a direction perpendicular to a substrate and further includes a first memory cell string connected between a selected bit line and a selected string selection line, a second memory cell string connected between the selected bit line and an unselected string selection line, and a third memory cell string connected to an unselected bit line. During a bit line setup section of a program operation, a ground voltage is provided to the selected bit line and a power supply voltage provided to the unselected string selection line is changed to the ground voltage. | 2016-01-28 |
20160027514 | NONVOLATILE MEMORY DEVICE AND PROGRAMMING METHOD THEREOF - According to example embodiments, a nonvolatile memory device includes a plurality of cell strings on a horizontal semiconductor layer. Each of the cell strings including a plurality of memory cells stacked in a direction perpendicular to the horizontal semiconductor layer. According to example embodiments, a programming method of the nonvolatile memory device includes setting up bitlines corresponding the cell strings, setting up a plurality of string select lines connected to the cell strings, and applying a negative voltage lower to a ground select line. The ground select line is connected to a plurality of ground select transistors between the memory cells and the semiconductor layer. The string select lines extend in a direction intersecting the bitlines. The negative voltage is lower than a ground voltage. | 2016-01-28 |
20160027515 | Pulse Control For Non-Volatile Memory - A nonvolatile memory device that uses pulsed control and rest periods to mitigate the formation of defect precursors. A first embodiment uses pulsed bitline control, where the coupling between a memory cell channel and a reference voltage is pulsed when it is desired to change state in the associated memory cell. Each pulse may be chosen to be less than about 20 nanoseconds, while a “rest period” between pulses can be on the order of about a hundred nanoseconds or greater. Because bitline control is used, very short rise times can be enabled, enabling generation of pulse durations of 50 nanoseconds or less. In other embodiments, these methods may also be more generally applied to other conductors (e.g., wordline or substrate well, for program or erase operations); segmented wordlines or bitlines may also be used, to minimize RC loading and enable sufficiently short rise times to make pulses robust. | 2016-01-28 |
20160027516 | EFFICIENT MODIFICATION OF DATA IN NON-VOLATILE MEMORY - Techniques are disclosed herein for efficient modification of data in non-volatile memory. In some examples, an update, such as a firmware update, may be generated for a first portion of data, such as firmware or a portion of firmware. In some cases, the first portion of data may be used in combination with a respective second portion of data. Also, in some cases, in combination with the update, various modifications may be determined for the second portion of data. Additionally, a set of tasks may be generated for performing the modifications to the second portion of data. The update may then be transmitted along with the set of tasks from one or more control devices to one or more update devices that are being updated with the update. | 2016-01-28 |
20160027517 | System And Method To Inhibit Erasing Of Portion Of Sector Of Split Gate Flash Memory Cells - A system and method to inhibit the erasing of a portion of a sector of split gate flash memory cells while allowing the remainder of the sector to be erased is disclosed. The inhibiting is controlled by control logic that applies one or more bias voltages to the portion of the sector whose erasure is to be inhibited. | 2016-01-28 |
20160027518 | MEMORY DEVICE AND METHOD FOR CONTROLLING THE SAME - A memory device connectable to a host device includes a non-volatile semiconductor memory unit including a plurality of memory blocks, each of the memory blocks including a plurality of pages, and a control unit configured to carry out data writing in the non-volatile semiconductor memory unit in units of a page and data erasing in the non-volatile semiconductor memory unit. When the control unit carries out data writing of a plurality of pages, the control unit splits data erasing of one memory block into a plurality of sub erasing steps and carries out one sub erasing step between the data writing of pages. | 2016-01-28 |
20160027519 | Bitline Regulator For High Speed Flash Memory System - A bitline regulator for use in a high speed flash memory system is disclosed. The bitline regulator is responsive to a set of trim bits that are generated by comparing the bias voltage of a bitline to a reference voltage. | 2016-01-28 |
20160027520 | SEMICONDUCTOR MEMORY DEVICE INCLUDING THREE-DIMENSIONAL MEMORY CELL ARRAY STRUCTURE AND OPERATING METHOD THEREOF - An operating method includes biasing channel regions of unselected cell strings among the cell strings to an initial voltage while applying a first pass voltage to the plurality of word lines; floating the channel regions of the unselected cell strings; increasing the first pass voltage to a second pass voltage during the floating of the channel regions; and reading data from selected memory cells of selected cell strings among the cell strings. | 2016-01-28 |
20160027521 | METHOD OF FLASH CHANNEL CALIBRATION WITH MULTIPLE LUTS FOR ADAPTIVE MULTIPLE-READ - Error Correction Codes, which are able to take soft-decision information, work much better when compared with hard-decision decoding. It can achieve much better performance. However, due to lack of direct soft-decision information for the NAND flash, multiple-reads with different voltage thresholds are used to generate the soft-decision information. Another invention disclosure describes a method to perform the multiple-read adaptively with different voltage threshold for the NAND flash in order to minimize the number of total multiple-read. The invention disclosure described here is a method of flash channel calibration, which will generate multiple LUTs for adaptive multiple-read with different voltage threshold. | 2016-01-28 |
20160027522 | RETENTION LOGIC FOR NON-VOLATILE MEMORY - An integrated circuit memory device includes an array of non-volatile, charge trapping memory cells, configured to store data values in memory cells in the array using threshold states, including a higher threshold state. Retention check logic executes to identify memory cells in the higher threshold state which fail a threshold retention check. Also, logic is provided to reprogram the identified memory cells. | 2016-01-28 |