04th week of 2010 patent applcation highlights part 59 |
Patent application number | Title | Published |
20100023733 | Microprocessor Extended Instruction Set Precision Mode - A method and apparatus to gain additional functionality of a microprocessor by adding an extended instruction set mode. In this mode, the result of executing an instruction may be changed without changing the instruction itself. In the extended instruction set mode, there is an increase to the number of bits of precision when executing the plus instruction. An additional bit position is added to the program counter register. When this bit is set, the microprocessor is in extended instruction set mode. In addition, a new one bit latch is provided. The latch may be changed only when the microprocessor is in extended instruction set mode. The latch is defined as holding a true carry bit. A significant bit of a register holding a sum is saved in the carry latch at the end of the plus instruction. | 2010-01-28 |
20100023734 | SYSTEM, METHOD AND COMPUTER PROGRAM PRODUCT FOR EXECUTING A HIGH LEVEL PROGRAMMING LANGUAGE CONDITIONAL STATEMENT - A method for executing an instruction, the method includes: executing a compare and configure mask instruction, wherein the executing comprises: performing a comparison to provide a comparison result; and configuring, in response to the comparison result, a multiple bit mask that is stored in a multiple-purpose register; wherein all bits of the multiple bit mask are configured to have the same value; and applying an algorithmic operation on the multiple bit mask to provide an algorithmic operation result; wherein the algorithmic operation result represents an outcome of a high level programming language conditional statement. | 2010-01-28 |
20100023735 | DEBUG MESSAGE GENERATION USING A SELECTED ADDRESS TYPE - A method for generating a debug message includes receiving a translated address and an untranslated address associated with a same processor operation, determining a value of one or more control indicators, selecting the translated address or the untranslated address as a selected address based on the value of the one or more control indicators, and creating a debug message using at least a portion of the selected address. | 2010-01-28 |
20100023736 | RECONFIGURABLE CIRCUIT, RESET METHOD, AND CONFIGURATION INFORMATION GENERATION DEVICE - The present invention provides a reconfigurable circuit that comprises a plurality of reconfiguration cells and changes a configuration of a computation processing unit included in each of the reconfiguration cells. Here, each of the reconfiguration cells further includes: a computation storage unit operable to store a result of a computation performed by the computation processing unit; a flag holding unit operable to hold an initialization flag indicating whether an initialization of the computation storage unit is required; and an initialization control unit operable to, during the configuration change of the computation processing unit, control the initialization of the computation storage unit based on the initialization flag held by the flag holding unit. | 2010-01-28 |
20100023737 | TEST MODE INITIALIZATION - A test mode initialization system includes beginning a power-on self-test (POST) wherein the POST may be performed by determining whether a system under test is in a quick test mode, and in response to being in the quick test mode, initialize only a portion of all memory in the system under test and initialize only a portion of a plurality of central processor unit (CPU) cores. | 2010-01-28 |
20100023738 | State Separation for Application Changes - Application states may be stored and retrieved using policies that define various contexts in which the application is used. The application states may define configurations or uses of the application, including connections to and interactions with other applications. Applications that are virtualized may have state that is defined within a usage context and multiple states or configurations may be stored and recalled based on the usage context. Policies may define the context and what parameters are to be saved, and may be applied when applications are operated in a virtualized manner. | 2010-01-28 |
20100023739 | METHOD AND APPARATUS FOR BOOTING A PROCESSING SYSTEM - Machine-readable media, methods, apparatus and system for booting a processing system are described. In an embodiment, whether an encrypted version of a closed operating system is authentic may be determined. The encrypted version of the closed operating system may be decrypted with a key retrieved from a processor register to provide the closed operating system, based at least in part on a determination that the encrypted version of the closed operating system is authentic. Then, whether the closed operating system is authentic may be determined and a virtual machine may be created so that the closed operating system may be launched in the virtual machine, if the closed operating system is authentic. | 2010-01-28 |
20100023740 | DIAGNOSTIC UTILITY AND METHOD FOR A DATA STORAGE DEVICE - The disclosure is related to systems and methods of a diagnostic utility for a data storage device. Further, the present disclosure is also related to monitoring host activity and storing information related to the host activity in a nonvolatile cache of a data storage device. In a particular embodiment, a method includes monitoring a host computer for an occurrence of data storage device related activity and storing information based on the data storage device related activity in a nonvolatile memory of a removable data storage device. | 2010-01-28 |
20100023741 | METHOD FOR SETTING BIOS AND RECREATING CHECKSUM VALUE - A method is used for setting a basic input output system (BIOS) and recreating a checksum value in a computer. The BIOS is stored in a complementary metal-oxide semiconductor (CMOS). The method includes modifying an original BIOS value to a new BIOS value, writing a preset value into a setting storage unit of the CMOS, checking a value in the setting storage unit against the preset value, recreating a new checksum value based on the new BIOS value, overwriting an original checksum value with the new checksum value, and clearing the setting storage unit. The checking and the recreating steps are executed before a BIOS checksum validation of the computer during a computer initialization process when the computer is restarted. | 2010-01-28 |
20100023742 | BIOS SHARING SYSTEM IN A HIGH DENSITY SERVER AND METHOD THEREOF - A BIOS sharing system in a high density servers includes a plurality of servers, a BIOS (Basic Input Out System), a switch and a micro controller. Each server has a motherboard hardware and a BMC (Baseboard Management Controller), wherein each BMC is operable to output a status order in response to a control information of each motherboard hardware. The BIOS is operable to initialize each motherboard hardware before the motherboard hardware being operating. The switch is interconnected between the BIOS and each server for selectively switching to one of the servers such that the BIOS is loaded to the one of the servers for initializing. The micro controller is interconnected between the switch and each BMC, wherein the micro controller is operable to order the switch for selectively switching to one of the servers in response to the status order. | 2010-01-28 |
20100023743 | METHODS AND APPARATUS FOR INTEGRITY MEASUREMENT OF VIRTUAL MACHINE MONITOR AND OPERATING SYSTEM VIA SECURE LAUNCH - Methods and apparatus to measure the integrity of a virtual machine monitor and an operating system via secure launch are disclosed. In one example, a method measures a first characteristic of a virtual machine monitor, stores the first measured characteristic in a first hardware protected location, measures a second characteristic of an operating system with the virtual machine monitor, wherein the measuring of the second characteristic is initiated by the operating system, and stores the second measured characteristic in a second hardware protected location. | 2010-01-28 |
20100023744 | Interface Monitoring Device, Computer System, and Method for Monitoring a Differential Interface Port - An interface monitoring device can be used with at least one differential interface port with a positive and a negative data line for connecting a peripheral device. The interface monitoring device has a monitoring circuit and a deactivation circuit. The monitoring circuit is designed to monitor at least one signal level dependent on the signal level of the positive and/or the negative data line and the deactivation circuit is designed to stop data traffic via the positive and/or the negative data line of the at least one interface port. | 2010-01-28 |
20100023745 | MEMORANDUM-PRESENTING METHOD AND COMPUTER SYSTEM USING THE SAME - A memorandum-information presenting method and a computer system using the method are provided. The computer system allows the memorandum-information to be presented and/or edited during a booting procedure, for example, while executing BIOS codes, initializing various components, checking hardware, allocating resources, or assisting to load an operating system. Accordingly, a user may read or edit the information without waiting for the computer system to successfully enter an operating system. | 2010-01-28 |
20100023746 | INFORMATION PROCESSING SYSTEM, INFORMATION PROCESSING APPARATUS, AND INFORMATION PROCESSING METHOD - This invention prevents confidential information included in information contents from leaking from an external apparatus when the external apparatus executes a layout process and print process of the information contents. An information processing system of this invention includes an information contents converter ( | 2010-01-28 |
20100023747 | Critical Security Parameter Generation and Exchange System and Method for Smart-Card Memory Modules - A storage device contains a smart-card device and a memory device, which is connected to a controller. The storage device may be used in the same manner as a conventional smart-card device, or it may be used to store a relatively large amount of data. The memory device may also be used to store data or instructions for use by the smart-card device. The controller includes a security engine that uses critical security parameters stored in, and received from, the smart-card device. The critical security parameters may be sent to the controller in a manner that protects them from being discovered. The critical security parameters may be encryption and/or decryption keys that may encrypt data written to the memory device and/or decrypt data read from the memory device, respectively. Data and instructions used by the smart-card device may therefore stored in the memory device in encrypted form. | 2010-01-28 |
20100023748 | SELF CHECKING ENCRYPTION AND DECRYPTION BASED ON STATISTICAL SAMPLING - The present invention is related to the checking of encryption. Embodiments of the present invention are based on the discovery that sufficiently high reliability may be established without checking every encryption block. Instead, embodiments of the present invention provide that data being encrypted may be sampled at certain rate (which may be constant or varying) and only the sampled data may be checked. In general, embodiments of the present inventions are applicable to a fast encryption circuit that may encrypt an entire stream of incoming data into a stream of encrypted data and one or more slower (or slow) encryption circuit and/or one or more slow decryption circuit that operate(s) only on selected samples of the incoming or encrypted data in order to check the encryption of the fast circuit. Thus, encryption can be verified without incurring the costs of exhaustively checking all encrypted data. | 2010-01-28 |
20100023749 | Harvesting Entropy from Trusted Cryptographic Sources - Extending entropy in a random number generation utility. Where a device has access to trusted sources of encrypted data, such as encrypted network traffic, such encrypted network traffic may be sampled and the bits fed into the entropy seeding routines of the random number generation utility. | 2010-01-28 |
20100023750 | System and Method for Controllably Concealing Data from Spying Application - A method for use in controllably concealing an input data that has been entered into a computer system via an input device, from being comprehended by a spying application during transportation of the input data across a communication link of the computer system, the method including the steps of: (i) encrypting the input data when the input data is being processed at a relatively low level within the computer system so as to form an encrypted input data; (ii) thereafter, transporting the encrypted input data across the communication link; (iii) thereafter, providing a device for decrypting the encrypted input data so as to obtain a decrypted input data; (iv) selectively providing access to the decrypted input data by at least one authorised software application operably connected to the computer system. | 2010-01-28 |
20100023751 | System and method for preventing web crawler access - Preventing web crawler access includes receiving a request for a webpage that includes web content that should be protected from a web crawler, encrypting the web content to be protected to generate encrypted content and responding to the request, including sending the encrypted content and a decryption instruction. The decryption instruction is configured to allow a web browser to decrypt the encrypted content. | 2010-01-28 |
20100023752 | METHOD AND DEVICE FOR TRANSMITTING GROUPCAST DATA IN A WIRELESS MESH COMMUNICATION NETWORK - A method for transmitting groupcast data in a wireless mesh communication network as provided improves security of groupcast data. The method comprises processing, at a supplicant node, authentication handshake data received from an authenticator node, wherein the supplicant node is a next-hop neighbor of the authenticator node away from a root node. The supplicant node then stores a group transient key (GTK) received from the authenticator node. Next, the supplicant node processes authentication handshake data received from a third node, wherein the third node is a next-hop neighbor of the supplicant node away from the root node. The GTK is then transmitted from the supplicant node to the third node. Encrypted groupcast data are then generated at the supplicant node by using the GTK to encrypt groupcast data received from the authenticator node. Finally, the encrypted groupcast data are transmitted from the supplicant node to the third node. | 2010-01-28 |
20100023753 | SYSTEM AND METHOD OF GENERATING SUBTITLING FOR MEDIA - A method for media subtitling is described, wherein subtitles and/or captions for media are first created on a web interface in a first language along with the appropriate synchronization information with respect to the media. The document content may be created via the web interface, or it may be created locally and uploaded to the interface. Subsequent to creation and/or upload of at least a portion of the subtitling, personnel in different locations (e.g., different terminals or different countries) then access the web interface, which includes the first language and the synchronization information, to create foreign/alternative subtitling. | 2010-01-28 |
20100023754 | SYSTEM AND METHOD FOR MONITORING UNAUTHORIZED TRANSPORT OF DIGITAL CONTENT - A system for network content monitoring and control, comprising: a transport data monitor, connectable to a point in a network, for monitoring data being transported past said point, a signature extractor, associated with said transport data monitor, for extracting a derivation of said data, said derivation being indicative of content of said payload, a database of preobtained signatures of content whose movements it is desired to monitor, and a comparator for comparing said derivation with said preobtained signatures, thereby to determine whether said payload comprises any of said content whose movements it is desired to monitor. The monitoring result may be used in bandwidth control on the network to restrict transport of the content it is desired to control. | 2010-01-28 |
20100023755 | METHOD AND APPARATUS FOR SECURE INFORMATION TRANSFER TO SUPPORT MIGRATION - A system and method are disclosed for providing and maintaining a high level of security during migration of data from one platform to another. The disclosed system combines user and equipment authentication with equipment environment authorization guaranteed by a security module such as supported by a trusted platform module (TPM) in parallel, for secure information transfer to support migration between platforms. | 2010-01-28 |
20100023756 | SPLITTING AN SSL CONNECTION BETWEEN GATEWAYS - A system for secure communication, including a first security computer communicatively coupled with a client computer via an SSL connection, including a certificate creator, for receiving certificate attributes of a server computer certificate and for creating a signed certificate therefrom, and an SSL connector, for performing an SSL handshake with the client computer using the signed certificate created by said certificate creator, and a second security computer communicatively coupled with a server computer via an SSL connection, and communicatively coupled with the first security computer via a non-SSL connection, including an SSL connector, for performing an SSL handshake with the server computer using a signed certificate provided by the server computer, and a protocol appender, for appending attributes of the signed certificate provided by the server computer within a message communicated to the first security computer. A method is also described and claimed. | 2010-01-28 |
20100023757 | METHODS AND SYSTEMS FOR SENDING SECURE ELECTRONIC DATA - A method and system for providing encryption are provided, involving a) transmitting a request from a sender to a database for a public key for a selected recipient, the database being configured to store for each member in a plurality of members a member public key for encrypting electronic data; b) determining if the selected recipient is in the plurality of members, and; c) if the selected recipient is in the plurality of members, then executing a member procedure, the member procedure comprising transmitting from the database to the sender the member public key stored in the database for the selected recipient; d) if the selected recipient is not in the plurality of members, then executing a non-member procedure, the non-member procedure comprising determining if at least one predetermined criterion is met, and, if the at least one predetermined criterion is met, generating a non-member public key for encrypting electronic data and a non-member private key for decrypting the electronic data encrypted using the non-member public key; otherwise, if the at least one predetermined criterion is not met the non-member public key and the non-member private key are not generated. | 2010-01-28 |
20100023758 | DOCUMENT AUTHENTICATION USING ELECTRONIC SIGNATURE - Embodiments of authenticating an electronic document are disclosed. A document authentication system is operatively connected with a professional system, a license management system and a certification authority system, for authenticating an electronic document of a client response to a request from a client system. An authentication unit included in the document authentication system receives the electronic document from the client system for review and seal thereof, transmits the electronic document to receive the electronic document with the electronic signature implemented and transmits the electronic signature to the license management system to verify license validity of the professional based on the electronic signature. Further, the authentication unit transmits the electronic document to the client system with the electronic signature including a seal imprint image of the professional if the license of the professional is valid. | 2010-01-28 |
20100023759 | METHOD AND SYSTEM FOR AUTHORIZING CLIENT DEVICES TO RECEIVE SECURED DATA STREAMS - A method and system for authorizing client devices to receive secured data streams through the use of digital certificates embedded in the client devices. A freely distributed cryptographically signed group file with an embedded expiration date is associated with each individual digital certificate. A single group file can be associated with more than one digital certificate but each digital certificate is associated with a single group file. The group file contains cryptographic keys that can be used to decrypt a section of the digital certificate revealing a set of client keys. The client keys are then used to encrypt a program key which are then sent back to the client device. When the client device requests a specific data stream or digital content, an issuance timestamp associated with the content is compared to the expiration date in the group file. If the issuance timestamp is after the expiration date, the client device is declined. If the issuance timestamp is before the expiration date, the requested content, encrypted utilizing the program key, is sent to the client device. | 2010-01-28 |
20100023760 | METHOD, SYSTEM, AND DATA SERVER FOR CHECKING REVOCATION OF CONTENT DEVICE AND TRANSMITTING DATA - A method of checking revocation of a device and software, and transmitting data to a secure device and secure software whose keys have not been leaked is provided. The method includes receiving authentication information of a device requesting transmission of data, and authentication information of software accessing the data in the device; checking revocation of the device and the software, based on the received authentication information; and transmitting the data to the software of the device, when the device and the software are not revoked as a result of the checking. By doing so, during transmission of data, such as content or a license, it is possible to check security of a device and software being executed in the device, so that the data can be more safely transmitted. | 2010-01-28 |
20100023761 | Systems and Methods Using Cryptography to Protect Secure Computing Environments - Secure computation environments are protected from bogus or rogue load modules, executables and other data elements through use of digital signatures, seals and certificates issued by a verifying authority. A verifying authority—which may be a trusted independent third party—tests the load modules or other executables to verify that their corresponding specifications are accurate and complete, and then digitally signs the load module or other executable based on tamper resistance work factor classification. Secure computation environments with different tamper resistance work factors use different verification digital signature authentication techniques (e.g., different signature algorithms and/or signature verification keys)—allowing one tamper resistance work factor environment to protect itself against load modules from another, different tamper resistance work factor environment. Several dissimilar digital signature algorithms may be used to reduce vulnerability from algorithm compromise, and subsets of multiple digital signatures may be used to reduce the scope of any specific compromise. | 2010-01-28 |
20100023762 | HTTP AUTHENTICATION AND AUTHORIZATION MANAGEMENT - Systems, methods and apparatus for a distributed security that provides authentication and authorization management. The system can include an epoch processor that is used to validate authentication and authorization data that is valid only for an epoch. The epoch processor can maintain a public key that can be used to decrypt the authentication and authorization data during the epoch that the key is valid. The epoch processor can receive a new public key during each epoch. The epoch processor can also determine if the authentication or authorization data was fraudulently generated based on the contents of the data, and verifying whether the data is valid for the epoch in which it was decrypted. | 2010-01-28 |
20100023763 | MULTI-INTERFACE MOBILITY CLIENT - A mobile node comprises: a plurality of network interfaces, each with a respective device driver; a network layer; a multi-interface driver capable of communication with each network interface by way of the respective device driver for that network interface, the multi-interface driver handling communications from the network layer to any of the network interfaces; the multi-interface driver switching from a first one of the network interfaces to a second one of the network interfaces by changing the one of the plurality of network interfaces with which the multi-interface driver communicates, while hiding the switching from the network layer. | 2010-01-28 |
20100023764 | SYSTEM AND METHOD FOR AUTHENTICATING COMPONENTS IN WIRELESS HOME ENTERTAINMENT SYSTEM - Configuration information is exchanged between a home entertainment system server and various wireless components by pushing a button on the server and a random button on a remote control device as it is pointed at the devices sought to be authenticated. | 2010-01-28 |
20100023765 | METHOD FOR UPDATING A ROUTING ENTRY - The present invention concerns method for updating a routing entry BC for a communication partner node CN communicating with a communication originating node MN via a network containing at least one routing node HA, the method comprising the steps of: requesting 1. a routing entry update from said communication originating node MN to said communication partner node CN, wherein said update request contains at least an identification BUIN of the request, submitting 2. request verification information, associated to said identification BUIN of the update request, from said communication originating node MN to said at least one routing node, requesting 4. verification of said routing entry update by said communication partner node CN to said routing node HA using said identification BUIN of the update request, retrieving 5. said request verification information from said routing node based on said identification BUIN of the update request. | 2010-01-28 |
20100023766 | Computer Program Product and Computer System for Peer-to-Peer Communications - A protocol for secure peer-to-peer communications is established based on existing cryptographic techniques and encryption algorithms. The peers ( | 2010-01-28 |
20100023767 | API for Diffie-Hellman secret agreement - Various technologies and techniques are disclosed for implementing a Diffie-Hellman secret agreement. An application programming interface is provided that is operable to allow a first computer to generate a Diffie-Hellman secret agreement for communicating securely with a second computer over an insecure channel. A get public key operation is performed upon receiving a request to perform the get public key operation. The get public key operation gets a public key of the first computer. A retrieval operation is performed upon receiving a request to perform the retrieval operation. The retrieval operation retrieves the Diffie-Hellman secret agreement upon supplying a public key of the second computer. | 2010-01-28 |
20100023768 | Method and system for security key agreement - A method and system for security key agreement is disclosed. The method may include broadcasting a first connectivity association discovery message and receiving a message from a second node on the network; if the second node is not a member of a connectivity association and the message from the second node is a second connectivity association discovery message, one of the first or second nodes may be assigned as a master node. The method may further include the master node sending an authentication request message, receiving an authentication response, sending a session key indication message, receiving a session key acknowledgement message, and broadcasting a connectivity association augment message. | 2010-01-28 |
20100023769 | METHODS AND APPARATUS FOR SECURE DOCUMENT PRINTING - Methods and apparatus are provided for securely printing a print job on a networked printer. An application program running on a networked computer instructs the printer to generate and exchange cryptographic keys. The application program then encrypts the print job using the keys, and then communicates the encrypted print job to the printer. The printer decrypts the received print job and prints the document. | 2010-01-28 |
20100023770 | METHODS AND APPARATUS FOR SECURE DOCUMENT PRINTING - Methods and apparatus are provided for securely printing a print job on a networked printer. An application program running on a networked computer instructs the printer to generate and exchange cryptographic keys. The application program then encrypts the print job using the keys, and then communicates the encrypted print job to the printer. The printer decrypts the received print job and prints the document. | 2010-01-28 |
20100023771 | IMPLICIT CERTIFICATE VERIFICATION - A method of computing a cryptographic key to be shared between a pair of correspondents communicating with one another through a cryptographic system is provided, where one of the correspondents receives a certificate of the other correspondents public key information to be combined with private key information of the one correspondent to generate the key. The method comprises the steps of computing the key by combining the public key information and the private key information and including in the computation a component corresponding to verification of the certificate, such that failure of the certificate to verify results in a key at the one corespondent that is different to the key computed at the other correspondent. | 2010-01-28 |
20100023772 | METHOD FOR GENERATING A ONE-TIME ACCESS CODE - A method for generating an access code for a device or system. The one-time access code generated by the method for the device or system is valid only once. The method can be used for supplying goods or services by means of automatic or semiautomatic access control devices or systems, for example. | 2010-01-28 |
20100023773 | SIGNATURE VERIFICATION APPARATUS, METHOD FOR CONTROLLING SIGNATURE VERIFICATION APPARATUS, SIGNING APPARATUS, METHOD FOR CONTROLLING SIGNING APPARATUS, PROGRAM, AND STORAGE MEDIUM - A signature verification apparatus includes a determining unit configured to determine a type of a signature affixed to a document file, a first generating unit configured to, when the determining unit determines that the signature is of a first type, check the validity of a certificate contained in the signature, detect whether the document file has been tampered with based on the signature, and generate a first verification result indicating whether the signature is valid based on the check and the detection, and a second generating unit configured to, when the determining unit determines that the signature is of a second type, without checking the validity of a certificate contained in the signature, detect whether the document file has been tampered with based on the signature, and generate a second verification result indicating whether the signature is valid based on the detection. | 2010-01-28 |
20100023774 | INFORMATION SECURITY DEVICE - An information security device is provided that, when information is circulated through a chain, permits changing of a usage rule for the information or collection (deletion) of the information after the circulation. | 2010-01-28 |
20100023775 | COMPRESSED ECDSA SIGNATURES - An improved compression scheme for compressing an ECDSA signature is provided. The scheme substitutes the integer s in a signature (r, s) by a smaller value c. The value c is derived from s and another value d, d being small enough such that c is smaller than s. The compressed signature (r, c) is verified by computing a value using r and e, e being a hash of a message m, and using this value with a value R recovered from r to derive the value d. The value s can then be recovered and the full signature then recovered and verified. | 2010-01-28 |
20100023776 | Method and System for Storing a Key in a Remote Security Module - The invention concerns a method for obtaining assurance that a content control key is securely stored in a remote security module for further secure communications between a content provider and said security. A security module manufacturer, which has a pre-established trustful relation with the security module, imports a symmetric transport key into the security module, wherein the symmetric transport key is unique to the security module. The content provider shares the symmetric transport key with the security module manufacturer and exchanges messages with the security module through a security module communication manager in order to get the proof that the security module stores the content control key. At least a portion of the messages exchanged between the content provider and the security module are protected using the symmetric transport key. | 2010-01-28 |
20100023777 | SYSTEM AND METHOD FOR SECURE FIRMWARE UPDATE OF A SECURE TOKEN HAVING A FLASH MEMORY CONTROLLER AND A SMART CARD - A system and method of operating a device to securely update the control firmware controlling the device. Downloading a firmware update package to a first microcontroller of the device. Determining a firmware update portion and an encrypted hash portion of the firmware update package wherein the encrypted hash portion is cryptographically signed by a signatory. Confirm that the encrypted hash portion conforms to the firmware update by independently computing the hash of the encrypted firmware update portion on the first microcontroller and comparing that value to the signed hash. Other systems and methods are disclosed. | 2010-01-28 |
20100023778 | Ticket Authorized Secure Installation And Boot - A method and apparatus for secure software installation to boot a device authorized by a ticket are described herein. A ticket request including a device identifier of the device is sent for the ticket which includes attributes for one or more components to boot the device into an operating state. The ticket is cryptographically validated to match the one or more components with corresponding attributes included in the ticket. If successfully matched, the one or more components are executed to boot the device. | 2010-01-28 |
20100023779 | CRYPTOGRAPHIC PROCESSING METHOD AND CRYPTOGRAPHIC PROCESSING APPARATUS - In a cryptographic processing method, middle data which is the result of operation at a predetermined stage during encryption and decryption processing is saved and the subsequent encryption and decryption processes are divided into a first encryption and decryption processing which uses the initial data as input for the initial operation and second encryption and decryption processing which uses the saved middle data as input for the first stage operation. | 2010-01-28 |
20100023780 | FLASH DEVICE SECURITY METHOD UTILIZING A CHECK REGISTER - Methods of operating memory systems and memory systems are disclosed, such as a memory system having a memory array storing a code generating program to instruct a processor to generate a code, and a register to store a code generated by the processor, where the register is configured to allow a write operation to the memory array in response to a match of a code stored in the register and where the match is controlled in response to a request from a utility program being executed by the processor. | 2010-01-28 |
20100023781 | DATA PROCESSING APPARATUS, DATA STORAGE DEVICE, AND DATA PROCESSING METHOD THEREFOR - A supported encryption and authentication function is inquired of a memory card having a digital data encryption and authentication function. An encryption and authentication function to be applied to digital data is selected based on the inquiry result. The memory card is notified of the selection result, and digital data is transmitted to the memory card. | 2010-01-28 |
20100023782 | CRYPTOGRAPHIC KEY-TO-POLICY ASSOCIATION AND ENFORCEMENT FOR SECURE KEY-MANAGEMENT AND POLICY EXECUTION - Key-to-policy association and hardware-based policy enforcement for file/folder encryption (FFE) and/or full-disk encryption (FDE) are provided. A CPU independent microprocessor (CIM) is coupled to a platform and provides a secure storage service, secure non-volatile storage, secure policy enforcement engine, and system interface for communication with platform components independent of the CPU. The CIM stores a key and its associated policies by generating a hardware-derived key to wrap the key prior to securely storing it in non-volatile storage on the CIM. Upon receiving a request for key-access by an application, policy status and credentials are verified before the key is returned. | 2010-01-28 |
20100023783 | SYSTEM AND METHOD OF DECRYPTING ENCRYPTED CONTENT - System and method of decrypting content. The content may be decrypted with decryption keys stored on a secured dongle. The dongle may be connect to a computer and used to decrypt the content for the computer, limiting the decryption-based processing demands on the computer. The computer may output the decrypted content to an output device for access by a user. The dongle may be single-use device pre-configured with a number of unchangeable keys and security measures. | 2010-01-28 |
20100023784 | Power Delivery Over Ethernet Cables - A method for power delivery comprises coupling an Ethernet cable comprising four wire pairs to a power delivery system and providing power to a powered device on all of the wire pairs. A power delivery system includes an interface operable to couple to an Ethernet cable comprising four wire pairs and a controller operable to provide power to a powered device on all of the wire pairs. | 2010-01-28 |
20100023785 | Unified Bus Architecture for PoE Communication and Control - Embodiments of a unified communication and control bus architecture for Ethernet and/or PoE systems are provided. Embodiments enable a unified communication and control bus architecture that significantly simplifies communication and control in Ethernet and/or PoE systems. Embodiments enable significant savings both in terms of cost and complexity as the number of communication and control buses is reduced down to one. Embodiments can be used in various Ethernet and/or PoE implementations, including, for example, single PCB-single PoE, single PCB-multiple PoE, chassis-based switch, and stackable-based switch configurations. Further, embodiments can be implemented using standard Ethernet as well as proprietary implementations. | 2010-01-28 |
20100023786 | SYSTEM AND METHOD FOR REDUCTION OF ELECTRICITY PRODUCTION AND DEMAND - A system and method of intermittently reducing power demand loads to postpone an activation of an incremental power supply source or hasten the deactivation of a power source. | 2010-01-28 |
20100023787 | CONTROLLING THE POWER UTILIZATION OF A COMPUTER SYSTEM BY ADJUSTING A COOLING FAN SPEED - Some embodiments of the present invention provide a system that controls a power utilization of a computer system by adjusting a cooling fan speed. During operation, a relationship between information related to the cooling fan speed and the power utilization is determined. Then, the cooling fan speed is adjusted based on the determined relationship to control the power utilization of the computer system. | 2010-01-28 |
20100023788 | Reducing Power Consumption by Offloading Applications - Methods of reducing power consumption in a computing device are described in which file sharing applications which are running in the background are offloaded onto a lower power subsystem and the rest of the computing device can be put into a low power state. The lower power subsystem runs application stubs which autonomously execute a subset of the operations performed by a file sharing application which was previously running on the computing device. Before the rest of the computing device goes into the low power state, application state information is passed to the lower power subsystem for use by the application stubs. In an example, the application stub may continue to download files whilst the rest of the computing device is in standby or is shutdown and the application state information may include details of the files that are to be downloaded. | 2010-01-28 |
20100023789 | Host device with power-saving function - A card reader with power-saving function is used for being inserted with a memory card so that a computer can access the memory card through the card reader. When the memory card is inserted in the card reader, the card reader is enabled to operate. On the other hand, when the memory card is not inserted in the card reader, the card reader enters to a power-down mode for saving power. | 2010-01-28 |
20100023790 | CPU POWER MANAGEMENT BASED ON UTILIZATION WITH LOWEST PERFORMANCE MODE AT THE MID-UTILIZATION RANGE - A demand-based method and system of a processor power management is described. A processor is caused to enter a particular performance mode based on a first and a second utilization threshold. The particular performance mode includes at least a first performance mode, a second performance mode, and a third performance mode. The processor is caused to operate with a clock frequency in the third performance mode that is lower than the clock frequency of the processor in the first and second performance modes. | 2010-01-28 |
20100023791 | Process for digital, bidirectional data transmission - The invention relates to a process for digital, bidirectional data transmission between a processing unit and a position encoder, as based on the transmission of frames of a predetermined bit length, such that each frame is provided with at least an initial bit length for the transmission of data from the processing unit to the position encoder and at least a second bit length for the transmission of data from the position encoder to the processing unit; and such that the frame is provided with a time slot in which data is neither transmitted from the processing unit to the position encoder nor from the position encoder to the processing unit. In the time slot a triggering signal (external sync signal) is transmitted from the processing unit to the position encoder and this triggers the acquisition of position data. In the first bit length, a clock signal for synchronizing the processing unit and the position encoder is transmitted from the processing unit to the position encoder, and after the acquisition of position data triggered by the external sync signal, the acquired position data is transmitted from the position encoder to the processing unit. Between the transmission of two successive external sync signals at least one additional position-data request signal (internal sync signal) is transmitted from the processing unit to the position encoder, and this signal triggers another acquisition of position data, which is followed by the transmission of the acquired position data from the position encoder to the processing unit. | 2010-01-28 |
20100023792 | SIGNAL SYNCHRONIZATION METHOD AND SIGNAL SYNCHRONIZATION CIRCUIT - There is provided a signal synchronization method of performing signal synchronization between a device which operates in synchronization with a first clock signal and a processor which operates in synchronization with a second clock signal with a different cycle from that of the first signal. | 2010-01-28 |
20100023793 | APPARATUS AND METHOD FOR GENERATING A DELAYED CLOCK SIGNAL - An apparatus and method for generating a delayed clock signal is provided. The clock signal generator includes a synchronizing circuit for generating an output clock signal from an input clock signal and further includes a delay circuit having an input coupled to the output of the synchronizing circuit. The delay circuit provides an output clock signal having a delay with respect to the clock signal from the synchronizing circuit according to one of a plurality of programmable time delays selected in accordance with a selection signal. The method of generating a clock signal includes synchronizing an internal clock signal to an external clock signal, and delaying the internal clock signal different amounts based on a selection value indicative of external clock frequency to provide the clock signal. | 2010-01-28 |
20100023794 | APPARATUS AND METHOD OF GENERATING POWER-UP SIGNAL OF SEMICONDUCTOR MEMORY APPARATUS - An apparatus for generating a power-up signal of a semiconductor memory apparatus includes a first power-up signal generator that generates a first power-up signal to be activated on the basis of a comparison between a power supply voltage level supplied to the semiconductor memory apparatus and a first set voltage level, and a second power-up signal generator that generates a second power-up signal to be activated with a predetermined delay time on the basis of a comparison between the power supply voltage level and a second set voltage level. | 2010-01-28 |
20100023795 | METHOD FOR HANDLING DATA - A method for handling data in which a serial data flow, with which a plurality of data is transmitted simultaneously per line, is transmitted using a serial protocol, which is formed from data blocks and synchronization blocks. | 2010-01-28 |
20100023796 | METHODS AND DEVICES FOR TREATING AND PROCESSING DATA - A data processing unit having a field of clocked logic cells (PAEs) which is operable in different configuration states and a clock preselecting means for preselecting logic cell clocking. The clock preselecting means is designed in such a way that, depending on the state, a first clock is preselected at least at a first cell (PAE) and an additional clock is preselected at least at an additional cell. | 2010-01-28 |
20100023797 | SEQUENCING TECHNIQUE TO ACCOUNT FOR A CLOCK ERROR IN A BACKUP SYSTEM - A method, apparatus, and system of a sequencing technique to account for a clock error in a storage area network are disclosed. In one embodiment, a system of a backup server includes a processing module to examine a data timestamped with a sequence of characters denoting a time according to a clock source, an analysis module to determine that the data has been timestamped at an earlier time than an other data previously received, a substitution module to provide the data an incremental sequence number placed with the data using an algorithm until a new data is received that includes a future timestamp with a later timestamp than the timestamp of the other data, and a storage module to store the data. | 2010-01-28 |
20100023798 | ERROR RECOVERY AND DIAGNOSIS FOR PUSHDOWN AUTOMATA - Error recovery and diagnosis is afforded for pushdown automata. Upon detection of an error, a recovery strategy is selected and dispatched to recover from the error to place an automaton in an error free state to enable continued processing. In one instance, recovery strategies can be specified and matched with respect to automaton configuration. Errors can be diagnosed as a function of the difference between a first error configuration and a second recovered configuration. | 2010-01-28 |
20100023799 | DETERMINING CORRECTNESS OF JOB PLANS IN A STREAM PROCESSING APPLICATION - Embodiments of the invention provide techniques for determining the correctness of similar job plan segments in a stream processing application. In one embodiment, a job manager may be configured to identify similar job plan segments based on data formats, functionality, and surrounding processing elements. The job manager plan may be further configured to determine whether the similar segments provide inconsistent results, and if so, to determine which of the inconsistent similar segments is invalid. The job manager may identify an invalid processing element included in the invalid segment. The job manager may also perform corrective actions to address the invalid processing element. | 2010-01-28 |
20100023800 | NAND Flash Memory Controller Exporting a NAND Interface - A NAND controller for interfacing between a host device and a flash memory device (e.g., a NAND flash memory device) fabricated on a flash die is disclosed. In some embodiments, the presently disclosed NAND controller includes electronic circuitry fabricated on a controller die, the controller die being distinct from the flash die, a first interface (e.g. a host-type interface, for example, a NAND interface) for interfacing between the electronic circuitry and the flash memory device, and a second interface (e.g. a flash-type interface) for interfacing between the controller and the host device, wherein the second interface is a NAND interface. According to some embodiments, the first interface is an inter-die interface. According to some embodiments, the first interface is a NAND interface. Systems including the presently disclosed NAND controller are also disclosed. Methods for assembling the aforementioned systems, and for reading and writing data using NAND controllers are also disclosed. | 2010-01-28 |
20100023801 | Method to recover from ungrouped logical path failures - A system and method for recovering from a single logical path failure. More specifically, although a host has not grouped its logical paths, the host knows which logical paths it has available. When a host detects a logical path failure, the host enters a path discovery mode of operation. If the host continues to detect a logical path failure while operating in the logical path discovery mode of operation, the host removes the logical path from a logical path mask, and the host does not use the removed logical path again. In the case of ungrouped logical paths, the host aborts its process because it does not have more paths available to continue its process. Additionally, in certain embodiments, a pseudo path group for ungrouped logical paths is created. | 2010-01-28 |
20100023802 | Method to recover from logical path failures - A system and method for recovering from logical path failures is set forth. More specifically, when a host detects a logical path failure, the host enters a path discovery mode of operation. If the host continues to detect a logical path failure while operating in the logical path discovery mode of operation, the host removes the logical path from a logical path mask, and the host does not use the removed logical path again. Additionally, the system and method facilitates recovery of the failed logical paths by using a plurality of logical path masks. A first mask is referred to as an intermediate failure logical path mask and a second mask is referred to as a permanent failure logical path mask. | 2010-01-28 |
20100023803 | TRANSITIONAL REPLACEMENT OF OPERATIONS PERFORMED BY A CENTRAL HUB - A central hub is coupled to a plurality of computational devices. The central hub stores a data structure that grants locks for accessing common data stored at the central hub, wherein the common data is shared by the plurality of computational devices. Each computational device maintains locally those locks that are held by the computational device in the data structure stored at the central hub. In response to a failure of the data structure stored at the central hub, a selected computational device of the plurality of computational devices is determined to be a manager system. Other computational devices besides the manager system communicate to the manager system all locks held by the other computational devices in the data structure stored at the central hub. The data structure and the common data are generated and stored at the manager system. Transactions are performed with respect to the data structure stored at the manager system, until the data structure stored at the central hub is operational. | 2010-01-28 |
20100023804 | TCAM BIST WITH REDUNDANCY - A method of providing redundancy in a ternary content addressable memory (TCAM), the method including detecting a defective entry in building block in a ternary content addressable memory (TCAM), configuring a failover logic to redirect a software query toward a spare building block and away from the building block with the defective entry, and avoiding in using the building block with the defective entry. | 2010-01-28 |
20100023805 | METHOD AND SYSTEM FOR DISASTER RECOVERY BASED ON JOURNALING EVENTS PRUNING IN A COMPUTING ENVIRONMENT - A method and system for automated disaster recovery in an information technology computing system including computing resources, is provided. One implementation involves logging system events in a journaling log file, filtering the events of the log file for each resource and storing the filtered log file, reading the filtered log file, and restarting from a backup file by applying the filtered events to a backup file for recovery. | 2010-01-28 |
20100023806 | TR-069 savepoints - A method for improving the security of actions performed by Remote Procedure Calls RPC invoked during a TR-069 Remote Management Protocol session between an Auto-Configuration Server ACS and a Customer Premises Equipment CPE of a DSL telecommunication system. The TR-069 session comprises several RPC's executing actions on parameters of an object model and the method comprises the steps of
| 2010-01-28 |
20100023807 | TEST DEVICE AND METHOD FOR THE SOC TEST ARCHITECTURE - A test device for the SoC test architecture is disclosed. The device comprises plural test groups connected in parallel and a test control flag register within a controller. Each test group comprises single or plural core circuits. The test control flag register enables a set of test signals to input in one of the test groups, testing the core circuits in the test group. | 2010-01-28 |
20100023808 | TRANSACTIONAL FLOW MANAGEMENT INTERRUPT DEBUG ARCHITECTURE - According to some embodiments, a first bus may be monitored, the first bus being to exchange data between a first processing system and a second processing system. A second bus may also be monitored, the second bus being to exchange data between the second processing system and a third processing system. Responsive to the monitoring of at least one of the first or second buses, execution of applications, executing on at least two of the processing units, may be interrupted. | 2010-01-28 |
20100023809 | Memory test circuit, semiconductor integrated circuit, and memory test method - A memory test circuit includes a counter circuit that outputs a set signal that is set to the first set value or the second set value alternately in a cycle of the clock signal, an OR circuit that calculates a logical sum of the set signal and the input signal each time when the set signal is output from the counter circuit and outputs a control signal indicating the logical sum of the set signal and the input signal, and a test pattern generation circuit that generates the test pattern for causing the memory to operate in each first cycle if a set value of the control signal is the first set value, or generates the test pattern for causing the memory to operate in each second cycle if the set value of the control signal is the second set value. | 2010-01-28 |
20100023810 | METHODS, MEDIA AND SYSTEMS FOR DETECTING ANOMALOUS PROGRAM EXECUTIONS - Methods, media, and systems for detecting anomalous program executions are provided. In some embodiments, methods for detecting anomalous program executions are provided, comprising: executing at least a part of a program in an emulator; comparing a function call made in the emulator to a model of function calls for the at least a part of the program; and identifying the function call as anomalous based on the comparison. In some embodiments, methods for detecting anomalous program executions are provided, comprising: modifying a program to include indicators of program-level function calls being made during execution of the program; comparing at least one of the indicators of program-level function calls made in the emulator to a model of function calls for the at least a part of the program; and identifying a function call corresponding to the at least one of the indicators as anomalous based on the comparison. | 2010-01-28 |
20100023811 | DYNAMIC ADDRESS-TYPE SELECTION CONTROL IN A DATA PROCESSING SYSTEM - A translated address and an untranslated address associated with a same processor operation are received. An address-type indicator is provided whose value is indicative of whether the translated or untranslated address is to be used for creating a debug message. The value of the address-type indicator is selectively modified in response to occurrence of one or more selected debug events. Based at least in part on the value of the address-type indicator, the translated or untranslated address is selected. The address-type indicator may be selectively overridden to select the translated or untranslated address as the selected address based on whether a process identifier is at least one of a set of process identifiers or whether at least one of the translated or untranslated address falls within one or more predetermined address ranges. A debug message is created using at least a portion of the selected address. | 2010-01-28 |
20100023812 | DEBUG TRACE MESSAGING WITH ONE OR MORE CHARACTERISTIC INDICATORS - In a data processing system, an address associated with a processing operation is received. A modified address is generated which includes a characteristic indicator within the address at a first predetermined bit position when the characteristic indicator is of a first type or at a second predetermined bit position when the characteristic indicator is of a second type. A first value of the characteristic indicator indicates a characteristic of the address. A modified address may also be generated which includes a characteristic indicator at a first predetermined bit position when a position indicator has a first value or at a second predetermined bit position when the position indicator has a second value. Address information can then be generated from the modified address, and a debug message can be created which includes the address information. | 2010-01-28 |
20100023813 | Data Filtering Method - The invention discloses a data filtering method for filtering a 3G data stream which is received. The data filtering method according to the invention includes the following steps. At first, a step (a) of receiving a 3G data stream continually is performed. Then, a step (b) of determining whether the 3G data stream comprises a complete filtering unit is performed. If the 3G data stream comprises a complete filtering unit, a step (c) of determining whether the 3G data stream includes invalid data is performed. If the 3G data stream includes invalid data, a step (d) of marking the invalid data according to a predetermined protocol is performed. Finally, a step (e) of filtering out the marked invalid data is performed. | 2010-01-28 |
20100023814 | HANDLING OF CLUSTERED MEDIA ERRORS IN RAID ENVIRONMENT - A method, apparatus, and system of improved handling of clustered media errors in raid environment are disclosed. In one embodiment, a method includes starting a command timer when a firmware accepts a command from a host, tracking an amount of time the command spends on handling of a clustered media error through the command timer, and stopping the command timer when at least one of the command is completed and a time limit expires. The method may complete a read as a success when a host IO is a read command. The method may complete a write as a success, after writing parity, and data when the host IO may be a write command. | 2010-01-28 |
20100023815 | MANAGING APPARATUS, MANAGING METHOD, MANAGING SYSTEM AND COMPUTER PRODUCT - An apparatus accepts an injustice (grievance) report containing injustice report source terminal information for identifying a terminal device transmitting the injustice report and injustice content holding terminal information identifying a terminal device holding the content altered from the original content and content identification information for identifying the content; accesses a correspondence relation recording unit recording, in association with content identification information identifying the content, notification destination terminal information identifying a terminal device to which the content holding terminal information is notified, and content holding terminal information notified to the notified terminal device; determines that the injustice report accepted by the injustice report accepting is false and discards the false injustice report, when the injustice report source terminal information contained in the injustice report is not coincident with the notification destination terminal information recorded in the correspondence relation recording unit. | 2010-01-28 |
20100023816 | METHOD FOR DETERMINING AN ASYMMETRICAL SIGNAL LAG OF A SIGNAL PATH INSIDE AN INTEGRATED CIRCUIT - A device has at least one integrated signal path having a measurable asymmetrical signal lag and/or jitter, an output signal of the integrated signal path being able to be decoupled in a first measuring operating mode using a controllable integrated multiplexer to measure an asymmetrical signal lag of a measuring path, which includes the integrated signal path and the integrated multiplexer, and a measuring signal being able to be decoupled in a second measuring operating mode using the controllable integrated multiplexer to measure the asymmetrical signal lag of the integrated multiplexer. | 2010-01-28 |
20100023817 | TEST SYSTEM AND METHOD - A test system includes a memory device having a data I/O circuit connected to a data write-in path and a data read-out path. During test mode, the data I/O circuit retains a copy of test pattern data received in the I/O circuit via the data write-in path as output test data before the test pattern data is stored in a memory cell array as write data. The test system also includes a test device generating the test pattern data, receiving the output test data from the memory device, comparing the output test data with the test pattern data, and generating an error detection signal on the basis of the comparison. The error detection signal indicates the presence or absence of a defect in the data write-in or read-out path. | 2010-01-28 |
20100023818 | MULTIPLE ACCESS TEST ARCHITECTURE FOR MEMORY STORAGE DEVICES - A new architecture for use with computer memory storage devices is disclosed that provides means by which a memory storage device may be accessed both as standard archive file device as well as in any unique physical and native command set modes supported by the device. A system architecture for accessing a memory storage device that provides access to the storage device via a standard memory storage method while alternatively providing direct access to the full physical and functional capabilities of the storage device. The system architecture has four main elements. Firstly, a central processing system which acts as the user interface and controls access to all attached peripheral functions. Secondly, an electronic bridge connected on one side to the central processing system via a standard I/O channel and on the other side to the memory device through a memory bridge presenting the memory device to the central processing system as a standard memory peripheral. Thirdly, a second processing unit which on one side is connected to the central processing system and on the other side is connected to the memory storage device via the multiplexer thus providing the second processing unit direct access to the memory storage device. And finally, the multiplexer that can connect either the electronic memory bridge or the second processing system to the memory storage device. | 2010-01-28 |
20100023819 | Programmable Device Testing - According to some embodiments, characterization data can be loaded onto a programmable device. The characterization data can be configured to cause the programmable device to perform one or more functions if executed on the programmable device. It can then be determined whether or not loading the characterization data onto the programmable device caused the programmable device to be successfully programmed. An indication can be transmitted for receipt by an external device, the indication indicating whether or not the programmable device was successfully programmed. | 2010-01-28 |
20100023820 | Asynchronous Communication Apparatus Using JTAG Test Data Registers - An adaptation of a test data register (TDR) structure defined by the IEEE 1149.1 Joint Tag Action Group (JTAG) interface standard to provide a debugging path. Existing multi-core processor solutions are covered, but an expansion for a more generic solution is provided. In general, the present apparatus is for extending the IEEE 1149.1 JTAG standard to provide an asynchronous protocol for bypassing test circuitry and bi-directionally communicating with functional circuitry. The apparatus includes an integrated circuit having function register and JTAG standard TDR. Digital logic is configured to control the direct transfer of data between the JTAG standard TDR and the function register. | 2010-01-28 |
20100023821 | Asynchronous Communication Using Standard Boundary Architecture Cells - An adaptation of standard boundary cell architecture defined by the IEEE 1149.1 Joint Test Action Group (JTAG) interface standard to provide paths to functional circuitry via the re-use of JTAG standard test data registers (TDR) and interface. Existing multi-core processor solutions are covered, but an expansion for a more generic solution is provided. In general, an integrated circuit is provided with a plurality of function registers along with a plurality of I/O units. The I/O units are arranged in a serial communications chain located around the boundary of the integrated circuit's functional circuitry. Each of the I/O units include JTAG standard serial TDR in serial communication with adjacent I/O units. Moreover, each I/O unit includes JTAG standard parallel TDR that is associated with and in parallel communication with the I/O unit's JTAG standard serial TDR. Further still, a digital logic interface is configured to control the direct transfer of data between the JTAG standard parallel TDR and a corresponding one of the plurality of function registers. As a result of the re-use of existing boundary scan architecture, a significant reduction in wiring congestion is realized. Thus, asynchronous communication is provided without sacrificing valuable integrated circuit real estate. | 2010-01-28 |
20100023822 | IP CORE DESIGN SUPPORTING USER-ADDED SCAN REGISTER OPTION - An integrated circuit carries an intellectual property core. The intellectual property core includes a test access port | 2010-01-28 |
20100023823 | AUTOMATABLE SCAN PARTITIONING FOR LOW POWER USING EXTERNAL CONTROL - Scan architectures are commonly used to test digital circuitry in integrated circuits. The present invention describes a method of adapting conventional scan architectures into a low power scan architecture. The low power scan architecture maintains the test time of conventional scan architectures, while requiring significantly less operational power than conventional scan architectures. The low power scan architecture is advantageous to IC/die manufacturers since it allows a larger number of circuits (such as DSP or CPU core circuits) embedded in an IC/die to be tested in parallel without consuming too much power within the IC/die. Since the low power scan architecture reduces test power consumption, it is possible to simultaneously test more die on a wafer than previously possible using conventional scan architectures. This allows wafer test times to be reduced which reduces the manufacturing cost of each die on the wafer. | 2010-01-28 |
20100023824 | METHODS FOR GENERATING TEST PATTERNS FOR SEQUENTIAL CIRCUITS - A single-pass method for test pattern generation for sequential circuits employs a local-fault at each time-frame. The result is that a fault arriving at circuit primary output lines unambiguously signals the discovery of a valid test pattern sequence for the fault. The valid test pattern sequence is reconstructed from stored history and is used to test a sequential circuit. | 2010-01-28 |
20100023825 | SELF-TEST CIRCUIT FOR HIGH-DEFINITION MULTIMEDIA INTERFACE INTEGRATED CIRCUITS - A high-definition multimedia interface circuit uses a high-definition multimedia interface encoder to produce a plurality of channels of data. An output circuit, connected to the high-definition multimedia interface encoder, produces a plurality of channels of high frequency data from the data produced by the high-definition multimedia interface encoder. A multiplexer selects a channel for sampling, and a capacitive coupler capacitively couples the multiplexer to a sampling circuit. The sampling circuit produces sampled data corresponding to the high frequency data having a clock rate less than a clock rate of the high frequency data. A test circuit compares the sampled data with the data produced by the high-definition multimedia interface encoder. | 2010-01-28 |
20100023826 | CLOCK DATA RECOVERING CIRCUIT AND CONTROL METHOD OF THE CLOCK DATA RECOVERING CIRCUIT - A clock data recovering circuit solving a problem in which a stable clock signal cannot be extracted is provided. A phase comparator includes a main-signal-discriminator. The main-signal-discriminator discriminates a reception signal by a clock signal to generate recovery data indicating the discrimination result. Phase comparator | 2010-01-28 |
20100023827 | SOFT ERROR CORRECTION METHOD, MEMORY CONTROL APPARATUS AND MEMORY SYSTEM - A soft error correction method is for a memory system having memory access controllers accessing memories for storing byte-sliced data in cycle synchronism, and a system controller receiving a memory access from an arbitrary one of MPUs and issuing a memory address to the memory access controllers. When a correctable error is detected in data read from one memory, an error address where the error was detected is held within a memory access controller, and an error notification is made to the system controller from the memory access controller. In response to the error notification, the memory access controller holds the error address from the system controller without intervention from the MPUs, and reads, corrects and rewrites the data to the error address. | 2010-01-28 |
20100023828 | IP Multicast with IP Unicast/Multicast Error Correction - A method of delivering digital information includes joining a multicast group, and receiving a segment from a server directed to the multicast group. Further, the method further includes determining a transmission error has occurred resulting in an incomplete segment, and sending an error notification to the server requesting retransmission of at least a portion of the incomplete segment. Additionally, the method includes receiving a retransmission of the at least a portion of the incomplete segment. The at least a portion of the incomplete segment may be received through an IP unicast connection or as a multicast retransmission. | 2010-01-28 |
20100023829 | METHOD AND APPARATUS FOR SELECTIVE ACKNOWLEDGEMENT - The present invention pertains to the field of data communications and is directed to providing ways and means for flexible receipt reporting. A transceiving unit ( | 2010-01-28 |
20100023830 | LINK ADAPTATION DEPENDENT CONTROL SIGNALING - The invention relates to a method and apparatus for providing an improved scheme for encoding control information for transmitting user data. Further the method and apparatus may allow for reducing the control signaling overhead. These advantages may be achieved by interpreting information on at least one link adaptation parameter for transmitting the user data to determine the at least one link adaptation parameter for transmitting the user data, wherein the at least one link adaptation parameter for transmitting the user data is comprised in control signaling. According to the invention the interpretation of the information depends on at least one link adaptation parameter employed for transmitting the control signaling. | 2010-01-28 |
20100023831 | METHOD AND DEVICE FOR ALLOCATING RESOURCES IN WIRELESS COMMUNICATION SYSTEM - The present invention relates to a resource allocation device for minimizing delay of an uplink retransmission resource allocation process in a wireless communication system having a high data rate, and a method thereof. In the method, user data are received and an ACK/NACK state of the received data is determined, and when the NACK state of the received data is determined, retransmission resource allocation is requested, retransmission resources are allocated, and retransmission resource allocation information is generated to be transmitted. | 2010-01-28 |
20100023832 | DATA ACKNOWLEDGEMENT - A method for generating acknowledgement messages in a data transmission system having a receiver for receiving datagrams and being capable of determining which of a series of datagrams have been incorrectly received, the method comprising generating a plurality of a data units, each data unit comprising: a status bit indicative of the status of the data unit; and a plurality of spacing bits together forming a binary representation of a number at least partially indicative of the spacing between one incorrectly received datagram and a succeeding incorrectly received datagram. Apparatus for carrying out various aspects of the methods are also provided. | 2010-01-28 |