04th week of 2011 patent applcation highlights part 61 |
Patent application number | Title | Published |
20110022843 | SECURITY IN A MOBILE COMMUNICATION SYSTEM - When a mobile terminal ( | 2011-01-27 |
20110022844 | AUTHENTICATION SYSTEMS AND METHODS USING A PACKET TELEPHONY DEVICE - Packet telephony devices with encryption keys are configured to enable authentication systems and methods for increasing the security of online account access and transactions. The instant disclosure leverages the security in customer equipment hardware such as a terminal adaptor (TA) or router to authenticate a web transaction. A packet telephony device has an encoded encryption key. The encryption key may be used with a display, a user actuable trigger or in a secure connection with a web-enabled device to authenticate a user or a website. | 2011-01-27 |
20110022845 | METHOD AND DEVICE FOR ISSUING A DIGITAL RESIDENCE CERTIFICATE - A method for issuing a digital residence certificate using a module associated with a counter. Data from the counter are continuously monitored, whereby the data are read and a consistency test is performed on the basis of a predetermined criterion. In addition, after receiving a residence certificate request, a decision is made as to whether or not the request should be fulfilled, based on the results of the continuous data monitoring. | 2011-01-27 |
20110022846 | Systems and Methods for Secure Transaction Management and Electronic Rights Protection - The present invention provides systems and methods for secure transaction management and electronic rights protection. Electronic appliances such as computers equipped in accordance with the present invention help to ensure that information is accessed and used only in authorized ways, and maintain the integrity, availability, and/or confidentiality of the information. Such electronic appliances provide a distributed virtual distribution environment (VDE) that may enforce a secure chain of handling and control, for example, to control and/or meter or otherwise monitor use of electronically stored or disseminated information. Such a virtual distribution environment may be used to protect rights of various participants in electronic commerce and other electronic or electronic-facilitated transactions. Distributed and other operating systems, environments and architectures, such as, for example, those using tamper-resistant hardware-based processors, may establish security at each node. These techniques may be used to support an all-electronic information distribution, for example, utilizing the “electronic highway.” | 2011-01-27 |
20110022847 | DATA PROCESSING APPARATUS AND METHOD - Generating a cryptographic key, for example using a received external key. A system to generate a cryptographic key may include a first data store which may store an authorization key. A system may include a second data store which may store a secure key and/or a public key. A system may include an access controller, which may allow access to a secure key, for example to an access request which may be accompanied by a digital signature. A system may include a key generator, which may generate a private key, for example using a received external key, a stored authorization key and/or a mapping function. A system may include an access request signal generator which may generate a digital signature and/or which may transmit an access request, for example including a generated digital signature, to an access controller to retrieve a secure key. | 2011-01-27 |
20110022848 | Method and Apparatus for Storing Confidential Information - Techniques for securely storing confidential information associated with a transaction are disclosed. An method for securely storing confidential information may include storing a data set related to a first transaction in a first server, the data set configured to be searchable by an authorized administrator, storing a plurality of encrypted files that include confidential information related to a plurality of transactions in a second server, including a first encrypted file that includes confidential information related to the first transaction, storing an identifier for the first encrypted file, where the identifier is configured to include at least one key required to access the confidential information related to the first transaction, linking the data set to the identifier, and limiting the access to the plurality of encrypted files by the administrator. | 2011-01-27 |
20110022849 | SYSTEM AND METHOD FOR SECURELY STORING INFORMATION - A system and method for storing information on a storage device is disclosed. An encrypted version of the information is stored on a storage device. The information is inspected in order to determine whether it may be stored on the storage device. If the information may be stored on the storage device then the stored encrypted version is decrypted, otherwise it is deleted. Other embodiments are described and claimed. | 2011-01-27 |
20110022850 | ACCESS CONTROL FOR SECURE PORTABLE STORAGE DEVICE - A secure portable storage device includes a control module. When a host sends a first key to the control module with a write command so as to command the control module to write the first key into a redirecting file, the control module stores the first key in a temporary working buffer and verifies whether the first key is valid; when the first key is valid, the control module sends a second key and an encrypted content data to the host for generating a third key by decrypting the second key according to the first key and decrypting the encrypted content data into a content data according to the third key. Moreover, when the host sends multiple read commands to the control module in sequence, the control module verifies whether a sequence of the read commands received is valid and sends the second key and the encrypted content data to the host for an encryption. Related apparatuses, methods and techniques also are provided. | 2011-01-27 |
20110022851 | DATA ENCRYPTION DEVICE - A portable data sensor tag ( | 2011-01-27 |
20110022852 | CRYPTOGRAPHIC COMPUTATION APPARATUS, CRYPTOGRAPHIC COMPUTATION PROGRAM, AND STORAGE MEDIUM - A flowchart shows a general processing procedure of cryptographic computation executed by a cryptographic computation apparatus | 2011-01-27 |
20110022853 | ENCRYPTING DATA IN VOLATILE MEMORY - Provided are a computer program product, system, and method to allocate blocks of memory in a memory device having a plurality of blocks. At least one unencrypted memory allocation function coded in an application is executed to request allocation of unencrypted blocks in the memory device. An encrypted memory allocation function coded in the application is executed to request allocation of encrypted blocks in the memory device. At least one unencrypted Input/Output (I/O) request function coded in the application indicating an I/O operation to perform against the unencrypted blocks in the memory device is executed. At least one encrypted I/O request function coded in the application indicating an I/O operation to perform against the encrypted blocks in the memory device is executed. An operating system uses an encryption key associated with the encrypted blocks to encrypt or decrypt data in the encrypted blocks to perform the encrypted I/O operation in response to processing the encrypted I/O request functions, wherein the unencrypted and encrypted memory allocation functions and unencrypted and encrypted I/O request functions comprise different functions in a library of functions available to the application. | 2011-01-27 |
20110022854 | Processor-implemented method for ensuring software integrity - The present invention provides a solution to the problem of guaranteeing the integrity of software programmes by encrypting all or part of each instruction of a programme using a key based on all or part of one or a plurality of previous instructions, thus resulting in a different encryption key per instruction. The invention is applicable to software programmes whose structures are not necessarily tree-like in nature and is also applicable when the programme includes loops, jumps, calls or breaks etc. The invention allows for an exception to be flagged when an encrypted instruction is wrongly decrypted. There is no need for the first instruction to be in clear, since the instruction key may be appropriately initialised as required. The invention can be realised in software or entirely in hardware thereby eliminating the possibility of a third party intercepting a decrypted instruction or a decryption key. | 2011-01-27 |
20110022855 | SYSTEM AND METHOD FOR THWARTING BUFFER OVERFLOW ATTACKS USING ENCRYPTED PROCESS POINTERS | 2011-01-27 |
20110022856 | Key Protectors Based On Public Keys - In accordance with one or more aspects, a key protector for a storage volume is created by generating an intermediate key and protecting, based at least in part on a public/private key pair, the intermediate key. A volume master key for encrypting and decrypting one or more volume encryption keys that are used to encrypt the storage volume can be encrypted in different manners, including being encrypted based at least in part on the intermediate key. A key protector for the storage volume is stored that includes both the encrypted volume master key and information indicating how to obtain the intermediate key. Subsequently, the key protector can be accessed and, based at least in part on a private key of the entity associated with the key protector, the intermediate key can be decrypted. The intermediate key can then be used to decrypt the volume master key. | 2011-01-27 |
20110022857 | THROTTLING COMPUTATIONAL UNITS ACCORDING TO PERFORMANCE SENSITIVITY - A power allocation strategy limits performance of a subset of a plurality of computational units in a computer system according to performance sensitivity of each of the plurality of computational units to a change performance capability, e.g., frequency change. The performance of the subset of computational units may be limited by setting a power state in which the subset may be operated and/or reducing a current power state of the subset to a lower power state. The subset whose performance is limited includes computational units that are least performance sensitive according to stored sensitivity data. The subset may include one or more processing cores and performance of the one or more processing cores may be limited in response to a CPU-bounded application or graphics processing unit (GPU)-bounded application being executed. | 2011-01-27 |
20110022858 | CONTROL CIRCUIT FOR POWER SUPPLYING - The control circuit for power supplying includes a driving module and a control module, wherein the driving module includes a first switch, a second switch, a third switch, and a fourth switch. In a first power supply mode, the first switch and the second switch are turned on, and the third switch and the fourth switch are turned off. The load current flows to the ground terminal via the first switch, the inductive load, and the second switch. When the control module sends a switching signal to the driving module, the first switch and the second switch are turned off and the third switch and the fourth switch are turned on, and the load current flows to the high potential terminal via the fourth switch, the inductive load, and the third switch due to the current inertia. | 2011-01-27 |
20110022859 | POWER MANAGEMENT APPARATUS AND METHODS - Power management integrated circuits (PMICs) and related methods. In one aspect a PMIC which is operable to provide a plurality of PMIC power states is arranged to provide a predetermined delay before a power state transition. The delay is applied after receipt by the PMIC control circuitry of a power state transition command. Applying a delay allows time for the system powered by the PMIC to perform any necessary shut-down procedures and terminate active processes before power is removed, preventing corruption of the system. The delay is preferably configurable. The PMIC may also be arranged to control power converters which are external to the PMIC. In another aspect the PMIC has translation circuitry for providing the control settings of one power block, e.g. power converter, with any necessary modifications to be used by another power block. This means that only one set of control settings needs to be updated to change the output of both power blocks simultaneously. | 2011-01-27 |
20110022860 | TECHNIQUES FOR MEASURING NETWORK CHANNEL RESISTIVE LOSS BETWEEN A POWER-SOURCING APPARATUS AND A POWERED DEVICE - A method and apparatus are provided for determining resistive power loss through a channel between Power Sourcing Equipment (PSE) and a Powered Device (PD). The method includes ( | 2011-01-27 |
20110022861 | REDUCING POWER CONSUMPTION IN DATA CENTERS HAVING NODES FOR HOSTING VIRTUAL MACHINES - According to an aspect of the present invention, nodes for hosting of new virtual machines (VM) are selected according to approaches designed to reduce power consumption in a grid. In an embodiment, the approaches are designed to facilitate the possibility of freeing one or more nodes from hosting VMs to power down the nodes, thereby reducing power consumption. Thus, an example approach is based on provisioning a new VM on a node which currently (immediately prior to provisioning) has the maximum resource consumption. Another example approach is based on provisioning a new VM on a node which currently has small-sized VMs in terms of resource requirements. In yet another embodiment, the approach is based on provisioning a new VM on a node located in a geographical area having low power tariffs. | 2011-01-27 |
20110022862 | POWER SUPPLY DEVICE, AND REMOTE CONTROL DEVICE THEREOF - A disclosed power supply device includes a power supply unit configured to switch supply or non-supply of power from an external power supply to an electronic apparatus, and a receiving unit configured to receive a control command for controlling the switching with the power supply unit from a remote controller. | 2011-01-27 |
20110022863 | ELECTRONIC APPARATUS HAVING REDUCIBLE POWER CONSUMPTION IN THE READINESS STATE - Method for an electronic device (IT) that is controllable in at least one operating state (OP) and one standby state (SBY), with which a main processing unit (MPU) controls the operating state (OP) and a preprocessing unit (PPU) controls the standby state (SBY), such that, by means of the preprocessing unit (PPU), the main processing unit (MPU) and, to some extent, the functional units of the electronic device (IT) that are implemented by circuitry are switched by the control into at least one state having reduced energy consumption. An advantage can be seen in the fact that, by using a preprocessing unit (PPU), in the operating state of “standby” (SBY) the total energy consumption of the electronic device (IT) is reduced, both due to the significantly reduced energy consumption of a preprocessor (PPE) in the preprocessing unit (PPU) and to the units (MPU) that have been switched by the control into a state having reduced energy consumption, and the electronic device can therefore be operated more economically. An additional advantage is that the reduction of the energy consumption is achieved exclusively by circuitry measures and that no implementations must be included in the programs of the electronic device (IT). | 2011-01-27 |
20110022864 | REAL-TIME CLOCK - A real-time clock circuit, comprising: an oscillator; and a counter, coupled to an output of the oscillator, for generating a real-time clock value. In a first mode the oscillator is configured to generate oscillations and the counter is configured to increment the real-time clock value based on the oscillations. In a second mode the oscillator is stopped, and the counter is configured to retain the real-time clock value at a frozen value. | 2011-01-27 |
20110022865 | INDEPENDENT POWER CONTROL OF PROCESSING CORES - Independent power control of two or more processing cores. More particularly, at least one embodiment of the invention pertains to a technique to place at least one processing core in a power state without coordinating with the power state of one or more other processing cores. | 2011-01-27 |
20110022866 | METHOD AND APPARATUS FOR THERMAL SENSITIVITY BASED DYNAMIC POWER CONTROL - A method and system provides dynamic power control based on thermal sensitivity of a processor system. The method and system includes a circuit that reduces the clock frequency for the processor system in response to thermal characteristics satisfying a pre-determined threshold that allows maximal thermal temperature limit utilization without substantially degrading processor performance. | 2011-01-27 |
20110022867 | APPARATUS AND METHOD FOR REDUCING THE STANDBY POWER CONSUMPTION OF A DISPLAY, AND DISPLAY WITH LOW STANDBY POWER CONSUMPTION - A display includes a power supply system using a power controller to switch a power switch to control power delivery, and an image scalar receiving a supply voltage and a supply current from the power supply system. An apparatus and method are proposed to determine a control signal in a standby mode by monitoring the supply voltage or the supply current, to wake up or turn off the power controller to reduce the switching times of the power switch in the standby mode, thereby reducing the switching loss of the power switch and the standby power consumption of the display. | 2011-01-27 |
20110022868 | Systems and Methods for Managing Power Consumption and Performance of a Processor - Processor-management techniques that purposely alternate a processor between an operating state and a non-operating state while the processor is executing the workload. The techniques leverage the “ultra-low-power” non-operating states of many processors to provide predictable power and/or frequency control of the processor. These techniques can provide better performance than known clock-throttling and dynamic voltage and frequency scaling schemes for controlling processors. | 2011-01-27 |
20110022869 | DEVICE HAVING MULTIPLE INSTRUCTION EXECUTION MODULES AND A MANAGEMENT METHOD - A multiple instruction execution modules device that comprises a first instruction execution module and a second instruction execution module and a context switch controller; wherein the first instruction execution module is logically identical to the second instruction execution module but substantially differs from the second instruction execution module by at least one power consumption characteristic; wherein the context switch controller controls a context switch between the first instruction execution module and the second instruction execution module; wherein an instruction execution module that its context has been transferred is shut down. | 2011-01-27 |
20110022870 | COMPONENT POWER MONITORING AND WORKLOAD OPTIMIZATION - A component level power monitoring system may analyze workloads by determining energy consumed by individual components for the workload. By comparing different system configurations or by modifying the software operation, an optimized workload may be performed per energy consumed. In some embodiments, several system configurations may be attempted to determine an optimized system configuration. In other embodiments, a monitoring system may change how an application is executed by changing thread affinity or otherwise assigning certain operations to specific components. The component level monitoring may be implemented as operating system level function calls. | 2011-01-27 |
20110022871 | System-On-Chip Queue Status Power Management - A system and method are provided for using queue status to manage power in a system-on-chip (SoC). Messages to be processed are accepted in an SoC with a plurality of selectively enabled processors, and queued. The message traffic can be from an external source via an input/output (IO) interface, or intra-SoC messages between processors. The number of queued messages is monitored and, in response to the number of queued messages exceeding a subscription threshold, one or more processors are enabled. Then, the queued messages are distributed to the enabled processors. Enabling a processor is defined by an action such as supplying power to an unpowered processor, increasing the power supply voltage levels to a processor, increasing the operating frequency of a processor, or a combination of the above-mentioned actions. Likewise, processors can be disabled in response to the number of queued messages falling below the subscription threshold. | 2011-01-27 |
20110022872 | Apparatus for and method of generating a time reference - In one embodiment, a system is configured to generate a time reference where the system includes a bi-directional loop configured to have a first propagation speed in a first direction and a second propagation speed in a second direction, wherein the first propagation speed is substantially equal to the second propagation speed. In one embodiment, the system further includes a plurality of system elements coupled to the bi-directional loop, wherein each respective system element of the plurality of system elements is configured to determine a time reference common to each as an average arrival time at the respective system element of a first signal transmitted in the first direction over the bi-directional loop and a second signal transmitted in the second direction over the bi-directional loop. | 2011-01-27 |
20110022873 | SYSTEM WITH POWER SAVING DELAY LOCKED LOOP CONTROL - The delay locked loop (“DLL”) delay interval can be locked to stop the DLL from wasting power in unnecessarily switching to synchronize the device with the DLL is associated to the system clock. This is achieved by adding logic sensing when a DRAM device will not imminently be called upon to output data and when the device has stabilized. Waiting for the DLL delay interval to stabilize before locking the delay interval still allows the DLL to immediately and effectively resume operations when the DLL is needed to synchronize the output of the DRAM device with the system clock. The DLL delay interval can be locked, together with the DLL clock, after the DRAM device is deselected by the chip select control line, after a number of no operation commands have been received, and/or after any command issued to the DRAM device has been completed. | 2011-01-27 |
20110022874 | DATA PROCESSING SYSTEM AND ADJUSTING METHOD THEREOF - A data processing system and an adjusting method thereof are disclosed. The data processing system includes a processor, a clock generator, a monitoring module and a determining module. When a target program is processed, the monitoring module monitors a first loading level of the processor, and transmits the first loading level to the determining module for recording. Furthermore, when a present program is processed, the monitoring module monitors a second loading level of the processor, and transmits the second loading level to the determining module. The determining module determines whether the second loading level matches with the first loading level within a preset period, and if it matches, the determining module generates and transmits a control signal to the clock generator, thereby making the clock generator generates a first clock signal to the processor, so as to increase the operating frequency of the processor. | 2011-01-27 |
20110022875 | Integrated Circuit with Interpolation to Avoid Harmonic Interference - An integrated circuit (IC) includes a clock circuit, a processing module, and processing circuitry. The clock circuit is coupled to produce a digital clock signal. The processing module is coupled to determine whether a harmonic component of the digital clock signal having a nominal digital clock rate is within the frequency passband and to provide an indication to the clock circuit to adjust its rate from the nominal digital clock rate to an adjusted digital clock rate when the harmonic component of the digital clock signal is within the frequency passband. The processing circuitry is coupled to process, at the adjusted digital clock rate, the data to produce processed data having a rate corresponding to the nominal digital clock rate and to interpolate, at an interpolation rate, the processed data to produce interpolated processed data having a rate corresponding to the interpolation rate. | 2011-01-27 |
20110022876 | COMPUTER SYSTEM AND OPERATING METHOD THEREOF - A computer system is provided with an event counter, a CPU, a memory, an external device, a hub M | 2011-01-27 |
20110022877 | PWM TIMER FOR POWER SUPPLY - A forward converter circuit includes a transformer having a primary winding and a secondary winding. A first transistor is coupled in series with the primary winding and a second transistor is coupled in series with the secondary winding. A control circuit generating control signals for controlling operation of the first and second transistors. The control signals are generated responsive to the values in certain triggered counting circuits satisfying programmable thresholds. | 2011-01-27 |
20110022878 | Configuring Multi-Bit Slave Addressing on a Serial Bus Using a Single External Connection - Unique addresses for a plurality of devices may be programmed through a single external connection (pin) on each device by using a one of a plurality of different analog voltage or current values on the single external pin in combination with a serial clock of a serial data bus for each device requiring a unique binary address. The unique binary address is stored in the device after detection of certain number of clocks on the serial data bus. Once the unique binary address has been stored in the device, the single external connection may be used for another purpose such as a multifunction external connection. This unique binary address may be retained by the device until a power-on-reset (POR) or general reset condition occurs. Address detection and address load commands on the serial bus may also perform the same address definition and storage functions. | 2011-01-27 |
20110022879 | AUTOMATED DISASTER RECOVERY PLANNING - A system and associated method for automated disaster recovery (DR) planning. A DR planning process receives disaster recovery requirements and a target environment configuration from a user to design DR plans for the target environment configuration that meets disaster recovery requirements. The DR planning process accesses a knowledgebase containing information on replication technologies, best practice recipes, and past deployment instances. The DR planning process creates the DR plans by analyzing the disaster recovery requirements into element risks, associating replication technologies to protect each element risks, combining associated replication technologies based on the best practice recipes, and selecting highly evaluated combination based on the past deployment instances. The DR planning process presents the DR plans as classified by replication strategy-architecture combination for each DR plans and marks how strongly each DR plans are recommended. | 2011-01-27 |
20110022880 | Enabling Existing Desktop Applications To Access Web Services Through The Use of a Web Service Proxy - The present invention enables desktop applications to access web services through Plug-ins and a Web Service Proxy Server. An administrator registers a web service by providing the URL of the WSDL file of the web service. The target desktop applications and the operations are identified using the WSDL file. Operations that are not compatible with the desktop applications are removed from a published list of operations. The administrator appends additional formatting information, communication standards and security policies to the WSDL file. A user accessing the web services is first authenticated and authorized. Thereafter, the user accesses the web services through Web Service Proxy Server. The communication with the web services complies with the standards and security policies specified in the WSDL files. The output data obtained from the web services are presented using template documents. These template documents are generated based on the formatting information provided in the WSDL files. | 2011-01-27 |
20110022881 | DISTRIBUTED RESOURCE MANAGING SYSTEM, DISTRIBUTED RESOURCE MANAGING METHOD, AND DISTRIBUTED RESOURCE MANAGING PROGRAM - A distributed resource managing system has one or more resource managing processes corresponding to each of predefined events that change the states of resources, on a communication network where each of a plurality of tasks can use a plurality of resources. Each of the one or more resource managing processes includes an assignor which, when it receives a request to protect any specific task against the event that changes states of resources to which its own process corresponds, assigns backup resources including a resource already selected by another resource managing process to the task in such a way that all tasks requested to be protected which use the resource can be protected from the event that changes the states of the resources, and an indicator which indicates information of the assigned backup resources to one or more recovery execution processes. | 2011-01-27 |
20110022882 | Dynamic Updating of Failover Policies for Increased Application Availability - Mechanisms are provided for performing a failover operation of an application from a faulty node of a high availability cluster to a selected target node. The mechanisms receive a notification of an imminent failure of the faulty node. The mechanisms further receive health information from nodes of a local failover scope of a failover policy associated with the faulty node. Moreover, the mechanisms dynamically modify the failover policy based on the health information from the nodes of the local failover scope and select a node from the modified failover policy as a target node for failover of an application running on the faulty node to the target node. Additionally, the mechanisms perform failover of the application to the target node based on the selection of the node from the modified failover policy. | 2011-01-27 |
20110022883 | Method for Voting with Secret Shares in a Distributed System - A replicated decentralized storage system comprises a plurality of servers that locally store disk images for locally running virtual machines as well as disk images, for failover purposes, for remotely running virtual machines. To ensure that disk images stored for failover purposes are properly replicated upon an update of the disk image on the server running the virtual machine, a hash of a unique value known only to the server running the virtual machine is used to verify the origin of update operations that have been transmitted by the server to the other servers storing replications of the disk image for failover purposes. If verified, the update operations are added to such failover disk images. To enable the replicated decentralized system to recover from a failure of the primary server, the master secret is subdivided into parts and distributed to other servers in the cluster. Upon a failure of the primary server, a secondary server receives a threshold number of the parts and is able to recreate the master secret and failover virtual machines that were running in the failed primary server. | 2011-01-27 |
20110022884 | DEFENSE COMMUNICATION MODE FOR AN APPARATUS ABLE TO COMMUNICATE BY MEANS OF VARIOUS COMMUNICATION SERVICES - An appliance communicates via a communication network via various communication services available for transmitting data via said communication network, said appliance comprising means of: detecting an anomaly in a communication that is established with said appliance via one of said communication services, implementing a defense communication mode, wherein the communications to be established with said appliance via a communication service for which a detection has occurred are inhibited, the communications to be established via another communication service being allowed. | 2011-01-27 |
20110022885 | Methods and Equipment for Fault Tolerant IP Service - An Internet Protocol (IP) terminal, comprises communication means for communicating via an IP network, a processor and memory. The memory contains an operating software for the IP terminal and the processor is configured to execute the operating software. The operating software comprises a normal mode logic for implementing a normal mode operation and a restricted mode logic for implementing a restricted mode operation. The normal mode logic comprises program code for initiating a call of a first type under control of instructions from one or more dedicated servers. The restricted mode logic comprises program code for collecting connection information of other IP terminals and for initiating a call of a second type without instructions from the one or more dedicated servers. | 2011-01-27 |
20110022886 | DATA STORAGE DEVICE AND DATA READ METHOD - The invention provides a data read method. First, a training sequence stored in a storage unit of a memory is read according to at least one sense voltage to obtain a read-out training sequence. Whether the read-out training sequence is correct is then determined. When the read-out training sequence is not correct, the sense voltage is adjusted. | 2011-01-27 |
20110022887 | VIRTUAL COMPUTER SYSTEM AND CONTROL METHOD THEREOF - When a failure occurs in an LPAR on a physical computer under an SAN environment, a destination LPAR is set in another physical computer to enable migrating of the LPAR and setting change of a security function on the RAID apparatus side is not necessary. When a failure occurs in an LPAR generated on a physical computer under an SAN environment, configuration information including a unique ID (WWN) of the LPAR where the failure occurs is read, a destination LPAR is generated on another physical computer, and the read configuration information of the LPAR is set to the destination LPAR, thereby enabling migrating of the LPAR when the failure occurs, under the control of a management server. | 2011-01-27 |
20110022888 | INFORMATION PROCESSING APPARATUS, CONTROL METHOD OF THE INFORMATION PROCESSING APPARATUS, AND RECORDING MEDIUM - An information processing apparatus connecting a plurality of hard disks rebuilds data stored in one hard disk of the plurality of hard disks to another hard disk of the plurality of hard disks. The information processing apparatus is controlled in such a manner that when the information processing started, the rebuild is not resumed immediately after the information processing apparatus is started, and the rebuild is resumed after a predetermined time has elapsed. | 2011-01-27 |
20110022889 | DISK ARRAY APPARATUS AND PHYSICAL DISK RESTORATION METHOD - The invention provides a disk array apparatus and a physical disk restoration method for managing a used area and an unused area of a faulty physical disk and shortening the time required for the physical disk to become usable by an external unit. The disk array apparatus includes: a unit for determining whether block areas of the physical disk are used areas or unused areas; a unit for recovering data in relation to block areas determined to be used areas and writing the recovered data to block areas of a spare disk corresponding to the used areas; a unit for transmitting a notification that the physical disk is usable to a host apparatus when data recovery is completed; and a unit for writing zero data to block areas of the spare disk corresponding to block areas determined to be unused areas after transmitting the notification. | 2011-01-27 |
20110022890 | CLOCK AND DATA RECOVERY CIRCUIT WITH ELIMINATING DATA-DEPENDENT JITTERS - The present invention relates to a clock and data recovery circuit (CDR), and in particular, to a CDR circuit in a full digital scheme which cancels the data-dependent jitter. A DDJ cancellation circuit according to the present invention efficiently cancels the data-dependent jitter, making it possible to configure the reliable clock and data recovery circuit in the serial link data communication through the channel of the predetermined bandwidth. | 2011-01-27 |
20110022891 | Method for the Generation of a Set of Conflicts for Model-Based System Diagnostics, and Corresponding Diagnostic Method - A method for the generation of a set of conflicts for model-based system diagnostics is described, with which system a plurality of sensors is associated for the observation of variables indicative of operation conditions. | 2011-01-27 |
20110022892 | AUTOMATIC TESTING APPARATUS - The present invention relates to an automatic testing apparatus, which comprises a device under test and a testing module. The device under test has a testing program and includes a plurality of functional modules. The testing module is coupled to the device under test. The device under test executes a testing program and communicates with the testing module so that the testing module can test the plurality of functional modules of the device under test. By adopting automatic testing, no tester is needed for performing testing. Thereby, the personnel cost can be reduced and the total testing time can be shortened. | 2011-01-27 |
20110022893 | DETECTING DATA RACE AND ATOMICITY VIOLATION VIA TYPESTATE-GUIDED STATIC ANALYSIS - Mechanisms for analyzing computer instructions implementing a program in which typestate analysis is informed by concurrency analysis. The concurrency-guided typestate analysis may simulate the “worst case” scenario due to thread interleaving by transitioning a simulated state of the variable to a special state whenever the variable is not guarded by its intended guarding lock. While in the special state, the analysis may assume that the state of the simulated variable is the worst possible state with respect to processing operations that may lead to an error depending on the state of the variable. Thus, the analysis performed may assume that referencing the variable in a state-dependent operation while the simulated state of the variable is in the special state may lead to an error, and the analysis may generate a warning, accordingly. The analysis may process the computer instructions to infer which lock is intended to guard a shared variable. | 2011-01-27 |
20110022894 | METHOD AND SYSTEM FOR DETERMINING AN INDIVIDUAL FAILURE RATE FOR THE EVALUATION OF AN INDIVIDUAL COMPLEX TECHNICAL OPERATING EQUIPMENT - A method and a system are disclosed for determining an individual failure rate for at least one individual technical operating equipment. For the calculation, a data processing unit receives not only the statistical data and characteristics specific for the type of the technical operating equipment, but also valid characteristic data for the individual technical operating equipment are used. Furthermore, additional characteristic values are used that are derived from information about influences by the site of use and the mode of operation of the individual technical operating equipment in an industrial plant. On the basis of the operating equipment type-specific data, an individualized average failure rate can be formed. Characteristic values associated with the individual operating equipment are used for forming a correcting factor. By linking the average failure rate to the correction factor, the individual failure rate is calculated. | 2011-01-27 |
20110022895 | Software Component Self-Scrubbing - Software components “self-scrub” to improve software reliability, serviceability and availability (RAS). Each component designates a routine to perform a component level consistency check on major data structures and to verify the state of component. This is performed as an on-going task during the life of the component. The component registers an entry point with the system to receive notification of scrubbing parameter changes. The entry point is also called with the request to perform component-scrubbing operations. The entry point functions are responsible for executing within limitations on central processing unit (CPU) usage and memory footprint when performing scrubbing operations. | 2011-01-27 |
20110022896 | METHODS AND SYSTEMS FOR FIRST OCCURENCE DEBUGGING - An embodiment relates generally to an apparatus for debugging. The apparatus includes a memory configured to store data and an arithmetic logic unit configured to perform logical and arithmetic operations. The apparatus also includes a control unit configured to interface with the memory and arithmetic logic unit and to decode instructions. The control unit is configured to write a data state designated to be overwritten by a currently executing instruction to a buffer allocated in the memory in response to a trace debug flag being set. | 2011-01-27 |
20110022897 | MICROCONTROLLER DEVICE, MICROCONTROLLER DEBUGGING DEVICE, METHOD OF DEBUGGING A MICROCONTROLLER DEVICE, MICROCONTROLLER KIT - A microcontroller device comprising a receiver component configured to receive a one or more reset signals for the microcontroller device; an identification component configured to identify a source of the or each reset signals received by the receiver component; a time interval determining component configured to determine a length of a time interval in accordance with the identified source of the or each reset signals received by the receiver component; a voltage setting component configured to set a voltage of an output of the microcontroller device to a first value on receipt of a reset signal by the receiver component; and a control component configured to maintain the voltage of the output at the first value for the duration of the determined length of the time interval; and set the voltage of the output to a second value on substantial completion of the determined length of the time interval. | 2011-01-27 |
20110022898 | NON-VOLATILE MEMORY SYSTEM WITH SELF TEST CAPABILITY - In a non-volatile memory system, test data may be retrieved by means of a circuit without the help of firmware. The circuit is triggered into action when it detects an abnormality in the processor or host interface. In such event, it formats the self test or status signals from the various blocks in the non-volatile memory system controller and sends a test message to the outside world without the assistance of the system processor or interface controller. When implemented in memory systems with multiple data lines, only one of the data lines may be utilized for such purpose, thereby allowing the testing to be performed while the system is still performing data transfer. Preferably, the system includes the test mode communication controller, which can select between a test channel and a host interface channel for the test message transfer so that the same testing may be performed when the memory system is in the test package as well as in an encapsulated package. The test message is transmitted repeatedly and the test message is structured so that it is easier for the receiver host to decipher the message without a handshake with the memory system. A communication controller preferably detects whether any of the communication channels is not used by the controller of a non-volatile memory system for sending signals and sends diagnostic signals through such channel. | 2011-01-27 |
20110022899 | PRODUCING OR EXECUTING A SCRIPT FOR AN OPERATION TEST OF A TERMINAL SERVER - A method of or system for producing or executing a script for a load test of a terminal server. During execution of a high-level application by the terminal server controlled by a user of a terminal client in which the terminal client and terminal server communicate according to remote-desktop protocol, a terminal-services agent on the terminal server may monitor a change in at least one window of the high-level application within a terminal-client desktop of the terminal client. Window-related information corresponding to the monitored change from the terminal-services agent may be sent to an operation-test tool resident on the terminal client. The operation-test tool may log the received window-related information. | 2011-01-27 |
20110022900 | SYSTEM AND METHOD FOR MULTI-LAYER NETWORK ANALYSIS AND DESIGN - Techniques for providing a method and system for multi-layer network analysis and design are disclosed. In one particular exemplary embodiment, the techniques may be realized as a method, comprising determining, using a computer model of a network, a minimum probability of failure path between a pair of network nodes at a first network layer for one or more pairs of network nodes, calculating, using a processor and stored network data, a value for the minimum probability of failure for the identified minimum probability of failure path between the pair of network nodes at the first network layer for the one or more pairs of network nodes. The method may include identifying a maximum of the determined minimum probability of failure values for the one or more pairs of network nodes for the first network layer. The method may include probability of failure calculations for one or more secondary network layers. | 2011-01-27 |
20110022901 | METHOD FOR TESTING HARD DISKS UNDER AN EXTENSIBLE FIRMWARE INTERFACE - A method for testing hard disks under an extensible firmware interface (EFI) provides a device tree of hard disks. Nodes of the device tree represent block devices or file systems of the hard disks. Devices paths and handles corresponding to each of the device paths are obtained from the device tree. Parent controller handles of each of the device paths are obtained. If there are parent controller handles the same as the obtained handles, the parent controller handles the same as the obtained handles are deleted. The computer determines that a number of the hard disks is equal to a number of the device paths corresponding to the remained parent controller handles. Nodes information of each of the device paths corresponding to the remained parent controller handles are determined as hard disk information of each of the hard disks. | 2011-01-27 |
20110022902 | DOCUMENT ANALYSIS, COMMENTING, AND REPORTING SYSTEM - A document analysis, commenting, and reporting system provides tools that automate quality assurance analysis tailored to specific document types. As one example, the system may implement state machines that evaluate document structure instances to determine whether the document structure instances conform to pre-defined syntaxes. The state machines may include error states and final states, and messages may be associated with the error states for display when a state machine reaches the error state, | 2011-01-27 |
20110022903 | DEVICE ENABLING THE USE OF A PROGRAMMABLE COMPONENT IN A NATURAL RADIATIVE ENVIRONMENT - A device for using a programmable component carrying out at least one logical function in a radiative environment includes: a mechanism for error detection in a data-storing working memory space actually serving to carry out each logical function of the device through use of data stored in at least one reference memory space storing a data copy implemented by at least one logical function; a mechanism blocking at least one output of at least one logical function of the component for which an error in the data implemented by the logical function is detected by the mechanism for detection; and a mechanism correcting each error detected in the working space. | 2011-01-27 |
20110022904 | MODEM-ASSISTED BIT ERROR CONCEALMENT FOR AUDIO COMMUNICATIONS SYSTEMS - Systems and methods are described for managing bit errors present in a series of encoded bits representative of a portion of an audio signal, wherein the series of encoded bits is received over a communication link in an audio communications system. At least one characteristic of a portion of a received modulated carrier signal that is demodulated to produce the series of encoded bits is determined. A number of bit errors present in the series of encoded bits is then determined based on the at least one characteristic. Based on the estimated number of bit errors, one of a plurality of methods for producing a series of digital audio samples representative of the portion of the audio signal is selectively performed. The series of digital audio samples produced by the selected method is then converted into a form suitable for playback to a user. | 2011-01-27 |
20110022905 | Test Circuit and Method for Multilevel Cell Flash Memory - A test device and method may be used to detect voltage, current or signals of a digital multilevel memory cell system or to test operation or performance by applying inputted voltages, currents or signals to the memory cell system. | 2011-01-27 |
20110022906 | METHOD AND SYSTEM FOR TEST POINT INSERTION - It is desired to suppress an increase of the TAT or a repetition of processing in inserting a test circuit on designing. A test point insertion method includes: extracting a plurality of logic cones from a net list; generating an order for the plurality of logic cones based on a connection relation of logic cells in each of the plurality of logic cones; and setting a test point in each of the plurality of logic cones in turn in accordance with the order. | 2011-01-27 |
20110022907 | FPGA Test Configuration Minimization - A method for automatically generating test patterns using a close-to-minimum number of configurations for a Field Programmable Gate Array (FPGA) to reduce test data volume and test application time. The FPGA can be a standalone programmable device or a circuit embedded in an Application Specific Integrated Circuit (ASIC). | 2011-01-27 |
20110022908 | ROBUST SCAN SYNTHESIS FOR PROTECTING SOFT ERRORS - A method for performing robust scan synthesis for soft-error protection on a design for generating a robust scan design in a system. The system is modeled selectively at a register-transfer level (RTL) or a gate level; the design includes at least a sequential element or a scan cell for mapping to a robust scan cell of a select robust scan cell type. The method comprises performing a scan replacement and a scan stitching on the design database based on a given control information file for synthesizing the robust scan cell on the design database; and generating the synthesized robust scan design at a pre-determined RTL or a pre-determined gate level. | 2011-01-27 |
20110022909 | APPARATUS AND METHOD FOR PROTECTING SOFT ERRORS - An apparatus and method for soft-error resilience or correction with the ability to perform a manufacturing test operation, a slow-speed snapshot operation, a slow-speed signature analysis operation, an at-speed signature analysis operation, a defect tolerance operation, or any combination of the above operations. In one embodiment, an apparatus includes a system circuit, a shadow circuit, and an output joining circuit for soft-error resilience. The output joining circuit coupled to the output terminals of the system circuit and the shadow circuit includes at least an S-element for defect tolerance. In another embodiment, an apparatus includes a system circuit, a shadow circuit, a debug circuit, and an output joining circuit for soft-error correction. The output joining circuit coupled to the output terminals of the system circuit, the shadow circuit, and the debug circuit includes at least a V-element for defect tolerance. | 2011-01-27 |
20110022910 | ARITHMETIC LOGIC UNIT FOR USE WITHIN A FLIGHT CONTROL SYSTEM - An arithmetic logic unit (ALU) for use within a flight control system is provided. The ALU comprises a first register configured to receive a first operand, a second register configured to receive a second operand, and an adder coupled to the first register and the second register. The adder is configured to generate a sum of the first operand and the second operand and to generate intermediate sums that are used to determine a product of the first operand and the second operand. | 2011-01-27 |
20110022911 | SYSTEM PERFORMANCE TEST METHOD, PROGRAM AND APPARATUS - A system performance test method for testing performance of a server system includes: (A) a step of issuing a plurality of types of request sequences with a specified issuance ratio to the server system; and (B) a step of measuring performance of the server system during processing of the plurality of types of request sequences. Each of the plurality of types of request sequences is comprised of a sequence of requests to the server system. | 2011-01-27 |
20110022912 | INTEGRATED CIRCUIT WITH JTAG PORT, TAP LINKING MODULE, AND OFF/CHIP TAP INTERFACE PORT - An IC includes an IEEE 1149.1 standard test access port (TAP) interface and an additional Off-Chip TAP interface. The Off-Chip TAP interface connects to the TAP of another IC. The Off Chip TAP interface can be selected by a TAP Linking Module on the IC. | 2011-01-27 |
20110022913 | NONVOLATILE MEMORY - For a nonvolatile memory permitting electrical writing and erasing of information to be stored, such as a flash memory, the load on the system developer is to be reduced, and it is to be made possible to avoid, even if such important data for the system as management and address translation information are damaged, an abnormal state in which the system becomes unable to operate. The nonvolatile memory is provided with a replacing function to replace a group of memory cells including defective memory cells which are incapable of normal writing or erasion with a group of memory cells including no defective memory cell, a numbers of rewrites averaging function to grasp the number of data rewrites in each group of memory cells and to so perform replacement of memory cell groups that there may arise no substantial difference in the number of rewrites among a plurality of memory cell groups, and an error correcting function to detect and correct any error in data stored in the memory array, wherein first address translation information deriving from the replacing function and second address translation information deriving from the numbers of rewrites averaging function are stored in respectively prescribed areas in the memory array, and the first address translation information and second address translation information concerning the same memory cell group are stored in a plurality of sets in a time series. | 2011-01-27 |
20110022914 | Replacement messages for identifying and preventing errors during the transmission of realtime-critical data - A destination node in a data network for transmission of real-time data by a data telegram, the data telegram including an identification, data and a transfer status, is provided. The destination node includes a device for receiving a first data telegram, a device for storing the data of the first data telegram and an assigned timer value, a device for receiving a second data telegram and a device for replacing the stored data of the first data telegram, wherein the stored data of the first data telegram is replaced with data of the second data telegram. Further, a method and a non-transitory storage medium are provided. | 2011-01-27 |
20110022915 | Data Processing In Signal Transmissions - A controller for a communications device, comprising: a receiver arranged for receiving a first data block and a second data block, each data block comprising a plurality of analogue signals; a digitizer arranged for converting each analogue signal into a digital value and marking each digital value as saturated when the digital value exceeds a digital range; and a processor arranged for modifying at least one digital value of the first block by combination with a corresponding digital value of the second block except where the digital value of the first block is marked as saturated and marking each modified value as saturated when the modified value is outside a defined range. | 2011-01-27 |
20110022916 | METHOD AND SYSTEM FOR SAVING POWER FOR PACKET RE-TRANSMISSION IN AN ENCRYPTED BLUETOOTH LOW POWER LINK LAYER CONNECTION - A Bluetooth low power (BLE) receiver receives a data packet in an encrypted link layer connection from a BLE transmitter. The data packet comprises a transmitted protocol data unit (PDU) and associated cyclic redundancy code (CRC). The PDU comprises a message integrity code (MIC). The BLE receiver determines a connection SNR. In a high connection SNR condition, the BLE receiver determines packet retransmission based on MIC verification without CRC checking. A MIC indication is generated by comparing a local MIC and the MIC in the received data packet. CRC checking is turned on or off for power saving based on the MIC indication and connection SNR. In a high connection SNR, the BLE receiver determines, without CRC checking, to retransmit the received data packet for a MIC failure indication. The local MIC is calculated using a shared secret Encryption Key of 32-bit, 64-bit or 128-bit derived from multiple entropy pools. | 2011-01-27 |
20110022917 | Protocols for Multi-Hop Relay System with Centralized Scheduling - Various example embodiments are disclosed herein. In an example embodiment, a method of transmitting data via a wireless transmission path that may include a user equipment as a first end point, a base station as second end point, and at least one relay station as an intermediate point(s). The method may include receiving a data transmission from a prior point in the transmission path. Substantially simultaneously: forwarding the received data to the next point in the transmission path, and determining if the received data is corrupt. Transmitting a transmission message to the next point in the transmission path indicating whether or not the received data was corrupt. And, if the data is not corrupt, transmitting a receipt message to the prior point indicating that the data was uncorrupt when received. | 2011-01-27 |
20110022918 | METHOD FOR TRANSMITTING DATA USING HARQ - A data transmission method using an HARQ includes transmitting a first transmission block which is a portion of bit streams of a mother codeword, receiving a retransmission request with respect to the mother codeword, and transmitting a second transmission block which is a bit stream subsequent to the first transmission block, according to the retransmission request, wherein a modulation order obtained from a first range of a modulation order product code rate (MPR) is applied to the first transmission block, a modulation order obtained from a second range of the MPR according to the number of retransmissions is applied to the second transmission block, and the second range of the MPR is adjusted as much as a linear offset to the first range. | 2011-01-27 |
20110022919 | Wireless Communication System, Wireless Communication Device and Wireless Communication Method - One object of the present invention is to improve stability of wireless communication by effectively requesting retransmission of data to a wireless communication device, which is a data transmission source, by switching ARQ and HARQ if an error has been detected in received data. | 2011-01-27 |
20110022920 | COMPACT DECODING OF PUNCTURED BLOCK CODES - k input bits are encoded according to a code with which is associated a m×n=m+k parity check matrix H. The resulting codeword is punctured, with n′2011-01-27 | |
20110022921 | COMPACT DECODING OF PUNCTURED BLOCK CODES - k input bits are encoded according to a code with which is associated a m×n=m+k parity check matrix H. The resulting codeword is punctured, with n′2011-01-27 | |
20110022922 | COMPACT DECODING OF PUNCTURED BLOCK CODES - k input bits are encoded according to a code with which is associated a m×n=m+k parity check matrix H. The resulting codeword is punctured, with n′2011-01-27 | |
20110022923 | System and Method for Achieving Greater Than 10 Gbit/s Transmission Rates for Twisted Pair Physical Layer Devices - A system and method for achieving greater than 10 Gbit/s transmission rates for twisted pair physical layer devices. An architecture is provided that enables transmission at the next standardized transmission rate over structured cabling. | 2011-01-27 |
20110022924 | Device and Method for Frame Erasure Concealment in a PCM Codec Interoperable with the ITU-T Recommendation G. 711 - A device and method for resynchronization and recovery after frame erasure concealment of an encoded sound signal comprise decoding, in a current frame, a correctly received signal after the frame erasure. Frame erasure concealment is extended in the current frame using an erasure-concealed signal from a previous frame to produce an extended erasure-concealed signal. The extended erasure-concealed signal is correlated with the decoded signal in the current frame and the extended erasure-concealed signal is synchronized with the decoded signal in response to the correlation. A smooth transition is produced in the current frame from the synchronized extended erasure-concealed signal to the decoded signal. | 2011-01-27 |
20110022925 | Turbo Coding for Upstream and Downstream Transmission in Cable Systems - A method of transmitting data in a cable modem system includes the steps of encoding the data using forward error correction. The data is then encoded with Turbo encoding. The data is then sent to a modulation scheme. The data is then transmitted over a cable channel. The data is then demodulated. The data is then decoded using a Turbo decoder. An inverse of the forward error correction is then applied to the data. | 2011-01-27 |
20110022926 | MESM: A FAST BJCR BASED DECODER IMPLEMENTATION SCHEME - A memory efficient, accelerated implementation architecture for BCJR based forward error correction algorithms. In this architecture, a memory efficiency storage scheme is adopted for the metrics and channel information to achieve high processing speed with a low memory requirement. Thus, BCJR based algorithms can be accelerated, and the implementation complexity can be 5 reduced. This scheme can be used in the BCJR based turbo decoder and LDPC decoder implementations. | 2011-01-27 |
20110022927 | COMPACT DECODING OF PUNCTURED CODES - k information bits are encoded according to a code with which is associated a parity check matrix H that has n columns. The entire resulting codeword is stored in a storage medium. At least n′2011-01-27 | |
20110022928 | CONTROLLER WITH ERROR CORRECTION FUNCTION, STORAGE DEVICE WITH ERROR CORRECTION FUNCTION, AND SYSTEM WITH ERROR CORRECTION FUNCTION - The invention is intended to curtail the circuit scale of the error correction circuit of a flash memory. The invention relates to a controller with error correction function capable of controlling writing and reading of data in a plurality of memories, including a buffer memory, an error correction circuit, and a plurality of interface modules provided individually corresponding to each one of the plurality of memories, for exchanging data with the memories, in which the plurality of interface modules have a plurality of syndrome generation function parts for receiving sector data from the memories and error correction codes corresponding to the sector data, and generating syndromes on the basis of the received sector data and error correction codes, the buffer memory. | 2011-01-27 |
20110022929 | Error correcting apparatus, method of controlling memory of error correcting apparatus, and optical disc recording/reproducing apparatus - An error correcting apparatus includes a memory for storing therein second block data at an interval of a time difference while it uses a part of a storage area of first block data having multiple pieces of frame data each having data having a predetermined length as one unit, and an error correcting portion configured to subject the first block data and the second block data each read out from the memory to error correction. | 2011-01-27 |
20110022930 | ERROR CORRECTION CIRCUIT AND ERROR CORRECTION METHOD - An error correction circuit | 2011-01-27 |
20110022931 | MEMORY MANAGEMENT IN A NON-VOLATILE SOLID STATE MEMORY DEVICE - A computer-implemented method of managing a memory of a non-volatile solid state memory device by balancing write/erase cycles among blocks to level block usage. The method includes: monitoring an occurrence of an error during a read operation in a memory unit of the device, wherein the error is correctable by error-correcting code; and programming the memory unit according to the monitored occurrence of the error; wherein the step of monitoring the occurrence of an error is carried out for at least one block; and wherein said step of programming comprises wear-leveling the monitored block according the error monitored for the monitored block. A computer system and a computer program-product is also provided. | 2011-01-27 |
20110022932 | VARIABLE SECTOR-COUNT ECC - Improved memory devices, circuitry, and data methods are described that facilitate the detection and correction of data in memory systems or devices by increasing the data area of user data being covered by the ECC code. This averages any possible bit errors over a larger data area and allows a greater number of errors to be corrected by a combining the ECC codes in the coverage area without substantially changing the overall size of ECC codes being stored over a single sector approach. In one embodiment of the present invention, the size of the data block utilized for ECC coverage is variable and can be selected such that differing areas of the memory array or data types can have a differing ECC data coverage sizes. It is also noted that the ECC algorithm, math base or encoding scheme can also be varied between these differing areas of the memory array. | 2011-01-27 |
20110022933 | APPARATUS AND METHOD OF EARLY DECODING IN COMMUNICATION SYSTEMS - A method and apparatus are disclosed for forming a frame of interleaved information bits in a communication system, where the decoding of the frame of interleaved information bits may begin before all of the bits in the frame are received. An exemplary interleaved frame is formed by receiving a frame of N information bits within the communication system; encoding the information bits at a code rate R to provide encoded bits; and arranging the encoded bits into a frame of N/R coded bits, wherein a plurality of puncturing patterns p | 2011-01-27 |
20110022934 | SYSTEM AND APPARATUS FOR SYNCHRONIZATION BETWEEN HETEROGENEOUS PERIODIC CLOCK DOMAINS, CIRCUIT FOR DETECTING SYNCHRONIZATION FAILURE AND DATA RECEIVING METHOD - The present invention relates to a system and an apparatus for synchronization between heterogeneous periodic clock domains, a synchronization failure detecting circuit, and a data receiving method. The synchronization system between heterogeneous periodic clock domains including a sender and a receiver operated according to heterogeneous periodic first clock and second clock, respectively, includes: a sender that outputs a prediction clock obtained by delaying the first clock for a first time; and a receiver that predicts success and failure of synchronization between the first clock and the second clock by using the prediction clock and selectively delays the second clock for a second time according to the predicted results to synchronize the second clock with the first clock. | 2011-01-27 |
20110022935 | Method and System for Interlocking Data Integrity for Network Adapters - Certain aspects of a method and system for interlocking data integrity for network adapters are disclosed. Aspects of one method may include executing a plurality of interlocking checks within a network adapter. Each interlocking check may comprise receiving a plurality of input check values associated with a plurality of input data packets corresponding to a first protocol. A plurality of check values may be generated which are associated with the plurality of input data packets and a plurality of output data packets corresponding to a second protocol. The data integrity of the plurality of input data packets and the plurality of output data packets may be validated based on one or more comparisons between one or more of the generated plurality of check values and one or more of the received plurality of input check values. | 2011-01-27 |
20110022936 | SENDING DEVICE, RECEIVING DEVICE, COMMUNICATION CONTROL DEVICE, COMMUNICATION SYSTEM, AND COMMUNICATION CONTROL METHOD - A receiving device including: a receiver receiving two frames, each including substantially same data attached thereto with a data error detection code, a frame error detection code, and safety flag information indicating a safety function or not, respectively; a first detector connected to the receiver for performing error detection of the frames by use of the frame error detection code, respectively; a second detector connected to the receiver for performing error detection of the data by use of the data error detection code, respectively; and a Direct Memory Access Controller (DMAC) connected to the first and second detectors for outputting one among the data included in the two frames under a condition of the safety function in the two frames when no error is detected in the frame and data error detections. | 2011-01-27 |
20110022937 | Assessing Quality of Service Using Digital Watermark Information - The disclosure details methods of measuring the quality of service of received media signals by analyzing digital watermarks embedded in such signals. The quality of a received video or audio signal can thereby be assessed without having the original version of the signal before transmission. Instead, the strength or quality of the embedded digital watermark is analyzed to determine the quality of the received signal. The degradation of a watermark signal is used to assess quality of service of signals, such as audio and video. Several other features and arrangements are also detailed. | 2011-01-27 |
20110022938 | APPARATUS, METHOD AND SYSTEM FOR MODIFYING PAGES - According to one embodiment of the present invention, there is provided a method of determining, for a first web page in a set of web pages comprising a web site, one or more further web pages from the set of web pages to be identified in the first web page. The method comprises analyzing a log of web pages previously requested from the web site to determine one or more further web pages of the web site to be identified in the first web page, and modifying the first web page to identify the one or more determined further pages. | 2011-01-27 |
20110022939 | Structure oriented graphical patchwork application environment - A graphical application developing and managing environment is described capable of representing and editing program modules using multiple display formats, which include embedding source code written in a functional language into a spreadsheet-like format. Methods are described for enabling the sharing of program modules by defining standardized interfaces into program modules and existing documents and by centrally locating module definitions. A patchwork mechanism is described requiring only basic spreadsheet editing skills on behalf of the user, enabling a user of the environment to connect external documents and program modules into a new program application. The invention allows complicated programming and simple end user programming to be achieved within a unified environment and allows the execution of program modules and tracing of variables simultaneously with the writing of a program application. The invention defines methods for representing the various parts of a source code, defining a program application, along with the application icon as determined by a user creating the application and thereby making parts of the source code accessible to end-users for run-time execution. | 2011-01-27 |
20110022940 | PROCESSING TECHNIQUES FOR VISUAL CAPTURE DATA FROM A RENDERED DOCUMENT - A facility for navigating an electronic document is described. The facility receives user input selecting a portion of the content of a rendered document that constitutes a sentence fragment. In response to receiving the user input, the facility identifies an electronic document contained in a corpus of electronic documents, the identified electronic document containing the selected document portion. In response to receiving the user input, the facility further identifies a position within the identified electronic document at which the selected document portion occurs. | 2011-01-27 |
20110022941 | Information Extraction Methods and Apparatus Including a Computer-User Interface - Disclosed is an information extraction system and method. The method comprises receiving a document and annotation data, the annotation data comprising instances of entities which have been identified in the document, the annotation entity data comprising identifiers of instances of one or more entities which have been identified in the document and data specifying the location of the identified instances of entities within the document, wherein the identifiers of instances of entities comprise references to ontology data; displaying the document to a user, with annotations dependent on the annotation data, highlighting one or more of the instances of entities whose location is specified in the annotation entity data at the location within the document specified by the annotation entity data; preparing revised annotation data from a user and outputting output data derived from the amended annotation data. The output data is typically used to populate a database. | 2011-01-27 |
20110022942 | SYSTEM AND METHOD FOR ANNOTATING MULTIMEDIA OBJECTS - The system and a computer-implemented method annotate a multimedia object on a web page hosted on a publisher computer system. A web page that includes a multimedia object is rendered in a web browser of a client computer system. One or more layers, including a transparent layer, at least partially located over the multimedia object displayed on the web page are generated wherein the one or more layers are configured to facilitate the creation and display of annotation data for the multimedia object based on user interface events produced by a user of the client computer system. Annotation data for the multimedia object is received from the user. The annotation data is transmitted to an annotation server for storage. A visual indicator indicating that the annotation data is associated with the multimedia object is displayed, wherein the visual indicator is rendered in the one or more layers. | 2011-01-27 |