04th week of 2011 patent applcation highlights part 42 |
Patent application number | Title | Published |
20110020940 | Marker Dyes for Petroleum Products - The present invention relates to using a marker in a functional fluid, which survives the use of the functional fluid in an application, with a reagent solution to identify the functional fluid rapidly either before, during or after the functional fluid's use and which is a suitable method for identifying a functional fluid in the field, and which may employ the use of test wipe, or medium, that contains the reagent solution. | 2011-01-27 |
20110020941 | GLYCOSYLATION MARKERS FOR PANCREATITIS, SEPSIS AND PANCREATIC CANCER - The present invention provides novel biomarkers for use in the diagnosis and prognosis of cancer and chronic inflammation and further of diseases which are mediated by chronic inflammation. The biomarkers are glycoproteins, the levels of which have been correlated by the inventors to correspond to particular disease conditions. The invention further extends to methods for monitoring the response to therapy of a treatment of a cancerous or chronic inflammatory condition. | 2011-01-27 |
20110020942 | MEASURING LEVELS OF A METABOLITE - Described herein are methods for determining an amount of an analyte in a test sample. The methods involve preparing a calibration curve using standard samples containing an isotopically-labeled standard in a biological matrix. | 2011-01-27 |
20110020943 | DRY TESTING TOOL, METHOD FOR MEASURING METAL, AND METHOD FOR PRODUCING DRY TESTING TOOL - The present invention provides a dry testing tool with which a metal in the various types of samples such as biological samples, food, and the like can be measured very easily, rapidly, high sensitively, and specifically by a simple colorimetric method and a method for measuring the metal. The dry testing tool of the present invention is a dry testing tool for measuring a metal in a sample, including a porous support and a chelate dye, wherein the chelate dye is bound to the porous support by a hydrophobic bond. The measuring method of the present invention is a method for measuring a metal in a sample, including the steps of: forming a composite of the chelate dye and the metal in the sample by supplying the sample to the porous support to which a chelate dye is bound by a hydrophobic bond; and detecting the metal in the sample using a developed color of the composite. | 2011-01-27 |
20110020944 | APPARATUS AND METHOD FOR DETECTING TRIACETONE TRIPEROXIDE - The present invention relates to an apparatus and a method for fast and reliable online detection of triacetone triperoxide (TATP), with at least three differently coated HFF quartz crystal oscillator sensors ( | 2011-01-27 |
20110020945 | ORAL DETECTION TEST FOR CANNABINOID USE - A method for confirming the active intake of marijuana and its active component Δ | 2011-01-27 |
20110020946 | CONVERSION OF JUST-CONTINUOUS METALLIC FILMS TO LARGE PARTICULATE SUBSTRATES FOR METAL-ENHANCED FLUORESCENCE - The present invention relates to a method of producing silver films having large nanoparticles caused by cracking during anaerobic annealing to provide surfaces that exhibit increased metal enhanced fluorescence. Preferably the annealing process is conducted on a silver film having a thickness from about 14 to 17 nm for about an hour at a temperature of approximately 190° C. to about 210° C. resulting in the conversion of the just-continuous films into large particulate films, not readily assessable by other chemical deposition techniques. | 2011-01-27 |
20110020947 | CHEMICAL COMPONENT AND PROCESSING DEVICE ASSEMBLY - A substantially dimensionally-stable chemical component is assembled with a sample processing device via a computer-controlled apparatus. In one embodiment, surface mount technology is used to assemble the chemical component with the processing device. The chemical component may include, for example, chemicals used for sample preparation or detection, such as a reagent. In different embodiments, the chemical component may be a tablet, microtablet, lyophilized pellet, bead, film, and so forth. In some embodiments, the chemical components are stored within a carrier that packages a plurality of chemical components. The carrier may define a plurality of pockets, where each pocket defines a discrete space for holding at least one chemical component. In some embodiments, a robotic arm aligns with a pocket in order to locate and remove a chemical component from the carrier and transfer the chemical component to a chamber of a processing device. | 2011-01-27 |
20110020948 | SPECIMEN PROCESSING APPARATUS AND CONTROL METHOD FOR THE SAME - A specimen processing apparatus comprising: a specimen processing section which includes a movable section and processes a specimen by moving the movable section; and a controller for determining whether the movable section was moved while a specimen processing operation by the specimen processing section was stopped, and controlling the specimen processing section to perform a preparing operation for starting the specimen processing operation based on the determination result, is disclosed. A control method for a specimen processing apparatus is also disclosed. | 2011-01-27 |
20110020949 | AUTOMATIC ANALYZER - In the field of automatic analyzers, as items to be analyzed are increase, various reagents differing in such properties as liquid viscosity and contact angle are being used more frequently, and this trend is expected to continue. Also, reagents now take various forms (e.g., a concentrated reagent to be diluted by the water of an automatic analyzer), and so does dilution water. Such being the case, the invention provides an automatic analyzer capable of sufficient stirring regardless of items to be analyzed. To sufficiently stir a substance to which a reagent has been added, the automatic analyzer is designed to alter stirring conditions after a given amount of time has passed since the addition of that reagent. | 2011-01-27 |
20110020950 | SCAFFOLD FOR COMPOSITE BIOMIMETIC MEMBRANE - Disclosed herein is a membrane scaffold comprising a planar material having a hydrophobic surface and a functional area comprising a plurality of apertures. The apertures have a diameter of from about 80 μm to about 3000 μm and the rims of the apertures comprise bulges extending above and/or below the surface level of the planar material. The membrane scaffold is useful in the preparation of a composite biomimetic membrane wherein functional channel forming molecules have been incorporated in said membrane. | 2011-01-27 |
20110020951 | PURIFIED SR-P70 PROTEIN - The invention relates to new nucleic acid sequences of the family of tumor-suppressing genes related to the gene for the p53 protein, and to corresponding protein sequences. | 2011-01-27 |
20110020952 | METHOD FOR DETERMINING THE STAGE OF ULCERATIVE COLITIS OR INTERSTITIAL PNEUMONITIS AND REAGENT KIT THEREOF - The invention provides a method capable of readily discriminating pathologic conditions and judging selection of a therapeutic drug, the degree of the therapeutic effect, discontinuation of medication, etc., wherein stages quantitatively judged by digitizing substances contained in urine, which is different from conventional methods for judging stages of an ulcerative colitis and an interstitial pneumonitis which are performed by observation of mucous lesions with endoscopy requiring the skill or by analysis of histological samples collected from the living body. | 2011-01-27 |
20110020953 | NMR device for detection of analytes - This invention relates generally to detection devices having one or more small wells each surrounded by, or in close proximity to, an NMR micro coil, each well containing a liquid sample with magnetic nanoparticles that self-assemble or disperse in the presence of a target analyte, thereby altering the measured NMR properties of the liquid sample. The device may be used, for example, as a portable unit for point of care diagnosis and/or field use, or the device may be implanted for continuous or intermittent monitoring of one or more biological species of interest in a patient. | 2011-01-27 |
20110020954 | CELLULOSE DERIVATIVE FINE PARTICLE, DISPERSION LIQUID THEREOF, DISPERSION BODY THEREOF AND DIAGNOSTIC REAGENT - An object of the present invention is to provide a hydrophilic cellulose derivative fine particle having a small particle size, a dispersion liquid thereof and a dispersion body thereof; and provide a diagnostic reagent composed of the hydrophilic particle, which is excellent in storage stability and does not require excess components, such as an emulsifier or surfactant. The cellulose derivative fine particle of the present invention is a cellulose derivative fine particle comprising a cellulose derivative with a part of hydroxyl groups of cellulose being substituted with a substituent, wherein the average particle diameter is from 9 to 1,000 nm; and the diagnostic reagent of the present invention is a diagnostic reagent obtained by loading a substance differentially interacting with a test object substance on the above-described cellulose derivative fine particle. | 2011-01-27 |
20110020955 | VAPOR PHASE REPAIR AND PORE SEALING OF LOW-K DIELECTRIC MATERIALS - A method of treating a nanoporous low-k dielectric material formed on a semiconductor substrate is provided. The low-k dielectric material has etched openings with an etch damaged region containing silanol groups on exterior surfaces of the etched openings and on interior surfaces of interconnected pores. First, the low-k dielectric material is contacted with a vapor phase catalyst in an amount effective to form hydrogen bonds between the catalyst and the silanol groups in the etch damaged region, forming a catalytic intermediary. Second, the low-k dielectric material is contacted with a vapor phase alkoxysilane repair agent in an amount effective to react with about 50% or more of the silanol groups in the etch damaged region, such that the alkoxysilane repair agent reacts with the catalytic intermediary; and/or the low-k dielectric material is contacted with a vapor phase alkoxysilane sealing agent in an amount effective to prevent diffusion of an overlying barrier layer into the interconnected pores, such that the alkoxysilane sealing agent reacts with the catalytic intermediary. | 2011-01-27 |
20110020956 | METHOD OF MEASURING PATTERN SHAPE, METHOD OF MANUFACTURING SEMICONDUCTOR DEVICE, AND PROCESS CONTROL SYSTEM - A method of measuring a pattern shape of performing a shape measurement of a semiconductor pattern at a high accuracy even when a process margin is narrow with respect to miniaturization of a semiconductor device is provided. In the method of measuring a pattern shape, when a best-match calculated waveform cannot be selected, at least one parameter among shape parameters is set as a fixed value based on information obtained by another measurement apparatus that uses a measurement method independent to the pattern shape measurement, a matching of a library and a detected waveform is performed again, a best-match calculated waveform is selected, and shape information of an object pattern is obtained from the best-match calculated waveform. | 2011-01-27 |
20110020957 | POSITIONING OF SEMICONDUCTOR SUBSTRATES IN A FURNACE - Methods of positioning semiconductor substrates in a furnace. One method determines a centered position of the substrates by conducting a heat treating to form an oxide layer on the substrate and measuring the substrate thickness at several points along its oxidized surface to determine a centered position. Also, a method of calibrating a device for heat treatment of the substrates, with the device including a positioner for providing the substrates on a retention support in the furnace. The positioner includes a memory unit that stores positioning parameters, and an actuator for positioning the substrate on the support according to the positioning parameters. The method includes positioning a test substrate on the support in a starting position according to starting parameters, determining a centered position for the test substrate, determining centering parameters corresponding to the centered position of the test substrate and storing the centering parameters in the memory unit. | 2011-01-27 |
20110020958 | METHOD AND SEMICONDUCTOR STRUCTURE FOR MONITORING ETCH CHARACTERISTICS DURING FABRICATION OF VIAS OF INTERCONNECT STRUCTURES - By forming a trench-like test opening above a respective test metal region during the etch process for forming via openings in a dielectric layer stack of sophisticated metallization structures of semiconductor devices, the difference in etch rate in the respective openings may be used for generating a corresponding variation of electrical characteristics of the test metal region. Consequently, by means of the electrical characteristics, respective variations of the etch process may be identified. | 2011-01-27 |
20110020959 | HUMIDITY CONTROL AND METHOD FOR THIN FILM PHOTOVOLTAIC MATERIALS - A method for processing a thin film photovoltaic module. The method includes providing a plurality of substrates, each of the substrates having a first electrode layer and an overlying absorber layer composed of copper indium gallium selenide (CIGS) or copper indium selenide (CIS) material. The absorber material comprises a plurality of sodium bearing species. The method maintains the plurality of substrates in a controlled environment after formation of at least the absorber layer through one or more processes up to a lamination process. The controlled environment has a relative humidity of less than 10% and a temperature ranging from about 10 Degrees Celsius to about 40 Degrees Celsius. The method subjects the plurality of substrates to a liquid comprising water at a temperature from about 10 Degrees Celsius to about 80 Degrees Celsius to process the plurality of substrates after formation of the absorber layer. The plurality of substrates having the absorber layer is subjected to an environment having a relative humidity of greater than about 10% to a time period of less then four hours. | 2011-01-27 |
20110020960 | METHOD FOR FABRICATING MICRO AND NANOSTRUCTURES IN A MATERIAL - A method to determine minimum etch mask dosage or thickness as a function of etch depth or maximum etch depth as a function of etch mask implantation dosage or thickness, for fabricating structures in or on a substrate through etch masking via addition or removal of a masking material and subsequent etching. | 2011-01-27 |
20110020961 | METHOD FOR MANUFACTURING LIGHT EMITTING DIODE ASSEMBLY - A method for manufacturing a light emitting diode (LED) assembly comprises the steps of: preparing a chip carrier comprising a carrier substrate, a P type electrode and an N type electrode, and arranging an LED chip onto the carrier substrate to electrically connect the LED chip with the P type electrode and the N type electrode; packaging the LED chip with a light-transmissible packaging gel and making the P type electrode and the N type electrode exposed to form a molded LED chip cell; preparing an arrangement carrier comprising a arrangement carrier substrate, a P type electrode plate and an N type electrode plate; forming an arrangement recess on the arrangement carrier substrate; and arranging the molded LED chip cell into the arrangement recess to make the P type electrode and the N type electrode electrically connect to the P type electrode plate and the N type electrode plate respectively. | 2011-01-27 |
20110020962 | TEST CIRCUIT UNDER PAD - Aspects of the present invention relate to the arrangement of points of interconnection of integrated circuit die to the package in which they are enclosed. More specifically, aspects of the present invention pertain to an arrangement of bond pads over the active circuitry of an integrated circuit die, in order to permit a reduction in size of the die. An embodiment of the present invention may place a first bond pad over the active area of an integrated circuit, wherein the first bond pad is electrically coupled to a second bond pad outside of the active area of the integrated circuit. Production and delivery of the integrated circuit may proceed using the second bond pad during packaging, in parallel with the testing of packaging using the first bond pad. When processes related to the use of the first bond pad have been proven successful and sustainable, the second bond pad may be eliminated, resulting in a reduction of the size of the integrated circuit device. This approach may be employed to save die area, increasing the number of devices that may be produced on a silicon wafer, resulting in a reduction in device cost. The approach of the present invention works well whether the chip is pad or core limited. Although reference has been made to the used of this technique on a silicon wafer, an embodiment of the present invention may be employed in the fabrication of integrated circuit device using other materials as well, without departing from the spirit and scope of the present invention. | 2011-01-27 |
20110020963 | METHOD AND APPARATUS FOR MANUFACTURING SOLAR CELL - A method for manufacturing a solar cell, includes: forming a photoelectric converter which includes a plurality of compartment elements, and in which the compartment elements adjacent to each other are electrically connected; specifying a compartment element having a structural defect in the photoelectric converter; restricting a portion in which the structural defect exists in the compartment element by specifying a defect portion based on a resistance distribution that is obtained by measuring resistances of portions between the compartment elements adjacent to each other; and removing the structural defect by supplying a bias voltage to the portion in which the structural defect exists. | 2011-01-27 |
20110020964 | METHOD OF FABRICATING INKJET PRINTHEAD ASSEMBLY HAVING BACKSIDE ELECTRICAL CONNECTIONS - A method of fabricating an inkjet printhead assembly having backside electrical connections. The method comprises the steps of: (a) providing printhead integrated circuits, each having a backside recessed edge portion and connectors extending through the integrated circuit, each connector having a head connected to frontside drive circuitry and a base in the recessed edge portion; (b) positioning a connection end of a connector film in the recessed edge portion; (c) connecting each film contact to the base of a corresponding connector; and (d) attaching the backside of each printhead integrated circuit together with the connector film to an ink supply manifold so as to provide the inkjet printhead assembly having backside electrical connections. | 2011-01-27 |
20110020965 | METHOD OF FABRICATING PRINTHEAD INTEGRATED CIRCUIT WITH BACKSIDE ELECTRICAL CONNECTIONS - A method of fabricating a printhead integrated circuit configured for backside electrical connections. The method comprises the steps of: (a) providing a wafer comprising a plurality of partially-fabricated nozzle assemblies on a frontside of the wafer and through-silicon connectors extending from the frontside towards a backside of the wafer; (b) depositing a conductive layer on the frontside of said wafer and etching to form an actuator for each nozzle assembly and a frontside contact pad over a head of each through-silicon connector; (c) performing further MEMS processing steps to complete formation of nozzle assemblies ink supply channels through-silicon connectors; and (d) dividing the wafer into individual printhead integrated circuits. Each printhead integrated circuit thus formed is configured for backside-connection to the drive circuitry via the through-silicon connectors the contact pads. | 2011-01-27 |
20110020966 | METHOD FOR PROCESSING SILICON SUBSTRATE AND METHOD FOR PRODUCING SUBSTRATE FOR LIQUID EJECTING HEAD - A method for processing a silicon substrate includes preparing a first silicon substrate including an etching mask layer including first and second opening portions; forming a first recess in a portion of the silicon substrate corresponding to a region in the first opening portion; etching the silicon substrate by crystal anisotropic etching through the etching mask layer with an etching apparatus and an etchant, the etching proceeding in the first and second opening portions to form a through hole in a position corresponding to the first opening portion and to form a second recess in a position corresponding to the second opening portion; calculating an etching rate of the silicon substrate in terms of the etchant by using the second recess; and determining, by using the calculated etching rate, an etching condition for etching another silicon substrate with the etching apparatus after the etching of the first silicon substrate. | 2011-01-27 |
20110020967 | LED CHIP PACKAGE STRUCTURE WITH HIGH-EFFICIENCY LIGHT EMISSION BY ROUGH SURFACES AND METHOD OF MAKING THE SAME - An LED chip package structure with high-efficiency light emission by rough surfaces includes a substrate unit, a light-emitting unit, and a package colloid unit. The substrate unit has a substrate body, and a positive electrode trace and a negative electrode trace respectively formed on the substrate body. The light-emitting unit has a plurality of LED chips arranged on the substrate body. Each LED chip has a positive electrode side and a negative electrode side respectively and electrically connected with the positive electrode trace and the negative electrode trace of the substrate unit. The package colloid unit has a plurality of package colloids respectively covering the LED chips. Each package colloid has a cambered colloid surface and a light-emitting colloid surface respectively formed on its top surface and a lateral surface thereof. | 2011-01-27 |
20110020968 | MANUFACTURING PROCESS OF TRANSFLECTIVE PIXEL STRUCTURE - A transflective pixel structure including a scan line, a data line, a thin film transistor, a pixel electrode and an organic material layer is provided. The scan line and the data line are disposed over a substrate. The thin film transistor is disposed over the substrate and electrically connected to the scan line and the data line. The pixel electrode is disposed over a substrate and is electrically connected to the thin film transistor. The pixel electrode has a reflective region and a transmissive region. The organic material layer covers both the thin film transistor and the pixel electrode. The organic material layer disposed correspondently above the transmissive region of the pixel electrode has a plurality of refracting patterns on its upper surface. | 2011-01-27 |
20110020969 | METHOD FOR APPLYING LAYERS ONTO THERMOELECTRIC MATERIALS - A method for applying at least one layer, selected from diffusion barriers, further protective layers, adhesion promoters, solders and electrical contacts, onto thermoelectric materials, is characterized by the fact that the at least one layer is rolled or pressed onto the thermoelectric material at a temperature at which the thermoelectric material is flowable. | 2011-01-27 |
20110020970 | ETCHING OR PLATING PROCESS AND RESIST INK - The present invention provides a process of etching or plating comprising the steps of: i) ink jet printing an alkali removeable water insoluble hot melt ink jet ink onto a substrate to form a resist image; ii) etching or plating the substrate in an aqueous acid medium; and iv) removing the resist image with an aqueous alkali. | 2011-01-27 |
20110020971 | Combinatorial Screening of Transparent Conductive Oxide Materials for Solar Applications - Embodiments of the current invention include methods of improving a process of forming a textured TCO film by combinatorial methods. The combinatorial method may include depositing a TCO by physical vapor deposition or sputtering, annealing the TCO, and etching the TCO where at least one of the depositing, the annealing, or the etching is performed combinatorially. Embodiments of the current invention also include improved methods of forming the TCO based on the results of combinatorial testing. | 2011-01-27 |
20110020972 | System And Method For Making A Photovoltaic Unit - A process of making a photovoltaic unit includes steps of simultaneously forming a first layer of n-type material and a second layer of p-type material using a continuous casting process, and continuously bonding the first and second layers to form a p-n junction. The process may be performed using a twin-roll type continuous casting system having a continuous casting mold that includes a first mold compartment for receiving molten n-type material and a second mold compartment for receiving molten p-type material. The molten n-type material and the molten p-type material are gradually solidified into semi-solid shells and are pressed together by opposed casting rolls, creating a metallurgical bond between the n-type material and the p-type material that forms an effective p-n junction. The process permits the large scale efficient manufacturing of photovoltaic units. | 2011-01-27 |
20110020973 | Method of Manufacturing a Photovoltaic Device - A photovoltaic device including a current collection element and a method of making same. The photovoltaic device includes a substrate, a conductive layer, an active photovoltaic material, a transparent electrode and a current collection element. The current collection element includes a transparent support and one or more conductive wires integrated therewith. The conductive wires are in electrical communication with the transparent electrode. Current generated by the active photovoltaic material passes to the transparent electrode. The current collection element facilitates delivery of current passing through the transparent electrode to leads that deliver the current to an external load. The method includes placing a pre-fabricated current collection element in direct contact with the transparent electrode of the photovoltaic device. The time and expense of assembling the conductive wires during fabrication of the photovoltaic device is thereby avoided and higher manufacturing speeds are achieved. | 2011-01-27 |
20110020974 | METHOD FOR PRODUCING A STACKED PHOTOVOLTAIC DEVICE - A stacked photovoltaic device which includes a first photovoltaic unit having an amorphous silicon layer | 2011-01-27 |
20110020975 | METHOD FOR MANUFACTURING PHOTODIODE DEVICE - A method of manufacturing photodiode device includes the following steps: providing a wafer having a substrate and an epitaxy layer, the substrate having a first surface and a second surface and the epitaxy layer formed on the first surface; forming a first conductive layer on the second surface of the substrate; forming a patterned conductive layer above the epitaxy layer; and etching the patterned conductive layer by a reactive ion etching (RIE) process performed under argon gas and helium gas. | 2011-01-27 |
20110020976 | SOLAR CELL, AND METHOD AND APPARATUS FOR MANUFACTURING THE SAME - A method for manufacturing a solar cell, includes: forming, on a silicon substrate whose conductivity type is p-type or n-type, a silicon layer including a dopant whose conductivity type is different from that of the silicon substrate; and diffusing the dopant included in the silicon layer into the silicon substrate by heat-treating the silicon layer. | 2011-01-27 |
20110020977 | Mechanical patterning of thin film photovoltaic materials and structure - A method for forming one or more patterns for a thin film photovoltaic material. The method includes providing a substrate including a molybdenum layer and an overlying absorber comprising a copper bearing species and a window layer comprising a cadmium bearing species. The substrate is supported to expose a surface of the window layer. In a specific embodiment, the method includes using a scribe device. The scribe device includes a scribe having a tip. The scribe device is configured to pivot about one or more regions and configured to apply pressure to the tip, such that the tip is placed on a selected region of the window layer or the absorber layer. The method moves the scribe device relative to the substrate in a direction to form a pattern on at least the window layer or the absorber layer at a determined speed maintaining the molybdenum layer free from the pattern. | 2011-01-27 |
20110020978 | SODIUM DOPING METHOD AND SYSTEM OF CIGS BASED MATERIALS USING LARGE SCALE BATCH PROCESSING - A method of processing a plurality of photovoltaic materials in a batch process includes providing at least one transparent substrate having an overlying first electrode layer and an overlying copper species based absorber precursor layer within an internal region of a furnace. The overlying copper species based absorber precursor layer has an exposed face. The method further includes disposing at least one soda lime glass comprising a soda lime glass face within the internal region of the furnace such that the soda lime glass face is adjacent by a spacing to the exposed face of the at least one transparent substrate. Furthermore, the method includes subjecting the at least one transparent substrate and the one soda lime glass to thermal energy to transfer one or more sodium bearing species from the soda lime glass face across the spacing into the copper species based absorber precursor layer via the exposed face. | 2011-01-27 |
20110020979 | BULK HETEROJUNCTION ORGANIC PHOTOVOLTAIC CELLS MADE BY GLANCING ANGLE DEPOSITION - A method of making a bulk heterojunction organic photovoltaic cell by glancing angle deposition. As the disclosed method relies on a trajectory of incident vapor flux that is not parallel to the substrate normal, micro and nano-scale columnar structures of thin films can be grown on the substrate. There is also disclosed a method of forming a donor-acceptor heterojunction by depositing at least one additional organic material over the columnar structures. | 2011-01-27 |
20110020980 | THERMAL PRE-TREATMENT PROCESS FOR SODA LIME GLASS SUBSTRATE FOR THIN FILM PHOTOVOLTAIC MATERIALS - A method for fabricating a thin film solar cell includes providing a soda lime glass substrate comprising a surface region, treating the surface region with one or more cleaning process including an aqueous solution to remove one or more contaminants and/or particulates, and forming a lower electrode layer overlying the surface region. The method also includes performing a thermal treatment process to remove any residual water species to substantially less than a monolayer of water species from the lower electrode layer and soda lime glass substrate. The thermal treatment process changes a temperature of the soda lime glass substrate from a first temperature to a second temperature to pre-heat the soda lime glass substrate. Additionally, the method includes transferring the soda lime glass substrate, which has been preheated, to a deposition chamber and forming a layer of photovoltaic material overlying the lower electrode layer within the deposition chamber. | 2011-01-27 |
20110020981 | Dichalcogenide Selenium Ink and Methods of Making and Using Same - A selenium ink comprising a chemical compound having a formula RZ-Se | 2011-01-27 |
20110020982 | METHOD FOR BONDING OF CHIPS ON WAFERS - Method for bonding a plurality of chips onto a base wafer. | 2011-01-27 |
20110020983 | FLIP-CHIP MOUNTING METHOD, FLIP-CHIP MOUNTING APPARATUS AND TOOL PROTECTION SHEET USED IN FLIP-CHIP MOUNTING APPARATUS - A flip-chip mounting apparatus has a shield film ( | 2011-01-27 |
20110020984 | Method of Manufacturing A Semiconductor Device - A semiconductor device manufacturing method comprising the steps of providing a matrix substrate having a main surface with plural device areas formed thereon, fixing plural semiconductor chips to the plural device areas respectively, then sealing the plural semiconductor chips all together with resin to form a block sealing member, dividing the block sealing member and the matrix substrate for each of the device areas by dicing, thereafter rubbing a surface of each of the diced sealing member portions with a brush, then storing semiconductor devices formed by the dicing once into pockets respectively of a tray, and conveying the semiconductor devices each individually from the tray. Since the substrate dividing work after block molding is performed by dicing while vacuum-chucking the surface of the block sealing member, the substrate division can be done without imposing any stress on an external terminal mounting surface of the matrix substrate. | 2011-01-27 |
20110020985 | Integrated Circuit Package and a Method for Forming an Integrated Circuit Package - A method of forming an integrated circuit package, such as a Flip Chip package, in which a void is provided in the underfill material in the central region of the package between the chip or die and the substrate on which the chip or die is mounted. This reduces delamination of the package as a result of moisture. | 2011-01-27 |
20110020986 | Offset Geometries for Area Reduction In Memory Arrays - An array with cells that have adjacent similar structures that are displaced from each other across a common cell border in a direction that is not perpendicular to the cell border thus avoiding an across cell border design rule violation between the adjacent similar structures. A method of forming reduced area memory arrays by displacing adjacent similar structures along a common cell border. A method of building arrays using conventional array building software by forming unit pairs with cells that are not identical and are not mirror images or rotated versions of each other. | 2011-01-27 |
20110020987 | NONPLANAR SEMICONDUCTOR DEVICE WITH PARTIALLY OR FULLY WRAPPED AROUND GATE ELECTRODE AND METHODS OF FABRICATION - A nonplanar semiconductor device and its method of fabrication is described. The nonplanar semiconductor device includes a semiconductor body having a top surface opposite a bottom surface formed above an insulating substrate wherein the semiconductor body has a pair laterally opposite sidewalls. A gate dielectric is formed on the top surface of the semiconductor body on the laterally opposite sidewalls of the semiconductor body and on at least a portion of the bottom surface of semiconductor body. A gate electrode is formed on the gate dielectric, on the top surface of the semiconductor body and adjacent to the gate dielectric on the laterally opposite sidewalls of semiconductor body and beneath the gate dielectric on the bottom surface of the semiconductor body. A pair source/drain regions are formed in the semiconductor body on opposite sides of the gate electrode. | 2011-01-27 |
20110020988 | CAPACITORLESS DRAM ON BULK SILICON - A method of forming capacitorless DRAM over localized silicon-on-insulator comprises the following steps: A silicon substrate is provided, and an array of silicon studs is defined within the silicon substrate. An insulator layer is defined atop at least a portion of the silicon substrate, and between the silicon studs. A silicon-over-insulator layer is defined surrounding the silicon studs atop the insulator layer, and a capacitorless DRAM is formed within and above the silicon-over-insulator layer. | 2011-01-27 |
20110020989 | METHOD FOR FORMING MICROCRYSTALLINE SEMICONDUCTOR FILM AND METHOD FOR MANUFACTURING THIN FILM TRANSISTOR - A microcrystalline semiconductor film having a high crystallinity is formed. Further, a thin film transistor having preferable electric characteristics and high reliability and a display device including the thin film transistor are manufactured with high mass productivity. A step in which a deposition gas containing silicon or germanium is introduced at a first flow rate and a step in which the deposition gas containing silicon or germanium is introduced at a second flow rate are repeated while hydrogen is introduced at a fixed rate, so that the hydrogen and the deposition gas containing silicon or germanium are mixed, and a high-frequency power is supplied. Therefore, a microcrystalline semiconductor film is formed over a substrate. | 2011-01-27 |
20110020990 | THIN FILM TRANSISTOR AND METHOD FOR FABRICATING THE SAME - A thin film transistor that has improved characteristics and uniformity is developed by uniformly controlling low concentration of crystallization catalyst and controlling crystallization position so that no seed exists and no grain boundary exists, or one grain boundary exists in a channel layer of the thin film transistor. The thin film transistor includes a substrate; a semiconductor layer pattern which is formed on the substrate, the semiconductor layer pattern having a channel layer of which no seed exists and no gram boundary exists; a gate insulating film formed on the semiconductor layer pattern; and a gate electrode formed on the gate insulating film. A method for fabricating the thin film transistor includes forming an amorphous silicon layer on a substrate; forming a semiconductor layer pattern having a channel layer in which no seed exists and no grain boundary exists by crystallizing and patterning the amorphous silicon layer; forming a gate insulating film on the semiconductor layer pattern; and forming a gate electrode on the gate insulating film. | 2011-01-27 |
20110020991 | VERTICAL JUNCTION FIELD EFFECT TRANSISTORS HAVING SLOPED SIDEWALLS AND METHODS OF MAKING - Semiconductor devices and methods of making the devices are described. The devices can be junction field-effect transistors (JFETs). The devices have raised regions with sloped sidewalls which taper inward. The sidewalls can form an angle of 5° or more from vertical to the substrate surface. The devices can have dual-sloped sidewalls in which a lower portion of the sidewalls forms an angle of 5° or more from vertical and an upper portion of the sidewalls forms an angle of <5° from vertical. The devices can be made using normal (i.e., 0°) or near normal incident ion implantation. The devices have relatively uniform sidewall doping and can be made without angled implantation. | 2011-01-27 |
20110020992 | Integrated Nanostructure-Based Non-Volatile Memory Fabrication - Nanostructure-based charge storage regions are included in non-volatile memory devices and integrated with the fabrication of select gates and peripheral circuitry. One or more nanostructure coatings are applied over a substrate at a memory array area and a peripheral circuitry area. Various processes for removing the nanostructure coating from undesired areas of the substrate, such as target areas for select gates and peripheral transistors, are provided. One or more nanostructure coatings are formed using self-assembly based processes to selectively form nanostructures over active areas of the substrate in one example. Self-assembly permits the formation of discrete lines of nanostructures that are electrically isolated from one another without requiring patterning or etching of the nanostructure coating. | 2011-01-27 |
20110020993 | Semiconductor Device and Method of Fabricating the Same - Provided are a semiconductor device and a method of fabricating the same. The semiconductor device includes a first interconnection disposed on a substrate. The interconnection includes a first silicon interconnection region and a first metal interconnection region sequentially stacked on the substrate. A second interconnection includes a second silicon interconnection region and a second metal interconnection region that are stacked sequentially. The second silicon interconnection region has a lower resistivity than the first silicon interconnection region. | 2011-01-27 |
20110020994 | MANUFACTURING METHOD OF SEMICONDUCTOR DEVICE - A method of forming a semiconductor device is described. First, a substrate is provided. Thereafter, a gate structure including, from bottom to top, a high-k layer, a work function metal layer, a wetting layer, a polysilicon layer and a mask layer is formed on the substrate. Afterwards, a spacer is formed on the sidewall of the gate structure. Source/drain regions are then formed in the substrate beside the gate structure. Further, an interlayer dielectric layer is formed over the substrate. Thereafter, a portion of the interlayer dielectric layer is removed to expose the surface of the mask layer. Afterwards, the mask layer and the polysilicon layer are sequentially removed to expose the surface of the wetting layer. A selective chemical vapor deposition process is then performed, so as to bottom-up deposit a metal layer from the surface of the wetting layer. | 2011-01-27 |
20110020995 | Nonvolatile semiconductor memory and method of manufacturing the same - A nonvolatile semiconductor memory has a semiconductor substrate, a first insulating film formed on a channel region on a surface portion of the semiconductor substrate, a charge accumulating layer formed on the first insulating film, a second insulating film formed on the charge accumulating layer, a control gate electrode formed on the second insulating film, and a third insulating film including an Si—N bond that is formed on a bottom surface and side surfaces of the charge accumulating layer. | 2011-01-27 |
20110020996 | SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD THEREFOR - There is provided a semiconductor device including a semiconductor substrate ( | 2011-01-27 |
20110020997 | NOISE REDUCTION IN SEMICONDUCTOR DEVICES - An integrated circuit and method of making it, includes a semiconductor substrate and a support layer disposed on the semiconductor substrate. A gate insulator including a support layer doped using a noise-reducing dopant can be disposed on the semiconductor substrate. A gate stack can be disposed on the gate insulator. | 2011-01-27 |
20110020998 | METHOD OF FORMING A SEMICONDUCTOR DEVICE HAVING A METAL ALLOY ELECTRODE - A semiconductor device includes an electrode having a metal silicide layer and a metal alloy layer, and a data storage element formed on the electrode. The metal silicide layer has a concave surface to correspond to a convex surface of the metal alloy layer such that the concave surface of the metal silicide layer and the convex surface of the metal alloy layer form a curved boundary. | 2011-01-27 |
20110020999 | Methods of Forming Dielectric Material-Containing Structures - Some embodiments include dielectric structures. The structures include first and second portions that are directly against one another. The first portion may contain a homogeneous mixture of a first phase and a second phase. The first phase may have a dielectric constant of greater than or equal to 25, and the second phase may have a dielectric constant of less than or equal to 20. The second portion may be entirely a single composition having a dielectric constant of greater than or equal to 25. Some embodiments include electrical components, such as capacitors and transistors, containing dielectric structures of the type described above. Some embodiments include methods of forming dielectric structures, and some embodiments include methods of forming electrical components. | 2011-01-27 |
20110021000 | METHOD FOR MANUFACTURING RESISTANCE CHANGE ELEMENT - The present invention provides a method for manufacturing a resistance change element that can reduce occurrence of corrosion without increasing a substrate temperature. A laminate film that includes a high melting-point metal film and a metal oxide film, is etched using a mask under a plasma atmosphere formed using any one of a mixture gas formed by adding at least one gas selected from the group consisting of Ar, He, Xe, Ne, Kr, O | 2011-01-27 |
20110021001 | Vapor Deposition Methods for Forming a Metal-Containing Layer on a Substrate - Atomic layer deposition methods as described herein can be advantageously used to form a metal-containing layer on a substrate. For example, certain methods as described herein can form a strontium titanate layer that has low carbon content (e.g., low strontium carbonate content), which can result in layer with a high dielectric constant. | 2011-01-27 |
20110021002 | Process for Making Contact with and Housing Integrated Circuits - A process for producing electrical contact connections for a component integrated in a substrate material is provided, the substrate material having a first surface region, and at least one terminal contact being arranged at least partially in the first surface region for each component, which is distinguished in particular by application of a covering to the first surface region and production of at least one contact passage which, in the substrate material, runs transversely with respect to the first surface region, in which process, in order to form at least one contact location in a second surface region which is to be provided, at least one electrical contact connection from the contact location to at least one of the terminal contacts is produced via the respective contact passages. | 2011-01-27 |
20110021003 | SUPPLY MECHANISM FOR THE CHUCK OF AN INTEGRATED CIRCUIT DICING DEVICE - A system for dicing substrates to singulate integrated circuit units within in them includes a dicing machine (Z) which operates with a chuck table ( | 2011-01-27 |
20110021004 | METHOD OF CUTTING A SUBSTRATE, METHOD OF CUTTING A WAFER-LIKE OBJECT, AND METHOD OF MANUFACTURING A SEMICONDUCTOR DEVICE - A laser beam machining method and a laser beam machining device capable of cutting a work without producing a fusing and a cracking out of a predetermined cutting line on the surface of the work, wherein a pulse laser beam is radiated on the predetermined cut line on the surface of the work under the conditions causing a multiple photon absorption and with a condensed point aligned to the inside of the work, and a modified area is formed inside the work along the predetermined determined cut line by moving the condensed point along the predetermined cut line, whereby the work can be cut with a rather small force by cracking the work along the predetermined cut line starting from the modified area and, because the pulse laser beam radiated is not almost absorbed onto the surface of the work, the surface is not fused even if the modified area is formed. | 2011-01-27 |
20110021005 | ADHESIVE COMPOSITION, PROCESS FOR PRODUCING THE SAME, ADHESIVE FILM USING THE SAME, SUBSTRATE FOR MOUNTING SEMICONDUCTOR AND SEMICONDUCTOR DEVICE - Disclosed is an adhesive composition which includes (a) an epoxy resin, (b) a curing agent and (c) a polymer compound incompatible with said epoxy resin, and further optionally includes (d) a filler and/or (e) a curing accelerator. Also disclosed are a process for producing an adhesive composition, including mixing (a) the epoxy resin and (b) the curing agent with (d) the filler, followed by mixing the resultant mixture with (c) the polymer compound incompatible with the epoxy resin; an adhesive film including the above-mentioned adhesive composition formed into a film; a substrate for mounting a semiconductor including a wiring board and the above-mentioned adhesive film disposed thereon on its side where chips are to be mounted; and a semiconductor device which includes the above-mentioned adhesive film or the substrate for mounting a semiconductor. | 2011-01-27 |
20110021006 | METHOD FOR RELEASING A THIN SEMICONDUCTOR SUBSTRATE FROM A REUSABLE TEMPLATE - The present disclosure relates to methods and apparatuses for releasing a thin semiconductor substrate from a reusable template. The method involves forming a mechanically weak layer conformally on a semiconductor template. Then forming a thin semiconductor substrate conformally on the mechanically weak layer. The thin semiconductor substrate, the mechanically weak layer and the template forming a wafer. Then defining the border of the thin-film semiconductor substrate to be released by exposing the peripheral of the mechanically weak layer. Then releasing the thin-film semiconductor substrate by applying a controlled air flow parallel to said mechanically weak layer wherein the controlled air flow separates the thin semiconductor substrate and template according to lifting forces. | 2011-01-27 |
20110021007 | LIQUID CHEMICAL DEPOSTION APPARATUS AND PROCESS AND PRODUCTS THEREFROM - A method, apparatus and material produced thereby in an amorphous or crystalline form having multiple elements with a uniform molecular distribution of elements at the molecular level. | 2011-01-27 |
20110021008 | Directional Solid Phase Crystallization of Thin Amorphous Silicon for Solar Cell Applications - Embodiments of the present invention provide a method for converting a doped amorphous silicon layer deposited onto a crystalline silicon substrate into crystalline silicon having the same grain structure and crystal orientation as the underlying crystalline silicon substrate upon which the amorphous silicon was initially deposited. Additional embodiments of the present invention provide depositing a dielectric passivation layer onto the amorphous silicon layer prior to the conversion. A temperature gradient is provided at a temperature and for a time period sufficient to provide a desired p-n junction depth and dopant profile. | 2011-01-27 |
20110021009 | LOW CLAMP VOLTAGE ESD METHOD - In one embodiment, an ESD device is configured to include a zener diode and a P-N diode and to have a conductor that provides a current path between the zener diode and the P-N diode. | 2011-01-27 |
20110021010 | METHOD FOR DOUBLE PATTERN DENSITY - A method deposits an undoped silicon layer on a primary layer, deposits a cap layer on the undoped silicon layer, patterns a masking layer on the cap layer, and patterns the undoped silicon layer into silicon mandrels. The method incorporates impurities into sidewalls of the silicon mandrels in a process that leaves sidewall portions of the silicon mandrels doped with impurities and that leaves central portions of at least some of the silicon mandrels undoped. The method removes the cap layer to leave the silicon mandrels standing on the primary layer and performs a selective material removal process to remove the central portions of the silicon mandrels and to leave the sidewall portions of the silicon mandrels standing on the primary layer. The method patterns at least the primary layer using the sidewall portions of the silicon mandrels as a patterning mask and removes the sidewall portions of the silicon mandrels to leave at least the primary layer patterned. | 2011-01-27 |
20110021011 | CARBON MATERIALS FOR CARBON IMPLANTATION - A method of implanting carbon ions into a target substrate, including: ionizing a carbon containing dopant material to produce a plasma having ions; optionally co-flowing an additional gas or series of gases with the carbon-containing dopant material; and implanting the ions into the target substrate. The carbon-containing dopant material is of the formula C | 2011-01-27 |
20110021012 | COMPOSITIONS FOR FORMING DOPED REGIONS IN SEMICONDUCTOR SUBSTRATES, METHODS FOR FABRICATING SUCH COMPOSITIONS, AND METHODS FOR FORMING DOPED REGIONS USING SUCH COMPOSITIONS - Compositions for forming doped regions in semiconductor substrates, methods for fabricating such compositions, and methods for forming doped regions using such compositions are provided. In one embodiment, a dopant-comprising composition comprises a conductivity-determining type impurity dopant, a silicate carrier, a solvent, and a moisture adsorption-minimizing component. In another embodiment, a dopant-comprising composition comprises a conductivity-determining type impurity dopant, a silicate carrier, a solvent, and a high boiling point material selected from the group consisting of glycol ethers, alcohols, and combinations thereof. The high boiling point material has a boiling point of at least about 150° C. | 2011-01-27 |
20110021013 | SEMICONDUCTOR DEVICE AND FABRICATION METHOD FOR THE SAME - The semiconductor device includes: memory cells each having a first multilayer electrode including a first lower electrode made of a first conductive film and a first upper electrode made of a second conductive film formed one on the other with a first interface film therebetween; and a diode having a diode electrode made of the second conductive film and a second interface film as a silicon oxide film formed at the interface between the diode electrode and a substrate. The first interface film has a thickness with which electrical connection between the lower electrode and the upper electrode is maintained, and the second interface film has a thickness with which epitaxial growth between the substrate and the diode electrode is inhibited. | 2011-01-27 |
20110021014 | Semiconductor memory devices performing erase operation using erase gate and methods of manufacturing the same - A semiconductor memory device performing an erase operation using an erase gate and a method of manufacturing the same are provided. The memory device may include a charge trap layer storing a first charge transfer medium having a first polarity and at least one erase gate. The at least one erase gate may be formed below the charge trap layer. A second charge transfer medium, which has a second polarity opposite to the first polarity, may be stored in the at least one erase gate. During the erase operation, the second charge transfer medium migrates to the charge trap layer causing the first charge transfer medium to combine with the second charge transfer medium. | 2011-01-27 |
20110021015 | Formation of a Masking Layer on a Dielectric Region to Facilitate Formation of a Capping Layer on Electrically Conductive Regions Separated by the Dielectric Regions - A masking layer is formed on a dielectric region of an electronic device so that, during subsequent formation of a capping layer on electrically conductive regions of the electronic device that are separated by the dielectric region, the masking layer inhibits formation of capping layer material on or in the dielectric region. The capping layer can be formed selectively on the electrically conductive regions or non-selectively; in either case (particularly in the latter), capping layer material formed over the dielectric region can subsequently be removed, thus ensuring that capping layer material is formed only on the electrically conductive regions. Silane-based materials, such as silane-based SAMs, can be used to form the masking layer. The capping layer can be formed of an electrically conductive material (e.g., a cobalt alloy, a nickel alloy, tungsten, tantalum, tantalum nitride), a semiconductor material, or an electrically insulative material, and can be formed using any appropriate process, including conventional deposition processes such as electroless deposition, chemical vapor deposition, physical vapor deposition or atomic layer deposition. | 2011-01-27 |
20110021016 | Semiconductor package and method of manufacturing the same - A semiconductor package is disclosed that includes a semiconductor device; a circuit board; and a connection mechanism including a first conductive terminal provided on the semiconductor device, and a second conductive terminal provided on the circuit board side, the connection mechanism electrically connecting the semiconductor device and the circuit board via the first conductive terminal and the second conductive terminal. At least one of the first conductive terminal and the second conductive terminal of the connection mechanism includes one or more carbon nanotubes each having one end thereof fixed to the surface of the at least one of the first conductive terminal and the second conductive terminal, and extending in a direction away from the surface. The first conductive terminal and the second conductive terminal engage each other through the carbon nanotubes. | 2011-01-27 |
20110021017 | METHOD FOR FABRICATING SEMICONDUCTOR DEVICE AND SEMICONDUCTOR DEVICE - A method for fabricating a semiconductor device includes the steps of forming a plurality of lower interconnections at intervals in a first insulating film; removing a portion of the first insulating film located between the lower interconnections, thereby forming an interconnection-to-interconnection gap; forming a second insulating film over the first insulating film in which the lower interconnections and the interconnection-to-interconnection gap are formed such that an air gap is formed out of the interconnection-to-interconnection gap; and forming, in the second insulating film, a connection portion connected to one of the lower interconnections and an upper interconnection connected to the connection portion. The connection portion is formed to be connected to one of the lower interconnections not adjacent to the air gap. | 2011-01-27 |
20110021018 | METHOD FOR MANUFACTURING SEMICONDUCTOR DEVICE - A semiconductor device manufacturing method including: forming a first interlayer insulating film on a semiconductor substrate; forming a first hole in the first interlayer insulating film; forming a barrier film inside the first hole; filling a conductive material in the first hole to form a first plug; forming a second interlayer insulating film on the first interlayer insulating film; forming a second hole reaching the first plug in the second interlayer insulating film; selectively etching an upper end of the barrier film inside the second hole; and forming a second plug for connection to the first plug inside the second hole. | 2011-01-27 |
20110021019 | METHOD FOR FORMING DOPED POLYSILICON VIA CONNECTING POLYSILICON LAYERS - The invention provides for polysilicon vias connecting conductive polysilicon layers formed at different heights. Polysilicon vias are advantageously used in a monolithic three dimensional memory array of charge storage transistors. Polysilicon vias according to the present invention can be used, for example, to connect the channel layer of a first device level of charge storage transistor memory cells to the channel layer of a second device layer of such cells formed above the first device level. Similarly, vias according to the present invention can be used to connect the wordline of a first device level of charge storage transistor memory cells to the channel layer of a second device layer of such cells. | 2011-01-27 |
20110021020 | SEMICONDUCTOR DEVICE AND FABRICATION PROCESS THEREOF - A semiconductor device includes a first interconnection pattern embedded in a first insulation film, a second insulation film covering the first interconnection pattern over the first insulation film, an interconnection trench formed in an upper part of the second insulation film, a via-hole extending downward from the interconnection trench at a lower part of the second insulation film, the via-hole exposing the first interconnection pattern, a second interconnection pattern filling the interconnection trench, a via-plug extending downward in the via-hole from the second interconnection pattern and making a contact with the first interconnection pattern, and a barrier metal film formed between the second interconnection pattern and the interconnection trench, the barrier metal film covering a surface of the via-plug continuously, wherein the via-plug has a tip end part invading into the first interconnection pattern across a surface of said first interconnection pattern, the interconnection trench has a flat bottom surface, and the barrier metal film has a larger film thickness at the tip end part of the via-plug as compared with a sidewall surface of the via-plug. | 2011-01-27 |
20110021021 | METHOD OF FABRICATING DUAL DAMASCENE STRUCTURE - A method of fabricating a dual damascene structure is described. A dielectric layer and a metal hard mask layer are sequentially formed on a substrate having thereon a conductive layer and a liner layer. The metal hard mask layer and the dielectric layer are patterned to form a via hole exposing a portion of the liner layer. A gap-filling layer is filled in the via hole, having a height of ¼ to ½ of the depth of the via hole. A trench is formed in the metal hard mask layer and the dielectric layer. The gap-filling layer is removed to expose the portion of the liner layer, which is then removed. A metal layer is formed filling in the via hole and the trench, and then the metal hard mask layer is removed. | 2011-01-27 |
20110021022 | METHOD OF MANUFACTURING A SEMICONDUCTOR INTEGRATED CIRCUIT DEVICE - In forming five trenches buried with an intermediate conductive layer for connecting transfer MISFETs and driving MISFETs with vertical MISFETs formed thereover, in which the second and third trenches, and the first, fourth, and fifth trenches are formed separately by twice etching using first and second photoresist films as a mask. Since all the trenches can be formed at a good accuracy even in a case where the shortest distance between the first trench and the second or third trench, and the shortest distance between the second or third trench and the fourth trench is smaller than the resolution limit for the exposure light, the distance between each of the five trenches arranged in one identical memory cell can be reduced to be smaller than resolution limit for the exposure light. | 2011-01-27 |
20110021023 | Surface Treatment of Silicon - A method of forming a resist pattern on a silicon semiconductor substrate having an anti-reflective layer thereon is described. The method includes the steps of a) modifying surface energy of the anti-reflective surface with a chemical treatment composition, b) applying a UV etch resist to the treated anti-reflective surface, and c) exposing the anti-reflective surface to a wet chemical etchant composition to remove exposed areas of the anti-reflective surface. Thereafter, the substrate can be metallized to provide a conductor pattern. The method may be used to produce silicon solar cells. | 2011-01-27 |
20110021024 | SURFACE TREATMENT IN SEMICONDUCTOR MANUFACTURING - The present invention provides a process for forming a capping layer on a conducting interconnect for a semiconductor device, the process comprising: providing a substrate comprising one or more conductors in a dielectric layer, the conductors having an oxide layer at their surface; exposing the surface of the substrate to a vapour of β-diketone or a β-ketoimine; and depositing a capping layer on the surface of at least some of the one or more conductors. The present invention further provides an apparatus for carrying out this method. | 2011-01-27 |
20110021025 | METHOD FOR PRODUCING LASER-MARKED SEMICONDUCTOR WAFER - A laser-marked semiconductor wafer having a good flatness in the vicinity of laser mark-printed sites is produced by a method comprising a slicing step; a planarization step; a laser mark printing step; a grinding step; an etching step; and a polishing step. | 2011-01-27 |
20110021026 | METHODS FOR FABRICATING FINFET SEMICONDUCTOR DEVICES USING L-SHAPED SPACERS - Methods for fabricating semiconductor structures, such as fin structures of FinFET transistors, are provided. In one embodiment, a method comprises providing a semiconductor substrate and forming a plurality of mandrels overlying the semiconductor substrate. Each of the mandrels has sidewalls. L-shaped spacers are formed about the sidewalls of the mandrels. Each L-shaped spacer comprises a rectangular portion disposed at a base of a mandrel and an orthogonal portion extending from the rectangular portion. Each L-shaped spacer also has a spacer width. The orthogonal portions are removed from each of the L-shaped spacers leaving at least a portion of the rectangular portions. The semiconductor substrate is etched to form fin structures, each fin structure having a width substantially equal to the spacer width. | 2011-01-27 |
20110021027 | METHODS FOR FABRICATING NON-PLANAR ELECTRONIC DEVICES HAVING SIDEWALL SPACERS FORMED ADJACENT SELECTED SURFACES - Methods are provided for fabricating an electronic device having at least one sidewall spacer formed adjacent a selected surface. In one embodiment, the method includes the step of depositing spacer material adjacent first and second raised structures formed on the substrate and extending along substantially perpendicular axes. The method further includes the step of selectively removing spacer material laterally adjacent one of the first raised structure and the second raised structure. During the step of selectively removing, the electronic device is bombarded with ions from a first predetermined direction forming a first predetermined grazing angle with the substrate such that the spacer material adjacent a first sidewall of the first raised structure is substantially exposed to the ion bombardment while the spacer material adjacent opposing sidewalls of the second raised structure is substantially shielded therefrom. | 2011-01-27 |
20110021028 | METHODS FOR FABRICATING SEMICONDUCTOR DEVICES INCLUDING AZEOTROPIC DRYING PROCESSES - Embodiments of a method for fabricating a semiconductor device are provided. In one embodiment, the method includes the steps of providing a partially-completed semiconductor device including a first feature formed in a porous material, wet cleaning the partially-completed semiconductor device with an aqueous cleaning solvent, exposing the partially-completed semiconductor device to a liquid chemical that forms an azeotropic mixture with water, and inducing evaporation of the azeotropic mixture to remove residual water from within the porous material absorbed during the wet cleaning step. | 2011-01-27 |
20110021029 | PLASMA ETCH METHOD TO REDUCE MICRO-LOADING - A method of producing plurality of etched features in an electronic device is disclosed that avoids micro-loading problems thus maintaining more uniform sidewall profiles and more uniform critical dimensions. The method comprises performing a first time-divisional plasma etch process step within a plasma chamber to a first depth of the plurality of etched features, and performing a flash process step to remove any polymers from exposed surfaces of the plurality of etched features without requiring an oxidation step. The flash process step is performed independently of the time-divisional plasma etch step. A second time-divisional plasma etch process step is performed within the plasma chamber to a second depth of the plurality of etched features. The method may be repeated until a desired etch depth is reached. | 2011-01-27 |
20110021030 | REDUCING TWISTING IN ULTRA-HIGH ASPECT RATIO DIELECTRIC ETCH - An apparatus for etching a dielectric layer contained by a substrate is provided. An etch reactor comprises a top electrode and a bottom electrode. An etch gas source supplies an etch gas into the etch reactor. A first Radio Frequency (RF) source generates a first RF power with a first frequency and supplies the first RF power into the etch reactor, whereas the first frequency is between 100 kilo Hertz (kHz) and 600 kHz. A second RF source generates a second RF power with a second frequency and supplies the second RF power into the etch reactor, whereas the second frequency is at least 10 mega Hertz (MHz). | 2011-01-27 |
20110021031 | HIGH LIFETIME CONSUMABLE SILICON NITRIDE-SILICON DIOXIDE PLASMA PROCESSING COMPONENTS - A method of increasing mean time between cleans of a plasma etch chamber and chamber parts lifetimes is provided. Semiconductor substrates are plasma etched in the chamber while using at least one sintered silicon nitride component exposed to ion bombardment and/or ionized halogen gas. The sintered silicon nitride component includes high purity silicon nitride and a sintering aid consisting of silicon dioxide. A plasma processing chamber is provided including the sintered silicon nitride component. A method of reducing metallic contamination on the surface of a silicon substrate during plasma processing is provided with a plasma processing apparatus including one or more sintered silicon nitride components. A method of manufacturing a component exposed to ion bombardment and/or plasma erosion in a plasma etch chamber, comprising shaping a powder composition consisting of high purity silicon nitride and silicon dioxide and densifying the shaped component. | 2011-01-27 |
20110021032 | Etching of AlGaInAsSb - The present invention relates to a wet acid etchant for wet acid etching of intrinsic, n-doped or p-doped Al | 2011-01-27 |
20110021033 | BATCH CVD METHOD AND APPARATUS FOR SEMICONDUCTOR PROCESS - A batch CVD method repeats a cycle including adsorption and reaction steps along with a step of removing residual gas. The adsorption step is preformed while supplying the source gas into the process container by first setting the source gas valve open for a first period and then setting the source gas valve closed, without supplying the reactive gas into the process container by keeping the reactive gas valve closed, and without exhausting gas from inside the process container by keeping the exhaust valve closed. The reaction step is performed without supplying the source gas into the process container by keeping the source gas valve closed, while supplying the reactive gas into the process container by setting the reactive gas valve open, and exhausting gas from inside the process container by setting the exhaust valve to gradually decrease its valve opening degree from a predetermined open state. | 2011-01-27 |
20110021034 | SUBSTRATE PROCESSING APPARATUS AND METHOD - Disclosed is a substrate processing apparatus and method. The substrate processing apparatus includes a chamber ( | 2011-01-27 |
20110021035 | DEPOSITION APPARATUS AND METHOD OF MANUFACTURING SEMICONDUCTOR DEVICE USING THE SAME - Provided are a deposition apparatus and a method of manufacturing a semiconductor device. In the method, a reaction chamber provided with a gaseous source supply unit and a liquid source supply unit is prepared, and an etch stop layer is formed on a substrate by using a gaseous source. Then, an interlayer insulation layer is formed on the etch stop layer by using a vaporized liquid source and a vaporized dopant source. In this way, the etch stop layer and the interlayer insulation layer are formed in-situ in the same reaction chamber. | 2011-01-27 |
20110021036 | METHOD OF SEALING AN AIR GAP IN A LAYER OF A SEMICONDUCTOR STRUCTURE AND SEMICONDUCTOR STRUCTURE - A method of sealing an air gap in a layer of a semiconductor structure comprises providing a first layer of the semiconductor structure having at least one air gap for providing isolation between at least two conductive lines formed in the first layer. The at least one air gap extends into the first layer from a first surface of the first layer. The method further comprises forming a barrier layer of a barrier dielectric material over the first surface of the first layer and the at least one air gap. The barrier dielectric material is selected to have a dielectric constant less than 3.5 and to provide a barrier to prevent chemicals entering the at least one air gap. In another embodiment, the at least one air gap extends from a first surface of the first layer to at least a portion of side surfaces of the at least two conductive lines to expose at least a portion of the side surfaces, and a barrier layer of a barrier dielectric material is formed over the exposed portions of the side surfaces of each of the at least two conductive lines. | 2011-01-27 |
20110021037 | COMPOSITION FOR MANUFACTURING SIO2 RESIST LAYERS AND METHOD OF ITS USE - The present invention relates to compositions, which are useful for the generation of patterned or structured SiO | 2011-01-27 |
20110021038 | HEATING DEVICE, SUBSTRATE PROCESSING APPARATUS, AND METHOD OF MANUFACTURING SEMICONDUCTOR DEVICE - Provided are a heating device, a substrate processing apparatus, and a method of manufacturing a semiconductor device, which can suppress differences between heating bodies, and simultaneously, can suppress shearing of a holder due to thermal deformation of the heating element. The heating device comprises: a heating element including a mountain part and a valley part that are alternately connected in plurality in a meander shape with both ends being fixed; holding body receiving parts respectively installed at ends of the valley parts and formed as cutout parts having a width larger than a width of the valley part; an insulating body installed at an outer circumference of the heating element; and a holding body disposed in the holding body receiving part and fixed to the insulating body. | 2011-01-27 |
20110021039 | HEATING DEVICE, SUBSTRATE PROCESSING APPARATUS, AND METHOD OF MANUFACTURING SEMICONDUCTOR DEVICE - Provided are a heating device, a substrate processing apparatus, and a method of manufacturing a semiconductor device. The heating device comprises: a heating element including a mountain part and a valley part that are alternately connected in plurality in a meander shape with both ends being fixed; holding body receiving parts respectively installed at ends of the valley parts and formed as cutout parts having a width larger than a width of the valley part; an insulating body installed at an outer circumference of the heating element; a holding body disposed in the holding body receiving part and fixed to the insulating body; the heating element having a ring shape; the insulating body installed in a manner of surrounding the outer circumference of the heating element; and a fixation part configured to fix the heating element to an inner wall of the insulating body. | 2011-01-27 |