04th week of 2012 patent applcation highlights part 43 |
Patent application number | Title | Published |
20120021546 | Method of fabricating semiconductor substrate and method of fabricating light emitting device - The present invention provides a method of fabricating a semiconductor substrate and a method of fabricating a light emitting device. The method includes forming a first semiconductor layer on a substrate, forming a metallic material layer on the first semiconductor layer, forming a second semiconductor layer on the first semiconductor layer and the metallic material layer, wherein a void is formed in a first portion of the first semiconductor layer under the metallic material layer during formation of the second semiconductor layer, and separating the substrate from the second semiconductor layer by etching at least a second portion of the first semiconductor layer using a chemical solution. | 2012-01-26 |
20120021547 | INK-JET INK FOR ORGANIC ELECTROLUMINESCENT DEVICES AND METHOD FOR PRODUCING ORGANIC ELECTROLUMINESCENT DEVICES - The problem is to provide such an ink-jet ink for organic EL devices that a jetted droplet trails no ligaments and wet-spreads well upon adhering. The solution is an ink-jet ink for organic electroluminescent device comprising water, a surfactant and an aqueous macromolecular material, wherein the ink has a static surface tension of 40 mN/m or less and a dynamic surface tension, measured by a maximum bubble pressure method at 100 Hz, of 55 mN/m or more. | 2012-01-26 |
20120021548 | Apparatus For Forming A Film And An Electroluminescence Device - A device having three evaporation sources and a unit for moving the respective evaporation sources in one chamber is used, whereby it becomes possible to increase efficiency of use of an evaporation material. Consequently, manufacturing cost can be reduced, and a uniform thickness can be obtained over an entire surface of a substrate even in the case in which a large area substrate is used. | 2012-01-26 |
20120021549 | METHOD FOR GROWING CRYSTALS OF NITRIDE SEMICONDUCTOR, AND PROCESS FOR MANUFACTURE OF SEMICONDUCTOR DEVICE - A nitride semiconductor layer formation method includes the steps of: (S1) placing a substrate in a reaction chamber, the substrate including a −r-plane nitride semiconductor crystal at least in an upper surface; (S2) increasing a temperature of the substrate by heating the substrate placed in the reaction chamber; and (S3) growing a nitride semiconductor layer on the substrate. In the temperature increasing step (S2), a nitrogen source gas and a Group III element source gas are supplied into the reaction chamber. | 2012-01-26 |
20120021550 | METHOD FOR FABRICATING A FIXED STRUCTURE DEFINING A VOLUME RECEIVING A MOVABLE ELEMENT IN PARTICULAR OF A MEMS - The fabrication of a semiconductor fixed structure defining a volume, for example of a MEMS micro electro-mechanical system includes, determining thicknesses beforehand depending on the functional distances associated with elements. At least one element is formed on a substrate by thermal oxidation of the substrate so as to form an oxide layer followed by selective etching of the oxide layer so as to define the volume in an etched portion by baring the underlying substrate so as to define the element in an unetched portion, and later oxidation of the substrate so as to form an oxide layer, in order to obtain the elements at the functional distances. | 2012-01-26 |
20120021551 | THERMOELECTRIC CONVERSION MODULE AND METHOD FOR MANUFACTURING THE SAME - A compact, high-performance thermoelectric conversion module includes a laminate having a plurality of insulating layers, p-type thermoelectric semiconductors and n-type thermoelectric semiconductors formed by a technique for manufacturing a multilayer circuit board, particularly a technique for forming a via-conductor. Pairs of the p-type thermoelectric semiconductors and the n-type thermoelectric semiconductors are electrically connected to each other in series through p-n connection conductors to define thermoelectric conversion element pairs. The thermoelectric conversion element pairs are connected in series through, for example, series wiring conductors. The thermoelectric semiconductors each have a plurality of portions in which the peak temperatures of thermoelectric figures of merit are different from each other. These portions are distributed in the stacking direction of the laminate. | 2012-01-26 |
20120021552 | Quartz Boat Method and Apparatus for Thin Film Thermal Treatment - A method of supporting a plurality of planar substrates in a tube shaped furnace for conducting a thermal treatment process is disclosed. The method uses a boat fixture having a base frame including two length portions and a first width portion, a second width portion, and one or more middle members connected between the two length portions. Additionally, the method includes mounting a removable first grooved rod respectively on the first width portion, the second width portion, and each of the one or more middle members, each first grooved rod having a first plurality of grooves characterized by a first spatial configuration. The method further includes inserting one or two substrates of a plurality of planar substrates into each groove in the boat fixture separated by a distance. | 2012-01-26 |
20120021553 | METHODS FOR DISCRETIZED PROCESSING AND PROCESS SEQUENCE INTEGRATION OF REGIONS OF A SUBSTRATE - The present invention provides methods and systems for discretized, combinatorial processing of regions of a substrate such as for the discovery, implementation, optimization, and qualification of new materials, processes, and process sequence integration schemes used in integrated circuit fabrication. A substrate having an array of differentially processed regions thereon is processed by delivering materials to or modifying regions of the substrate. | 2012-01-26 |
20120021554 | METHOD OF FORMATION OF NANOWIRES AND METHOD OF MANUFACTURE OF ASSOCIATED OPTICAL COMPONENT - A method of formation of nanowires at a surface of a substrate attached to a solid immersion lens. The method includes formation of a catalyst element at the surface of the substrate and growth of nanowires from the catalyst element formed at the surface of the substrate. The catalyst element is a metal nanoparticle and the formation of the catalyst element at the surface of the substrate deposits the metal nanoparticle using a light beam focused by the solid immersion lens at the surface of the substrate. | 2012-01-26 |
20120021555 | PHOTOVOLTAIC CELL TEXTURIZATION - A photovoltaic cell texturization method is disclosed. The method includes providing a photovoltaic cell substrate; and texturizing a surface of the photovoltaic cell substrate. The texturizing implements a nanoimprint lithography process to expose a portion of the surface of the photovoltaic cell substrate. An etching process is performed on the exposed portion of the exposed portion of the surface of the photovoltaic cell substrate. | 2012-01-26 |
20120021556 | DEPOSITION SYSTEM - A selenium deposition system can improve the selenium vapor distribution. | 2012-01-26 |
20120021557 | METHOD FOR MANUFACTURING A SOLAR CELL - A method for manufacturing a solar cell comprises disposing a first doping layer on a substrate, forming a first doping layer pattern by patterning the first doping layer to expose a portion of the substrate, disposing a second doping layer on the first doping layer pattern to cover the exposed portion of the substrate, diffusing an impurity from the first doping layer pattern which forms a first doping region in a surface of the substrate, and diffusing an impurity from the second doping layer which forms a second doping region in the surface of the substrate, wherein the forming of the first doping layer pattern uses an etching paste. | 2012-01-26 |
20120021558 | SEMICONDUCTOR SUBSTRATE FOR SOLID-STATE IMAGE SENSING DEVICE AS WELL AS SOLID-STATE IMAGE SENSING DEVICE AND METHOD FOR PRODUCING THE SAME - There is provided a semiconductor substrate for solid-state image sensing device in which the production cost is lower than that of a gettering method through a carbon ion implantation and problems such as occurrence of particles at a device production step and the like are solved. | 2012-01-26 |
20120021559 | HIGH SPEED LASER CRYSTALLIZATION OF PARTICLES OF PHOTOVOLTAIC SOLAR CELLS - A system and method for enhancing the conversion efficiency of thin film photovoltaics. The thin film structure includes a photovoltaic absorbent layer covered by a confinement layer. A laser beam passes through the confinement layer and hits the photovoltaic absorbent layer. The laser can be pulsed to create localized rapid heating and cooling of the photovoltaic absorbent layer. The confinement layer confines the laser induced plasma plume creating a localized high-pressure condition for the photovoltaic absorbent layer. The laser beam can be scanned across specific regions of the thin film structure. The laser beam can be pulsed as a series of short pulses. The photovoltaic absorbent layer can be made of various materials including copper indium diselenide, gallium arsenide, and cadmium telluride. The photovoltaic absorbent layer can be sandwiched between a substrate and the confinement layer, and a molybdenum layer can be between the substrate and the photovoltaic absorbent layer. | 2012-01-26 |
20120021560 | TRUNCATED PYRAMID STRUCTURES FOR SEE-THROUGH SOLAR CELLS - The present disclosure presents a partially-transparent (see-through) three-dimensional thin film solar cell (3-D TFSC) substrate. The substrate includes a plurality of unit cells. Each unit cell structure has the shape of a truncated pyramid, and its parameters may be varied to allow a desired portion of sunlight to pass through. | 2012-01-26 |
20120021561 | PLASMA PROCESSING APPARATUS AND METHOD FOR MANUFACTURING SOLAR CELL USING SAME - A method of manufacturing a solar cell in which qualities and thicknesses of formed films are uniformed is obtained. This method of manufacturing a solar cell includes steps of forming a substrate-side electrode ( | 2012-01-26 |
20120021562 | METHOD FOR FORMING TERMINAL OF STACKED PACKAGE ELEMENT AND METHOD FOR FORMING STACKED PACKAGE - A semiconductor chip module having high degree of freedom in assignment of a circuit to each semiconductor chip and in position of a connection terminal of each semiconductor chip is provided. The present invention relates to a semiconductor chip module in which a plurality of semiconductor chips, each provided on the side face thereof with a part of a connection terminal coupled with a circuit pattern formed on the front face, have been stacked and bonded. Connection terminal portions on the side faces of the respective semiconductor chips are interconnected by a wiring pattern. The connection terminal on the semiconductor chip is led from the front face to the side face and formed by applying spraying of a conductive material in a mist state. | 2012-01-26 |
20120021563 | METHOD AND APPARATUS FOR MANUFACTURING THREE-DIMENSIONAL INTEGRATED CIRCUIT - There is provided a three-dimensional integrated circuit manufacturing method for temporarily attaching a chip to a transcription substrate, and securely detaching the chip from the transcription substrate when the chip is transferred to a supporting substrate. When a chip is temporarily attached to a transcription substrate, by evaporating a liquid existing between the chip and the transcription substrate, the solids of the chip and the transcription substrate can be attached to each other. Accordingly, the chip can be temporarily attached to the transcription substrate so as not to be deviated from its own position. Further, by setting adhesive strength between the chip and a supporting substrate to be higher than that between the chip and the transcription substrate, the chip can be securely detached from the transcription substrate when the chip is transferred from the transcription substrate to the supporting substrate. | 2012-01-26 |
20120021564 | Method for packaging semiconductor device - The present invention provides a method for packaging semiconductor device which is using more than once reflow processes to heat the solder ball to prevent the deformation of solder ball, so that the yield of the manufacturing process can be increased and the reliability of the semiconductor device can be increased. | 2012-01-26 |
20120021565 | METHOD OF FORMING A PACKAGED SEMICONDUCTOR DEVICE - A method is used to form a packaged semiconductor device. A semiconductor device, which has an active surface, is placed in an opening of a circuit board. The circuit board has a first major surface and a second major surface having the opening, first vias that extend between the first major surface and the second major surface, first contact pads terminating the vias at the first major surface, and second contact pads terminating the vias at the second major surface. A dielectric layer is applied over the semiconductor device and the second major surface of the circuit board. An interconnect layer is formed over the dielectric layer. The interconnect layer has second vias electrically connected to the second contact pads, third vias that are electrically connected to the active surface of the semiconductor device, an exposed surface, and third contact pads at the exposed surface. | 2012-01-26 |
20120021566 | CARBON NANOTUBE MICRO-CHIMNEY AND THERMO SIPHON DIE-LEVEL COOLING - A method, apparatus and system with a semiconductor package including a microchimney or thermosiphon using carbon nanotubes to modify the effective thermal conductivity of an integrated circuit die. | 2012-01-26 |
20120021567 | NOVEL REWORKABLE UNDERFILLS FOR CERAMIC MCM C4 PROTECTION - The present invention provides chip containing electronic devices such as Multichip Ceramic Modules (MCM's) containing a plurality of chips on a substrate which chips are underfilled with a reworkable composition which allows one or more chips to be removed from the device and replaced. The reworkable compositions contain a base resin which is not cross-linkable and which forms a matrix with a linear curable component or preferably a combination of linear curable components which curable components are cross-linkable and when cured form a cross-linked domain in the base resin matrix. A suitable cross-linking catalyst such as Pt is used and optionally a filler preferably silane surface treated silica. The preferred base resin is linear polydimethylsiloxane and the preferred curable components are vinyl terminated linear poly dimethyl siloxane and hydrogen terminated linear poly dimethyl siloxane. | 2012-01-26 |
20120021568 | METHOD OF MANUFACTURING CIRCUIT DEVICE - Provided is a method of manufacturing a circuit device in which a circuit element is resin-sealed with sealing resins formed integrally with each other. In the present invention, a resin sheet and a circuit board are housed in a cavity of a mold, and thereafter a first sealing resin formed of a tablet in melted form is injected into the cavity. At the time of injecting the first sealing resin, a second sealing resin formed of the resin sheet in melted form is not yet cured and is maintained in liquid form. Accordingly, the injected first sealing resin and the second sealing resin are mixed at the boundary therebetween, preventing the generation of a gap in the boundary portion and therefore preventing the deterioration of the moisture resistance and withstand voltage at the boundary portion. | 2012-01-26 |
20120021569 | MANUFACTURING METHOD OF SOI HIGH-VOLTAGE POWER DEVICE - The present invention relates to a manufacturing method of SOI devices, and in particular, to a manufacturing method of SOI high-voltage power devices. The method comprises steps of: forming a first oxide layer in a section on the surface of the SOI substrate; removing the first oxide layer to form a depressed area in the corresponding section of the upper surface of the SOI substrate; forming a second oxide layer, the upper surface of which is as high as the that of the SOI substrate, in the depressed area formed in step (B); performing photoetching and doping processes to form a P-type region, an N-type region and a gate region on the thus-formed structure where the second oxide layer is formed; forming a third oxide layer by deposition on the drift region of the structure after P-type and N-type regions are formed; wherein the total thickness of the third oxide layer and the second oxide layer approximates to the thickness of the buried oxide layer in the SOI substrate; and forming metal sub-regions, which are respectively in contact with the P-type region, the N-type region and the gate region, on the structure where the third oxide layer is formed, thereby forming a high-voltage power device. | 2012-01-26 |
20120021570 | METHOD FOR FORMING MICROCRYSTALLINE SEMICONDUCTOR FILM AND METHOD FOR MANUFACTURING SEMICONDUCTOR DEVICE - A seed crystal including mixed phase grains having high crystallinity with a low grain density is formed under a first condition, and a microcrystalline semiconductor film is formed over the seed crystal under a second condition which allows the mixed phase grains in the seed crystal to grow to fill a space between the mixed phase grains. In the first condition, the flow rate of hydrogen is 50 times or greater and 1000 times or less that of a deposition gas containing silicon or germanium, and the pressure in a process chamber is greater than 1333 Pa and 13332 Pa or less. In the second condition, the flow rate of hydrogen is 100 times or greater and 2000 times or less that of a deposition gas containing silicon or germanium, and the pressure in the process chamber is 1333 Pa or greater and 13332 Pa or less. | 2012-01-26 |
20120021571 | Method of Reducing Floating Body Effect of SOI MOS Device Via a Large Tilt Ion Implantation - The present invention discloses a method of reducing floating body effect of SOI MOS device via a large tilt ion implantation including a step of: (a) implanting ions in an inclined direction into an NMOS with a buried insulation layer forming a highly doped P region under a source region of the NMOS and above the buried insulation layer, wherein the angle between a longitudinal line of the NMOS and the inclined direction is ranging from 15 to 45 degrees. Through this method, the highly doped P region under the source region and a highly doped N region form a tunnel junction so as to reduce the floating body effect. Furthermore, the chip area will not be increased, manufacturing process is simple and the method is compatible with conventional CMOS process. | 2012-01-26 |
20120021572 | METHOD FOR FABRICATING SEMICONDUCTOR DEVICE - A method for fabricating a semiconductor device includes forming ohmic electrodes on a source region and a drain region of a nitride semiconductor layer, forming a low-resistance layer between an uppermost surface of the nitride semiconductor layer and the ohmic electrodes by annealing the nitride semiconductor layer, removing the ohmic electrodes from at least one of the source region and the drain region after forming the low-resistance layer, and forming at least one of a source electrode and a drain electrode on the low-resistance layer, the at least one of a source electrode and a drain electrode having an edge, a distance between the edge and a gate electrode is longer than a distance between an edge of the low-resistance layer and the gate electrode. | 2012-01-26 |
20120021573 | Methods Of Forming An Array Of Memory Cells, Methods Of Forming A Plurality Of Field Effect Transistors, Methods Of Forming Source/Drain Regions And Isolation Trenches, And Methods Of Forming A Series Of Spaced Trenches Into A Substrate - A method of forming a series of spaced trenches into a substrate includes forming a plurality of spaced lines over a substrate. Anisotropically etched sidewall spacers are formed on opposing sides of the spaced lines. Individual of the lines have greater maximum width than minimum width of space between immediately adjacent of the spacers between immediately adjacent of the lines. The spaced lines are removed to form a series of alternating first and second mask openings between the spacers. The first mask openings are located where the spaced lines were located and are wider than the second mask openings. Alternating first and second trenches are simultaneously etched into the substrate through the alternating first and second mask openings, respectively, to form the first trenches to be wider and deeper within the substrate than are the second trenches. Other implementations and embodiments are disclosed. | 2012-01-26 |
20120021574 | METHOD FOR FABRICATING VERTICAL CHANNEL TYPE NONVOLATILE MEMORY DEVICE - A method for fabricating a vertical channel type nonvolatile memory device includes: stacking a plurality of interlayer insulating layers and a plurality of gate electrode conductive layers alternately over a substrate; etching the interlayer insulating layers and the gate electrode conductive layers to form a channel trench exposing the substrate; forming an undoped first channel layer over the resulting structure including the channel trench; doping the first channel layer with impurities through a plasma doping process; and filling the channel trench with a second channel layer. | 2012-01-26 |
20120021575 | DIFFUSING IMPURITY IONS INTO PILLARS TO FORM VERTICAL TRANSISTORS - A method for manufacturing a semiconductor device comprises: forming a pillar pattern including a sidewall contact over a semiconductor substrate; forming a silicon layer in a lower portion disposed between the pillar patterns; implanting ions into the silicon layer; diffusing the implanted impurity ions into the inside of the pillar pattern to form an ion-implanting region; removing the silicon layer; and burying a conductive material in the lower portion disposed between the pillar patterns. The method can prevent a floating body effect by adding a process of a vertical channel transistor. | 2012-01-26 |
20120021576 | VERTICAL TRANSISTOR AND METHOD FOR FORMING THE SAME - A vertical transistor and a method for forming the same. The vertical transistor includes a semiconductor substrate having pillar type active patterns formed on a surface thereof; first junction regions formed in the surface of the semiconductor substrate on both sides of the active patterns; screening layers formed on sidewalls of the first junction regions; second junction regions formed on upper surfaces of the active patterns; and gates formed on sidewalls of the active patterns including the second junction regions to overlap with at least portions of the first junction regions. | 2012-01-26 |
20120021577 | GATE TRENCH CONDUCTOR FILL - Semiconductor devices and methods for making such devices are described. The semiconductor devices contain a substrate with a trench in an upper portion thereof, a gate insulating layer on a sidewall and bottom of the trench, and a conductive gate of an amorphous silicon or polysilicon material on the gate oxide layer. The amorphous silicon or polysilicon layer can be doped with nitrogen, as well as B and/or P dopants, which have been activated by microwaves. The devices can be made by providing a trench in the upper surface of a semiconductor substrate, forming a gate insulating layer on the trench sidewall and bottom, and depositing a doped amorphous silicon or polysilicon layer on the gate insulating layer, and then activating the deposited amorphous silicon or polysilicon layer at low temperatures using microwaves. The resulting polysilicon or amorphous silicon layer contains fewer voids resulting from Si grain movement. Other embodiments are described. | 2012-01-26 |
20120021578 | METHOD OF MANUFACTURING SEMICONDUCTOR DEVICE - A trench gate type power transistor of high performance is provided. A trench gate as a gate electrode is formed in a super junction structure comprising a drain layer and an epitaxial layer. In this case, the gate electrode is formed in such a manner that an upper surface of the epitaxial layer becomes higher than that of a channel layer formed over the drain layer. Then, an insulating film is formed over each of the channel layer and the epitaxial layer and thereafter a part of the insulating film is removed to form side wall spacers over side walls of the epitaxial layer. Subsequently, with the side wall spacers as masks, a part of the channel layer and that of the drain layer are removed to form a trench for a trench gate. | 2012-01-26 |
20120021579 | SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD THEREOF - An aspect of the present invention provides a semiconductor device that includes a first conductivity type semiconductor body, a source region in contact with the semiconductor body, whose bandgap is different from that of the semiconductor body, and which formed heterojunction with the semiconductor body, a gate insulating film in contact with a portion of junction between the source region and the semiconductor body, a gate electrode in contact with the gate insulating film, a source electrode, a low resistance region in contact with the source electrode and the source region, and connected ohmically with the source electrode, and a drain electrode connected ohmically with the semiconductor body. | 2012-01-26 |
20120021580 | METHOD OF MANUFACTURING TRENCH MOSFET STRUCTURES USING THREE MASKS PROCESS - In according with the present invention, a semiconductor device is formed as follows. A contact insulation layer is deposited on the top surface of said silicon layer. A contact mask is applied and following with a dry oxide etching to remove the contact insulation layer from contact open areas. The silicon layer is implanted with a source dopant through the contact open areas and the source dopant is diffused to form source regions, thereby a source mask is saved. A dry silicon etch is carried out to form trenched source-body contacts in the contact open areas, penetrating through the source regions and extending into the body regions. | 2012-01-26 |
20120021581 | SELF-ALIGNED CONTACT STRUCTURE LATERALLY ENCLOSED BY AN ISOLATION STRUCTURE OF A SEMICONDUCTOR DEVICE - By forming an isolation structure that extends above the height level defined by the semiconductor material of an active region, respective recesses may be defined in combination with gate electrode structures of the completion of basic transistor structures. These recesses may be subsequently filled with an appropriate contact material, thereby forming large area contacts in a self-aligned manner without requiring deposition and patterning of an interlayer dielectric material. Thereafter, the first metallization layer may be formed, for instance, on the basis of well-established techniques wherein the metal lines may connect directly to respective “large area” contact elements. | 2012-01-26 |
20120021582 | METHOD OF MANUFACTURING SEMICONDUCTOR DEVICE - A method of manufacturing a semiconductor device includes: forming a lower electrode layer in contact with a surface of a nitride semiconductor layer; forming an Al layer on the lower electrode layer; performing a heat treatment after the formation of the Al layer; removing the Al layer after the heat treatment is performed; and forming an upper electrode layer on the lower electrode layer after the removal of the Al layer. | 2012-01-26 |
20120021583 | SEMICONDUCTOR PROCESS - A semiconductor process is disclosed. The semiconductor process includes the steps of: providing a substrate having a specific area defined thereon; and performing an etch process by using an etchant comprising H | 2012-01-26 |
20120021584 | SEMICONDUCTOR DEVICE AND METHOD FOR MANUFACTURING THE SAME - The present invention provides a semiconductor device and a method for manufacturing the same. The method includes: providing a substrate; forming a gate stack on the substrate; forming an inter layer dielectric (ILD) to cover the device; etching the ILD at both sides of the gate stack and the substrate below the ILD, so as to form a groove of source and drain regions respectively; depositing a metal diffusion barrier layer in the groove; and filling the groove with a metal to form the source and drain regions. The semiconductor device includes: a substrate; a gate stack on the substrate; an inter layer dielectric (ILD) covering the device; a groove of source and drain regions formed in the ILD at both sides of the gate stack and the substrate below the ILD; and a metal diffusion barrier layer and a metal filler formed in the groove. According to the present invention, the S/D parasitic resistance in the MOS device is reduced, the S/D stress on the channel is increased, the process temperature is lowered, and the process compatibility between the high k gate dielectric layer and the metal gate is improved. | 2012-01-26 |
20120021585 | METHOD OF MANUFACTURING POLYCRYSTALLINE SILICON LAYER, AND METHOD OF MANUFACTURING TRANSISTOR HAVING THE POLYCRYSTALLINE SILICON LAYER - An embodiment is directed to a method of manufacturing a polycrystalline silicon layer, the method including providing a crystallization substrate, the crystallization substrate having an amorphous silicon layer on a first substrate, providing a reflection substrate, the reflection substrate having a first region with a reflection panel therein and a second region without the reflection panel, disposing the crystallization substrate and the reflection substrate on one another, and selectively crystallizing the amorphous silicon layer by directing a laser beam onto the crystallization substrate and the reflection substrate, and reflecting the laser beam from the reflection panel. | 2012-01-26 |
20120021586 | METHODS FOR FORMING VARACTOR DIODES - Methods are disclosed for forming an improved varactor diode having first and second terminals. The methods include providing a substrate having a first surface in which are formed isolation regions separating first and second parts of the diode. A varactor junction is formed in the first part with a first side coupled to the first terminal and a second side coupled to the second terminal via a sub-isolation buried layer (SIBL) region extending under the bottom and partly up the sides of the isolation regions to a further doped region that is ohmically connected to the second terminal. The first part does not extend to the SIBL region. The varactor junction desirably comprises a hyper-abrupt doped region. The combination provides improved tuning ratio, operating frequency and breakdown voltage of the varactor diode while still providing adequate Q. | 2012-01-26 |
20120021587 | Systems and Methods for Forming Metal Oxide Layers - A method of forming (and apparatus for forming) a metal oxide layer, preferably a dielectric layer, on a substrate, particularly a semiconductor substrate or substrate assembly, using a vapor deposition process and ozone with one or more metal organo-amine precursor compounds. | 2012-01-26 |
20120021588 | METHOD FOR MANUFACTURING SOI SUBSTRATE AND SEMICONDUCTOR DEVICE - One object is to provide excellent electric characteristics of an end portion of a single crystal semiconductor layer having a tapered shape. An embrittled region is formed in a single crystal semiconductor substrate by irradiating the single crystal semiconductor substrate with accelerated ions. Then, the single crystal semiconductor substrate and a base substrate are bonded to each other with an insulating film interposed therebetween and a first single crystal semiconductor layer is formed over the base substrate with the insulating film interposed therebetween by separating the single crystal semiconductor substrate at the embrittled region. After that, a second single crystal semiconductor layer having a tapered end portion is formed by performing dry etching on the first single crystal semiconductor layer, and etching is performed on the end portion of the second single crystal semiconductor layer in a state where a potential on the base substrate side is a ground potential. | 2012-01-26 |
20120021589 | METHOD OF FABRICATION OF A SEMICONDUCTOR DEVICE HAVING REDUCED PITCH - Provided is a photolithography apparatus including a photomask. The photomask includes a pattern having a plurality of features, in an example, dummy line features. The pattern includes a first region being in the form of a localized on-grid array and a second region where at least one of the features has an increased width. The apparatus may include a second photomask which may define an active region. The feature with an increased width may be adjacent, and outside, the defined active region. | 2012-01-26 |
20120021590 | Tellurium Precursors for Film Deposition - Methods and compositions for depositing a tellurium-containing film on a substrate are disclosed. A reactor and at least one substrate disposed in the reactor are provided. A tellurium-containing precursor is provided and introduced into the reactor, which is maintained at a temperature ranging from approximately 20° C. to approximately 100° C. Tellurium is deposited on to the substrate through a deposition process to form a thin film on the substrate. | 2012-01-26 |
20120021591 | Method of Manufacturing Nitride Substrate for Semiconductors - In an independent GaN film manufactured by creating a GaN layer on a base heterosubstrate using vapor-phase deposition and then removing the base substrate, owing to layer-base discrepancy in thermal expansion coefficient and lattice constant, bow will be a large ±40 μm to ±100 μm. Since with that bow device fabrication by photolithography is challenging, reducing the bow to +30 μm to −20 μm is the goal. The surface deflected concavely is ground to impart to it a damaged layer that has a stretching effect, making the surface become convex. The damaged layer on the surface having become convex is removed by etching, which curtails the bow. Alternatively, the convex surface on the side opposite the surface having become convex is ground to generate a damaged layer. With the concave surface having become convex due to the damaged layer, suitably etching off the damaged layer curtails the bow. | 2012-01-26 |
20120021592 | APPARATUS AND METHOD FOR DOPING - There is proposed an apparatus for doping a material to be doped by generating plasma (ions) and accelerating it by a high voltage to form an ion current is proposed, which is particularly suitable for processing a substrate having a large area. The ion current is formed to have a linear sectional configuration, and doping is performed by moving a material to be doped in a direction substantially perpendicular to the longitudinal direction of a section of the ion current. | 2012-01-26 |
20120021593 | METHOD FOR MANUFACTURING SEMICONDUCTOR DEVICE - A method for manufacturing a semiconductor device includes implanting indium into a first region of a semiconductor substrate; forming a first gate insulation film having a first film thickness in the first region and a second region different from the first region after the implanting; removing the first gate insulation film from the first region; applying heat treatment to the semiconductor substrate after the forming; and forming a second gate insulation film having a second film thickness on the first region after the applying. In the method, a temperature falling rate of the heat treatment in the applying is 20° C. per second or higher. | 2012-01-26 |
20120021594 | Methods of Forming a Plurality of Transistor Gates, and Methods of Forming a Plurality of Transistor Gates Having at Least Two Different Work Functions - A method of forming a plurality of transistor gates having at least two different work functions includes forming first and second transistor gates over a substrate having different widths, with the first width being narrower than the second width. A material is deposited over the substrate including over the first and second gates. Within an etch chamber, the material is etched from over both the first and second gates to expose conductive material of the first gate and to reduce thickness of the material received over the second gate yet leave the second gate covered by the material. In situ within the etch chamber after the etching, the substrate is subjected to a plasma comprising a metal at a substrate temperature of at least 300° C. to diffuse said metal into the first gate to modify work function of the first gate as compared to work function of the second gate. | 2012-01-26 |
20120021595 | SEMICONDUCTOR MEMORY DEVICE AND METHOD OF MANUFACTURING THE SAME - A method of manufacturing a semiconductor device includes providing a substrate having junction regions and contact plugs formed thereon. A second insulating layer is formed over a first insulating layer and includes first and second pad holes extending in different directions and exposing the contact plugs. First and second conductive pads are formed in the first and second pad holes, respectively. A third insulating layer is formed and includes dual damascene patterns and pad contact holes. The dual damascene pattern exposes the first conductive pad, and each pad contact hole exposes a second conductive pad. First pad contact plugs and a first bit line are formed in the dual damascene pattern and a second pad contract plug is formed in each pad contact hole. A fourth insulating layer including trenches is formed. Each trench exposes a second pad contact plug. A second bit line is formed in each trench. | 2012-01-26 |
20120021596 | METHOD OF MANUFACTURING A SEMICONDUCTOR DEVICE - The present invention relates to the field of semiconductor manufacturing. The present invention provides a method of manufacturing a semiconductor device, which comprises: providing a semiconductor substrate; forming an interface layer, a gate dielectric layer and a gate electrode on the substrate; forming a metal oxygen absorption layer on the gate electrode; performing a thermal annealing process on the semiconductor device so that the metal oxygen absorption layer absorbs oxygen in the interface layer and the thickness of the interface layer is reduced. By means of the present invention, the thickness of the interface layer can be reduced on one hand, and on the other hand the metal in the metal oxygen absorption layer is made to diffuse into the gate electrode and/or the gate dielectric layer through the annealing process, which further achieves the effects of adjusting the effective work function and controlling the threshold voltage. | 2012-01-26 |
20120021597 | METHOD FOR FABRICATING SEMICONDUCTOR DEVICE - A method for fabricating a semiconductor device including: forming a silicon layer on an upper face of a nitride semiconductor layer including a channel layer of a FET; thermally treating the nitride semiconductor layer in the process of forming the silicon layer or after the process of forming the silicon layer; and forming an insulating layer on an upper face of the silicon layer after the process of forming the silicon layer. | 2012-01-26 |
20120021598 | METHOD FOR FABRICATING SEMICONDUCTOR DEVICE - A method for fabricating a semiconductor device having a GaN-based semiconductor layer on a first surface of a substrate made of SiC, a pad being provided on the GaN-based layer, includes: forming a first via hole in the substrate by etching, with fluorine based gas, from a second surface of the substrate opposite to the first surface, the etching being carried out with the GaN-based layer being used as an etch stopper; and forming a second via hole in the GaN-based semiconductor layer, with chlorine based gas, from a bottom surface of the first via hole, the etching being carried out with the pad being used as an etching stopper, the chlorine based gas being an etchant different from the fluorine based gas. | 2012-01-26 |
20120021599 | Methods for Avoiding Parasitic Capacitance in an Integrated Circuit Package - An integrated circuit package substrate includes a first and an additional electrically conductive layer separated from each other by an electrically insulating layer, a contact pad formed in the first electrically conductive layer for making a direct connection between the integrated circuit package substrate and a printed circuit board, and a cutout formed in the additional electrically conductive layer wherein the cutout encloses an area that completely surrounds the contact pad for avoiding parasitic capacitance between the additional electrically conductive layer and the printed circuit board. | 2012-01-26 |
20120021600 | METHOD OF FABRICATING FILM CIRCUIT SUBSTRATE AND METHOD OF FABRICATING CHIP PACKAGE INCLUDING THE SAME - A method of fabricating a film circuit substrate and a method of fabricating a chip package. The method of fabricating a film circuit substrate can include providing a base film including a chip packaging area to package a chip and a separation area to separate the two chip packaging areas from each other, the separation area including a cut area and an uncut area; forming a reserve interconnection pattern having a first height on the base film; and forming an interconnection pattern having a second height that is lower than the first height on the out area by selectively etching the reserve interconnection pattern of the cut area. | 2012-01-26 |
20120021601 | Methods of Forming Through Substrate Interconnects - A method of forming a through substrate interconnect includes forming a via into a semiconductor substrate. The via extends into semiconductive material of the substrate. A liquid dielectric is applied to line at least an elevationally outermost portion of sidewalls of the via relative a side of the substrate from which the via was initially formed. The liquid dielectric is solidified within the via. Conductive material is formed within the via over the solidified dielectric and a through substrate interconnect is formed with the conductive material. | 2012-01-26 |
20120021602 | LOW RESISTANCE AND RELIABLE COPPER INTERCONNECTS BY VARIABLE DOPING - A method and system is provided for efficiently varying the composition of the metal interconnects for a semiconductor device. A metal interconnect according to the present disclosure has an intermediate layer on a dielectric material, the intermediate layer having a relatively higher concentration of an impurity metal along with a primary metal, the impurity metal having a lower reduction potential than the primary metal. The metal interconnect has a main layer of the metal alloy interconnect on top of the intermediate layer and surrounded by the intermediate layer, the main layer having a relatively higher concentration of the primary metal than the intermediate layer, wherein the intermediate and main layers of the metal alloy interconnect each maintains a material uniformity. | 2012-01-26 |
20120021603 | METHOD FOR FORMING COPPER INTERCONNECTION STRUCTURES - A method for forming a copper interconnection structure includes the steps of forming an opening in an insulating layer, forming a copper alloy layer including a metal element on an inner surface of the opening, and conducting a heat treatment on the copper alloy layer so as to form a barrier layer. An enthalpy of oxide formation for the metal element is lower than the enthalpy of oxide formation for copper. The heat treatment is conducted at temperatures ranging from 327° C. to 427° C. and for a time period ranging from 1 minute to 80 minutes. | 2012-01-26 |
20120021604 | Controlling Defects in Thin Wafer Handling - A method includes bonding a wafer on a carrier through an adhesive, and performing a thinning process on the wafer. After the step of performing the thinning process, a portion of the adhesive not covered by the wafer is removed, while the portion of the adhesive covered by the wafer is not removed. | 2012-01-26 |
20120021605 | SEMICONDUCTOR DEVICE PRODUCING METHOD - In a semiconductor device producing method according to one embodiment, an insulating film containing silicon is formed on a semiconductor substrate, a resist is deposited on the insulating film, the resist is patterned into a predetermined pattern, and the insulating film is processed by a dry etching treatment in which gas containing C, F, Br, H, and O is used with the resist having the predetermined pattern as a mask. A deposited film in which C and Br are coupled is produced on the resist. | 2012-01-26 |
20120021606 | PROCESS FOR PRODUCING TWO INTERLEAVED PATTERNS ON A SUBSTRATE - A process for producing two interleaved patterns on a substrate uses photolithography and etching to produce, on the substrate, a first pattern of first material protruding regions separated by recessed regions. A non-conformal deposition of a second material on the first pattern forms cavities in the recessed regions of the first pattern. These cavities are opened and filled with a third material. The second material is then removed, and the remaining third material forms a second pattern of third material protruding regions, wherein the second pattern is interleaved with the first pattern. | 2012-01-26 |
20120021607 | METHOD OF PITCH DIMENSION SHRINKAGE - An embodiment of the disclosure includes a method of pitch reduction. A substrate is provided. A first material layer is formed over the substrate. A second material layer is formed on the first material layer. A hardmask layer is formed on the second material layer. A first imaging layer is formed on the hardmask layer. The first imaging layer is patterned to form a plurality of first features over the hardmask layer. The hardmask layer is etched utilizing the first imaging layer as a mask to form the first features in the hardmask layer. The first imaging layer is removed to expose the etched hardmask layer and a portion of a top surface of the second material layer. A second imaging layer is formed and the process is repeated, such that first and second features are alternating with a pitch substantially half the original pitch. | 2012-01-26 |
20120021608 | SUBSTRATE PROCESSING METHOD, SEMICONDUCTOR CHIP MANUFACTURING METHOD, AND RESIN-ADHESIVE-LAYER-BACKED SEMICONDUCTOR CHIP MANUFACTURING METHOD - To provide a substrate processing method and a semiconductor chip manufacturing method that enable low-cost formation of a mask for etching using plasma etching. During formation of a mask used in plasma dicing for separating a semiconductor wafer | 2012-01-26 |
20120021609 | DEPOSITION OF VISCOUS MATERIAL - Embodiments of the invention provide methods and systems for depositing a viscous material on a substrate surface. In one embodiment, the invention provides a method of depositing a viscous material on a substrate surface, the method comprising: applying a pre-wet material to a surface of a substrate; depositing a viscous material atop the pre-wet material; rotating the substrate about an axis to spread the viscous material along the surface of the substrate toward a substrate edge; and depositing additional pre-wet material in a path along the surface and adjacent the spreading viscous material. | 2012-01-26 |
20120021610 | Methods of Forming Material on a Substrate, and a Method of Forming a Field Effect Transistor Gate Oxide on a Substrate - The invention includes methods of forming material on a substrate and methods of forming a field effect transistor gate oxide. In one implementation, a first species monolayer is chemisorbed onto a substrate within a chamber from a gaseous first precursor. The first species monolayer is discontinuously formed over the substrate. The substrate having the discontinuous first species monolayer is exposed to a gaseous second precursor different from the first precursor effective to react with the first species to form a second species monolayer, and effective to form a reaction product of the second precursor with substrate material not covered by the first species monolayer. The substrate having the second species monolayer and the reaction product is exposed to a third gaseous substance different from the first and second precursors effective to selectively remove the reaction product from the substrate relative to the second species monolayer. Other implementations are contemplated. | 2012-01-26 |
20120021611 | COATING TREATMENT METHOD, NON-TRANSITORY COMPUTER STORAGE MEDIUM AND COATING TREATMENT APPARATUS - A coating treatment method includes: a first step of rotating a substrate at a first rotation number; a second step of rotating the substrate at a second rotation number being slower than the first rotation number; a third step of rotating the substrate at a third rotation number being faster than the second rotation number and slower than the first rotation number; a fourth step of rotating the substrate at a fourth rotation number being slower than the third rotation number; and a fifth step of rotating the substrate at a fifth rotation number being faster than the fourth rotation number. A supply of a coating solution to a central portion of the substrate is continuously performed from the first step to a middle of the second step or during the first step, and the fourth rotation number is more than 0 rpm and 500 rpm or less. | 2012-01-26 |
20120021612 | METHODS FOR MANUFACTURING DIELECTRIC FILMS - A method for manufacturing a dielectric film having a high dielectric constant is provided. | 2012-01-26 |
20120021613 | FINISHING METHOD FOR A SILICON ON INSULATOR SUBSTRATE - The invention relates to a finishing method for a silicon-on-insulator (SOI) substrate that includes an oxide layer buried between an active silicon layer and a support layer of silicon. The method includes applying the following steps in succession: a first rapid thermal annealing (RTA) of the SOI substrate; a sacrificial oxidation of the active silicon layer of the substrate conducted to remove a first oxide thickness; a second RTA of the substrate; and a second sacrificial oxidation of the active silicon layer conducted to remove a second oxide thickness that is thinner than the first oxide thickness. | 2012-01-26 |
20120021614 | Electrical Connector - An electrical connector. In one embodiment of the present invention, the electrical connector includes a first main body, including a first insulating body and a first conductive member set fixed to the first insulating body, in which each conductive member of the first conductive member set includes a first internal connecting portion; and a second main body, including a second insulating body and a second conductive member set fixed to the second insulating body, in which each conductive member of the second conductive member set includes a second internal connecting portion, and the second internal connecting portion of each conductive member of the second conductive member set is in contact with the first internal connecting portion of the corresponding conductive member of the first conductive member set respectively. The second main body is movably mounted on the first main body and is capable of rotating relative to the first main body, and during rotation, each of the second internal connecting portions is maintained in contact with the corresponding first internal connecting portion. | 2012-01-26 |
20120021615 | ROTATABLE PLUG AND ELECTRONIC DEVICE HAVING SUCH ROTATABLE PLUG - An electronic device includes a plug and a main body. The plug includes a casing and a base. The casing has an opening. An extension part is formed on an inner surface of the casing. The base includes at least two conducting pieces. The main body includes a coupling member. The coupling member has a fixing structure and two pins. After the fixing structure is penetrated through the opening, the fixing structure is rotated to be moved along the extension part to a fixed location, so that plug and the main body are combined together and the two pins are respectively contacted with the conducting pieces. | 2012-01-26 |
20120021616 | Electronic Connector, And Corresponding Electric Connection Element, Electric Linking Member, And Assembling Method - The invention relates to an electric connector that comprises a plurality of electric connection elements ( | 2012-01-26 |
20120021617 | ELECTRONIC PART AND LEAD - A lead configured to join to a signal line of an electronic part through solder is disposed in an opposing relationship to the signal line and extends for sliding movement. A first opposing face section including a pair of faces having wettability to the solder is formed on surfaces of the signal line and the lead. Further, a second opposing face section including a pair of faces having wettability lower than the wettability of the first opposing face section is formed on the surfaces of the signal line and the lead along an extending direction of the lead. | 2012-01-26 |
20120021618 | Magnetically Enhanced Electrical Signal Conduction Apparatus and Methods - Apparatus and methods for magnetically enhanced electrical signal conduction are disclosed. An embodiment electrical connector comprises a connector body, a first active signal contact mechanically attached to and at least partially disposed within the connector body, a ground contact mechanically attached to the connector body, an insulator mechanically separating and electrically isolating the first active signal contact and the ground contact, and a first permanent magnet electrically connected to the first active signal contact. An embodiment electrical cable comprises an elongated insulating sheath, a first active signal electrical conductor disposed within the sheath, a first connector body mechanically attached to a first end of the sheath, a first active signal contact mechanically attached to the first connector body, and electrically connected to the first active signal electrical conductor, and a first permanent magnet electrically connected to the first active signal electrical conductor. | 2012-01-26 |
20120021619 | PROGRAMMABLE MAGNETIC CONNECTORS - Connectors and methods of coupling electronic devices and cables are provided. In one embodiment, a connector has a first coded magnet on a first surface of a first device. The first coded magnet has at least two different polarity regions on the first surface. A second coded magnet on a second surface of a second device is also provided. The second coded magnet is configured to provide identifying information regarding the device on which it is located. | 2012-01-26 |
20120021620 | ELECTRICAL CONNECTOR WITH FLOATING CONTACT - An electrical connector is provided for mounting on a printed circuit. The electrical connector includes a housing having a mating face, a mounting face, and an interior cavity. The mounting face is configured to be mounted on the printed circuit. A port extends through the mating face into the interior cavity. The interior cavity is defined by an interior wall of the housing. An electrical contact is held by the housing. The electrical contact includes a mating segment and a mounting segment. The mating segment extends within the interior cavity of the housing. The mating segment includes an exterior surface and a mating interface positioned proximate the port. At least a portion of the mounting segment extends along the mounting face of the housing for engagement with the printed circuit. A clearance exists between the exterior surface of the mating segment and the interior wall of the housing. The mating segment is movable within the interior cavity relative to the housing via the clearance. | 2012-01-26 |
20120021621 | METHOD FOR MANUFACTURING MULTILAYERED FLEXIBLE CIRCUIT BOARD - Disclosed herein is a method of manufacturing a multilayered flexible circuit board. The method of manufacturing a multilayered flexible circuit board may include integrally forming a first flexible printed circuit board and a second flexible printed circuit board divided in a symmetrical shape with respect to a reference line on the same plane to provide an original plate; attaching the first flexible printed circuit board to the second flexible printed circuit board by folding the original plate with respect to the reference line; and electrically connecting the first flexible printed circuit board to the second flexible printed circuit board. | 2012-01-26 |
20120021622 | STACKED MULTILAYER CONNECTOR - A stacked multilayer connector includes two seat bodies oppositely disposed on a circuit board and two connection seats. Multiple electronic card units can be previously held between the connection seats as stacked layers and then the connection seats with the electronic card units can be plugged into the seat bodies into electrical contact with the circuit board. Each seat body has multiple terminal passageways in which multiple first terminals are inlaid. Each connection seat has multiple terminal passages in which multiple second terminals are inlaid. Each second terminal has multiple electronic card contact sections for clamping the electronic card units and a contact arm for contacting with the first terminal. The contact arm of the second terminal is a projection below the electronic card contact sections, whereby the width of the insulation main body of the connection seat is reduced to minify the required installation space and lower manufacturing cost. | 2012-01-26 |
20120021623 | SAFETY MODULE ELECTRICAL DISTRIBUTION SYSTEM - A wiring module that can be installed in an electrical junction box and can receive a removable electrical outlet module, a removable electrical switch module, or other types of electrical functional modules. The wiring module and the removable electrical outlet and switch modules may include connectors having a mechanical portion and an electrical portion. The electrical connector portions may be configured so as not to be exposed to user contact when the mechanical connector portions are at least partially engaged. | 2012-01-26 |
20120021624 | ADAPTER - A system and method for adapting a peripheral expansion card to a peripheral expansion slot are disclosed herein. A first board of an expansion card adapter is configured to mate with an expansion card connector. A second board of the expansion card adapter is configured to mate with peripheral expansion card that is incompatible with the expansion card adapter. | 2012-01-26 |
20120021625 | SOCKET AND METHOD OF FABRICATING THE SAME - A socket detachably connects a connecting item to a substrate via connecting terminals. The socket includes a support member with first and second surfaces to fix the connecting terminals, and penetrating holes formed in the support member. Each connecting terminal includes first and second connecting parts formed on opposite ends thereof. Each connecting terminal is inserted into a corresponding penetrating hole in a state in which the first connecting part is fixed to the first surface and the second connecting part projects from the second surface of the support member. | 2012-01-26 |
20120021626 | ELECTRICAL CARD CONNECTOR HAVING IMPROVED SPRING MEMBER - An electrical card connector ( | 2012-01-26 |
20120021627 | PLUG CONNECTOR HAVING IMPROVED RELEASING MECHANISM AND A CONNECTOR ASSEMBLY HAVING THE SAME - A connector assembly ( | 2012-01-26 |
20120021628 | DATA TRANSFER HINGE - A data transfer hinge is disclosed. Embodiments of the present invention provide a door hinge that facilitates transmission of data from LAN wiring in a building through a door frame to a door mounted device. Power and ground connections can also pass through the hinge. Channels ( | 2012-01-26 |
20120021629 | INTELLIGENT ELECTRICAL CONNECTOR - An intelligent electrical includes a metallic shielding case, an insulating main body, plural conducting terminals and at least one detecting element. The metallic shielding case includes a receiving space and at least one elastic sustaining element. The insulating main body includes a first body part and a second body part. The first body part is accommodated within the receiving space. The second body part is exposed outside the metallic shielding case. The detecting element is disposed on the second body part, arranged beside the elastic sustaining element of the metallic shielding case, and selectively contacted with or separated from the elastic sustaining element. When the elastic sustaining element is contacted with the detecting element, the electricity is permitted to be transmitted through the intelligent electrical connector. Whereas, when the elastic sustaining element is separated from the detecting element, the electricity fails to be transmitted through the intelligent electrical connector. | 2012-01-26 |
20120021630 | FORMED GASKET FOR AN ELECTRONIC CONNECTOR - Described is an electronic connector. The electronic connector has a substrate body for housing electronic pins and a cable. The substrate body is fabricated from a first material, such as hard plastic and has at least one passage from its exterior to its interior. The overmold is fabricated from a resilient material having a lower melting point than the first material. The resilient material is overmolded onto the substrate body and flows through the at least one passage in the substrate body and forms a gasket on the connecting surface of the substrate body. | 2012-01-26 |
20120021631 | SYSTEM AND METHOD FOR SEALING A CONNECTOR - A connector assembly includes a connector having a connector housing including a flange and a mating end. The flange has a flange surface. The mating end has an opening extending therethrough. A flange seal extends along the flange surface. A mating end seal extends around the mating end of the connector housing. The connector housing is configured to couple to a panel so that a flange side of the panel is positioned adjacent the flange surface of the connector housing. The mating end of the connector housing is configured to extend through an opening formed in the panel. The flange seal is configured to be positioned between the flange surface of the connector housing and the flange side of the panel. The mating end seal is configured to be positioned between the panel and the mating end of the connector housing to seal the opening of the panel. | 2012-01-26 |
20120021632 | WATERPROOF CONNECTOR - There is provided a waterproof connector in which swing of electric wires inside a rear holder can be prevented, and insertion of the rear holder into a connector body can be easily performed with a small force. The waterproof connector includes a connector body | 2012-01-26 |
20120021633 | CONNECTOR - A connector in which terminal extraction work using an extraction jig can surely be done when necessary and also at the normal time, a terminal of the other connector can be connected to a terminal of the inside of a terminal receiving chamber without any mistakes and fear of a poor fit can be removed is provided. In the connector having two connector housings | 2012-01-26 |
20120021634 | DEVICE FOR CONNECTING TWO ELECTRICAL CONDUCTORS - The invention relates to a device for connecting two electrical conductors ( | 2012-01-26 |
20120021635 | DEVICE FOR CONNECTING A FIRST ELECTRIC CABLE TO A SECOND ELECTRIC CABLE, DISTRIBUTOR ARRANGEMENT AND AIR- OR SPACECRAFT - The present invention provides a device for connecting a first electric cable to a second electric cable, said device comprising: a first cable lug which comprises a first connection portion for electrically contacting the first electric cable and a socket portion having a conical socket; a second cable lug which comprises a second connection portion for electrically contacting the second electric cable and a plug portion having a conical plug; wherein the plug can be inserted into the socket and conductively contacted therewith in order to connect the first cable to the second cable in an electrically conductive manner. | 2012-01-26 |
20120021636 | TELECOMMUNICATIONS CONNECTOR - An electrically conductive contact for electrically connecting an insulated conductor to an electrically conductive track of a printed circuit board, including bifurcate contact arms extending from a common section of the contact, an open end section of the contact arms being adapted to receive an end section of the insulated conductor, pierce the insulation and effect electrical connection therewith; and a fastener for electrically coupling the contact to the track of the printed circuit board, wherein the arms include torsion inhibitors for resiliently inhibiting movement of the arms about respective axes when the insulated conductor is forced therebetween. | 2012-01-26 |
20120021637 | Insulation Displacement Connector System - A mechanical insulation displacement connection system which creates an electrical connection between an enamel insulated wire and a terminal inserted in a special seat or pocket. The enamel insulated wire is wound at the beginning and end of the winding onto a central pin in the seat. The terminal is provided with two, sufficiently flexible inner tabs which, during insertion of the terminal in the seat, slide over the enamel insulated wire removing the enamel and permitting electrical contact with the copper wire. Once in position, the tabs press the wire against the central pin to ensure constant electrical contact over time. | 2012-01-26 |
20120021638 | MODULAR NETWORK CONNECTOR - A modular network connector configured to receive a network plug of a cable includes a base and a moveable member. The base includes a plurality of connection pins and network conductors. The moveable member is rotatably coupled to the base. The moveable member is configurable to a first position in which the movable member is parallel to the base and to a second position substantially perpendicular to the base and configured to electrically and mechanically receive the network plug of a cable. | 2012-01-26 |
20120021639 | Lighted USB - An illuminated universal serial bus (USB) port that is illuminated with a light emitting diode (LED). The illuminated USB port comprises a USB port with a LED disposed directly behind the USB port to illuminate the USB port through the opaque white plastic and the existing openings in the USB port. The illuminated USB port is easily located in low light or dark environments. The illuminated USB port can also indicate the power on status of a USB port. | 2012-01-26 |
20120021640 | COMMUNICATION CABLE - A serial-parallel conversion circuit provided on one end of a cable body converts a first serial signal into parallel signals and outputs the parallel signals to parallel signal lines. A parallel-serial conversion circuit provided on another end of the cable body converts the parallel signals inputted from the parallel signal lines into a second serial signal and outputs the second serial signal to outside. | 2012-01-26 |
20120021641 | MOUNTING PLATE FOR MOUNTING AN ELECTRICAL CONNECTOR TO A CIRCUIT BOARD - An electrical connector is provided including a housing. A mounting plate is provided having a mounting surface configured to be mechanically coupled to a circuit board. An opening extends through the mounting plate. The opening has an interior contour shaped to slidably receive a post of the housing as the mounting plate is loaded onto the post until the mounting plate rests on a plate surface of the housing. An engagement feature is provided on the mounting plate. The engagement feature secures the mounting plate to the housing. The engagement feature displaces a plate securing portion formed on the housing to secure the mounting plate to the housing with an interference fit. | 2012-01-26 |
20120021642 | PORT SEIZING CABLE CONNECTOR NUT AND ASSEMBLY - A coaxial cable connector includes a connector body having a first end and a second end, a coupling nut freely rotatable and disposed in relation to the first end of the connector body and a post having a first end and a second end, the post further including a open-ended port retaining portion. The coupling nut includes an internal threaded portion and is disposed in overlaying relation relative to the port retaining portion, which is configured for engaging an external port. The port retaining portion defines a locking collet that prevents loosening of the engaged port, while still guaranteeing electrical continuity without requiring excessive tightening of the connector. | 2012-01-26 |
20120021643 | ELECTRICAL CONNECTOR FOR PROVIDING ELECTRICAL POWER TO AN ANTENNA - An electrical connector is provided for terminating an electrical cable having an insulated conductor surrounded by a ground shield. The electrical connector includes a housing, an electrical contact held by the housing, an inner ferrule configured to extend between the ground shield and the insulated conductor of the electrical cable, and an outer ferrule extending around the inner ferrule such that the ground shield of the electrical cable extends between the inner and outer ferrules when the electrical connector terminates the electrical cable. A rear cover is connected to the housing. The rear cover extends around and compresses the outer ferrule such that the ground shield of the electrical cable is captured between the inner and outer ferrules when the electrical connector terminates the electrical cable. | 2012-01-26 |
20120021644 | COAXIAL INSPECTION CONNECTOR AND RECEPTACLE - This disclosure provides a coaxial inspection connector that is connectable to and disconnectable from a receptacle, the receptacle including an external conductor, a fixed terminal, and a movable terminal that is in pressed contact with the fixed terminal from below. Housing includes an end portion that contacts the external conductor. A probe extends vertically in the end portion. The probe is insulated from the housing, and includes a plunger. The plunger includes a plunger body and a tip. The plunger body contacts the fixed terminal when the external conductor contacts the end portion. The tip is an insulating portion disposed at a lower end of the plunger. The tip pushes the movable terminal downward and separates the movable terminal from the fixed terminal when the external conductor contacts the end portion. | 2012-01-26 |
20120021645 | COAXIAL CONNECTOR WITH INNER SHIELDING ARRANGEMENT AND METHOD OF ASSEMBLING ONE - Externally insulated coaxial connector ( | 2012-01-26 |