04th week of 2012 patent applcation highlights part 15 |
Patent application number | Title | Published |
20120018746 | ARRAY-TYPE LED DEVICE - An array-type LED device includes a substrate; and a plurality of light-emitting elements located on the substrate, wherein each of the plurality of light-emitting elements includes a first semiconductor layer having a first region and a second region; and a second semiconductor layer with an oblique angle located on the second region. The light-emitting element further includes a first electrical-contact region located on the first region, and a second electrical-contact region located on the second semiconductor layer, wherein the lateral resistance of the second semiconductor layer is larger than that of the first semiconductor layer. | 2012-01-26 |
20120018747 | LED LEAD FRAME AND METHOD OF MAKING THE SAME - An LED lead frame assembly comprises a wiring board having a plurality set of positive and negative poles arranged on a top surface thereof A plurality of LED chips are disposed on the wiring board, and electrically bonded to the bus line. A transparent cover is arranged upon the wiring board and covering the LED chip and the conductive lead. | 2012-01-26 |
20120018748 | LIGHT EMITTING DIODE DEVICE AND METHOD FOR FABRICATING THE SAME - A light emitting diode device includes: at least one light emitting diode chip, which includes a semiconductor unit, two electrodes that are disposed on an electrode-mounting surface of the semiconductor unit, a light-transmissive insulating layer that is disposed on the electrode-mounting surface and that has two via holes, a reflective metal layer disposed on a portion of the light-transmissive insulating layer, a protective insulating layer that is disposed on the reflective metal layer, a conductor-receiving insulating layer that has two conductor-receiving holes respectively in communication with the via holes, and two conductor units that are formed respectively in the conductor-receiving holes; and a light-transmissive envelope layer that covers a surface of the light emitting diode chip opposite to the electrode-mounting surface, that extends to cover outer lateral surfaces of the light emitting diode chip, and that is doped with a fluorescence powder. | 2012-01-26 |
20120018749 | ORGANIC LIGHT EMITTING DISPLAY APPARATUS AND METHOD FOR MANUFACTURING THE SAME - An organic light emitting display apparatus is manufactured using a simplified manufacturing process and prevents or reduces the formation of dark spots. The organic light emitting display apparatus includes: red, green, and blue sub-pixel regions, each including a first electrode on a substrate; a distributed Bragg reflector (DBR) layer between the substrate and the first electrode; a hole injection layer on the DBR layer and covering the first electrode; a hole transport layer on the hole injection layer; an auxiliary layer between the hole injection layer and the hole transport layer in the green sub-pixel region; a green light-emission layer on the hole transport layer in the blue and green sub-pixel regions; a blue light-emission layer on the green light-emission layer in the blue sub-pixel region; and a red light-emission layer on the hole transport layer in the red sub-pixel region. | 2012-01-26 |
20120018750 | SEMICONDUCTOR OPTOELECTRONIC DEVICE AND THE METHOD OF MANUFACTURING THE SAME - A semiconductor optoelectronic device comprises an operating substrate; a semiconductor epitaxial stack unit disposed on the operating substrate comprising a first semiconductor material layer having a first electrical conductivity disposed on the operating substrate and a second semiconductor material layer having a second electrical conductivity disposed on the first semiconductor material layer; a transparent conductive layer disposed on the second semiconductor material layer, wherein the transparent conductive layer comprises a first surface, a directly contacting part disposed on the first surface and directly contacting with the second semiconductor material layer, a second surface substantially parallel with the first surface, and a directly contacting corresponding part disposed on the second surface corresponding to the directly contacting part; and a first electrode disposed on the operating substrate and electrically connected with the semiconductor epitaxial stack by the transparent conductive layer, wherein the first electrode is connected with the transparent conductive layer by an area excluding the directly contacting part and the directly contacting corresponding part. | 2012-01-26 |
20120018751 | LIGHTING DEVICE - A first lighting device comprises at least one plural cavity element and a plurality of solid state light emitters. A second lighting device comprises at least one plural cavity element, a plurality of solid state light emitters and at least one encapsulant region, at least a portion of the plural cavity element being surrounded by the encapsulant region. Each plural cavity element has at least two optical cavities. Each optical cavity comprises a concave region in the plural cavity element. At least one solid state light emitter is present in each of at least two of the optical cavities. | 2012-01-26 |
20120018752 | SEMICONDUCTOR DEVICE AND METHOD FOR MANUFACTURING THE SAME - According to one embodiment, a semiconductor device includes a substrate and a stacked body on the substrate via a joining metal layer. The stacked body includes a device portion and a peripheral portion. The device portion includes from a bottommost layer to a topmost layer included in the stacked body. The peripheral portion surrounding and provided around the device portion; the peripheral portion is a portion of the bottommost layer to the topmost layer included in the stacked body and includes a portion of a semiconductor layer in contact with the joining metal layer. | 2012-01-26 |
20120018753 | ULTRAVIOLET LIGHT EMITTING DIODE DEVICES AND METHODS FOR FABRICATING THE SAME - A UV LED device and the method for fabricating the same are provided. The device has aluminum nitride nucleating layers, an intrinsic aluminum gallium nitride epitaxial layer, an n-type aluminum gallium nitride barrier layer, an active region, a first p-type aluminum gallium nitride barrier layer, a second p-type aluminum gallium nitride barrier layer, and a p-type gallium nitride cap layer arranged from bottom to top on a substrate. A window region is etched in the p-type gallium nitride cap layer for emitting the light generated. | 2012-01-26 |
20120018754 | LIGHT TRANSMISSION CONTROL FOR MASKING APPEARANCE OF SOLID STATE LIGHT SOURCES - A light emitter device, package, or lamp that comprises and light emitter and a light transmission control material to mask the appearance of at least the light emitter. In one embodiment, a light emitting diode (LED) based lamp is disclosed, comprising an LED light source. A phosphor is arranged remote to the light source such that light emitted from the light source passes through this phosphor and is converted by this phosphor. A light transmission control material is applied at least partially outside the LED light source and the phosphor to reversibly mask the appearance of the LED light source and the phosphor. The light transmission control material is less masking when the LED light source is active. A method for masking the appearance of inactive light emitters is also disclosed that comprising providing at least one light emitter. Each of the at least one light emitters is provided with a light transmission control material over the light emitters to reversibly mask the appearance of the light emitters while the light emitters are inactive. The light transmission control material is less masking when the LED light source is active. | 2012-01-26 |
20120018755 | LIGHT EMITTING DEVICES WITH EMBEDDED VOID-GAP STRUCTURES THROUGH BONDING OF STRUCTURED MATERIALS ON ACTIVE DEVICES - A method of fabricating optoelectronic devices with embedded void-gap structures on semiconductor layers through bonding is provided. The embedded void-gaps are fabricated on a semiconductor structure by bonding a patterned layer or slab onto a flat surface, or by bonding a flat layer or slab onto a patterned surface. The void-gaps can be filled with air, gases, conductive or dielectric materials, or other substances, in order to provide better isolation of optical modes from dissipative regions, or better light extraction properties. | 2012-01-26 |
20120018756 | LIGHT EMITTING DEVICES - Light-emitting devices, and related components, systems and methods are disclosed. | 2012-01-26 |
20120018757 | LIGHT EMITTING DEVICE, LIGHT EMITTING DEVICE PACKAGE COMPRISING THE SAME AND LIGHTING SYSTEM - Disclosed is a light emitting device including a light emitting structure including a first conductive semiconductor layer, an active layer and a second conductive semiconductor layer, a first electrode disposed on the first conductive semiconductor layer, a reflective electrode disposed on the second conductive semiconductor layer, a channel layer disposed on the light emitting structure and surrounds the reflective electrode, and a support substrate connected to the channel layer through an adhesive layer. | 2012-01-26 |
20120018758 | OPTOELECTRONIC DEVICES WITH EMBEDDED VOID STRUCTURES - An optoelectronic structure, and method of fabricating same, comprised of semiconductors having growth-embedded void-gap gratings or photonic crystals in one or two dimensions, which are optimized to yield high interaction of the guided light and the photonic crystals and planar epitaxial growth. Such structure can be applied to increase light extraction efficiency in LEDs, increase modal confinement in lasers or increase light absorption in solar cells. The optimal dimensions of the growth-embedded void-gap gratings or photonic crystals are calculated by numerical simulation using scattering matrix formalism. The growth-embedded void-gap gratings are applicable to any semiconductor device, as well as optoelectronic devices, such as light-emitting diodes, laser diodes and solar cells. | 2012-01-26 |
20120018759 | SUBSTRATE FOR MOUNTING LIGHT-EMITTING ELEMENT, PRODUCTION PROCESS THEREOF AND LIGHT-EMITTING DEVICE - To provide a substrate for mounting a light-emitting device, which is provided with a silver reflection layer having a high reflectance and being less susceptible to deterioration of the reflectance due to corrosion and which has an improved light extraction efficiency. | 2012-01-26 |
20120018760 | LIGHT EMITTING DIODE PACKAGE AND METHOD FOR FABRICATING THE SAME - A method for fabricating light emitting diode packages includes: providing a light emitting diode wafer which has a plurality of light emitting diode chips, each of the light emitting diode chips including a semiconductor unit that has p-type and n-type electrode regions, and two electrodes; forming a light-transmissive insulating layer on the light emitting diode chips; forming a reflective metal layer on a portion of the light-transmissive insulating layer; forming a layer of insulating material on the light-transmissive insulating layer and the reflective metal layer, and performing exposing and developing treatments to form the layer of insulating material into a plurality of protective insulating structures; forming a conductor-receiving insulating layer on the light-transmissive insulating layer and the protective insulating structures; and performing a cutting process to obtain a plurality of light emitting diode packages each having at least one of the light emitting diode chips. | 2012-01-26 |
20120018761 | PHOSPHOR MEMBER, METHOD OF MANUFACTURING PHOSPHOR MEMBER, AND ILLUMINATING DEVICE - In the present invention, provided is a phosphor member capable of improving a yield and an extraction rate, in addition to high environmental tolerance, high heat resistance, high durability and a high color rendering property, by which variations of color and an amount of light are reduced, and also provided are a method of manufacturing the phosphor member and an illuminating device. Disclosed is a phosphor member prepared separately from an LED light source constituting a white illuminating device, wherein the phosphor member possesses phosphor particles and an inorganic layer having been subjected to coating and a heat treatment. | 2012-01-26 |
20120018762 | SEMICONDUCTOR DEVICE - This disclosure provides a semiconductor device that can demonstrate an efficient heat releasing effect. The device includes a mount part | 2012-01-26 |
20120018763 | RADIATION-EMITTING SEMICONDUCTOR CHIP AND METHOD FOR PRODUCING A RADIATION-EMITTING SEMICONDUCTOR CHIP - A radiation-emitting semiconductor chip includes: a carrier and a semiconductor body with a semiconductor layer sequence including an active region that generates radiation, a first semiconductor layer and a second semiconductor layer; wherein the active region is arranged between the first semiconductor layer and the second semiconductor layer; the first semiconductor layer is arranged on a side of the active region which faces away from the carrier; the semiconductor body comprises at least one recess which extends through the active region; the first semiconductor layer is electrically conductively connected to a first connection layer extending in the recess from the first semiconductor layer in a direction of the carrier; and the first connection layer is electrically connected to the second semiconductor layer via a protective diode. | 2012-01-26 |
20120018764 | SEMICONDUCTOR LIGHT EMITTING DEVICE - The present invention relates to a vertical/horizontal light-emitting diode for a semiconductor. An exemplary embodiment of the present invention provides a semiconductor light-emitting diode comprising: a conductive substrate; a light-emitting structure including a first conductive semiconductor layer, an active layer and a second conductive semiconductor layer sequentially formed over the conductive substrate; a second conductive electrode including a conductive via that passes through the first conductive semiconductor and active layers to be connected with the second conductive semiconductor layer therein, and an electrical connector that extends from the conductive via and is exposed outside the light-emitting structure; a passivation layer for covering a dielectric and at least the side surface of the active layer of the light-emitting structure, the dielectric serving to electrically isolate the second conductive electrode from the conductive substrate, the first conductive semiconductor layer and the active layer; and a surface relief structure formed on the pathway of light emitted from the active layer. According to the present invention, a semiconductor light-emitting diode exhibiting enhanced external light extraction efficiency, especially the diode's side light extraction efficiency, can be obtained. | 2012-01-26 |
20120018765 | SEMICONDUCTOR LIGHT-EMITTING DEVICE AND METHOD OF PRODUCING THE SAME - A semiconductor light-emitting device includes a substrate, an n-type semiconductor layer located above the substrate, a semiconductor light-emitting layer located on the n-type semiconductor layer, a p-type semiconductor layer located on the semiconductor light-emitting layer. The semiconductor light-emitting device also includes an insulation film located on part of the p-type semiconductor layer in an unexposed section, a first transparent conductive film located on substantially the whole of the p-type semiconductor layer where the insulation film is not located in the unexposed section, and a second transparent conductive film located on the insulation film and the first transparent conductive film. The semiconductor light-emitting device further includes an n-side electrode located above the n-type semiconductor layer in an exposed section and electrically connected to the n-type semiconductor layer, and a p-side electrode located on the second transparent conductive film above the insulation film and electrically connected to the p-type semiconductor layer. | 2012-01-26 |
20120018766 | LIGHT EMITTING ELEMENT - A semiconductor light emitting element has a first electrode and a second electrode provided on a semiconductor layer; the first electrode has a first external connector and a first extended portion and second extended portion that extend from the first external connector, the second electrode has a second external connector, and a third extended portion, a fourth extended portion, and a fifth extended portion that extend from the second external connector, the third extended portion extends along the first extended portion and farther outside than the first extended portion, the fourth extended portion extends along the second extended portion and farther outside than the second extended portion, and the fifth extended portion extends an area between the third extended portion and the fourth extended portion to the first external connector side, and the fifth extended portion is either on a line that links a point on the first extended portion at the position closest to the second external connector and a point on the second extended portion at the position closest to the second external connector, or closer to the second external connector side than the line. | 2012-01-26 |
20120018767 | Light-Emitting Device, Lighting Device, and Manufacturing Method of Light-Emitting Device - The manufacturing method of the light-emitting device is provided in which an auxiliary electrode in contact with an electrode formed using a transparent conductive film of a light-emitting element is formed using a mask, and direct contact between the auxiliary electrode and an EL layer is prevented by oxidizing the auxiliary electrode. Further, the light-emitting device manufactured according to the method and the lighting device including the light-emitting device are provided. | 2012-01-26 |
20120018768 | LED-BASED LIGHT EMITTING DEVICES - An LED-based light emitting device comprises: a substrate; at least one LED die mounted to the substrate; at least one bond wire that electrically connects the LED die; and a light transmissive material (silicone) encapsulating the at least one LED die and at least one bond wire. The at least one bond wire has a hook-shaped portion that loops back on itself. | 2012-01-26 |
20120018769 | Light-Emitting Device, Lighting Device, and Manufacturing Method of Light-Emitting Device - It is an object to provide a light-emitting device which has high power efficiency and high light-extraction efficiency and emits light uniformly in a plane. It is another object to provide a manufacturing method of the light-emitting device. It is another object to provide a lighting device including the light-emitting device. One embodiment of the present invention provides a light-emitting device which includes: a first electrode provided over a substrate; a layer containing a light-emitting organic compound provided over the first electrode; an island-shaped insulating layer provided over the layer containing the light-emitting organic compound; an island-shaped auxiliary electrode layer provided over the island-shaped insulating layer; and a second electrode having a property of transmitting visible light provided over the layer containing the light-emitting organic compound and the island-shaped auxiliary electrode layer. | 2012-01-26 |
20120018770 | OLED LIGHT SOURCE HAVING IMPROVED TOTAL LIGHT EMISSION - An OLED light source has a reduced area metal cathode such as a fine mesh cathode and a highly conductive electron conduction layer adjacent the cathode that allows for rapid lateral conduction of electrical current beneath the cathode to cause exciton formation over substantially the entire light emitting area of the OLED. By substantially reducing the coverage area of the cathode, cathode-exciton energy transfer (cathode quenching) produced by the presence of a metal cathode can be substantially reduced, and total light output from the OLED increased. | 2012-01-26 |
20120018771 | LIGHT EMITTING ELEMENT, LIGHT EMITTING DEVICE AND SEMICONDUCTOR DEVICE - It is an object of the present invention to provide a semiconductor device, in particular, a light emitting element which can be easily manufactured with a wet method. One feature of the invention is a light emitting device including a transistor and a light emitting element. In the light emitting element, an organic layer, a light emitting layer, and a second electrode are sequentially formed over a first electrode, and the transistor is electrically connected to the light emitting element through a wiring. Here, the wiring contains aluminum, carbon, and titanium. The organic layer is formed by a wet method. The first electrode which is in contact with the organic layer is formed from indium tin oxide containing titanium oxide. | 2012-01-26 |
20120018772 | LIGHT EMITTING DEVICE AND METHOD OF MANUFACTURING THE LIGHT EMITTING DEVICE - A light emitting device includes a base body forming a recess defined by a bottom surface and a side wall thereof, a conductive member whose upper surface being exposed in the recess and whose lower surface forming an outer surface, a protruding portion disposed in the recess, a light emitting element mounted in the recess and electrically connected to the conductive member, and a sealing member disposed in the recess to cover the light emitting element. The base body has a bottom portion and a side wall portion integrally formed of a resin, an inner surface of the side wall portion is the side wall defining the recess and has a curved portion, and the protruding portion is disposed in close vicinity to the curved surface. With this arrangement, a thin and small-sized light emitting device excellent in light extraction efficiency and reliability can be obtained. | 2012-01-26 |
20120018773 | ALTERNATING-CURRENT LIGHT EMITTING DIODE STRUCTURE WITH OVERLOAD PROTECTION - The present invention relates to an alternating current (AC) light emitting diode (LED) structure with overload protection, which comprises an AC LED, a heat dissipating unit and an overload protecting unit. The AC LED is thermally connected with the heat dissipating unit, and the overload protecting unit is connected in series between the AC LED and a power source. Thus, when an overload current is inputted to the AC LED structure, the temperature of the overload protecting unit will rise to disconnect the AC LED from the power source. In this way, an open-circuit status can be produced timely in the AC LED structure to block the power input into the AC LED for purpose of protection against overload. | 2012-01-26 |
20120018774 | FABRICATION OF NITRIDE NANOPARTICLES - A method of manufacturing a nitride nanoparticle comprises manufacturing the nitride nanostructure from constituents including: a material containing metal, silicon or boron, a material containing nitrogen, and a capping agent having an electron-accepting group for increasing the quantum yield of the nitride nanostructure. Nitride nanoparticles, for example nitride nanocrystals, having a photoluminescence quantum yield of at least 1%, and up to 20% or greater, may be obtained. | 2012-01-26 |
20120018775 | ELECTROSTATIC DISCHARGE PROTECTION DEVICE AND METHOD FOR FABRICATING THE SAME - The present invention provides an ESD protection device comprising a SCR structure that is a transverse PNPN structure formed by performing a P-type implantation and an N-type implantation in an N-well and a P-well on a silicon substrate, respectively, wherein a P-type doped region in the N-well is used as an anode, and N-type doped region in the P-well is used as a cathode, characterized in that, N-type dopants are implanted into the N-well to form one lead-out terminal of a resistor, P-type dopants are implanted into the P-well to form another lead-out terminal for the resistor, and the two leading-out terminals are connected by the resistor. | 2012-01-26 |
20120018776 | SEMICONDUCTOR INTEGRATED CIRCUIT - A first annular isolation trench is formed in a periphery of an element region, and a second annular isolation trench is formed around the first annular isolation trench with a predetermined distance provided from the first annular isolation trench, and a semiconductor layer between the first annular isolation trench and the second annular isolation trench is separated into a plurality of portions by a plurality of linear isolation trenches formed in the semiconductor layer between the first annular isolation trench and the second annular isolation trench, and the semiconductor layer (source-side isolation region) which opposes a p-type channel layer end portion and is located between the first annular isolation trench and the second annular isolation trench is separated from other semiconductor layers (drain-side isolation regions) by the linear isolation trenches. | 2012-01-26 |
20120018777 | THREE LEVEL POWER CONVERTING DEVICE - Aspects of the invention are directed to a three-level power converter that has, as one phase, a bidirectional switching element connected to the series connection point of a series circuit of a first insulated gate bi-polar transistor (“IGBT”) and second IGBT and an intermediate electrode of a direct current power supply. Also included is a fuse connected between the bidirectional switching element and the intermediate electrode of the direct current power supply, and an overcurrent shutdown unit provided in each gate drive circuit of the first and second IGBTs, are provided as protection from a power supply short circuit phenomenon occurring in the event of a short circuit failure of any of the IGBTs or diodes. | 2012-01-26 |
20120018778 | ESD PROTECTION DEVICE WITH VERTICAL TRANSISTOR STRUCTURE - A new ESD protection device with an integrated-circuit vertical transistor structure is disclosed, which includes a heavily doped p-type substrate (P | 2012-01-26 |
20120018779 | METHOD FOR PRODUCING MICROMECHANICAL PATTERNS HAVING A RELIEF-LIKE SIDEWALL OUTLINE SHAPE OR AN ADJUSTABLE ANGLE OF INCLINATION - A method for producing micromechanical patterns having a relief-like sidewall outline shape or an angle of inclination that is able to be set, the micromechanical patterns being etched out of a SiGe mixed semiconductor layer that is present on or deposited on a silicon semiconductor substrate, by dry chemical etching of the SiGe mixed semiconductor layer; the sidewall outline shape of the micromechanical pattern being developed by varying the germanium proportion in the SiGe mixed semiconductor layer that is to be etched; a greater germanium proportion being present in regions that are to be etched more strongly; the variation in the germanium proportion in the SiGe mixed semiconductor layer being set by a method selected from the group including depositing a SiGe mixed semiconductor layer having varying germanium content, introducing germanium into a silicon semiconductor layer or a SiGe mixed semiconductor layer, introducing silicon into a germanium layer or an SiGe mixed semiconductor layer and/or by thermal oxidation of a SiGe mixed semiconductor layer. | 2012-01-26 |
20120018780 | SEMICONDUCTOR DEVICE AND METHOD FOR MANUFACTURING SAME - According to one embodiment, a method is disclosed for manufacturing a semiconductor device. A side face parallel to a channel direction of a plurality of gate electrodes provided via a gate insulating film above a semiconductor substrate is included as a part of an inner wall of an isolation groove provided between the adjacent gate electrodes. The method can include forming a protection film covering the side face of the gate electrode. The method can include etching the semiconductor substrate using the gate electrode as a mask to form the isolation groove. The side face of the gate electrode is covered with the protection film. The method can include forming a first insulating film by oxidizing a surface of the isolation groove to fill a bottom portion of the isolation groove. In addition, the method can include forming a second insulating film on the first insulating film to fill an upper portion of the isolation groove including the side face of the gate electrode. | 2012-01-26 |
20120018781 | MODULATION-DOPED MULTI-GATE DEVICES - Modulation-doped multi-gate devices are generally described. In one example, an apparatus includes a semiconductor substrate having a surface, one or more buffer films coupled to the surface of the semiconductor substrate, a first barrier film coupled to the one or more buffer films, a multi-gate fin coupled to the first barrier film, the multi-gate fin comprising a source region, a drain region, and a channel region of a multi-gate device wherein the channel region is disposed between the source region and the drain region, a spacer film coupled to the multi-gate fin, and a doped film coupled to the spacer film. | 2012-01-26 |
20120018782 | SEMICONDUCTOR DEVICE - An objective is to provide a semiconductor device capable of utilizing properties of a high-mobility electron transport layer with a thin film stacked structure having large ΔEc, high electron mobility, and simplified element fabrication process even when the substrate material and the electron transport layer greatly differ in lattice constant. The semiconductor device includes: a semiconductor substrate ( | 2012-01-26 |
20120018783 | SEMICONDUCTOR DEVICE AND METHOD FOR MANUFACTURING SAME - According to one embodiment, a method is disclosed for manufacturing a semiconductor device. A side face parallel to a channel direction of a plurality of gate electrodes provided above a semiconductor substrate is included as a part of an inner wall of an isolation groove provided between the adjacent gate electrodes. The method can include forming a first isolation groove penetrating through a conductive film serving as the gate electrode to reach the semiconductor substrate. The method can include forming a protection film covering a side wall of the first isolation groove including a side face of the gate electrode. The method can include forming a second isolation groove by etching the semiconductor substrate exposed to a bottom surface of the first isolation groove. The method can include oxidizing an inner surface of the second isolation groove provided on each of both sides of the gate electrode to form first insulating films, which are connected to each other under the gate electrode. In addition, the method can include filling an inside of the first isolation groove and an inside of the second isolation groove with a second insulating film. | 2012-01-26 |
20120018784 | Method for Forming a Nickelsilicide FUSI Gate | 2012-01-26 |
20120018785 | FINFET SEMICONDUCTOR DEVICE - The present disclosure provides a FinFET element. The FinFET element includes a germanium-FinFET element (e.g., a multi-gate device including a Ge-fin). In one embodiment, device includes a fin having a first portion including Ge and a second portion, underlying the first portion and including an insulating material (e.g., silicon dioxide). A gate structure may be formed on the fin. | 2012-01-26 |
20120018786 | HIGHLY STRAINED SOURCE/DRAIN TRENCHES IN SEMICONDUCTOR DEVICES - A semiconductor device is formed by a multi-step etching process that produces trench openings in a silicon substrate immediately adjacent transistor gate structures formed over the substrate surface. The multi-step etching process is a Br-based etching operation with one step including nitrogen and a further step deficient of nitrogen. The etching process does not attack the transistor structure and forms the openings. The openings are bounded by upper surfaces that extend downwardly from the substrate surface and are substantially vertical, and lower surfaces that bulge outwardly from the upper vertical sections and undercut the transistor structure. The openings may be filled with a suitable source/drain material to produce SSD transistors with desirable I | 2012-01-26 |
20120018787 | SOLID-STATE IMAGE PICKUP DEVICE - A solid-state image pickup device includes a pixel array having a plurality of photodiodes that are disposed in a matrix, electric charge transfer gates, and a floating diffusion (FD), and further includes a reset transistor and an amplifier transistor each shared by the four adjacent photodiodes. In the solid-state image pickup device, the photodiodes include first to fourth photodiodes. In a state where the amplifier transistor is activated, electric charge transfer gates connected respectively to the first to fourth photodiodes are sequentially turned ON and electric charges accumulated in the photodiodes are sequentially read out through the FD. Accordingly, a readout blanking period can be minimized to and signal charges can be read out at high speed. Moreover, readout signal lines need only to be provided for every two columns of the photodiodes, so that openings of the photodiodes can be increased in size. | 2012-01-26 |
20120018788 | MAGNETIC STACK WITH LAMINATED LAYER - A magnetic stack with a multilayer free layer having a switchable magnetization orientation, the free layer comprising a first ferromagnetic portion and a second ferromagnetic portion with an electrically conducting non-magnetic intermediate layer between the first portion and the second portion. The magnetic stack also includes a first ferromagnetic reference layer having a pinned magnetization orientation, a first non-magnetic spacer layer between the free layer and the first reference layer, a second ferromagnetic reference layer having a pinned magnetization orientation, and a second non-magnetic spacer layer between the free layer and the second reference layer. | 2012-01-26 |
20120018789 | Systems and Devices Including Multi-Gate Transistors and Methods of Using, Making, and Operating the Same - Disclosed are methods of forming transistors. In one embodiment, the transistors are formed by forming a plurality of elliptical bases in a substrate and forming fins form the elliptical bases. The transistors are formed within the fin such that they may be used as access devices in a memory array. | 2012-01-26 |
20120018790 | NON-VOLATILE MEMORY AND FABRICATING METHOD THEREOF - A non-volatile memory including a substrate, a stacked gate structure, two doped regions and a plurality of spacers is provided. The stacked gate structure is disposed on the substrate, wherein the stacked gate structure includes a first dielectric layer, a charge storage layer, a second dielectric layer and a conductive layer in sequence from bottom to top relative to the substrate. The doped regions are disposed in the substrate at two sides of the stacked gate structure, respectively, and bottom portions of the doped regions contact with the substrate under the doped regions. The spacers are respectively disposed between each side of each of the doped regions and the substrate, and top portions of the spacers are lower than top portions of the doped regions. | 2012-01-26 |
20120018791 | FLASH MEMORY DEVICE AND MANUFACTURING METHOD OF THE SAME - A flash memory device includes a semiconductor substrate, a gate stack formed on the semiconductor substrate; a channel region below the gate stack; spacers outside the gate stack; and source/drain regions outside the channel region and in the semiconductor substrate, in which the gate stack includes a first gate dielectric layer on the channel region; a first conductive layer covering an upper surface of the first gate dielectric layer and inner walls of the spacers; a second gate dielectric layer covering a surface of the first conductive layer; and a second conductive layer covering a surface of the second gate dielectric layer. A method for manufacturing a flash memory device disclosed herein. | 2012-01-26 |
20120018792 | NONVOLATILE SEMICONDUCTOR MEMORY DEVICE AND METHOD OF MANUFACTURING THE SAME - A method of manufacturing a nonvolatile semiconductor memory device according to an embodiment, includes: forming a first insulating film on a semiconductor substrate; forming a charge trapping film on the first insulating film, the forming of the charge trapping film including; forming a first nitride layer on the first insulating film at a heat treatment temperature of 550° C. or higher, forming a first oxynitride layer on the first nitride layer by oxidizing a surface of the first nitride layer, and forming a second nitride layer on the first oxynitride layer; forming a second insulating film on the charge trapping film; and forming a control gate on the second insulating film. | 2012-01-26 |
20120018793 | Device structure and manufacturing method using HDP deposited using deposited source-body implant block - This invention discloses a semiconductor power device. The trenched semiconductor power device includes a trenched gate, opened from a top surface of a semiconductor substrate, surrounded by a source region encompassed in a body region near the top surface above a drain region disposed on a bottom surface of a substrate. The semiconductor power device further includes an implanting-ion block disposed above the top surface on a mesa area next to the body region having a thickness substantially larger than 0.3 micron for blocking body implanting ions and source ions from entering into the substrate under the mesa area whereby masks for manufacturing the semiconductor power device can be reduced. | 2012-01-26 |
20120018794 | NON-VOLATILE SEMICONDUCTOR MEMORY DEVICE WITH INTRINSIC CHARGE TRAPPING LAYER - A non-volatile semiconductor memory device includes a substrate, a first gate formed on a first region of a surface of the substrate, a second gate formed on a second region of the surface of the substrate, a charge storage layer filled between the first gate and the second gate, a first diffusion region formed on a first side of the charge storage layer, and a second diffusion region formed opposite the charge storage layer from the first diffusion region. The first region and the second region are separated by a distance sufficient for forming a self-aligning charge storage layer therebetween. | 2012-01-26 |
20120018795 | NON-VOLATILE MEMORY AND MANUFACTURING METHOD THEREOF - A manufacturing method of a non-volatile memory is disclosed. A gate structure is formed on a substrate and includes a gate dielectric layer and a gate conductive layer. The gate dielectric layer is partly removed, thereby a symmetrical opening is formed among the gate conductive layer, the substrate and the gate dielectric layer, and a cavity is formed on end sides of the gate dielectric layer. A first oxide layer is formed on a sidewall and bottom of the gate conductive layer, and a second oxide layer is formed on a surface of the substrate. A nitride material layer is formed covering the gate structure, the first and second oxide layer and the substrate and filling the opening. An etching process is performed to partly remove the nitride material layer, thereby a nitride layer is formed on a sidewall of the gate conductive layer and extending into the opening. | 2012-01-26 |
20120018796 | NONVOLATILE SEMICONDUCTOR MEMORY DEVICE AND METHOD FOR MANUFACTURING THE SAME - According to one embodiment, a nonvolatile semiconductor memory device includes first and second stacked structures, first and second semiconductor pillars, first and second memory units, and a semiconductor connection portion. The stacked structures include electrode films and first inter-electrode insulating films alternately stacked in a first direction. The second stacked structure is aligned with the first stacked structure in a second direction perpendicular to the first. The first and second semiconductor pillars pierce the first and second stacked structures, respectively. The first and second memory units are provided between the electrode films and the semiconductor pillar, respectively. The semiconductor connection portion connects the first and second semiconductor pillars and includes: an end connection portion; and a first protrusion having a side face continuous with a side face of the first semiconductor pillar. The semiconductor connection portion does not include a portion smaller than a diameter of the first semiconductor pillar. | 2012-01-26 |
20120018797 | NONVOLATILE MEMORY DEVICE, AND METHODS OF MANUFACTURING AND DRIVING THE SAME - A nonvolatile memory device includes a device isolation film defining an active region in a semiconductor substrate, a pocket well region formed in an upper portion of the active region and having a first conductivity type, a gate electrode formed on the active region and extending to intersect the active region, a tunnel insulating film, a charge storage film, and a blocking insulating film sequentially disposed between the active region and the gate electrode, a source region and a drain region respectively formed in a first region and a second region of the active region exposed on both sides of the gate electrode, and each having a second conductivity type opposite to the first conductivity type, a pocket well junction region formed in the first region adjacent to the source region and contacting the pocket well region, and having the first conductivity type, and a metal silicide layer formed in the first region and contacting the source region and the pocket well junction region. | 2012-01-26 |
20120018798 | Method for Protecting a Semiconductor Device Against Degradation, a Semiconductor Device Protected Against Hot Charge Carriers and a Manufacturing Method Therefor - A method for protecting a semiconductor device against degradation of its electrical characteristics is provided. The method includes providing a semiconductor device having a first semiconductor region and a charged dielectric layer which form a dielectric-semiconductor interface. The majority charge carriers of the first semiconductor region are of a first charge type. The charged dielectric layer includes fixed charges of the first charge type. The charge carrier density per area of the fixed charges is configured such that the charged dielectric layer is shielded against entrapment of hot majority charge carriers generated in the first semiconductor region. Further, a semiconductor device which is protected against hot charge carriers and a method for forming a semiconductor device are provided. | 2012-01-26 |
20120018799 | SEMICONDUCTOR DEVICE AND METHOD FOR MANUFACTURING THE SAME - A semiconductor device and a method for manufacturing the same are provided. The method includes forming a cell structure where a storage node contact is coupled to a silicon layer formed over a gate, thereby simplifying the manufacturing process of the device. The semiconductor device includes a bit line buried in a semiconductor substrate; a plurality of gates disposed over the semiconductor substrate buried with the bit line; a first plug disposed in a lower portion between the gates and coupled to the bit line; a silicon layer disposed on the upper portion and sidewalls of the gate; and a second plug coupled to the silicon layer disposed over the gate. | 2012-01-26 |
20120018800 | Trench Superjunction MOSFET with Thin EPI Process - Methods for fabricating MOSFET devices with superjunction having high breakdown voltages (>600 volts) with competitively low specific resistance include growing an epitaxial layer of a second conductivity type on a substrate of a first conductivity type, forming a trench in the epitaxial layer, and growing a second epitaxial layer along the sidewalls and bottom of the trench. The second epitaxial layer is doped with a dopant of first conductivity type. MOSFET devices with superjunction having high breakdown voltages include a first epitaxial layer of a second conductivity type disposed over a substrate of a first conductivity type and a trench formed in the epitaxial layer. The trench includes a second epitaxial layer grown along the sidewalls and bottom of the trench. | 2012-01-26 |
20120018801 | VERTICAL CHANNEL TRANSISTOR ARRAY AND MANUFACTURING METHOD THEREOF - A vertical channel transistor array has an active region formed by a plurality of semiconductor pillars. A plurality of embedded bit lines are arranged in parallel in a semiconductor substrate and extended along a column direction. A plurality of bit line contacts are respectively disposed on a side of one of the embedded bit lines. A plurality of embedded word lines are arranged in parallel above the embedded bit lines and extended along a row direction. Besides, the embedded word lines connect the semiconductor pillars in the same row with a gate dielectric layer sandwiched between the embedded word lines and the semiconductor pillars. The current leakage isolation structure is disposed at terminals of the embedded bit lines to prevent current leakage between the adjacent bit line contacts. | 2012-01-26 |
20120018802 | Ultra-low-cost three mask layers trench MOSFET and method of manufacture - An ultra-low-cost three mask layers trench MOSFET and its method of manufacture, wherein the method includes posting a uniform-covering dielectric layer deposition, and then the topography of trenches with different open size is quite different, wherein the smaller open size trench is fully filled, while only bottom and sidewall are covered for the bigger one. After a patterned dry etch process, the bottom of the bigger trench is opened with dielectric spacer left on sidewall, and the smaller one is still filled with dielectric material. The remained dielectric material is used as masks for following N+ source implantation and/or P-body implantation. A self-aligned source contact process is performed using the remained dielectric material in the trench as hard mask, so the limitation coming from source contact trench to gate trench mis-alignment during photo process is eliminated. Therefore, the much higher cell density, means high device performance, could be achieved. | 2012-01-26 |
20120018803 | LATERAL DRAIN MOSFET WITH SUBSTRATE DRAIN CONNECTION - In one form a lateral MOSFET includes an active gate positioned laterally between a source region and a drain region, the drain region extending from an upper surface of a monocrystalline semiconductor body to a bottom surface of the monocrystalline semiconductor body, and a non-active gate positioned above the drain region. In another form the lateral MOSFET includes a gate positioned laterally between a source region and a drain region, the drain region extending from an upper surface of a monocrystalline semiconductor body to a bottom surface of the monocrystalline semiconductor body, the source region and the drain region being of a first conductivity type, a heavy body region of a second conductivity type in contact with and below the source region, and the drain region comprising a lightly doped drain (LDD) region proximate an edge of the gate and a sinker extending from the upper surface of the monocrystalline body to the bottom surface of the monocrystalline semiconductor body. | 2012-01-26 |
20120018804 | Guard Ring Integrated LDMOS - An LDMOSFET transistor ( | 2012-01-26 |
20120018805 | SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING THE SAME - According to embodiments, a semiconductor device includes a semiconductor substrate and an element isolation insulating film which isolates a element formation region in a surface portion of the semiconductor substrate. A depletion-type channel region of a first conductivity type is formed in an inner region which is in the element formation region of the semiconductor substrate and is a predetermined distance or more away from the element isolation insulating film. A gate electrode is formed above the element formation region with a gate insulating film located in between in such a manner as to traverse over the channel region and to overlap with portions of the element isolation insulating film which are located on both sides of the element formation region. Source/drain regions of the first conductivity type are formed in the channel region respectively on both sides of the gate electrode. | 2012-01-26 |
20120018806 | SEMICONDUCTOR-ON-INSULATOR (SOI) STRUCTURE WITH SELECTIVELY PLACED SUB-INSULATOR LAYER VOID(S) AND METHOD OF FORMING THE SOI STRUCTURE - Disclosed is a semiconductor-on-insulator (SOI) structure having sub-insulator layer void(s) selectively placed in a substrate so that capacitance coupling between a first section of a semiconductor layer and the substrate will be less than capacitance coupling between a second section of the semiconductor layer and the substrate. The first section may contain a first device on an insulator layer and the second section may contain a second device on the insulator layer. Alternatively, the first and second sections may comprise different regions of the same device on an insulator layer. For example, in an SOI field effect transistor (FET), sub-insulator layer voids can be selectively placed in the substrate below the source, drain and/or body contact diffusion regions, but not below the channel region so that capacitance coupling between the these various diffusion regions and the substrate will be less than capacitance coupling between the channel region and the substrate. Also, disclosed is an associated method of forming such an SOI structure. | 2012-01-26 |
20120018807 | SEMICONDUCTOR DEVICE, METHOD FOR MANUFACTURING SAME, AND SEMICONDUCTOR STORAGE DEVICE - In an SOI-MISFET that operates with low power consumption at a high speed, an element area is reduced. While a diffusion layer region of an N-conductivity type MISFET region of the SOI type MISFET and a diffusion layer region of a P-conductivity type MISFET region of the SOI type MISFET are formed as a common region, well diffusion layers that apply substrate potentials to the N-conductivity type MISFET region and the P-conductivity type MISFET region are separated from each other by an STI layer. The diffusion layer regions that are located in the N- and P-conductivity type MISFET regions) and serve as an output portion of a CMISFET are formed as a common region and directly connected by silicified metal so that the element area is reduced. | 2012-01-26 |
20120018808 | SEMICONDUCTOR DEVICE AND METHOD FOR MANUFACTURING THE SAME - A semiconductor device and a method for manufacturing a semiconductor device are provided. A semiconductor device comprises a first single-crystal semiconductor layer including a first channel formation region and a first impurity region over a substrate having an insulating surface, a first gate insulating layer over the first single-crystal semiconductor layer, a gate electrode over the first gate insulating layer, a first interlayer insulating layer over the first gate insulating layer, a second gate insulating layer over the gate electrode and the first interlayer insulating layer, and a second single-crystal semiconductor layer including a second channel formation region and a second impurity region over the second gate insulating layer. The first channel formation region, the gate electrode, and the second channel formation region are overlapped with each other. | 2012-01-26 |
20120018809 | MOS DEVICE FOR ELIMINATING FLOATING BODY EFFECTS AND SELF-HEATING EFFECTS - A MOS device having low floating charge and low self-heating effects are disclosed. The device includes a connective layer coupling the active gate channel to the Si substrate. The connective layer provides electrical and thermal passages during device operation, which could eliminate floating effects and self-heating effects. An example of a MOS device having a SiGe connector between a Si active channel and a Si substrate is disclosed in detail and a manufacturing process is provided. | 2012-01-26 |
20120018810 | Structure And Method For Dual Work Function Metal Gate CMOS With Selective Capping - A CMOS device having an NMOS transistor with a metal gate electrode comprising a mid-gap metal with a low work function/high oxygen affinity cap and a PMOS transistor with a metal gate electrode comprising a mid gap metal with a high work function/low oxygen affinity cap and method of forming. | 2012-01-26 |
20120018811 | FORMING BIPOLAR TRANSISTOR THROUGH FAST EPI-GROWTH ON POLYSILICON - Provided is a semiconductor device that includes a first transistor and a second transistor that are formed on the same substrate. The first transistor includes a first collector, a first base, and a first emitter. The first collector includes a first doped well disposed in the substrate. The first base includes a first doped layer disposed above the substrate and over the first doped well. The first emitter includes a doped element disposed over a portion of the first doped layer. The second transistor includes a second collector, a second base, and a second emitter. The second collector includes a doped portion of the substrate. The second base includes a second doped well disposed in the substrate and over the doped portion of the substrate. The second emitter includes a second doped layer disposed above the substrate and over the second doped well. | 2012-01-26 |
20120018812 | METHOD AND STRUCTURE FOR BALANCING POWER AND PERFORMANCE USING FLUORINE AND NITROGEN DOPED SUBSTRATES - Methods and systems evaluate an integrated circuit design for power consumption balance and performance balance, using a computerized device. Based on this process of evaluating the integrated circuit, the methods and systems can identify first sets of integrated circuit transistor structures within the integrated circuit design that need reduced power leakage and second sets of integrated circuit transistor structures that need higher performance to achieve the desired power consumption balance and performance balance. With this, the methods and systems alter the integrated circuit design to include implantation of a first dopant into a substrate before a gate insulator formation for the first sets of integrated circuit transistor structures; and alter the integrated circuit design to include implantation of a second dopant into the substrate before a gate insulator formation for the second sets of integrated circuit transistor structures. The method and system then output the altered integrated circuit design from the computerized device and/or manufactures the device according to the altered integrated circuit design. | 2012-01-26 |
20120018813 | BARRIER COAT FOR ELIMINATION OF RESIST RESIDUES ON HIGH k/METAL GATE STACKS - A technique for substantially eliminating resist residues from a gate stack that includes, from bottom to top, a high k gate dielectric and a metal gate, e.g., a high k/metal gate stack, is provided. In particular and in one embodiment, a method is disclosed in which a patterned resist and optionally a patterned barrier coating are formed atop a surface of the metal gate electrode of a high k/metal gate stack prior to patterning the metal gate electrode. At least the metal gate electrode not protected by the patterned material is then etched. The presence of the barrier coating eliminates resist residues from the resultant gate stack. The technique provided can be used in fabricating planar semiconductor devices such as, for example, metal oxide semiconductor field effect transistors (MOSFETS) including complementary metal oxide semiconductor (CMOS) field effect transistors, as well as non-planar semiconductor devices such as, for example, finFETs. | 2012-01-26 |
20120018814 | SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING THE SAME - According to one embodiment, a method of manufacturing a semiconductor device is disclosed as follows. A first oxide film in a first region and a second oxide film in a second region are formed on a semiconductor substrate. A high-k insulating film is formed on the first oxide film and the second oxide film. A film containing at least one of elements of Mg, La, Y, Dy, Sc, Al is formed on the high-k insulating film. After forming the film containing the element, thermal treatment is performed, so that the element in the film is diffused into the first oxide film and the second oxide film via the high-k insulating film. A metal gate electrode containing a metal material is formed on the high-k insulating film on the first oxide film and on the high-k insulating film on the second oxide film. | 2012-01-26 |
20120018815 | Semiconductor device with reduced contact resistance and method of manufacturing thereof - A method (and semiconductor device) of fabricating a semiconductor device provides a filed effect transistor (FET) with reduced contact resistance (and series resistance) for improved device performance. An impurity is implanted in the source/drain (S/D) regions after contact silicide formation and a spike anneal process is performed that lowers the schottky barrier height (SBH) of the interface between the silicide and the lower junction region of the S/D regions. This results in lower contact resistance and reduces the thickness (and Rs) of the region at the silicide-semiconductor interface. | 2012-01-26 |
20120018816 | SELF-ALIGNED SILICIDATION FOR REPLACEMENT GATE PROCESS - A semiconductor device is formed with low resistivity self aligned silicide contacts with high-K/metal gates. Embodiments include postponing silicidation of a metal layer on source/drain regions in a silicon substrate until deposition of a high-K dielectric, thereby preserving the physical and morphological properties of the silicide film and improving device performance. An embodiment includes forming a replaceable gate electrode on a silicon-containing substrate, forming source/drain regions, forming a metal layer on the source/drain regions, forming an ILD over the metal layer on the substrate, removing the replaceable gate electrode, thereby forming a cavity, depositing a high-K dielectric layer in the cavity at a temperature sufficient to initiate a silicidation reaction between the metal layer and underlying silicon, and forming a metal gate electrode on the high-K dielectric layer. | 2012-01-26 |
20120018817 | METHOD FOR FABRICATING A GATE STRUCTURE - An method of fabricating the gate structure comprises: sequentially depositing and patterning a dummy oxide layer and a dummy gate electrode layer on a substrate; surrounding the dummy oxide layer and the dummy gate electrode layer with a nitrogen-containing dielectric layer and an interlayer dielectric layer; removing the dummy gate electrode layer; removing the dummy oxide layer by exposing a surface of the dummy oxide layer to a vapor mixture comprising NH3 and a fluorine-containing compound at a first temperature; heating the substrate to a second temperature to form an opening in the nitrogen-containing dielectric layer; depositing a gate dielectric; and depositing a gate electrode. | 2012-01-26 |
20120018818 | MEMS APPARATUS - According to an embodiment of the present invention, a MEMS apparatus includes a plurality of recesses opened to a surface, a substrate having an insulator, an air gap, or an insulator and an air gap formed in the recesses, an insulating layer formed on the substrate, and a MEMS device having a signal line formed on the insulating layer, wherein the position of the signal line in a direction parallel to the surface of the substrate overlaps the position of the recess in the direction. | 2012-01-26 |
20120018819 | PROCESS FOR MANUFACTURING A MICROMECHANICAL STRUCTURE HAVING A BURIED AREA PROVIDED WITH A FILTER - A process for manufacturing a micromechanical structure envisages: forming a buried cavity within a body of semiconductor material, separated from a top surface of the body by a first surface layer; and forming an access duct for fluid communication between the buried cavity and an external environment. The method envisages: forming an etching mask on the top surface at a first access area; forming a second surface layer on the top surface and on the etching mask; carrying out an etch such as to remove, in a position corresponding to the first access area, a portion of the second surface layer, and an underlying portion of the first surface layer not covered by the etching mask until the buried cavity is reached, thus forming both the first access duct and a filter element, set between the first access duct and the same buried cavity. | 2012-01-26 |
20120018820 | SEMICONDUCTOR DEVICE - A semiconductor device includes a converter that converts an acoustic pressure into an electrical signal and an amplifier element that includes an amplifier circuit that amplifies the electrical signal outputted from the converter. The converter includes a pedestal including a cavity formed from an upper face to a lower face thereof, and a vibration film located so as to cover an opening of the cavity on the side of the upper face. The vibration film vibrates in accordance with the acoustic pressure to thereby convert the acoustic pressure into an electrical signal. The amplifier element is located under the converter so as to cover the cavity. | 2012-01-26 |
20120018821 | MICRO FORCE SENSOR PACKAGE FOR SUB-MILLINEWTON ELECTROMECHANICAL MEASUREMENTS - A force sensor package includes the following main parts: a MEMS force sensor, an interface circuit converting a change of capacitance into an analog or digital sensor output signal, and a substrate on which the MEMS force sensor and the IC are attached. The interface circuit is a die in order to minimize the size of the force sensor. The MEMS force sensor and the interface circuit are attached to the substrate by an adhesive, e.g. glue. Electrical contacts are then realized by wire-bonding. Alternatively, the two parts may also be attached to the substrate by a flip-chip process using solder. A protective cover may be placed over the assembly. | 2012-01-26 |
20120018822 | Writable Magnetic Element - The invention relates to a writable magnetic element comprising a stack of layers presenting a write magnetic layer, wherein the stack has a central layer of at least one magnetic material presenting a direction of magnetization that is perpendicular to the plane of the central layer, said central layer being sandwiched between first and second outer layers of non-magnetic materials, the first outer layer comprising a first non-magnetic material and the second outer layer comprising a second non-magnetic material that is different from the first non-magnetic material, at least the second non-magnetic material being electrically conductive, and wherein it includes a device for causing current to flow through the second outer layer in a current flow direction parallel to the plane of the central layer, and a device for applying a magnetic field along a magnetic field direction that is perpendicular to the plane of the central layer. | 2012-01-26 |
20120018823 | SPIN TRANSFER TORQUE MAGNETIC RANDOM ACCESS MEMORY (STTMRAM) HAVING GRADED SYNTHETIC FREE LAYER - A spin transfer torque memory random access memory (STTMRAM) element is capable of switching states when electrical current is applied thereto for storing data and includes the following layers. An anti-ferromagnetic layer, a fixed layer formed on top of the anti-ferromagnetic layer, a barrier layer formed on top of the second magnetic layer of the fixed layer, and a free layer including a first magnetic layer formed on top of the barrier layer, a second magnetic layer formed on top of the first magnetic layer, a non-magnetic insulating layer formed on top of the second magnetic layer and a third magnetic layer formed on top of the non-magnetic insulating layer. A capping layer is formed on top of the non-magnetic insulating layer. | 2012-01-26 |
20120018824 | MAGNETIC MEMORY LAYER AND MAGNETIC MEMORY DEVICE INCLUDING THE SAME - A magnetic memory layer and a magnetic memory device including the same, the magnetic memory layer including a first seed layer; a second seed layer on the first seed layer, the second seed layer grown according to a <002> crystal direction with respect to a surface of the first seed layer; and a main magnetic layer on the second seed layer, the main magnetic layer grown according to the <002> crystal direction with respect to a surface of the second seed layer. | 2012-01-26 |
20120018825 | MAGNETIC MEMORY DEVICES, ELECTRONIC SYSTEMS AND MEMORY CARDS INCLUDING THE SAME, METHODS OF MANUFACTURING THE SAME, AND METHODS OF FORMING A PERPENDICULAR MAGNETIC FILM OF THE SAME - Magnetic memory devices, electronic systems and memory cards including the same, methods of manufacturing the same, and methods of forming perpendicular magnetic films are provided. The magnetic memory device may include a seed pattern on a substrate having a first crystal structure, a perpendicular magnetic pattern on the seed pattern having a second crystal structure, and an interlayer pattern between the seed pattern and the perpendicular magnetic pattern. The interlayer pattern may reduce a stress caused by a difference between horizontal lattice constants of the first and the second crystal structures. | 2012-01-26 |
20120018826 | SEMICONDUCTOR MEMORY AND MANUFACTURING METHOD THEREOF - A method for manufacturing a semiconductor memory device includes sequentially depositing a bottom electrode layer, a magnetic tunnel junction (MTJ) layer, a first top electrode layer, a second top electrode layer and a mask layer, etching the mask layer and forming a mask pattern, etching the second top electrode layer and the first top electrode layer by using the mask pattern as an etch barrier, etching the MTJ layer by using the mask layer and the second top electrode layer as an etch barrier, and etching the bottom electrode layer by using the first top electrode layer as an etch barrier. | 2012-01-26 |
20120018827 | MULTI-SENSOR INTEGRATED CIRCUIT DEVICE - A multiple sensor-types integrated circuit device includes a semiconductor die including a first sensor type and a second sensor type formed thereon, an electrically insulating package enclosing the semiconductor die and a plurality of electrically conductive leads coupled to the semiconductor die and extending from the package. By way of example and not limitation, a multiple sensor-types integrated circuit die includes a semiconductor substrate of a first polarity, a plurality of regions of the first polarity formed in the substrate, where the plurality of regions are relatively more heavily doped than the substrate, multiple wells formed in the substrate, and a covering layer formed over the substrate. | 2012-01-26 |
20120018828 | Sodium Sputtering Doping Method for Large Scale CIGS Based Thin Film Photovoltaic Materials - A method of processing sodium doping for thin-film photovoltaic material includes forming a metallic electrode on a substrate. A sputter deposition using a first target device comprising 4-12 wt % Na | 2012-01-26 |
20120018829 | TEMPERATURE-ADJUSTED SPECTROMETER - A temperature-adjusted spectrometer can include a light source and a temperature sensor. | 2012-01-26 |
20120018830 | Packaging device of image sensor - A packaging device of an image sensor includes a supporting seat and the image sensor. The supporting seat is a hollow frame having a predetermined thickness, a first surface, a second surface, and an inner edge receding from the second surface toward the first surface to form a recessed step. Plural contacts in the recessed step and in the outer periphery of the supporting seat are electrically connected by plural electrical connection structures. The image sensor has an active surface set on the recessed step by a flip-chip packaging technique. The image sensor also has plural conductive ends electrically connected to the contacts in the recessed step. An insulating material covers an inactive surface of the image sensor and fills the gap between the recessed step of the supporting seat and the image sensor to provide dust-proofness, shock resistance, and prevention against static electricity and leakage of light. | 2012-01-26 |
20120018831 | LIGHT PIPE FABRICATION WITH IMPROVED SENSITIVITY - In accordance with at least some embodiments of the present disclosure, a process for fabricating a light pipe (LP) is described. The process may be configured to etch a first portion of a LP funnel in a dielectric layer of a semiconductor structure using a web etching process, wherein the dielectric layer is above a photodiode region. The process may also be configured to etch a second portion of the LP funnel in the dielectric layer subsequent to the etching of the first portion of the LP funnel, wherein the second portion of the LP funnel is etched below the first portion of the LP funnel using a dry etching process. | 2012-01-26 |
20120018832 | METHODS, STRUCTURES, AND DESIGN STRUCTURES FOR IMPROVED ADHESION OF PROTECTIVE LAYERS OF IMAGER MICROLENS STRUCTURES - Methods, structures, and design structures for improved adhesion of protective layers of imager microlens structures are disclosed. A method of fabricating a semiconductor structure includes forming an interfacial region between a microlens and a protective oxide layer. The interfacial region has a lower concentration of oxygen than the protective oxide layer. | 2012-01-26 |
20120018833 | Light-Guiding Structure, Image Sensor Including The Light-Guiding Structure, And Processor-Based System Including The Image Sensor - An example embodiment relates to a light-guiding structure. The light-guiding structure may include a bottom surface and a sidewall defined by a first, a second, and a third insulating layer disposed on a semiconductor substrate. The bottom surface may be parallel to a main surface of the semiconductor substrate and may be disposed in the first insulating layer. The sidewall may penetrate the second and third insulating layers to extend to the first insulating layer, and the sidewall may be tapered with respect to the main surface of semiconductor substrate. The light-guiding structure may be included in a image sensor. The image sensor may be included in a processor-based system. | 2012-01-26 |
20120018834 | LINEAR IMAGE SENSOR - In a linear image sensor | 2012-01-26 |
20120018835 | Thermoelectric Conversion Module - A pressing member is prevented from being damaged by heat, heat dissipation through the pressing member on the higher-temperature side and reduction in thermoelectric conversion efficiency due to it are suppressed, and good electrical conduction is achieved even if thermoelectric conversion elements and electrodes are not cemented through a binder. A lower-temperature side electrode | 2012-01-26 |
20120018836 | SCHOTTKY BARRIER DIODE - A Schottky barrier diode includes a semiconductor layer having a plurality of trenches formed by digging in from a top surface and having mesa portions formed between adjacent trenches, and a Schottky metal formed to contact the top surface of the semiconductor layer including inner surfaces of the trenches. | 2012-01-26 |
20120018837 | SCHOTTKY BARRIER DIODE WITH PERIMETER CAPACITANCE WELL JUNCTION - A Schottky barrier diode comprises a first-type substrate, a second-type well isolation region on the first-type substrate, and a first-type well region on the second-type well isolation region. With embodiments herein a feature referred to as a perimeter capacitance well junction ring is on the second-type well isolation region. A second-type well region is on the second-type well isolation region. The perimeter capacitance well junction ring is positioned between and separates the first-type well region and the second-type well region. A second-type contact region is on the second-type well region, and a first-type contact region contacts the inner portion of the first-type well region. The inner portion of the first-type well region is positioned within the center of the first-type contact region. Additionally, a first ohmic metallic layer is on the first-type contact region and a second ohmic metallic layer is on the first-type well region. The first ohmic metallic layer contacts the second ohmic metallic layer at a junction that makes up the Schottky barrier of the Schottky barrier diode. | 2012-01-26 |
20120018838 | METHOD FOR MODULAR ARRANGEMENT OF A SILICON BASED ARRAY AND MODULAR SILICON BASED ARRAY - A silicon based module, including: a substrate; a first chip assembly fixed to the substrate, the first chip assembly including a first silicon chip and a first driver die having electrical circuitry; and a second chip assembly fixed to the substrate, the second chip assembly including a second silicon chip and a second driver die having electrical circuitry. Portions of the first and second chip assemblies are aligned in a longitudinal direction for the substrate; and portions of the first and second silicon chips are aligned in a width direction orthogonal to the longitudinal direction. Method for forming a silicon based module. | 2012-01-26 |
20120018839 | SEMICONDUCTOR DEVICE - CMOS inverters are included in a standard cell. Power supply lines are electrically connected to CMOS inverters, and include lower layer interconnects and upper layer interconnect. Lower layer interconnects extend along a boundary of standard cells adjacent to each other and on the boundary. Upper layer interconnects are positioned more inside in standard cell than lower layer interconnects, as viewed from a plane. CMOS inverters are electrically connected through upper layer interconnects to lower layer interconnects. Thus, a semiconductor device is obtained that can achieve both higher speeds and higher integration. | 2012-01-26 |
20120018840 | ELEMENT ISOLATION STRUCTURE OF SEMICONDUCTOR AND METHOD FOR FORMING THE SAME - Disclosed are an element isolation structure of a semiconductor device and a method for forming the same, the method including preparing a semiconductor substrate having an inactive region and an active region defined thereon, forming a first hard mask on the semiconductor substrate, exposing the inactive region of the semiconductor substrate by patterning the first hard mask, forming a second hard mask on the entire surface of the semiconductor substrate including the first hard mask, forming a deep trench in the semiconductor substrate by patterning the second hard mask and the semiconductor substrate, removing the patterned second hard mask, forming a shallow trench overlapped with the deep trench by patterning the semiconductor substrate using the first hard mask as a mask, forming an insulation film on the entire surface of the substrate including the shallow trench and the deep trench, filling the shallow trench and the deep trench by forming an element isolation film on the insulation film, and forming an element isolation film pattern in the deep trench and the shallow trench by selectively removing the element isolation film. | 2012-01-26 |
20120018841 | SEMICONDUCTOR DEVICE - A semiconductor device comprises an active region formed in a semiconductor substrate and a gate electrode formed on the active region via a gate insulating film formed on a surface of the active region. A peripheral portion of the gate electrode and a peripheral portion of the active region overlap each other at a position where the active region is not divided by the gate electrode when viewed in plan view, thus forming an overlap region. | 2012-01-26 |
20120018842 | SWITCHING ELEMENT, VARIABLE INDUCTOR, AND ELECTRONIC CIRCUIT DEVICE HAVING CIRCUIT CONFIGURATION INCORPORATING THE SWITCHING ELEMENT AND THE VARIABLE INDUCTOR - An inexpensive variable inductor has inductance value continuously changeable without reducing a Q value. When a control voltage is applied to a control terminal of a MOS transistor from a power supply, a continuity region is formed in a channel, and a region between main terminals becomes conductive. When the control voltage is changed, length of the continuity region in the channel is changed. This changes length of a path area of an induced current, flowing in an induced current film. Thus, the amount of induced current is increased or decreased. Therefore, when the control voltage of the MOS transistor is changed, the inductance value of the coil is continuously changed. | 2012-01-26 |
20120018843 | Scalable Integrated Circuit High Density Capacitors - The present invention provides several scalable integrated circuit high density capacitors and their layout techniques. The capacitors are scaled, for example, by varying the number of metal layers and/or the area of the metal layers used to from the capacitors. The capacitors use different metallization patterns to form the metal layers, and different via patterns to couple adjacent metal layers. In embodiments, optional shields are included as the top-most and/or bottom-most layers of the capacitors, and/or as side shields, to reduce unwanted parasitic capacitance. | 2012-01-26 |
20120018844 | Solid-State Thin-Film Capacitor - Solid-state thin-film capacitors are provided. Aspects of the solid-state thin-film capacitors include a first electrode layer of a transition metal, a dielectric layer of an oxide of the transition metal, and a second electrode layer of a metal oxide. Also provided are methods of making the solid-state thin-film capacitors, as well as devices that include the same. The capacitor may have one or more cathodic arc produced structures, i.e., structures produced using a cathodic arc deposition process. The structures may be stress-free metallic structures, porous layers and layers displaying crenulations. Aspects of the invention further include methods of producing capacitive structures using chemical vapor deposition and/or by sputter deposition. | 2012-01-26 |
20120018845 | Polysilicon Plug Bipolar Transistor For Phase Change Memory - Memory devices and methods for manufacturing are described herein. A memory device described herein includes a plurality of memory cells. Memory cells in the plurality of memory cells comprise respective bipolar junction transistors and memory elements. The bipolar junction transistors are arranged in a common collector configuration and include an emitter comprising doped polysilicon having a first conductivity type, the emitter contacting a corresponding word line in a plurality of word lines to define a pn junction. The bipolar junction transistors include a portion of the corresponding word line underlying the emitter acting as a base, and a collector comprising a portion of the single-crystalline substrate underlying the base. | 2012-01-26 |