04th week of 2013 patent applcation highlights part 38 |
Patent application number | Title | Published |
20130023070 | PRODUCTION METHOD FOR OXIDIZED CARBON THIN FILM, AND ELEMENT HAVING OXIDIZED CARBON THIN FILM AND PRODUCTION METHOD THEREFOR - The production method for the oxidized carbon thin film of the present disclosure includes: a first step of preparing a carbon thin film and iron oxide that is in contact with the carbon thin film and contains Fe | 2013-01-24 |
20130023071 | DONOR SUBSTRATE, METHOD OF MANUFACTURING A DONOR SUBSTRATE AND METHOD OF MANUFACTURING AN ORGANIC LIGHT EMITTING DISPLAY DEVICE USING A DONOR SUBSTRATE - A donor substrate may include a base substrate, an expansion layer positioned on the base substrate, a light-to-heat conversion layer on the expansion layer, an insulation layer located on the light-to-heat conversion layer, and an organic transfer layer on the insulation layer. The donor substrate may effectively and uniformly transfer the organic transfer layer onto a display substrate of an organic light emitting display device. | 2013-01-24 |
20130023072 | Substrate For Integrated Modules - A method of fabricating a plurality of components using wafer-level processing can include bonding first and second wafer-level substrates together to form a substrate assembly, such that first surfaces of the first and second substrates confront one another, the first substrate having first electrically conductive elements exposed at the first surface thereof, forming second electrically conductive elements contacting the first conductive elements, and processing the second substrate into individual substrate elements. The second conductive elements can extend through a thickness of the first substrate and can be exposed at a second surface thereof opposite the first surface. The processing can include trimming material to produce the substrate elements at least some of which have respective different controlled thicknesses between first surfaces adjacent the first substrate and second surfaces opposite therefrom. | 2013-01-24 |
20130023073 | USING NON-ISOLATED EPITAXIAL STRUCTURES IN GLUE BONDING FOR MULTIPLE GROUP-III NITRIDE LEDS ON A SINGLE SUBSTRATE - A method for forming a plurality of semiconductor light emitting devices includes forming an epitaxial layer having a first type doped layer, a light emitting layer, and a second type doped layer on a first temporary substrate. A second temporary substrate is coupled to an upper surface of the epitaxial layer with a first adhesive layer. The first temporary substrate is removed from the epitaxial layer to expose a bottom surface of the epitaxial layer. A permanent semiconductor substrate is coupled to the bottom surface of the epitaxial layer with a second adhesive layer. The second temporary substrate and the first adhesive layer are removed from the upper surface of the epitaxial layer. A plurality of semiconductor light emitting devices are formed from the epitaxial layer on the permanent semiconductor substrate. | 2013-01-24 |
20130023074 | USING ISOLATED EPITAXIAL STRUCTURES IN GLUE BONDING FOR MULTIPLE GROUP-III NITRIDE LEDS ON A SINGLE SUBSTRATE - A method for forming a plurality of semiconductor light emitting devices includes forming an epitaxial layer having a first type doped layer, a light emitting layer, and a second type doped layer on a first temporary substrate. The epitaxial layer is separated into a plurality of epitaxial structures on the first temporary substrate. A second temporary substrate is coupled to the epitaxial layer with a first adhesive layer and the first temporary substrate is removed from the epitaxial layer. A permanent semiconductor substrate is coupled to the epitaxial layer with a second adhesive layer. The second temporary substrate and the first adhesive layer are removed from the epitaxial layer. The permanent semiconductor substrate is separated into a plurality of portions with each portion corresponding to at least one of the plurality of epitaxial structures to form a plurality of semiconductor light emitting devices. | 2013-01-24 |
20130023075 | Method of Forming Process Substrate Using Thin Glass Substrate and Method of Fabricating Flat Display Device Using the Same - A method for fabricating a process substrate includes: providing a first substrate; providing a substrate and an auxiliary substrate; contacting the substrate and the auxiliary substrate with each other in a vacuum state, thereby forming micro spaces of a vacuum state between the substrate and the auxiliary substrate; and increasing a pressure at the outside of the contacted substrate and auxiliary substrate to attach the substrate and the auxiliary substrate to each other by a pressure difference between the micro spaces and the outside of the contacted substrate and auxiliary substrate. | 2013-01-24 |
20130023076 | METHOD FOR MANUFACTURING LIGHT-EMITTING DEVICE - A light-emitting device manufacturing method comprises the steps of irradiating a substrate | 2013-01-24 |
20130023077 | METHOD FOR MANUFACTURING SEMICONDUCTOR OPTICAL DEVICE AND SEMICONDUCTOR OPTICAL DEVICE - A method for manufacturing a semiconductor optical device includes the steps of growing a stacked semiconductor layer on a substrate having a cleavage direction in a first direction; forming a first mask having a plurality of openings arranged in the first direction; forming a mark array by etching the stacked semiconductor layer using the first mask; forming a second mask having first and second openings extending in a second direction intersecting the first direction; forming first and second grooves, and a waveguide mesa by etching the stacked semiconductor layer using the second mask; and producing a laser diode bar by cleaving a substrate product including the waveguide mesa. First and second residual marks are formed on the upper surface of the waveguide mesa. First and second transfer marks are formed on the bottoms of the first and the second grooves, respectively. | 2013-01-24 |
20130023078 | METHOD OF MANUFACTURING A DISPLAY SUBSTRATE - A method of manufacturing a display substrate is disclosed. In one embodiment, an electrode layer may be formed on a base substrate including a first cell area, a second cell area and an intervening area between the first and the second cell areas. First electrodes may be formed in display regions of the first and the second cell areas by patterning the electrode layer. The electrode layer in an intervening area may be removed. Source electrodes and drain electrodes of thin film transistor may be formed in the first and the second cell areas where the first electrodes are formed. | 2013-01-24 |
20130023079 | FABRICATION OF LIGHT EMITTING DIODES (LEDS) USING A DEGAS PROCESS - Methods of fabricating light emitting diodes using a degas process are described. For example, a method includes providing a partially formed group III-V material layer stack of an LED. Contaminants are removed from the partially formed group III-V material layer stack by a degas process. Formation of the group III-V material layer stack of the LED is then completed. | 2013-01-24 |
20130023080 | CHEMICAL VAPOR DEPOSITION AND METHOD OF MANUFACTURING LIGHT-EMITTING DEVICE USING CHEMICAL VAPOR DEPOSITION - A chemical vapor deposition (CVD) method includes forming a first semiconductor layer on a substrate that is mounted on a satellite disk at a first process temperature; and forming a second semiconductor layer on the first semiconductor layer at a second process temperature. Also, a method of manufacturing a light-emitting device (LED) includes: forming a quantum well layer on a substrate that is mounted on a satellite disk at a first process temperature; and forming a quantum barrier layer on the quantum well layer at a second process temperature. | 2013-01-24 |
20130023081 | METHOD FOR FABRICATING INTEGRATED CIRCUIT - A method for fabricating integrated circuit is provided. First, a first interconnect structure including a plurality of first dielectric layers and a plurality of first conductive patterns stacked therewith alternately is formed on a MEMS region of a conductive substrate. Next, an interlayer is formed on the first interconnect structure and covering the first conductive patterns. Next, a poly silicon mask layer corresponding to the first conductive patterns is formed on the interlayer and exposing a portion of the media layer. Next, the portion of the interlayer exposed by the poly silicon mask layer and a portion of the first dielectric layer corresponding thereto are removed to form a plurality of openings. Then, a portion of the conductive substrate in the MEMS region is removed. | 2013-01-24 |
20130023082 | Apparatus and Method of Wafer Bonding Using Compatible Alloy - A method of forming a MEMS device provides first and second wafers, where at least one of the first and second wafers has a two-dimensional array of MEMS devices. The method deposits a layer of first germanium onto the first wafer, and a layer of aluminum-germanium alloy onto the second wafer. To deposit the alloy, the method deposits a layer of aluminum onto the second wafer and then a layer of second germanium to the second wafer. Specifically, the layer of second germanium is deposited on the layer of aluminum. Next, the method brings the first wafer into contact with the second wafer so that the first germanium in the aluminum-germanium alloy contacts the second germanium. The wafers then are heated when the first and second germanium are in contact, and cooled to form a plurality of conductive hermetic seal rings about the plurality of the MEMS devices. | 2013-01-24 |
20130023083 | METHOD FOR FORMING STRUCTURE FOR REDUCING NOISE IN CMOS IMAGE SENSORS - A method and device is disclosed for reducing noise in CMOS image sensors. An improved CMOS image sensor includes a light sensing structure surrounded by a support feature section. An active section of the light sensing structure is covered by no more than optically transparent materials. A light blocking portion includes an opaque layer or a black light filter layer in conjunction with an opaque layer, covering the support feature section. The light blocking portion may also cover a peripheral portion of the light sensing structure. The method for forming the CMOS image sensors includes using film patterning and etching processes to selectively form the opaque layer and the black light filter layer where the light blocking portion is desired, but not over the active section. The method also provides for forming microlenses over the photosensors in the active section. | 2013-01-24 |
20130023084 | Substrate for Use in Preparing Solar Cells - Conductive material is combined with other substances to form a composite material for use as a conductive back face substrate for a thin silicon wafer solar cell. In at least one embodiment, a conductive composite substrate material is fabricated by filling granular conductive material with a mineral or ceramic or other small particulate with a low CTE; the composite is cast and fired so that it has an electrically conductive continuous phase and a discontinuous phase that will control and match the CTE of the substrate to be equal to or close to that of silicon, thereby diminishing the effects of bowing from CTE-mismatch. | 2013-01-24 |
20130023085 | METHOD FOR FORMING METAL OXIDES AND SILICIDES IN A MEMORY DEVICE - Embodiments of the invention generally relate to memory devices and methods for fabricating such memory devices. In one embodiment, a method for fabricating a resistive switching memory device includes depositing a metallic layer on a lower electrode disposed on a substrate and exposing the metallic layer to an activated oxygen source while heating the substrate to an oxidizing temperature within a range from about 300° C. to about 600° C. and forming a metal oxide layer from an upper portion of the metallic layer during an oxidation process. The lower electrode contains a silicon material and the metallic layer contains hafnium or zirconium. Subsequent to the oxidation process, the method further includes heating the substrate to an annealing temperature within a range from greater than 600° C. to about 850° C. while forming a metal silicide layer from a lower portion of the metallic layer during a silicidation process. | 2013-01-24 |
20130023086 | ACTIVE MATRIX SUBSTRATE, DISPLAY PANEL PROVIDED WITH SAME, AND METHOD FOR MANUFACTURING ACTIVE MATRIX SUBSTRATE - An active matrix substrate includes a plurality of pixel electrodes (P) provided in a matrix, and a plurality of TFTs ( | 2013-01-24 |
20130023087 | METHOD FOR PROCESSING OXIDE SEMICONDUCTOR FILM AND METHOD FOR MANUFACTURING SEMICONDUCTOR DEVICE - To provide an oxide semiconductor film including a low-resistance region, which can be applied to a transistor. To provide a transistor including the oxide semiconductor film, which can perform at high speed. To provide a high-performance semiconductor device including the transistor including the oxide semiconductor film, which can perform at high speed, with high yield. A film having a reducing property is formed over the oxide semiconductor film. Next, part of oxygen atoms are transferred from the oxide semiconductor film to the film having a reducing property. Next, an impurity is added to the oxide semiconductor film through the film having a reducing property and then, the film having a reducing property is removed, so that a low-resistance region is formed in the oxide semiconductor film. | 2013-01-24 |
20130023088 | METHODS OF FORMING FULLY EMBEDDED BUMPLESS BUILD-UP LAYER PACKAGES AND STRUCTURES FORMED THEREBY - Methods of forming a microelectronic packaging structure and associated structures formed thereby are described. Those methods may include a die embedded in a coreless substrate, wherein a mold compound surrounds the die, and wherein the die comprises TSV connections on a first side and C4 pads on a second side of the die, a dielectric material on a first side and on a second side of the mold compound; and interconnect structures coupled to the C4 pads and to the TSV pads. Embodiments further include forming packaging structures wherein multiple dies are fully embedded within a BBUL package without PoP lands. | 2013-01-24 |
20130023089 | LESS EXPENSIVE HIGH POWER PLASTIC SURFACE MOUNT PACKAGE - A high power surface mount package including a thick bond line of solder interposed between the die and a heatsink, and between the die and a lead frame, wherein the lead frame has the same coefficient of thermal expansion as the heatsink. The heatsink and the lead frame preferably comprise the same material. The package can be assembled using standard automated equipment, and does not require a weight or clip to force the parts close together, which force typically reduces the solder bond line thickness. Advantageously, the thermal stresses on each side of the die are effectively balanced, allowing for a large surface area die to be packaged with conventional and less expensive materials. One type of die that benefits from the present invention can include a transient voltage suppressor, but could include other dies generating a significant amount of heat, such as those in excess of 0.200 inches square. | 2013-01-24 |
20130023090 | FIBER SOI SUBSTRATE, SEMICONDUCTOR DEVICE USING THIS, AND MANUFACTURING METHOD THEREOF - The present invention provides a SOI substrate that can realize a composite device formed of a MOS integrated circuit and a passive device and can reduce a size and a manufacturing cost of a semiconductor device. There is provided a fiber SOI substrate | 2013-01-24 |
20130023091 | FUSED BUSS FOR PLATING FEATURES ON A SEMICONDUCTOR DIE - A method for forming a semiconductor structure includes forming a plurality of fuses over a semiconductor substrate; forming a plurality of interconnect layers over the semiconductor substrate and a plurality of interconnect pads at a top surface of the plurality of interconnect layers; and forming a seal ring, wherein the seal ring surrounds active circuitry formed in and on the semiconductor substrate, the plurality of interconnect pads, and the plurality of fuses, wherein each fuse of the plurality of fuses is electrically connected to a corresponding interconnect pad of the plurality of interconnect pads and the seal ring, and wherein when each fuse of the plurality of fuses is in a conductive state, the fuse electrically connects the corresponding interconnect pad to the seal ring. | 2013-01-24 |
20130023092 | METHOD OF MANUFACTURING SEMICONDUCTOR DEVICE - According to one embodiment, a method of manufacturing a semiconductor device including forming a first SiGe layer on an insulating film, processing the first SiGe layer to have an island shape which includes a first region and a second region, the first region having a width larger than a width of the second region in a direction perpendicular to a connecting direction of the second region, subjecting the first SiGe layer having the island shape to thermal oxidation, thereby increasing Ge composition of the first and second region, and setting the Ge composition of the second region to be higher than the Ge composition of the first region, melting the second region having the increased Ge composition by heat treatment, and recrystallizing the melted second region from an interface between the first and second region. | 2013-01-24 |
20130023093 | RECESSED CONTACT FOR MULTI-GATE FET OPTIMIZING SERIES RESISTANCE - A method to fabricate a transistor including forming at least one electrically conductive channel structure over a substrate, the channel having a length, a width and a first height (h | 2013-01-24 |
20130023094 | METHOD OF FABRICATING AN INTEGRATED CIRCUIT DEVICE - A method for fabricating an integrated device is disclosed. A protective layer is formed over a gate structure when forming epitaxial (epi) features adjacent to another gate structure uncovered by the protective layer. The protective layer is thereafter removed after forming the epitaxial (epi) features. The disclosed method provides an improved method for removing the protective layer without substantial defects resulting. In an embodiment, the improved formation method is achieved by providing a protector over an oxide-base material, and then removing the protective layer using a chemical comprising hydrofluoric acid. | 2013-01-24 |
20130023095 | METHOD OF MANUFACTURING DEVICE - A semiconductor pillar which has a first conductive type and protrudes from a semiconductor substrate, is formed. A bottom diffusion layer having a second conductive type is formed in the semiconductor substrate around a bottom of the semiconductor pillar. A gate insulator film which covers a side surface of the semiconductor pillar, is formed. A gate electrode which covers the gate insulator film, is formed. A top diffusion layer having the second conductive type is formed at a top portion of the semiconductor pillar. The top diffusion layer including a semiconductor body is formed by an epitaxial growth which contains an impurity. | 2013-01-24 |
20130023096 | SINGLE CRYSTAL U-MOS GATES USING MICROWAVE CRYSTAL REGROWTH - Semiconductor devices and methods for making such devices are described. The UMOS semiconductor devices contain single-crystal gates that have been re-grown or formed at low temperature using microwaves. The devices can be formed by providing a semiconductor substrate, forming a trench in the substrate, forming an insulating layer in the trench, depositing a pre-gate layer on the insulating layer, the pre-gate layer comprising a conductive and/or semiconductive material (Si or SiGe) with a non-single crystal structure, contacting the pre-gate layer with a seed layer with a single-crystal structure, and heating the pre-gate layer using microwaves at low temperatures to recrystallize the non-single crystal structure into a single-crystal structure. These processes can improve the resistance and mobility of the gate either as a single crystal structure, optionally with a silicide contact above the source-well junction, enabling a higher switching speed UMOS device. Other embodiments are described. | 2013-01-24 |
20130023097 | U-MOS TRENCH PROFILE OPTIMIZATION AND ETCH DAMAGE REMOVAL USING MICROWAVES - Semiconductor devices and methods for making such devices are described. The UMOS (U-shaped MOSFET) semiconductor devices can be formed by providing a semiconductor substrate, forming a trench in the substrate using a wet or dry etching process, and then radiating the trench structure using microwaves (MW) at low temperatures. The MW radiation process improves the profile of the trench and repairs the damage to the trench structure caused by the dry etching process. The microwave radiation can help re-align the Si or SiGe atoms in the semiconductor substrate and anneal out the defects present after the dry etching process. As well, the microwave radiation can getter atoms or ions used in the dry etching process that are left in the lattice of the trench structure. Other embodiments are described. | 2013-01-24 |
20130023098 | MANUFACTURING METHOD FOR METAL GATE - A manufacturing method for a metal gate includes providing a substrate having a dielectric layer and a polysilicon layer formed thereon, the polysilicon layer, forming a protecting layer on the polysilicon layer, forming a patterned hard mask on the protecting layer, performing a first etching process to etch the protecting layer and the polysilicon layer to form a dummy gate having a first height on the substrate, forming a multilayered dielectric structure covering the patterned hard mask and the dummy gate, removing the dummy gate to form a gate trench on the substrate, and forming a metal gate having a second height in the gate trench. The second height of the metal gate is substantially equal to the first height of the dummy gate. | 2013-01-24 |
20130023099 | METHOD OF MANUFACTURING NONVOLATILE SEMICONDUCTOR MEMORY DEVICE - In one embodiment, a method of manufacturing a nonvolatile semiconductor memory includes forming a plurality of memory cell transistors and a plurality of selection transistors on a substrate. The method further includes burying first and second insulators successively between memory cell transistors and between a memory cell transistor and a selection transistor, and forming the first and second insulators successively on side surfaces of selection transistors, the side surfaces facing a space between the selection transistors. The method further includes burying third to fifth insulators successively between the selection transistors via the first and second insulators. The method further includes removing the second and fourth insulators by a first etching so that the second and fourth insulators partially remain between the selection transistors. The method further includes removing the second and fourth insulators remaining between the selection transistors by a second etching performed after the first etching. | 2013-01-24 |
20130023100 | METHOD OF FABRICATING SEMICONDUCTOR DEVICE - A method of fabricating a semiconductor device, the method including forming on a substrate a transistor that includes a gate electrode and a source and drain region, forming an interlayer insulating film on the transistor, forming a contact hole in the interlayer insulating film to expose a top surface of the source and drain region, and a thin film is formed at an interface between the contact hole and the exposed top surface of the source and drain region. The method further including selectively removing at least a portion of the thin film by performing an etching process in a non-plasma atmosphere, forming an ohmic contact film on the source and drain region where at least a portion of the thin film was selectively removed, and forming a contact plug by filling the contact hole with a conductive material. | 2013-01-24 |
20130023101 | METHOD AND MANUFACTURE FOR EMBEDDED FLASH TO ACHIEVE HIGH QUALITY SPACERS FOR CORE AND HIGH VOLTAGE DEVICES AND LOW TEMPERATURE SPACERS FOR HIGH PERFORMANCE LOGIC DEVICES - A method and manufacture for memory device fabrication is provided. Spacer formation and junction formation is performed on both: a memory cell region in a core section of a memory device in fabrication, and a high-voltage device region in a periphery section of the memory device in fabrication. The spacer formation and junction formation on both the memory cell region and the high-voltage device region includes performing a rapid thermal anneal. After performing the spacer formation and junction formation on both the memory cell region and the high-voltage device region, spacer formation and junction formation is performed on a low-voltage device region in the periphery section. | 2013-01-24 |
20130023102 | METHOD OF MANUFACTURING SEMICONDUCTOR DEVICE - According to one embodiment, a method of manufacturing a semiconductor device includes forming a gate electrode on a channel region in a silicon substrate via a gate insulation film; forming a source region and a drain region in the silicon substrate so as to sandwich the channel region along a channel direction by injecting desired impurities to the silicon substrate; forming amorphous regions containing the impurities on surfaces of the source region and the drain region by amorphousizing the surfaces of the source region and the drain region; forming nickel films on the amorphous regions; and forming crystal layers containing the activated impurities and forming nickel silicide films on the crystal layers at low temperature by radiating microwaves to the amorphous regions and the nickel films. | 2013-01-24 |
20130023103 | METHOD FOR FABRICATING SEMICONDUCTOR DEVICE BY USING STRESS MEMORIZATION TECHNIQUE - A method for fabricating a semiconductor device is implemented by using a stress memorization technique. The method includes the following steps. Firstly, a substrate is provided, wherein a gate structure is formed over the substrate. Then, a pre-amorphization implantation process is performed to define an amorphized region at a preset area of the substrate with the gate structure serving as an implantation mask. During the pre-amorphization implantation process is performed, the substrate is controlled at a temperature lower than room temperature. Then, a stress layer is formed on the gate structure and a surface of the amorphized region. Then, a thermal treatment process is performed to re-crystallize the amorphized region of the substrate. Afterwards, the stress layer is removed. | 2013-01-24 |
20130023104 | METHOD FOR MANUFACTURING SEMICONDUCTOR DEVICE - According to an embodiment, a method for manufacturing a semiconductor device includes a step of forming an impurity layer on a semiconductor layer, the impurity layer including an impurity element to be doped to the semiconductor layer, and a step of applying a first gas in a plasma state including a first noble gas atom and a second gas in a plasma state including a second noble gas atom or hydrogen (H) toward the impurity layer, the second noble gas atom having a smaller atomic mass than the first noble gas atom. | 2013-01-24 |
20130023105 | MEMORY DEVICE WITH A TEXTURED LOWERED ELECTRODE - Embodiments of the invention generally relate to memory devices and methods for manufacturing such memory devices. In one embodiment, a method for forming a memory device with a textured electrode is provided and includes forming a silicon oxide layer on a lower electrode disposed on a substrate, forming metallic particles on the silicon oxide layer, wherein the metallic particles are separately disposed from each other on the silicon oxide layer. The method further includes etching between the metallic particles while removing a portion of the silicon oxide layer and forming troughs within the lower electrode, removing the metallic particles and remaining silicon oxide layer by a wet etch process while revealing peaks separated by the troughs disposed on the lower electrode, forming a metal oxide film stack within the troughs and over the peaks of the lower electrode, and forming an upper electrode over the metal oxide film stack. | 2013-01-24 |
20130023106 | DEVICE HAVING MEMRISTIVE MEMORY | 2013-01-24 |
20130023107 | METHOD OF PROCESSING DEVICE WAFER - A method of processing a device wafer includes the carrier wafer preparing step of preparing a carrier wafer including an excessive carrier region on a surface thereof which is disposed in a position corresponding to an excessive outer circumferential region on a surface of the device wafer, the recess forming step of forming a recess in the excessive carrier region the carrier wafer, after the recess forming step, the adhesive placing step of placing an adhesive in the recess so as to project from the surface of the carrier wafer, after the adhesive placing step, the wafer bonding step of bonding the surface of the carrier wafer and the surface of the device wafer to each other, thereby securing the device wafer to the carrier wafer with the adhesive, and after the wafer bonding step, the thinning step of thinning the device wafer to a predetermined thickness by grinding or polishing a reverse side of the device wafer. | 2013-01-24 |
20130023108 | METHOD FOR MANUFACTURING SOI SUBSTRATE - An insulating layer is formed on a surface of a semiconductor wafer which is to be a bond substrate and an embrittlement region is formed in the semiconductor wafer by irradiation with accelerated ions. Then, a base substrate and the semiconductor wafer are attached to each other. After that, the semiconductor wafer is divided at the embrittlement region by performing heat treatment and an SOI substrate including a semiconductor layer over the base substrate with the insulating layer interposed therebetween is formed. Before the SOI substrate is formed, heat treatment is performed on the semiconductor wafer at a temperature of higher than or equal to 1100° C. under a non-oxidizing atmosphere in which the concentration of impurities is reduced. In this manner, the planarity of the film formed on the semiconductor wafer when heat treatment is performed can be improved. | 2013-01-24 |
20130023109 | Temporary Wafer Bonding Method for Semiconductor Processing - A method for temporary wafer bonding employs a curable adhesive composition and a degradation agent combined with the curable adhesive composition. The adhesive composition may include (A) a polyorganosiloxane containing an average of at least two silicon-bonded unsaturated organic groups per molecule, (B) an organosilicon compound containing an average of at least two silicon-bonded hydrogen atoms per molecule in an amount sufficient to cure the composition, (C) a catalytic amount of a hydrosilylation catalyst, and (D) a base. The film prepared by curing the composition is degradable and removable by heating. | 2013-01-24 |
20130023110 | METHOD AND APPARATUS FOR FORMING AMORPHOUS SILICON FILM - A method of forming an amorphous silicon film includes: forming a seed layer on a surface of a base by heating the base and supplying an amino silane-based gas to the heated base, forming the amorphous silicon film with thickness for layer growth on the seed layer by heating the base and supplying a silane-based gas containing no amino group to the seed layer on the surface of the heated base, and decreasing a film thickness of the amorphous silicon film by etching the amorphous silicon film formed with thickness for layer growth. | 2013-01-24 |
20130023111 | LOW TEMPERATURE METHODS AND APPARATUS FOR MICROWAVE CRYSTAL REGROWTH - Semiconductor devices and methods for making such devices are described. The semiconductor devices contain an epitaxial layer made by providing a semiconductor substrate containing an upper surface with a single-crystal structure; forming a layer on the upper surface of the substrate, wherein the layer comprises substantially the same material as the semiconductor substrate and comprises an amorphous or polycrystalline structure; and heating the layer using low temperature microwaves to change the amorphous structure to a single-crystal structure. The epitaxial layer can also be made by providing the semiconductor substrate with an upper surface of a single-crystal material and then forming an epitaxial layer on the substrate upper surface using microwaves at a wafer temperature less than about 550° C. In-situ or implanted dopants in the epitaxial layer can be activated using the same, or separate, low temperature microwave processing. Other embodiments are described. | 2013-01-24 |
20130023112 | METHODS FOR POST DOPANT IMPLANT PURGE TREATMENT - Methods for processing substrates are provided herein. In some embodiments, a method of processing a substrate may include implanting a substrate with a dopant in a first vacuum chamber; transferring the substrate to a second vacuum chamber at a first pressure below atmospheric; providing an inert gas to the second vacuum chamber to raise the pressure to a second pressure; pumping down the second vacuum chamber to a third pressure below the second pressure; and providing the inert gas to the second vacuum chamber to raise the pressure to a fourth pressure above the third pressure. | 2013-01-24 |
20130023113 | METHOD FOR MANUFACTURING SEMICONDUCTOR DEVICE - A method for manufacturing a MOSFET includes the steps of: introducing an impurity into a silicon carbide layer; forming a carbon layer in a surface layer portion of the silicon carbide layer having the impurity introduced therein, by selectively removing silicon from the surface layer portion; and activating the impurity by heating the silicon carbide layer having the carbon layer formed therein. | 2013-01-24 |
20130023114 | Method for making semiconductor device - One or more embodiments relate to a method for forming a memory device, the memory device including a control gate, a charge storage structure and a select gate, the method comprising: forming a gate tower, the gate tower including the control gate over the charge storage structure; forming a dummy tower laterally spaced apart from the gate tower; and forming a select gate between the gate tower and the dummy tower. | 2013-01-24 |
20130023115 | Borderless Contacts in Semiconductor Devices - A method includes depositing a dummy fill material over exposed portions of a substrate and a gate stack disposed on the substrate, removing portions of the dummy fill material to expose portions of the substrate, forming a layer of spacer material over the exposed portions of the substrate, the dummy fill material and the gate stack, removing portions of the layer of spacer material to expose portions of the substrate and the dummy fill material, depositing a dielectric layer over the exposed portions of the spacer material, the substrate, and the gate stack, removing portions of the dielectric layer to expose portions of the spacer material, removing exposed portions of the spacer material to expose portions of the substrate and define at least one cavity in the dielectric layer, and depositing a conductive material in the at least one cavity. | 2013-01-24 |
20130023116 | METHOD FOR THE FORMATION OF CO FILM AND METHOD FOR THE FORMATION OF CU INTERCONNECTION FILM - A Co film is formed by supplying cobalt alkylamidinate, and a combined gas containing H | 2013-01-24 |
20130023117 | SEMICONDUCTOR DEVICE MANUFACTURING METHOD AND SEMICONDUCTOR DEVICE MANUFACTURING APPARATUS - A method of manufacturing a semiconductor device includes: preparing a wafer member, the wafer member including a wafer, a conductive layer formed on a surface of the wafer and a negative photoresist formed on the conductive layer; applying a light blocking material so as to cover at least a part of an outer edge of the wafer member from an upper surface of the negative photoresist to a side surface of the negative photoresist; exposing the negative photoresist to exposure light; removing the light blocking material; and developing the negative photoresist. | 2013-01-24 |
20130023118 | METHOD FOR FORMING PATTERN AND METHOD FOR FABRICATING SEMICONDUCTOR DEVICE USING THE SAME - There is provided a method for forming a pattern comprising, forming a first layer on an underlying layer including a substrate, forming a first mask pattern including a first opening pattern on the first layer, and forming a second mask pattern including a second opening pattern on the first mask pattern, wherein the second opening pattern includes a first region overlapping the first opening pattern and a second region not overlapping the first opening pattern, and etching is performed using the second mask pattern such that a third opening pattern corresponding to the first region and exposing an upper surface of the underlying layer is formed in the first layer, and a fourth opening pattern corresponding to the second region is formed in the first mask pattern. | 2013-01-24 |
20130023119 | METHODS FOR FABRICATING SEMICONDUCTOR DEVICES - In a method for fabricating a semiconductor device, a substrate is provided including an interlayer dielectric layer and first and second hard mask patterns sequentially stacked thereon. A first trench is provided in the interlayer dielectric layer through the second hard mask pattern and the first hard mask pattern. A filler material is provided on the interlayer dielectric layer and the second hard mask pattern to fill the first trench. An upper portion of the second hard mask pattern is exposed by partially removing the filler material. The second hard mask pattern is removed, and remaining filler material is removed from the first trench. A wiring is formed by filling the first trench with a conductive material. | 2013-01-24 |
20130023120 | METHOD OF FORMING MASK PATTERN AND METHOD OF MANUFACTURING SEMICONDUCTOR DEVICE - A method of forming a mask pattern includes a first pattern forming step of etching an anti-reflection coating film by using as a mask a first line portion made up of a photo resist film formed on the anti-reflection film to form a pattern including a second line portion made up of the photo resist film and the anti-reflection film; an irradiation step of irradiating the photo resist film with electrons; a silicon oxide film forming step to cover the second line portion isotropically; and an etch back step of etching back the silicon oxide film such that the silicon oxide film is removed from the top of the second line portion as sidewalls of the second line portion. The method further includes a second pattern forming step of ashing the second line portion to form a mask pattern including a third line portion made up of the silicon oxide film and remains. | 2013-01-24 |
20130023121 | DOUBLE PATTERNING METHOD USING TILT-ANGLE DEPOSITION - Methods for patterning material layers, which may be implemented in forming integrated circuit device features, are disclosed. In an example, a method includes forming a first resist layer over a material layer; forming a second resist layer over the first resist layer; forming an opening that extends through the second resist layer and the first resist layer to expose the material layer, wherein the opening has a substantially constant width in the second resist layer and a tapered width in the first resist layer; and performing a tilt-angle deposition process to form a feature over the exposed material layer. | 2013-01-24 |
20130023122 | METHOD OF MULTIPLE PATTERNING OF A LOW-K DIELECTRIC FILM - Methods of multiple patterning of low-k dielectric films are described. For example, a method includes forming and patterning a first mask layer above a low-k dielectric layer, the low-k dielectric layer disposed above a substrate. A second mask layer is formed and patterned above the first mask layer. A pattern of the second mask layer is transferred at least partially into the low-k dielectric layer by modifying first exposed portions of the low-k dielectric layer with a first plasma process and removing the modified portions of the low-k dielectric layer. Subsequently, a pattern of the first mask layer is transferred at least partially into the low-k dielectric layer by modifying second exposed portions of the low-k dielectric layer with a second plasma process and removing the modified portions of the low-k dielectric layer. | 2013-01-24 |
20130023123 | METHOD OF REMOVING A PHOTORESIST FROM A LOW-K DIELECTRIC FILM - Methods of removing photoresists from low-k dielectric films are described. For example, a method includes forming and patterning a photoresist layer above a low-k dielectric layer, the low-k dielectric layer disposed above a substrate. Trenches are formed in the exposed portions of the low-k dielectric layer. A plurality of process cycles is performed to remove the photoresist layer. Each process cycle includes forming a silicon source layer on surfaces of the trenches of the low-k dielectric layer, and exposing the photoresist layer to an oxygen source to form an Si—O-containing layer on the surfaces of the trenches of the low-k dielectric layer and to remove at least a portion of the photoresist layer. | 2013-01-24 |
20130023124 | METHOD OF PATTERNING A LOW-K DIELECTRIC FILM - Methods of patterning low-k dielectric films are described. For example, a method includes forming and patterning a mask layer above a low-k dielectric layer, the low-k dielectric layer disposed above a substrate. Exposed portions of the low-k dielectric layer are modified with a plasma process. The modified portions of the low-k dielectric layer are removed selective to the mask layer and unmodified portions of the low-k dielectric layer. | 2013-01-24 |
20130023125 | METHODS AND APPARATUS FOR ATOMIC LAYER ETCHING - Substrate processing systems and methods for etching an atomic layer are disclosed. The methods and systems are configured to introducing a first gas into the chamber, the gas being an etchant gas suitable for etching the layer and allowing the first gas to be present in the chamber for a period of time sufficient to cause adsorption of at least some of the first gas into the layer. The first gas is substantially replaced in the chamber with an inert gas, and metastables are then generated from the inert gas to etch the layer with the metastables while substantially preventing the plasma charged species from etching the layer. | 2013-01-24 |
20130023126 | Method for the manufacture of electronic devices with purified fluorine - Elemental fluorine is used as etching agent for the manufacture of electronic devices, especially semiconductor devices, micro-electromechanical devices, thin film transistors, flat panel displays and solar panels, and as chamber cleaning agent mainly for plasma-enhanced chemical vapor deposition (PECVD) apparatus. For this purpose, fluorine often is produced on-site. The invention provides a process for the manufacture of electronic devices wherein fluorine is produced on site and is purified from HF by a low temperature treatment. A pressure of between 1.5 and 20 Bars absolute is especially advantageous. | 2013-01-24 |
20130023127 | METHOD OF FORMING A CONTACT HOLE AND APPARATUS FOR PERFORMING THE SAME - A method of forming a contact hole includes loading a substrate into a plasma chamber, the substrate including an etch stop layer, an insulation interlayer, a mask layer and a photoresist pattern sequentially disposed thereon, applying a DC voltage to an upper electrode and applying a first high frequency power and a second high frequency power to a lower electrode to generate plasma in the chamber, the first frequency power and second high frequency powers having different frequency levels, supplying a reaction gas to the chamber to etch the mask layer and the insulation interlayer, wherein the chamber is maintained at a temperature of 100° C. to 200° C.; and etching the etch stop layer to form a contact hole | 2013-01-24 |
20130023128 | METHOD FOR MANUFACTURING NITRIDE SEMICONDUCTOR SUBSTRATE - There is provided a method for manufacturing a nitride semiconductor substrate, comprising: etching and flattening a surface of a nitride semiconductor substrate disposed facing a surface plate, by using the surface plate having a surface composed of any one of Ni, Ti, Cr, W, and Mo or nitride of any one of them, disposing the surface of the surface plate and a flattening surface of a nitride semiconductor substrate proximately so as to be faced each other, and supplying gas containing at least hydrogen and ammonia between the surface of the surface plate and the surface of the nitride semiconductor substrate, wherein the surface plate and the nitride semiconductor substrate facing each other are set in a high temperature state of 900° C. or more. | 2013-01-24 |
20130023129 | PRESSURE TRANSMITTER FOR A SEMICONDUCTOR PROCESSING ENVIRONMENT - Embodiments related to measuring process pressure in low-pressure semiconductor processing environments are provided. In one example, a semiconductor processing module for processing a substrate with a process gas in a vacuum chamber is provided. The example module includes a reactor positioned within the vacuum chamber for processing the substrate with the process gas and a pressure-sensitive structure operative to transmit a pressure transmission fluid pressure to a location exterior to the vacuum chamber. In this example, the pressure transmission fluid pressure varies in response to the process gas pressure within the vacuum chamber. | 2013-01-24 |
20130023130 | STIRRING APPARATUS FOR COMBINATORIAL PROCESSING - An apparatus and system for stirring liquid inside a flow cell. In one implementation, the apparatus includes a rotatable disc configured to receive liquid at a top side of the disc and distribute the liquid substantially evenly around a periphery of the flow cell. The disc has a triangular cross sectional area. The apparatus may further include a set of fins attached to a bottom side of the disc, wherein the set of fins is configured to draw the liquid from the periphery of the flow cell into the center of the flow cell. | 2013-01-24 |
20130023131 | CONNECTING PART BETWEEN LEAD-IN AND MARINE STREAMER AND METHOD - Seismic data acquisition system, method, and connecting part configured to connect a lead-in to a streamer. The connecting part includes a single body extending along a longitudinal axis (X) between the lead-in and the streamer; the single body has a first end configured to connect to the lead-in through a first connection device and the body also has a second end configured to connect to the streamer through a second connection device; at least a link connecting the first end to the second end and configured to receive a tension that appears in the single body; a cable extending through the single body and configured to provide data communications; and plural modules provided on the single body. The single body is configured to wound-up on a spool. | 2013-01-24 |
20130023132 | FORMED SHIELDING FEATURE - An electrical device, includes electrical pins that protrude from an enclosing metal housing. A compressible protrusion around the pins is formed out of the material of the metal housing. The protrusion is formed such that (1) an EMI shield does not exist around the pins when the pins are not engaged to an electrical coupler, and (2) the EMI shield is formed around the electrical pins when the protrusion is compressed by an electrical coupler engaging the electrical pins. | 2013-01-24 |
20130023133 | WIND TURBINE JUNCTION BOX HAVING INDIVIDUAL RUN - A wind turbine junction box having an individual run, a housing, and an electrical circuit connector. The housing has a top surface that includes a plurality of apertures formed therein in an individual run on an axis that extends between side walls of the housing. The electrical circuit connector includes a non-conductive cross beam having first and second ends, each of which is secured to a respective side wall of the housing. Electrical connectors are secured to the cross beam, with each of the electrical connectors oriented along an axis that extends from the top to the bottom of the housing. | 2013-01-24 |
20130023134 | CONNECTOR MECHANISM FOR CONNECTING A BOARD CARD - A connector mechanism includes a circuit board whereon an electrical contact and a hole are formed, a socket where an end of a board card is inserted, a fixing base disposed on a side of the socket, a positioning component disposed on the fixing base and inserted into the hole at an end so as to fix the fixing base on the circuit board, and a connecting component detachably installed on the fixing base. The connecting component includes an engaging portion for engaging with the fixing base and contacting with the electrical contact, and a connecting terminal installed on an end of the engaging portion for contacting with a terminal on the other end of the board card as the engaging portion engages with the fixing base and the end of the board card is inserted into the socket. | 2013-01-24 |
20130023135 | TERMINAL HOUSING APPARATUS AND ELECTRONIC APPLIANCE - There is provided a terminal housing apparatus including: a housing portion that is provided with an opening and houses a terminal; a terminal operating lever that is rotatably supported at one end thereof, engages the terminal at another end thereof, moves the terminal in a first direction so as to extend the terminal outside the housing portion, and moves the terminal in a second direction so as to store the terminal in the housing portion; and an operation portion that engages the terminal operating lever and is operable to rotate the terminal operating lever when operated by the user. | 2013-01-24 |
20130023136 | APPARATUS FOR INSERTING/EXTRACTING INSERT TYPE CARD FOR ELECTRONIC DEVICE - An apparatus for inserting/extracting an insert type card for an electronic device using a card cover includes: a card insert slot formed in the electronic device; a card cover installed in the card insert slot; and at least one card inserting/extracting portion formed at a circumference of the card insert slot, wherein the card inserting/extracting portion allows the card cover to push the insert type card. | 2013-01-24 |
20130023137 | ELECTRICAL CONNECTOR - An electrical connector includes an electrical terminal and a housing having a front end and a back end with an opening configured to receive the electrical terminal therethrough. The housing includes a first lock system configured to allow insertion of the electrical terminal into the housing and prohibit removal of the electrical terminal from the housing. The housing is configured such that the first lock system is accessible from the front of the housing to release the electrical terminal from the first lock system. A second lock system is configured for insertion into the housing to prohibit removal of the electrical terminal from the housing independently from the first lock system. | 2013-01-24 |
20130023138 | CONNECTOR - The invention provides a connector including a housing, contacts, and an actuator. The housing includes a first depression and second depressions. The second depressions include bottom surfaces. The contacts include hooks to be disposed within the first depression. The actuator includes bosses, received in the second depressions, and a shaft, received in the first depression. The bosses each include an axial center and first and second contact portions. The distance between the axial center and the first contact portion is smaller than the distance between the axial center and the second contact portion. When the actuator is in an upright position, the first contact portions are on the bottom surfaces and the shaft is on the lower side of the hooks. When the actuator rotates to a lying position, the bosses rotate along the bottom surfaces and the shaft move to the upper side to be engaged with the hooks. | 2013-01-24 |
20130023139 | ELECTRICAL CONTACT COUPLING FOR A TRACK-BORNE VEHICLE, PARTICULARLY A RAILWAY VEHICLE - An electrical contact coupling for a track-borne vehicle has a coupling housing and a protective flap articulated to the coupling housing. In order to ensure a reliable sealing of the coupling housing in the closed state of the electrical contact coupling, a seal is utilized which exhibits an upper sealing area running parallel to the axis of rotation and a lower sealing area running parallel to the axis of rotation. The upper sealing area associates with a sealing face aligned perpendicular to the housing end face and the lower sealing area associates with a sealing face aligned substantially parallel to the housing end face. | 2013-01-24 |
20130023140 | WATERPROOF CONNECTOR - A waterproof connector ( | 2013-01-24 |
20130023141 | CHARGING COUPLING AND CHARGING COUPLING ARRANGEMENT FOR A MOTOR VEHICLE, AND MOTOR VEHICLE - A charging coupling ( | 2013-01-24 |
20130023142 | CONNECTOR - The invention provides a connector including a housing, contacts, and an actuator. The housing includes a first depression and second depressions. The second depressions are provided at opposite edges of the first depression and each include a bottom surface forming a slope. The contacts are arranged at intervals in the housing and each include a hook to be disposed within the first depression. The actuator includes bosses and a shaft. The bosses are received in the second depressions. The shaft is received in the first depression. When the actuator is in an upright position, the bosses are on the slopes and the shaft is positioned on the other side of the hooks. When the actuator rotates from the upright position to a lying position, the bosses rotatingly move up along the slopes and the shaft thereby move, to the one side to be engaged with the hooks. | 2013-01-24 |
20130023143 | ELECTRICAL ASSEMBLY WITH SOCKET AND PLUG - The invention relates to a plug assembly ( | 2013-01-24 |
20130023144 | ELECTRICAL CONNECTOR ASSEMBLY - An electrical connector assembly includes a male connector and a female connector connectable to the male connector. The male connector includes a male insulating housing and a number of first terminals assembled in the male insulating housing. a protrusion extends up from the top surface of the male insulating housing. The protrusion forms an ejecting surface at a rear side of the protrusion. The female connector includes a female insulating housing and a number of second terminals assembled to the female insulating housing for connecting with the first terminals. a fastening hole is defined in the top surface of the female insulating housing to hold the protrusion therein. The ejecting surface of the protrusion of the male connector is substantially arc-shaped or inclined. | 2013-01-24 |
20130023145 | POWER FEEDING CONNECTOR - In a power feeding connector | 2013-01-24 |
20130023146 | CABLE CONNECTION SYSTEM AND METHOD FOR CONNECTING A CABLE TO A CABLE CONNECTION SYSTEM - The invention relates to a cable connection system, in particular a cable connection plug, comprising a guide device, a cap nut adapted to be screwed onto a connection part comprising at least one connection element and at least one insulation displacement connector, wherein the guide device comprises a cable receiving part for receiving and clamping an end region of a cable comprising at least one wire and a wire guide part for guiding the wire by means of at least one wire guide structure. The invention also relates to a method for connecting a shielded cable to a cable connection system of this kind. | 2013-01-24 |
20130023147 | RECONFIGURABLE PLUG STRIP - A power strip for conducting electrical power between an electrical power outlet having at least a live receptacle and a neutral receptacle, and at least two electrical device power plugs, each plug having at least a live prong and a neutral prong. The power strip includes a first housing segment having a first receptacle configured to receive at least an electrically conductive portion of a first device plug and a second housing segment having a second receptacle configured to receive at least an electrically conductive portion of a second device plug. The second housing is coupled to the first housing for pivotal movement relative to said first housing; | 2013-01-24 |
20130023148 | EXTENSION SOCKET WITH CORD STORAGE AND DISPENSING SYSTEM - Extension socket ( | 2013-01-24 |
20130023149 | RISING RECEPTACLE BOX ASSEMBLY - A rising receptacle box assembly includes a receptacle assembly for housing receptacles and jacks. The receptacle assembly can move between a lowered position and a raised position. In the raised position, the receptacle assembly is substantially level with a work surface on which the rising receptacle box assembly is supported, so that the receptacles and jacks are easily accessible. In the lowered position, the receptacle assembly is lowered beneath the work surface so that inserted plugs and connectors are stowed away in a recess below the work surface. Raising and lowering of the receptacle assembly can be coupled to the opening and closing of a lid of the rising receptacle box assembly. The lid may include one or more cutouts so that cables associated with inserted plugs and connectors can pass through when the receptacle assembly moves to the lowered position. | 2013-01-24 |
20130023150 | MODULAR OPEN FUSE HOLDER - A fuse holder includes a two piece base assembly allowing assembly and attachment of fuse clips and terminals without separately provided, external fasteners such as screws. Fuse rejection features may be built-in to the base assembly adjacent one of the fuse clips. | 2013-01-24 |
20130023151 | COAXIAL CABLE CONNECTOR WITH CONDUCTIVE SEAL - A coaxial cable connector for connection to a terminal includes inner and outer spaced concentric sleeves configured to cooperate in retaining an end of a coaxial cable, at least one of the inner and outer sleeves having a flange at its forward end and a coupling member configured to draw the flange toward an end of the terminal. The coupling member and the flange have confronting surface portions therebetween. The connector further includes an annular electrically conductive member disposed between the confronting surface portions for establishing conductivity between the coupling member and the flange when the coupling member and the flange are drawn into proximity with one another. | 2013-01-24 |
20130023152 | Broadband Interface Connection System - The present invention provides a universal broadband interface connection system, which increases the reliability of a drop system. The present invention provides a cable connection system including a nut assembly including a nut and a donut; a slug assembly including a first sleeve, a second sleeve, and a ferrule; and a port assembly including a port and an insulative ring. | 2013-01-24 |
20130023153 | ELECTRICAL CONNECTOR - An electrical connector has a housing that includes a carrier and a shield matable to define the housing. The carrier has terminal channels and terminal latches extending into the terminal channels. The shield having lead-in channels through a face of the shield. Terminals are received in corresponding terminal channels. The terminals are held in the terminal channels by the terminal latches. The carrier and the shield are molded as a single piece with a bridge connecting the carrier and the shield. The bridge is broken during assembly to allow coupling of the shield to the carrier. The lead-in channels are aligned with, and positioned forward of, the terminal channels when the shield is mated with the carrier. The lead-in channels guide mating contacts for mating with the terminals held in the terminal channels. | 2013-01-24 |
20130023154 | Shielded Connector and Method for Assembling The Shielded Connector - A shielded connector includes an inner housing that has a plurality of terminal accommodating chambers into which terminals which are crimped to ends of a plurality of shielded wires of a shielded electric wire are inserted, and a shield shell that includes a shield part which covers the inner housing and a barrel part which fixes a sheath part of the shielded electric wire. The inner housing has divided constructions into which the terminals can be inserted for each of a plurality of terminal groups. | 2013-01-24 |
20130023155 | Shielded Connector - A shielded connector includes an inner housing to which terminals connected to a shielded electric wire is attached, a shield shell that includes a shield part and a barrel part, and a shield shell cover that covers a shielded wire exposure part of the shielded electric wire. The shield shell cover has a pair of insertion lap parts which are inserted between two side surfaces of the inner housing and two side surfaces of the shield part. A backlash preventing unit is provided on a top surface and a bottom surface of the inner housing and parts of the shield part which opposite to the top surface and the bottom surface of the inner housing so as to prevent a shaking between the inner housing and the shield shell. | 2013-01-24 |
20130023156 | MODULAR OPEN FUSEHOLDER WITH MULTI-STAGE POSITIONABLE COVER - A modular fuse holder includes a cover that is movable from a closed position to an open position relative to a base along two different paths of motion to prevent inadvertent opening or closing of the cover. | 2013-01-24 |
20130023157 | ELECTRICAL CONTACT WITH ADJUSTABLE LENGTH - An electrical contact includes a primary segment having a primary outer end, and a secondary segment having a secondary outer end. An intermediate segment joins the primary and secondary segments together. The intermediate segment includes a primary segment connector engaged with the primary segment such that the intermediate segment is electrically and mechanically connected to the primary segment. The intermediate segment includes a secondary segment connector engaged with the secondary segment such that the intermediate segment is electrically and mechanically connected to the secondary segment. The electrical contact has a length defined from the primary outer end of the primary segment to the secondary outer end of the secondary segment. At least one of the primary segment is selectively positionable relative to the primary segment connector of the intermediate segment or the secondary segment is selectively positionable relative to the secondary segment connector of the intermediate segment such that the length of the electrical contact is adjustable. | 2013-01-24 |
20130023158 | LOW HEIGHT CONNECTOR AND METHOD OF PRODUCING THE SAME - A method of producing a low height connector, includes: removing an insulating covering from a first part of an electric wire; forming the electric wire into a predetermined shape in which the first part of the electric wire is bent; joining a terminal to a second part of the electric wire; and molding the electric wire to surround at least the first part and the second part of the electric wire with a housing to obtain the low height connector. | 2013-01-24 |
20130023159 | CABLE CONNECTOR - A cable connector for detachably connecting a lead having at least one contact to a system analyzer comprising a nonconductive base, a first conductive clip assembly connected to the base, and a second conductive clip assembly connected to the base. Each of the first and second conductive clip assemblies defining a lead contact receiving space which is in axial alignment with the other lead contact receiving space. The base further comprises a first base section and a second base section wherein the first conductive clip assembly is connected to the first base section and the second conductive clip assembly is connected to the second base section and wherein the first base section is selectively detachable from the second base section. | 2013-01-24 |
20130023160 | DELAYED CONTACT ACTION CONNECTOR - A connector with terminals for connecting to a circuit card and a method therefore are disclosed. The connector includes a socket having a casing with an aperture for receiving the circuit card therein and electrically conductive terminals. The terminals include an elongated portion and a substantially L-shaped portion joined together by a U-shaped portion. The elongated portion has a proximal end and a distal end, and includes a support section and a bending section between the proximal end and the distal end. The U-shaped portion is disposed at the distal end of the elongated portion. The terminal continues from the U-shaped portion to approximately halfway towards the proximal end of the elongated portion and turns away from the elongated portion thereby forming the substantially L-shaped portion. The L-shaped portion ends in a lip section curving towards the proximal end of the elongated portion. | 2013-01-24 |
20130023161 | ELECTRICAL CHARGER WITH BASE UNIT AND ADAPTOR UNIT - There is provided an electrical charger including a base unit and an adaptor unit. The base unit is configured for being coupled to an electronic device, and includes an electrical connector plug which includes a plurality of electrical connector plug contacts. The adaptor unit is configured for being coupled to a power supply, and includes a plurality of adaptor unit contacts and a receiving aperture defining an opening for an electrical connector plug receiving receptacle configured for receiving the electrical connector plug. | 2013-01-24 |
20130023162 | LOW PROFILE ELECTRICAL CONNECTOR HAVING IMPROVED TERMINALS - An electrical connector includes an insulative housing defining a receiving cavity extending along a longitudinal direction and a plurality of stamped terminals arranged in the insulative housing along the longitudinal direction with each terminal disposed in a transverse plane perpendicularly to the longitudinal direction. Each terminal defines a retaining portion retained in the insulative housing, a contacting portion projecting into the receiving cavity, and a connecting arm connecting the retaining portion with the contacting portion, the contacting portion defines opposite first and second contacting arms upwardly extending toward each other from the connecting arm. The first contacting arm abuts against the second contacting arm when the terminal mating with a counterpart terminal so as to provide a low profile electrical connector. | 2013-01-24 |
20130023163 | ELECTRICAL CONNECTOR - An electrical connector includes an electrical terminal and a housing having a front end and a back end with an opening configured to receive the electrical terminal. The housing includes a first lock system configured to allow insertion of the electrical terminal into the housing and prohibit removal of the electrical terminal from the housing. It also includes a tapered surface and for guiding the electrical terminal to a desired position when the electrical terminal is inserted into the housing. A second lock system cooperates with the housing in a lock position for prohibiting removal of the electrical terminal from the housing. It also cooperates with the housing in a pre-lock position wherein a tapered surface of the second lock system is configured to cooperate with the tapered surface of the housing for guiding the electrical terminal to the desired position when the electrical terminal is inserted into the housing. | 2013-01-24 |
20130023164 | CASE STRUCTURE OF A GROUND ROD - A case structure of a ground rod includes a first block having a positioning hole, a second block having a positioning hole, a through-hole and a gap communicating with the through-hole. The positioning holes of the first and second blocks are capable of being extended through by a fixing member to adjust a width of the gap. | 2013-01-24 |
20130023165 | SCREW TERMINAL BLOCK, ELECTRIC MOTOR CONTROLLER, AND ELECTRICAL DEVICE - An electric motor controller with a screw terminal block including: a terminal fitting connected with a solderless terminal having a crimping portion crimped to wire cores of an electrical wire; a plate-shaped square washer having a cut-out portion in at least one edge thereof, the cut-out portion for avoiding interference with the crimping portion of the solderless terminal or the wire cores projecting from the crimping portion to an end of the electrical wire; and a terminal screw fixing the solderless terminal between the square washer and the terminal fitting. | 2013-01-24 |
20130023166 | SILVER PLATED ELECTRICAL CONTACT - A method for silver plating an electrical contact is provided. The method includes cleaning an electrical contact by removing oil or other contaminants and exposing the electrical contact to at least one of an acid or base. The method also includes preparing a silver plating bath including a silver compound, a transition metal compound, and a supporting salt, wherein the transition metal is at least one of nickel or cobalt. The method further includes silver plating the electrical contact in the silver plating bath. | 2013-01-24 |
20130023167 | WATER JET PROPULSION WATERCRAFT - A water jet propulsion watercraft includes a hull having a sealed engine room, an engine installed in the engine room, a jet propulsion unit arranged to be driven by the engine so as to suck in water from around the hull and jet the water, a saddle type seat disposed above the engine room, a first exhaust pipe, an exhaust pipe cooling unit, and a catalyst unit. The first exhaust pipe is attached to a side of the engine inside the engine room, extends rearward from the side of the engine, and is arranged to guide exhaust gas discharged from the engine. The exhaust pipe cooling unit is arranged to cool the first exhaust pipe. The catalyst unit is connected to the first exhaust pipe, is disposed inside the engine room so as to oppose a rear surface of the engine, and is arranged to promote reaction of components contained in the exhaust gas. | 2013-01-24 |
20130023168 | Fin - A fin comprising a foot pocket, two ribs and a web portion is provided in this invention. The foot pocket has a surrounding portion and a base portion, which together define a foot receiving space. The surrounding portion has a plurality of first and second structures; the ribs extend forwards from two sides of the foot pocket respectively; and the web portion is formed between the two ribs. The first structures and the second structures are alternately arranged, and a first thickness of each of the first structures is thicker than a second thickness of each of the second structures. Thereby, the foot pocket of the fin is made flexible and elastic for swimmers or divers with different foot forms and sizes. | 2013-01-24 |
20130023169 | Tri-Hulled Stand-Up Paddle Board - A trimaran standup paddleboard includes a main hull having a bow, a mid-beam and a stern. The main hull has a length and shape that extends from a point at the bow, broadens out to the mid-beam, and narrows to a point at the stern. The trimaran standup paddleboard further includes a platform on top and aft the main hull, the platform being planar and extending out sideways beyond the mid-beam of the main hull, and a pair of lateral struts extending laterally out from opposing sides of the main hull behind the platform from a proximal end of each lateral strut. The trimaran standup paddleboard further includes a pair of outrigger hulls, each outrigger hull being connected to a distal end of one of the pair of lateral struts, and positioned parallel with and spaced apart from the main hull aft the platform. | 2013-01-24 |