04th week of 2020 patent applcation highlights part 57 |
Patent application number | Title | Published |
20200027908 | High-Q Integrated Circuit Inductor Structure and Methods - FET IC structures that enable formation of high-Q inductors in a “flipped” SOI IC structure made using a back-side access process, such as an single layer transfer (SLT) process. Essentially, the interconnect layer superstructure of an IC is split into two parts, a “lower” superstructure and an “upper” superstructure. In various embodiments, one or more low-resistance interconnect layers are fabricated within an upper superstructure formed after the application of a back-side access process, allowing fabrication of inductors in one or more low-resistance interconnect layer. A significant advantage of such IC structures is that the low-resistance interconnect layer or layers are relocated from being near the handle wafer of a conventional SLT IC to being spaced away from the handle wafer by intervening structures. Fabricating inductors in such spaced low-resistance interconnect layer or layers reduces electromagnetic coupling with the handle wafer and thus increases the Q factor of the inductors. | 2020-01-23 |
20200027909 | LIGHT RECEIVING ELEMENT, RANGING MODULE, AND ELECTRONIC APPARATUS - Disclosed is a light receiving element including an on-chip lens, a wiring layer, and a semiconductor layer disposed between the on-chip lens and the wiring layer. The semiconductor layer includes a photodiode, a first transfer transistor that transfers electric charge generated in the photodiode to a first charge storage portion, a second transfer transistor that transfers electric charge generated in the photodiode to a second charge storage portion, and an interpixel separation portion that separates the semiconductor layers of adjacent pixels from each other, for at least part of the semiconductor layer in the depth direction. The wiring layer has at least one layer including a light blocking member. The light blocking member is disposed to overlap with the photodiode in a plan view. | 2020-01-23 |
20200027910 | SOLID-STATE IMAGING DEVICE, METHOD FOR FABRICATING SOLID-STATE IMAGING DEVICE, AND ELECTRONIC APPARATUS - One object of the present invention is to provide a solid-state imaging device, a method for fabricating a solid-state imaging device, and an electronic apparatus that implement both a wide dynamic range and a high sensitivity. A storage capacitor serving as a storage capacitance element includes a first electrode and a second electrode on a second substrate surface side. The first electrode is formed of a p+ region (the second conductivity type semiconductor region) formed in the surface of a second substrate surface of a substrate, and the second electrode is formed above the second substrate surface so as to be opposed at a distance to the first electrode in the direction perpendicular to the substrate surface. The first electrode and the second electrode are arranged so as to spatially overlap with a photoelectric conversion part in the direction perpendicular to the substrate surface. | 2020-01-23 |
20200027911 | EXTENDED DYNAMIC RANGE IMAGING SENSOR AND OPERATING MODE OF THE SAME - An imaging system for capturing light over a wide dynamic range and method for operating the same are provided. In some aspects, the method includes positioning an imaging pixel to image a scene described by light signals that extend over a wide dynamic range, and selecting a different integration time for at least two photodiodes in the imaging pixel based on light signals received by the imaging pixel, wherein the photodiodes are coupled to a sense node, and each photodiode is controlled using a different transfer gate. The method also includes performing a readout of the imaging pixel using a readout circuit connected to the sense node, wherein a capacitance associated with the sense node is modified during the readout of the at least two photodiodes. | 2020-01-23 |
20200027912 | IMAGE SENSORS - An image sensor may include a substrate which includes a plurality of block regions. Each block region may include a separate plurality of pixel regions. Each pixel region may include a separate photoelectric element of a plurality of photoelectric elements in the substrate and a separate micro lens of a plurality of micro lenses on the substrate. Each micro lens of the plurality of micro lenses may be laterally offset from a vertical centerline of the pixel region towards a center of the block region. Each block region of the plurality of block regions may include a common shifted shape of the plurality of micro lenses of the block region. | 2020-01-23 |
20200027913 | IMAGING ELEMENT AND ELECTRONIC APPARATUS - The present disclosure relates to an imaging element and an electronic apparatus configured to achieve higher-resolution image taking. The imaging element includes: a photoelectric conversion portion provided in a semiconductor substrate for each pixel that performs photoelectric conversion on light that enters through a filter layer; an element isolation portion configured to separate the photoelectric conversion portions of adjacent pixels; and an inter-pixel light shielding portion disposed between the pixels in a layer and provided between the semiconductor substrate and the filter layer and separated from a light receiving surface of the semiconductor substrate by a predetermined interval. Moreover, an interval between the light receiving surface of the semiconductor substrate and a tip end surface of the inter-pixel light shielding portion is smaller than a width of the tip end surface of the inter-pixel light shielding portion. The present technology is applicable to back-illuminated CMOS image sensors, for example. | 2020-01-23 |
20200027914 | IMAGE SENSOR - An image sensor includes a pixel array including a plurality of pixels arranged in a first direction and a second direction. Each pixel of the plurality of pixels includes a plurality of photodiodes disposed adjacent to one another in at least one of the first direction and the second direction. The image sensor further includes a control logic configured to generate image data by obtaining pixel signals from the plurality of pixels, and read a pixel voltage corresponding to charges generated by two or more of the plurality of photodiodes included in one of the plurality of pixels, at substantially the same time. | 2020-01-23 |
20200027915 | OPTICAL SENSOR DEVICE - An optical sensor device is provided. The optical sensor device includes a semiconductor substrate, a trench isolation element, and a photodiode. The semiconductor substrate has a back semiconductor surface and a front semiconductor surface opposing to the back semiconductor surface. The back semiconductor surface has a textured surface. The trench isolation element is extended from the back semiconductor surface to the front semiconductor surface. The photodiode is in the semiconductor substrate. | 2020-01-23 |
20200027916 | PIXEL FOR UNCOOLED INFRARED FOCAL PLANE DETECTOR AND PREPARATION METHOD THEREFOR - Provided are a pixel of an uncooled infrared focal plane detector and a preparation method therefor. The pixel includes a structure of three layers sequentially located on a semiconductor substrate from bottom to top. The first layer is a bridge structure including a metal reflection layer, an insulation dielectric layer, a first supporting layer, a first support layer protection layer, a first metal electrode layer and a first silicon nitride dielectric layer. The second layer is a thermal conversion structure including a second support layer, a second support layer protection layer, a thermal sensitive layer, a thermal sensitive layer production layer, a second metal electrode layer and a second silicon nitride dielectric layer. The third layer is an absorption structure including a third support layer, an absorption layer and an absorption layer protection layer. | 2020-01-23 |
20200027917 | LIGHT EMITTING DEVICE PACKAGE - A light emitting device package includes a cell array having a first surface and a second surface located opposite to the first surface and including, on a portion of a horizontal extension line of the first surface, semiconductor light emitting units each including a first conductivity type semiconductor layer, an active layer, and a second conductivity type semiconductor layer sequentially located on a layer surface including a sidewall of the first conductivity type semiconductor layer; wavelength converting units corresponding respectively to the semiconductor light emitting units and each arranged corresponding to the first conductivity type semiconductor layer; a barrier structure arranged between the wavelength converting units corresponding to the cell array; and switching units arranged in the barrier structure and electrically connected to the semiconductor light emitting units. | 2020-01-23 |
20200027918 | DISPLAY PANEL - A display panel comprises a first substrate and a shading layer. The first substrate comprises a plurality of pixel zones arranging in an array form. Each of the pixel zones comprises a first color LED and a second color LED. The first color LED comprise a first light-emitting surface in a display direction. The second color LED comprise a second light-emitting surface in the display direction. An area of the first light-emitting surface is larger than an area of the second light-emitting surface. The shading layer is disposed in the plurality of pixel zones, and the shading layer overlaps some of the first light-emitting surfaces at the display direction. | 2020-01-23 |
20200027919 | FABRICATION METHODS - Various fabrication method are disclosed. In one such method, at least one structure is formed on a substrate which protrudes outwardly from a plane of the substrate. A beam is used to form a layer of material, at least part of which is in direct contact with a semiconductor structure on the substrate, the semiconductor structure comprising at least one nanowire. The beam has a non-zero angle of incidence relative to the normal of the plane of the substrate such that the beam is incident on one side of the protruding structure, thereby preventing a portion of the nanowire in a shadow region adjacent the other side of the protruding structure in the plane of the substrate from being covered with the material. | 2020-01-23 |
20200027920 | MAGNETIC TUNNEL JUNCTION ELEMENT, MAGNETIC MEMORY USING THE SAME, AND MANUFACTURE METHOD OF MAGNETIC TUNNEL JUNCTION ELEMENT - To provide a magnetic tunnel junction (MTJ) element that is adapted to suppress the degradation of magnetic properties of a magnetic tunnel junction layer due to plasma CVD layer formation and adapted for miniaturization. The MTJ element includes a magnetic tunnel junction layer ( | 2020-01-23 |
20200027921 | NEARLY 2D ELECTRONIC MICROPARTICLES - An particle can include a first sheet comprising a layer including a first material, wherein the first sheet includes a first outer surface and a first inner surface; and a second sheet comprising a layer including a second material, where the second sheet includes a second outer surface and a second inner surface, wherein the first sheet and the second sheet form a space, the space is encapsulated by the first sheet and the second sheet. | 2020-01-23 |
20200027922 | MEMORY CIRCUIT AND FORMATION METHOD THEREOF - The present disclosure, in some embodiments, relates to an integrated chip. The integrated chip includes a control device arranged within a substrate and having a terminal. A first memory device is coupled between the terminal of the control device and a first bit-line. A second memory device is coupled between the terminal of the control device and a second bit-line. | 2020-01-23 |
20200027923 | MEMORY DEVICE - According to one embodiment, a memory device includes first and second electrically conductive portions, a first variable resistance portion, and a first region. A direction from the first electrically conductive portion toward the second electrically conductive portion is aligned with a first direction. The first variable resistance portion is provided between the first and second electrically conductive portions. A second direction from the first variable resistance portion toward the first region crosses the first direction. The first region includes a first layer portion, and a second layer portion provided between the first layer portion and the first variable resistance portion in the second direction. A first distance between the first and second layer portions is longer than first or second lattice length. The first lattice length is a lattice length of the first layer portion. The second lattice length is a lattice length of the second layer portion. | 2020-01-23 |
20200027924 | RRAM MEMORY CELL WITH MULTIPLE FILAMENTS - The present disclosure, in some embodiments, relates to an integrated chip. The integrated chip includes a conductive element disposed within a dielectric structure over the substrate. The conductive element has a top surface extend between outermost sidewalls of the conductive element. A first resistive random access memory (RRAM) element is arranged within the dielectric structure and has a first data storage layer directly contacting the top surface of the conductive element. A second RRAM element is arranged within the dielectric structure and has a second data storage layer directly contacting the top surface of the conductive element. | 2020-01-23 |
20200027925 | VARIABLE RESISTANCE MEMORY DEVICE INCLUDING SYMMETRICAL MEMORY CELL ARRANGEMENTS AND METHOD OF FORMING THE SAME - A variable resistance non-volatile memory device can include a semiconductor substrate and a plurality of first conductive lines each extending in a first direction perpendicular to the semiconductor substrate and spaced apart in a second direction on the semiconductor substrate. A second conductive line can extend in the second direction parallel to the semiconductor substrate on a first side of the plurality of first conductive lines and a third conductive line can extend in the second direction parallel to the semiconductor substrate on a second side of the plurality of first conductive lines opposite the first side of the plurality of first conductive lines. A plurality of first non-volatile memory cells can be on the first side of the plurality of first conductive lines and each can be coupled to the second conductive line and to a respective one of the plurality of first conductive lines, where each of the plurality of first non-volatile memory cells can include a switching element, a variable resistance element, and an electrode arranged in a first sequence. A plurality of second non-volatile memory cells can be on the second side of the plurality of first conductive lines and each can be coupled to the third conductive line and to a respective one of the plurality of first conductive lines, wherein each of the plurality of second non-volatile memory cells includes a switching element, a variable resistance element, and an electrode that are arranged in a second sequence, wherein the first sequence and the second sequence are symmetrical with one another about the plurality of first conductive lines. | 2020-01-23 |
20200027926 | CROSS-POINT MEMORY AND METHODS FOR FABRICATION OF SAME - The disclosed technology relates generally to integrated circuit devices, and in particular to cross-point memory arrays and methods for fabricating the same. In one aspect, a memory device of the memory array comprises a substrate and a memory cell stack formed between and electrically connected to first and second conductive lines. The memory cell stack comprises a first memory element over the substrate and a second memory element formed over the first element, wherein one of the first and second memory elements comprises a storage element and the other of the first and second memory elements comprises a selector element. The memory cell stack additionally comprises a first pair of sidewalls opposing each other and a second pair of sidewalls opposing each other and intersecting the first pair of sidewalls. The memory device additionally comprises first protective dielectric insulating materials formed on a lower portion of the first pair of sidewalls and an isolation dielectric formed on the first protective dielectric insulating material and further formed on an upper portion of the first pair of sidewalls. | 2020-01-23 |
20200027927 | MANUFACTURING METHOD OF DISPLAY DEVICE AND THIN-FILM DEPOSITION APPARATUS USING THE SAME - A method of manufacturing a display device, including: providing a display element layer on a substrate; forming a thin film encapsulation layer covering the display element layer; aging the thin film encapsulation layer by using a light source emitting artificial sunlight; and forming a window on the aged thin film encapsulation layer. | 2020-01-23 |
20200027928 | ORGANIC LIGHT EMITTING DIODE DISPLAY - Provided is an organic light emitting diode display. The OLED display includes a thin film transistor substrate, a white OLED layer, a quantum dot photoluminescence film and a color filter film. The OLED display includes sub-pixels, which are sequentially disposed. The sub-pixels include a red sub-pixel, a green sub-pixel and a blue sub-pixel. A region of the quantum dot photoluminescence film corresponding to the red sub-pixel is provided with red quantum dots, and a region corresponding to the green sub-pixel is provided with green quantum dots. The red quantum dots and the green quantum dots are excited by white light emitted by the WOLED layer to emit high-purity red light and green light, respectively, and then filtered by the color filter film to be emitted. Thus, the OLED display has higher color saturation, which effectively broadens color gamut and can fully utilize the short-wavelength light. | 2020-01-23 |
20200027929 | DISPLAY APPARATUS WITH TOUCH SENSOR - A display apparatus includes a substrate having active and non-active areas; data lines and gate lines on the substrate; a driving line in the non-active area; a plurality of pixels connected to the data lines and the gate lines, each pixel including: a light emitting diode, and a driving transistor with the driving line under a cathode of the light emitting diode in the non-active area; a shield layer between the cathode and the driving line; an encapsulation layer on the cathode; a touch electrode on the encapsulation layer in the active area, and a touch line on the encapsulation layer to supply a touch signal to the touch electrode. The driving line is below the touch line in the non-active area. The encapsulation layer has a sloped surface, and the touch line is on the sloped surface such that the touch line has a corresponding slope. | 2020-01-23 |
20200027930 | Display Substrate and Manufacturing Method Thereof, Display Panel and Display Device - A display substrate and a fabrication method thereof, a display panel and a display device are provided. The display substrate includes pixels. Each of the pixels includes sub-pixels that emit light of different colors, each of the sub-pixels includes a light emitting element, and at least one of the sub-pixels further includes a color filter. The color filter of the at least one of the sub-pixels covers a portion of a light emitting region of the light emitting element of the at least one of the sub-pixels, and a color of the color filter of the at least one of the sub-pixels is the same as a color of light emitted by the light emitting element of the at least one of the sub-pixels. | 2020-01-23 |
20200027931 | Hybrid Wearable Organic Light Emitting Diode (OLED) Illumination Devices - Embodiments of the disclosed subject matter provide a wearable device that includes an organic light emitting diode (OLED) light source to output light having one peak wavelength from a single OLED emissive layer, and a first barrier layer that is disposed over or between the single OLED emissive layer and one or more down-conversion layers. One or more regions of the single OLED emissive layer are independently switchable and controllable so that the wearable device is configurable to output a plurality of wavelengths of light. One of the plurality of wavelengths of light that is output is near infrared light. | 2020-01-23 |
20200027932 | HEAD MOUNTED DISPLAY DEVICE AND DISPLAY PANEL INCLUDED THEREIN - A head mounted display device comprises a display panel comprising first to third subpixels defined at a substrate, a reflection plate provided in the first, second and third subpixels, first electrodes vertically spaced apart from a lower surface of the reflection plate by a first distance, a second distance and a third distance at the first, second and third subpixels, respectively, a white organic stack on the first electrodes at the first, second and third subpixels, a second electrode on the white organic stack, and a first color filter on the second electrode at the third subpixel to transmit light having a long wavelength. | 2020-01-23 |
20200027933 | DISPLAY DEVICE - A display device includes a substrate having a display area and a non-display area located at an outer periphery of the display area; a transistor layer disposed on the substrate; a plurality of partition walls disposed on the transistor layer in the display area; a light emitting element disposed between the partition walls; and a spacer configured to be disposed in the non-display area of the substrate, wherein the spacer may include a spacer body disposed on the same layer as the partition walls and on at least a portion of the transistor layer. | 2020-01-23 |
20200027934 | ORGANIC EL DEVICE - The present invention provides an organic EL device that can ensure safety by automatic light emission of afterglow illumination even when the power is shut off due to a power failure, turning-off, or the like. The organic EL device of the present invention includes: a substrate; an organic EL element part; and a charge storage part, wherein the organic EL element part is disposed on one surface of the substrate, the charge storage part is disposed on the organic EL element part, the organic EL element part includes a pair of electrodes and an organic EL layer, and the organic EL layer is sealed inside so as to be shielded from the outside air by any of the substrate, the pair of electrodes of the organic EL element part, and the charge storage part. | 2020-01-23 |
20200027935 | DISPLAY APPARATUS AND METHOD OF MANUFACTURING THE SAME - A display apparatus includes a base substrate, a thin film transistor layer on the base substrate, an insulation layer on the thin film transistor layer, a first electrode on the insulation layer and in a light emitting area, a pixel defining layer having an opening that has a size and a shape substantially same as that of the first electrode, and on the insulation layer, a light emitting layer on the first electrode, and a second electrode on the light emitting layer. | 2020-01-23 |
20200027936 | DISPLAY PANEL, MANUFACTURE METHOD THEREOF AND DISPLAY DEVICE - A display panel is provided, which includes a substrate, multiple light emitting structures arranged in an array on the substrate, a blocking structure at least arranged in a peripheral region of the substrate, and a cathode layer arranged on the multiple light emitting structures and the blocking structure. The cathode layer is discontinuous at a location corresponding to the blocking structure. | 2020-01-23 |
20200027937 | LIGHT-EMITTING DEVICE AND ELECTRONIC APPARATUS - A light-emitting device includes a display unit including a light-emitting portion and a non-light-emitting portion disposed around the light-emitting portion, and a driving line that is disposed in the display unit. The shorter a part of the driving line disposed in the light-emitting portion is, the longer a part of the driving line disposed in the non-light-emitting portion is. | 2020-01-23 |
20200027938 | PIXEL CIRCUIT, MANUFACTURING METHOD THEREOF, AND DISPLAY DEVICE - A pixel circuit includes a substrate, and a first thin film transistor and a second transistor which are disposed on the substrate. The first thin film transistor is in a top-gate structure, and the second thin film transistor is in a bottom-gate structure; a first electrode of the first thin film transistor is electrically connected with a gate electrode of the second thin film transistor, and the first electrode of the first thin film transistor and the gate electrode of the second thin film transistor are in a same layer on the substrate. The pixel circuit can have a relatively high switch speed and a relatively large driving current, a manufacturing method is easily realized and a process cost is relatively low. | 2020-01-23 |
20200027939 | PIXEL AND ORGANIC LIGHT EMITTING DISPLAY DEVICE INCLUDING THE SAME - Provided is pixel including a first transistor including a first drain region electrically connected to a light emitting diode, a first gate electrode, a first channel region overlapping the first gate electrode, and a first source region, a first sub-transistor including a first sub-gate electrode, a first sub-channel region overlapping the first sub-gate electrode, a first sub-drain region connected to the first gate electrode, and a first sub-source region, a second sub-transistor including a second sub-gate electrode, a second sub-channel region overlapping the second sub-gate electrode, a second sub-drain region connected to the first sub-source region, and a second sub-source region, and a shielding pattern overlapping the first sub-source region and the second sub-drain region and not overlapping the first sub-channel region, wherein a width of the first sub-channel region is greater than a width of the second sub-channel region. | 2020-01-23 |
20200027940 | DISPLAY PANEL, METHOD FOR MANUFACTURING THE SAME AND DISPLAY DEVICE - Provided are a display panel, a method for manufacturing the same, and a display device. The display panel includes: flexible substrate; multiple thin film transistor structures arranged in an array and on the flexible substrate; and an organic layer located on the multiple thin film transistor structures. Through holes are arranged between adjacent thin film transistor structures, each through hole penetrates the organic layer and the flexible substrate, and the organic layer covers a first surface of at least one thin film transistor structure far away from the flexible substrate, and side surfaces of the at least one thin film transistor structure proximate to the corresponding through holes. | 2020-01-23 |
20200027941 | ARRAY SUBSTRATE, DISPLAY PANEL, LIGHT-DETECTING METHOD THEREFOR AND METHOD FOR CONTROLLING THE SAME - An array substrate, a display panel, a light-detecting method for a display panel, and a method for controlling a display panel are provided. The array substrate includes a base substrate; a plurality of pixel regions arranged in an array on the base substrate, the pixel regions each including a light-emitting region; and a light-detecting circuit in at least one pixel region, the light-detecting circuit configured to detect light emitted from the light-emitting region of the at least one pixel region in which the light-detecting circuit is provided. | 2020-01-23 |
20200027942 | LIGHT-EMITTING DEVICE AND ELECTRONIC APPARATUS - The light-emitting device includes a display unit in which rectangular light-emitting pixels are arranged, and a light-shielding portion that defines a light-emitting region in the display unit and shields light in a region other than the light-emitting region of the display unit, and at least a part of a boundary between the light-emitting region and the light-shielding portion has a curved shape. | 2020-01-23 |
20200027943 | DISPLAY DEVICE HAVING A TRENCH PORTION - A display device includes a substrate including a trench portion. The substrate includes a display area and a peripheral area adjacent to the display area. The display area includes a first display area and a second display area arranged with the trench portion therebetween to display an image. A thin-film transistor and a display element are each arranged in the display area. A built-in circuit portion is over the peripheral area and is adjacent to the trench portion. A first wiring is in the first display area and a second wiring is in the second display area. A connecting wiring connects the first wiring to the second wiring and overlaps the built-in circuit portion. | 2020-01-23 |
20200027944 | Array Substrate And Method For Repairing Array Substrate - The present disclosure relates to an array substrate and a method for repairing an array substrate. The array substrate includes: a plurality of sub-pixels located on a substrate, each sub-pixel including a driving transistor and a light emitting device, a control electrode of the driving transistor being coupled to a data signal terminal and a first electrode of the driving transistor being coupled to a first voltage terminal, the light emitting device being connected in series between a second electrode of the driving transistor and a second voltage terminal, the sub-pixels including a first sub-pixel and a second sub-pixel adjacent to the first sub-pixel that emits light of the same color as that of the first sub-pixel; and a first repairing line insulated from and intersecting with a connection line between the light emitting device and the second electrode of the driving transistor of the first sub-pixel and a connection line between the light emitting device and the second electrode of the driving transistor of the second sub-pixel. | 2020-01-23 |
20200027945 | STRETCHABLE DISPLAY DEVICE - A stretchable display device comprises a lower substrate; a plurality of island substrates spaced apart from each other and disposed on the lower substrate; a plurality of pixels defined on the plurality of island substrates; a plurality of base polymers disposed between adjacent island substrates of the plurality of island substrates; and a plurality of conductive particles distributed in the base polymer and electrically connecting a plurality of pads disposed on the adjacent island substrates. | 2020-01-23 |
20200027946 | CAPACITOR STRUCTURES AND METHODS FOR FABRICATING THE SAME - A capacitor structure includes a first electrode plate disposed on a substrate, a first capacitor dielectric layer disposed on the first electrode plate, and a second electrode plate disposed on the first capacitor dielectric layer. A portion of the first electrode plate extends beyond an end of the second electrode plate to form a step. The capacitor structure also includes an etching stop layer, an inter-metal dielectric layer, a first via and a second via. The etching stop layer is disposed on the second electrode plate. The inter-metal dielectric layer covers the etching stop layer, the second electrode plate, the first capacitor dielectric layer and the first electrode plate. The first via penetrates through the inter-metal dielectric layer to contact the first electrode plate at the portion extending beyond the second electrode plate. The second via penetrates through the inter-metal dielectric layer to contact the second electrode plate. | 2020-01-23 |
20200027947 | SEMICONDUCTOR DEVICE - A semiconductor device includes a substrate, a bottom electrode on the substrate, a first support layer on the substrate next to a sidewall of the bottom electrode, a dielectric layer covering the sidewall and a top surface of the bottom electrode, and a top electrode on the dielectric layer. The bottom electrode includes a first part having a plurality of protrusions that protrude from a sidewall of the first part. The first part of the bottom electrode may be on the first support layer. | 2020-01-23 |
20200027948 | SEMICONDUCTOR DEVICE FOR HIGH VOLTAGE ISOLATION - A semiconductor device includes a substrate of a first conductivity type with relatively low impurity concentration; a first region of a second conductivity type with relatively low impurity concentration, =located in the substrate; a second region of the first conductivity type with relatively high impurity concentration, located in the substrate; first and second conductors, located on the first region and separated from each other by an isolator layer; and a third conductor, separated from the first and second conductors by the isolator layer, and located on the second region. The first conductor provides a drain terminal. The second conductor provides a source terminal. The third conductor provides a gate terminal. | 2020-01-23 |
20200027949 | Semiconductor Device with Compensation Structure - A switched-mode power supply includes a power semiconductor device that includes a semiconductor body comprising transistor cells and a drift zone between a drain layer and the transistor cells, the transistor cells comprising source zones, wherein the device exhibits a first output charge gradient when a voltage between the drain layer and the source zones of the transistor cells increases from a depletion voltage of the semiconductor device to a maximum drain/source voltage of the semiconductor device, wherein the device exhibits a second output charge gradient when a voltage between the drain layer and the source zones of the semiconductor device decreases from the maximum drain/source voltage to the depletion voltage of the semiconductor device, and wherein the semiconductor device is configured such that the first output charge gradient deviates by less than 5% from the second output charge gradient. | 2020-01-23 |
20200027950 | SEMICONDUCTOR DEVICE, METHOD OF MANUFACTURING THE SAME AND ELECTRONIC DEVICE INCLUDING THE SAME - A semiconductor device including a substrate, a first source/drain layer, a channel layer and a second source/drain layer stacked on the substrate in sequence, and a gate stack surrounding a periphery of the channel layer. The channel layer includes a semiconductor material causing an increased ON current and/or a reduced OFF current as compared to Si. | 2020-01-23 |
20200027951 | SEMICONDUCTOR STRUCTURE WITH INSULATING SUBSTRATE AND FABRICATING METHOD THEREOF - A semiconductor structure includes an insulating substrate, an engineered layer, a semiconductor layer, a gate structure, a source region, and a drain region. The engineered layer is surrounding the insulating substrate. The semiconductor layer including a first region and a second region is formed over the engineered layer. The gate structure is formed over the semiconductor layer. The source region and the drain region are formed in the semiconductor layer and located on both sides of the first gate structure. | 2020-01-23 |
20200027952 | METHOD FOR MANUFACTURING SEMICONDUCTOR DEVICE, AND POWER CONVERSION DEVICE - The semiconductor device includes: an epitaxial layer of a first conductivity type formed on a first principal surface of a semiconductor substrate; a first semiconductor region of the first conductivity type formed from an outermost surface to an inner portion of the epitaxial layer; and a third semiconductor region of a second conductivity type formed from a bottom surface of the first semiconductor region to an inner portion of the semiconductor substrate. The method includes: (a) polishing a second principal surface opposite to the first principal surface of the semiconductor substrate above which at least a source region, a drain region, and a gate electrode are formed to thin the substrate; and (b) ion-implanting impurities of the second conductivity type from the second principal surface of the polished semiconductor substrate to form the third semiconductor region. | 2020-01-23 |
20200027953 | SCHOTTKY DIODE WITH HIGH BREAKDOWN VOLTAGE AND SURGE CURRENT CAPABILITY USING DOUBLE P-TYPE EPITAXIAL LAYERS - A method for manufacturing a Silicon Carbide (SiC) Schottky diode may include steps of providing a substrate; forming a first epitaxial layer with a first conductivity type on top of the substrate; forming a second epitaxial layer with a second conductivity type on top of the first epitaxial layer; forming a third epitaxial layer with the second conductivity type on top of the second epitaxial layer; patterning and etching the second and third epitaxial layers to form a plurality of trenches; depositing a first ohmic contact metal on a backside of the substrate; forming a second ohmic contact metal on top of the second epitaxial layer; forming a Schottky contact metal at a bottom portion of each trench; and forming a pad electrode on top of the Schottky contact metal. | 2020-01-23 |
20200027954 | SiC-SOI DEVICE AND MANUFACTURING METHOD THEREOF - The object of the present invention is to increase the breakdown voltage without thickening an SOI layer in a wafer-bonded dielectric isolated structure. A device region of a SiC-SOI device includes: a first trench continuously or intermittently surrounding an n | 2020-01-23 |
20200027955 | OXIDE SEMICONDUCTOR AND SEMICONDUCTOR DEVICE - Provided are an oxide semiconductor excellent in transparency, mobility, and weatherability, etc., and a semiconductor device having the oxide semiconductor, a p-type semiconductor being realizable in the oxide semiconductor. The oxide semiconductor consists of a composite oxide, which has a crystal structure including a pyrochlore structure, containing at least one or more kinds of elements selected from Nb and Ta, and containing Sn element, and its holes become charge carriers by the condition that Sn | 2020-01-23 |
20200027956 | SEMICONDUCTOR DEVICE - A current collapse characteristic is sufficiently suppressed. After forming a large opening (first opening) passing through both of a TEOS oxide layer | 2020-01-23 |
20200027957 | SEMICONDUCTOR DEVICE - A semiconductor device, includes: a first semiconductor chip including a first semiconductor substrate; and a second semiconductor chip including a second semiconductor substrate, wherein the first semiconductor substrate has a first substrate main surface and a first substrate back surface facing opposite directions in a first direction, and includes a first region and a second region disposed on the first substrate main surface, wherein the first semiconductor chip includes: a first MOSFET of a first type structure formed to include the first region; and a control circuit formed to include the second region, wherein the second semiconductor chip includes a second MOSFET of a second type structure formed to include the second semiconductor substrate, and wherein the second type structure is different from the first type structure. | 2020-01-23 |
20200027958 | ACTIVE MATRIX SUBSTRATE AND LIQUID CRYSTAL DISPLAY PANEL - An active matrix substrate according to an embodiment of the present invention includes a plurality of thin film transistors supported on a substrate and an inorganic insulating layer covering the plurality of thin film transistors. Each thin film transistor includes a gate electrode, an oxide semiconductor layer, a gate insulating layer, a source electrode, and a drain electrode. At least one of the gate insulating layer and the inorganic insulating layer is an insulating layer stack having a multilayer structure including a silicon oxide layer and a silicon nitride layer. The insulating layer stack further includes an intermediate layer disposed between the silicon oxide layer and the silicon nitride layer, the intermediate layer having a refractive index n | 2020-01-23 |
20200027959 | TRANSISTOR STRUCTURES WITH REDUCED PARASITIC CAPACITANCE AND IMPROVED JUNCTION SHARPNESS - Nanosheet transistor structures with reduced parasitic capacitance and improved junction sharpness generally include a bilayer spacer adjacent a dummy gate disposed on a nanosheet stack. The bilayer spacer includes an inner spacer layer on sidewalls of the gate and a sacrificial layer on the inner spacer layer. The sacrificial layer can be laterally trimmed to bring the in situ doped source/drain regions closer to the channel, which improves junction sharpness. Additionally, the sacrificial spacer layer can be later removed during the process for forming the transistor so as to form an airgap spacer adjacent the gate, which minimizes parasitic capacitance. | 2020-01-23 |
20200027960 | SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING THE SAME - In a method for manufacturing a semiconductor device, a gate structure is formed over a channel layer and an isolation insulating layer. A first sidewall spacer layer is formed on a side surface of the gate structure. A sacrificial layer is formed so that an upper portion of the gate structure with the first sidewall spacer layer is exposed from the sacrificial layer and a bottom portion of the gate structure with the first sidewall spacer layer is embedded in the first sacrificial layer. A space is formed between the bottom portion of the gate structure and the sacrificial layer by removing at least part of the first sidewall spacer layer. After the first sidewall spacer layer is removed, an air gap is formed between the bottom portion of the gate structure and the sacrificial layer by forming a second sidewall spacer layer over the gate structure. | 2020-01-23 |
20200027961 | METAL OXIDE, FIELD-EFFECT TRANSISTOR, AND METHOD FOR PRODUCING THE SAME - Method for producing field-effect transistor including source electrode and drain electrode, gate electrode, active layer, and gate insulating layer, the method including etching the gate insulating layer, wherein the gate insulating layer is metal oxide including A-element and at least one selected from B-element and C-element, the A-element is at least one selected from Sc, Y, Ln (lanthanoid), Sb, Bi, and Te, the B-element is at least one selected from Ga, Ti, Zr, and Hf, the C-element is at least one selected from Group 2 elements in periodic table, etching solution A is used when at least one selected from the source electrode and the drain electrode, the gate electrode, and the active layer is formed, and etching solution B that is etching solution having same type as the etching solution A is used when the gate insulating layer is etched. | 2020-01-23 |
20200027963 | Semiconductor Device and Manufacturing Method Thereof - A semiconductor device includes a substrate, at least one active semiconductor fin, at least one first dummy semiconductor fin, and at least one second dummy semiconductor fin. The active semiconductor fin is disposed on the substrate. The first dummy semiconductor fin is disposed on the substrate. The second dummy semiconductor fin is disposed on the substrate and between the active semiconductor fin and the first dummy semiconductor fin. A top surface of the first dummy semiconductor fin and a top surface of the second dummy semiconductor fin are curved in different directions. | 2020-01-23 |
20200027964 | GATE STRUCTURE AND METHODS THEREOF - A method and structure providing a high-voltage transistor (HVT) including a gate dielectric, where at least part of the gate dielectric is provided within a trench disposed within a substrate. In some aspects, a gate oxide thickness may be controlled by way of a trench depth. By providing the HVT with a gate dielectric formed within a trench, embodiments of the present disclosure provide for the top gate stack surface of the HVT and the top gate stack surface of a low-voltage transistor (LVT), formed on the same substrate, to be substantially co-planar with each other, while providing a thick gate oxide for the HVTs. Further, because the top gate stack surface of HVT and the top gate stack surface of the LVT are substantially co-planar with each other, over polishing of the HVT gate stack can be avoided. | 2020-01-23 |
20200027965 | TRENCH CONTACT STRUCTURES FOR ADVANCED INTEGRATED CIRCUIT STRUCTURE FABRICATION - Embodiments of the disclosure are in the field of advanced integrated circuit structure fabrication and, in particular, 10 nanometer node and smaller integrated circuit structure fabrication and the resulting structures. In an example, an integrated circuit structure includes a fin. A gate dielectric layer is over the top of the fin and laterally adjacent the sidewalls of the fin. A gate electrode is over the gate dielectric layer over the top of the fin and laterally adjacent the sidewalls of the fin. First and second semiconductor source or drain regions are adjacent the first and second sides of the gate electrode, respectively. First and second trench contact structures are over the first and second semiconductor source or drain regions, respectively, the first and second trench contact structures both comprising a U-shaped metal layer and a T-shaped metal layer on and over the entirety of the U-shaped metal layer. | 2020-01-23 |
20200027966 | SEMICONDUCTOR DEVICE AND MANUFACTURE THEREOF - A semiconductor device and its manufacturing method are presented. The manufacturing method includes providing a semiconductor structure comprising a substrate, at least one source region on the substrate, an interlayer dielectric layer covering a portion of the source region and having a cavity on the source region, and a pseudo gate insulation layer at the bottom of the cavity covering a portion of the source region; forming a barrier layer in the cavity; forming a loss reduction region in the interlayer dielectric layer by conducting an ion implantation process comprising silicon ion or carbon ion; removing the barrier layer; removing the pseudo gate insulation layer to expose a portion of the source region; and forming a gate structure on the exposed portion of the source region. This inventive concept reduces the loss of the interlayer dielectric layer, thus reduces the height loss of the gate electrode. | 2020-01-23 |
20200027967 | REPLACEMENT METAL GATE STRUCTURES - Replacement metal gate structures with improved chamfered workfunction metal and self-aligned contact and methods of manufacture are provided. The method includes forming a replacement metal gate structure in a dielectric material. The replacement metal gate structure is formed with a lower spacer and an upper spacer above the lower spacer. The upper spacer having material is different than material of the lower spacer. The method further includes forming a self-aligned contact adjacent to the replacement metal gate structure by patterning an opening within the dielectric material and filling the opening with contact material. The upper spacer prevents shorting with the contact material. | 2020-01-23 |
20200027968 | SEMICONDUCTOR POWER DEVICE AND MANUFACTURING METHOD THEREOF - A semiconductor power device and a manufacturing method thereof are provided. In the manufacturing method, before the self-aligned silicide process is performed, a gate stacked structure and a spacer are formed on a semiconductor layer having a body region and a source region. The spacer defines a portion of the source region for forming a silicide layer. Subsequently, the self-aligned silicide process is performed with the gate stacked structure and the spacer functioning as a mask to form the silicide layer at the defined portion of the source region. Thereafter, an interconnection structure including an interlayer dielectric layer and a source conductive layer is formed on the semiconductor layer. The source conductive layer is electrically connected to the source region. The silicide layer extends toward the gate stacked structure from a position under the source conductive layer to another position under the interlayer dielectric layer. | 2020-01-23 |
20200027969 | Method for Producing a Semiconductor Component - A method for producing a semiconductor component includes: providing a semiconductor body having a first dopant of a first conductivity type; forming a first trench in the semiconductor body starting from a first side; filling the first trench with a semiconductor filler material; forming a superjunction structure by introducing a second dopant of a second conductivity type into the semiconductor body, the semiconductor filler material being doped with the second dopant; forming a second trench in the semiconductor body starting from the first side; and forming a trench structure in the second trench. | 2020-01-23 |
20200027970 | FinFETs having Epitaxial Capping Layer on Fin and Methods for Forming the Same - A FinFET and methods for forming a FinFET are disclosed. A method includes forming a semiconductor fin on a substrate, implanting the semiconductor fin with dopants, and forming a capping layer on a top surface and sidewalls of the semiconductor fin. The method further includes forming a dielectric on the capping layer, and forming a gate electrode on the dielectric. | 2020-01-23 |
20200027971 | FORM AND FABRICATION OF SEMICONDUCTOR-SUPERCONDUCTOR NANOWIRES AND QUANTUM DEVICES BASED THEREON - The disclosure relates to a quantum device and method of fabricating the same. The device comprises one or more semiconductor-superconductor nanowires, each comprising a length of semiconductor material and a coating of superconductor material coated on the semiconductor material. The nanowires may be formed over a substrate. In a first aspect at least some of the nanowires are full-shell nanowires with superconductor material being coated around a full perimeter of the semiconductor material along some or all of the length of the wire, wherein the device is operable to induce at least one Majorana zero mode, MZM, in one or more active ones of the full-shell nanowires. In a second aspect at least some of the nanowires are arranged vertically relative to the plane of the substrate in the finished device. | 2020-01-23 |
20200027972 | Semiconductor Quantum Dot Device And Method For Forming A Scalable Linear Array Of Quantum Dots - Scalable quantum dot devices and methods are described. An example quantum dot device may comprise one or more repeated cells of a repeating quantum dot structure. The repeated cells may be arranged as a linear array of quantum dots. A single repeated cell may comprise a plurality of quantum dots. The repeated cells may be configured to cause movement of a single electron between adjacent quantum dots. A repeated cell may also comprise a charge sensor for readout of the plurality of quantum dots. | 2020-01-23 |
20200027973 | INTEGRATED CIRCUIT HEAT DISSIPATION USING NANOSTRUCTURES - An approach for heat dissipation in integrated circuit devices is provided. A method includes forming an isolation layer on an electrically conductive feature of an integrated circuit device. The method also includes forming an electrically conductive layer on the isolation layer. The method additionally includes forming a plurality of nanowire structures on a surface of the electrically conductive layer | 2020-01-23 |
20200027974 | TUNNEL FIELD EFFECT TRANSISTOR HAVING ANISOTROPIC EFFECTIVE MASS CHANNEL - A tunnel field effect transistor (TFET) device includes a substrate, heavily doped source and drain regions disposed at opposite ends of a channel region forming a PiN or NiP structure, the channel region including a first substantially parallelogram portion having a first length defined along a longitudinal axis extending from the source region to the drain region and a second substantially parallelogram portion having a second length defined along the longitudinal axis larger than the first length, the TFET device having an effective channel length that is an average of the first and second lengths. The channel region includes a channel material with a first effective mass along a longitudinal axis extending from the source region to the drain region and a second effective mass along a lateral axis perpendicular to the longitudinal axis, the first effective mass being greater than the second effective mass. | 2020-01-23 |
20200027975 | SEMICONDUCTOR DEVICE - Provided is a low cost semiconductor device in which occurrence of chipping and a crack during dicing is suppressed. A nitride layer (silicon nitride layer) | 2020-01-23 |
20200027976 | SEMICONDUCTOR DEVICE AND METHOD FOR MANUFACTURING THE SAME - According to one embodiment, a semiconductor device includes first to third electrodes, first to third layers, and a first insulating layer. The first layer includes first to fifth partial regions. The first partial region is between the fourth and third partial regions. The second partial region is between the third and fifth partial regions. The first insulating layer includes first and second inter-layer regions. The second layer includes first and second intermediate regions. The first intermediate region is provided between the first partial region and the first inter-layer region. The second intermediate region is provided between the second partial region and the second inter-layer region. The third layer includes first to third nitride regions. The first inter-layer region is between the first intermediate region and the first nitride region. The second inter-layer region is between the second intermediate region and the second nitride region. | 2020-01-23 |
20200027977 | SEMICONDUCTOR DEVICE AND METHOD FOR MANUFACTURING THE SAME - According to one embodiment, a semiconductor device includes first to third electrodes, first to fifth layers, and an insulating portion. A position of the third electrode is between a position of the first electrode and a position of the second electrode. The first layer includes first to fifth partial regions. The first partial region is between the fourth and third partial regions. The second partial region is between the third and fifth partial regions. The second layer includes first and second semiconductor regions. The third layer is provided between the third partial region and the third electrode. The fourth layer is provided between the third partial region and the third layer. The fifth layer includes first and second intermediate regions. The third layer is provided between the first and second intermediate regions. The insulating portion includes a first insulating region provided between the third layer and the third electrode. | 2020-01-23 |
20200027979 | METHODS OF FORMING SPACERS ADJACENT GATE STRUCTURES OF A TRANSISTOR DEVICE - One illustrative method disclosed herein includes forming a low-k sidewall spacer adjacent opposing sidewalls of a gate structure, forming contact etch stop layers (CESLs) adjacent the low-k sidewall spacer in the source/drain regions of the transistor, and forming a first insulating material above the CESLs. In this example, the method also includes recessing the first insulating material so as to expose substantially vertically oriented portions of the CESLs, removing a portion of a lateral width of the substantially vertically oriented portions of the CESLs so as to form trimmed CESLs, and forming a high-k spacer on opposite sides of the gate structure, wherein at least a portion of the high-k spacer is positioned laterally adjacent the trimmed substantially vertically oriented portions of the trimmed CESLs. | 2020-01-23 |
20200027980 | TRENCH-GATE FIELD EFFECT TRANSISTOR WITH IMPROVED ELECTRICAL PERFORMANCES AND CORRESPONDING MANUFACTURING PROCESS - A field effect transistor has a semiconductor layer with a top surface extending in a horizontal plane, and an active area defined in which are trench gate regions, which extend in depth with respect to the top surface and have an insulating coating layer and a conductive inner layer, and source regions, adjacent to the trench gate regions so as to form a conductive channel extending vertically. The trench gate regions have a plurality of first gate regions, which extend in length in the form of stripes through the active area along a first direction of the horizontal plane, and moreover a plurality of second gate regions, which extend in length in the form of stripes through the same active area along a second direction of the horizontal plane, orthogonal to, and crossing, the first gate regions. In particular, the first gate regions and second gate regions cross in the active area, joining with a non-zero curvature radius. | 2020-01-23 |
20200027981 | FIN CUT LAST METHOD FOR FORMING A VERTICAL FINFET DEVICE - A fin cut last methodology for manufacturing a vertical FinFET includes forming a plurality of semiconductor fins over a substrate, forming shallow trench isolation between active fins and, following the formation of a functional gate of the active fins, using a selective etch to remove a sacrificial fin from within an isolation region. A further etching step can be used to remove a portion of the gate stack proximate to the sacrificial fin to create an isolation trench and a laterally-extending cavity within the isolation region that are back-filled with an isolation dielectric. | 2020-01-23 |
20200027982 | SEMICONDUCTOR DEVICES INCLUDING ELECTRICALLY CONDUCTIVE CONTACTS AND RELATED SYSTEMS AND METHODS - A semiconductor device comprises an array region, a dummy region, pillars of an electrically insulative material in the array region and the dummy region. The semiconductor device further comprises electrically conductive contacts between adjacent pillars of the electrically insulative material in the array region, another electrically insulative material between adjacent pillars of the electrically insulative material in the dummy region, an electrically conductive material over the conductive contacts in the array region and over the electrically insulative material in the dummy region, and an oxide between the electrically conductive material in the dummy region and the electrically insulative material in the dummy region. Related semiconductor devices, systems, and methods are also disclosed. | 2020-01-23 |
20200027983 | UNIFORM BOTTOM SPACER FOR VFET DEVICES - Vertical field effect transistor (VFET) structures and methods of fabrication include a bottom spacer having a uniform thickness. The bottom spacer includes a bilayer portion including a first layer formed of an oxide, for example, and a second layer formed of a nitride, for example, on the first layer, and a monolayer portion of a fourth layer of a nitride for example, immediately adjacent to and intermediate the fin and the bilayer portion. | 2020-01-23 |
20200027984 | VERTICAL FIELD-EFFECT TRANSISTOR INCLUDING A FIN HAVING SIDEWALLS WITH A TAPERED BOTTOM PROFILE - A method of forming a semiconductor structure includes forming at least one fin disposed over a substrate, wherein sidewalls of the at least one fin includes a first portion proximate a top surface of the substrate having a tapered profile and a second portion disposed above the first portion. The method also includes forming a bottom source/drain region surrounding at least part of the first portion of the sidewalls of the at least one fin having the tapered profile and forming a bottom spacer disposed over a top surface of the bottom source/drain region surrounding at least part of the second portion of the sidewalls of the at least one fin. The at least one fin provides a channel for a vertical field-effect transistor. | 2020-01-23 |
20200027985 | SEMICONDUCTOR DEVICE AND METHOD FOR FABRICATING THE SAME - A method for fabricating semiconductor device includes the steps of: providing a substrate having a first silicon layer, an insulating layer on the first silicon layer, and a second silicon layer on the insulating layer; forming a metal-oxide semiconductor (MOS) transistor on the substrate; forming an interlayer dielectric layer (ILD) on the MOS transistor; removing part of the ILD layer to form a first trench to expose the insulating layer; and performing a wet etching process through the first trench to remove part of the insulating layer for forming a first air gap under the MOS transistor. | 2020-01-23 |
20200027986 | FIN FIELD EFFECT TRANSISTORS HAVING LINERS BETWEEN DEVICE ISOLATION LAYERS AND ACTIVE AREAS OF THE DEVICE - An integrated circuit device includes a fin-type active area protruding from a substrate; a plurality of liners sequentially covering lower side walls of the fin-type active area; a device isolation layer covering the lower side walls of the fin-type active area with the plurality of liners between the device isolation layer and the fin-type active area; and a gate insulating layer extending to cover a channel region of the fin-type active area, the plurality of liners, and the device isolation layer, and including protrusions located on portions of the gate insulating layer which cover the plurality of liners. | 2020-01-23 |
20200027987 | GATE-ALL-AROUND FIN DEVICE - A gate-all around fin double diffused metal oxide semiconductor (DMOS) devices and methods of manufacture are disclosed. The method includes forming a plurality of fin structures from a substrate. The method further includes forming a well of a first conductivity type and a second conductivity type within the substrate and corresponding fin structures of the plurality of fin structures. The method further includes forming a source contact on an exposed portion of a first fin structure. The method further comprises forming drain contacts on exposed portions of adjacent fin structures to the first fin structure. The method further includes forming a gate structure in a dielectric fill material about the first fin structure and extending over the well of the first conductivity type. | 2020-01-23 |
20200027988 | STRUCTURE AND FORMATION METHOD OF SEMICONDUCTOR DEVICE STRUCTURE - Structures and formation methods of a semiconductor device structure are provided. The semiconductor device structure includes a fin structure over a semiconductor substrate. The semiconductor device structure also includes a gate stack covering a portion of the fin structure. The gate stack includes a first portion and a second portion adjacent to the fin structure, and the first portion is wider than the second portion. | 2020-01-23 |
20200027989 | RADIATION HARDENED THIN-FILM TRANSISTORS - A thin-film transistor comprises an annealed layer comprising crystalline zinc oxide. A passivation layer is adjacent to the thin-film transistor. The passivation layer has a thickness and material composition such that when a dose of radiation from a radiation source irradiates the thin-film transistor, a portion of the dose that includes an approximate maximum concentration of the dose is located within the annealed layer. The annealed layer has a thickness and threshold displacement energies after it has been annealed such that: a) a difference between a transfer characteristic value of the thin-film transistor before and after the dose is less than a first threshold; and b) a difference between a transistor output characteristic value of the thin-film before and after the dose is less than a second threshold. The thresholds are based on a desired performance of the thin-film transistor. | 2020-01-23 |
20200027990 | SEMICONDUCTOR DEVICES COMPRISING CHANNEL MATERIALS - A semiconductor device structure is disclosed. The semiconductor device structure includes a mesa extending above a substrate. The mesa has a channel region between a first side and second side of the mesa. A first gate is on a first side of the mesa, the first gate comprising a first gate insulator and a first gate conductor comprising graphene overlying the first gate insulator. The gate conductor may comprise graphene in one or more monolayers. Also disclosed are a method for fabricating the semiconductor device structure; an array of vertical transistor devices, including semiconductor devices having the structure disclosed; and a method for fabricating the array of vertical transistor devices. | 2020-01-23 |
20200027991 | TECHNIQUES FOR FORMING VERTICAL TRANSPORT FET - Techniques for reducing work function metal variability along the channel of VFET devices are provided. In one aspect, a method of forming a VTFET device includes: patterning fins in a wafer; forming bottom source/drains at a base of the fins and bottom spacers on the bottom source/drains; forming gate stacks over the fins including a gate conductor having a combination of work function metals including an outer layer and at least one inner layer of the work function metals; isotropically etching the work function metals which recesses the gate stacks with an outwardly downward sloping profile; isotropically etching the at least one inner layer while covering the outer layer of the work function metals to eliminate the outwardly downward sloping profile of the gate stacks; forming top spacers above the gate stacks; and forming top source and drains at tops of the fins. A VTFET device is also provided. | 2020-01-23 |
20200027992 | SEMICONDUCTOR DEVICE - A semiconductor device includes first active patterns on a PMOSFET section of a logic cell region of a substrate, second active patterns on an NMOSFET section of the logic cell region, third active patterns on a memory cell region of the substrate, fourth active patterns between the third active patterns, and a device isolation layer that fills a plurality of first trenches and a plurality of second trenches. Each of the first trenches is interposed between the first active patterns and between the second active patterns. Each of the second trenches is interposed between the fourth active patterns and between the third and fourth active patterns. Each of the third and fourth active patterns includes first and second semiconductor patterns that are vertically spaced apart from each other. Depths of the second trenches are greater than depths of the first trenches. | 2020-01-23 |
20200027993 | OXIDE SEMICONDUCTOR THIN-FILM AND THIN-FILM TRANSISTOR CONSISTED THEREOF - The present application discloses an oxide semiconductor thin-film and a thin-film transistor consisted thereof. The oxide semiconductor thin-film is fabricated by doping a certain amount of rare-earth oxide (RO) as light stabilizer to metal oxide (MO) semiconductor. The thin-film transistor comprising a gate electrode, a channel layer consisted by the oxide semiconductor thin-film, a source and drain electrode; the thin-film transistor employing etch-stop structure, a back-channel etch structure or a top-gate self-alignment structure. | 2020-01-23 |
20200027994 | NANOMETER SEMICONDUCTOR DEVICES HAVING HIGH-QUALITY EPITAXIAL LAYER - There are provided a nanometer semiconductor device with a high-quality epitaxial layer and a method of manufacturing the same. According to an embodiment, the semiconductor device may include: a substrate; at least one nanowire spaced apart from the substrate; at least one semiconductor layer, each formed around a periphery of respective one of the at least one nanowire to at least partially surround the corresponding nanowire, wherein the semiconductor layer(s) formed around the respective nanowire(s) are separated from each other; an isolation layer formed on the substrate, exposing the at least one semiconductor layer; and a gate stack formed on the isolation layer and intersecting the at least one semiconductor layer, wherein the gate stack includes a gate dielectric layer at least partially surrounding a periphery of respective one of the at least one semiconductor layer and a gate conductor layer. | 2020-01-23 |
20200027995 | NANOMETER SEMICONDUCTOR DEVICES HAVING HIGH-QUALITY EPITAXIAL LAYER - There are provided a nanometer semiconductor device with a high-quality epitaxial layer and a method of manufacturing the same. According to an embodiment, the semiconductor device may include: a substrate; at least one nanowire spaced apart from the substrate; at least one semiconductor layer, each formed around a periphery of respective one of the at least one nanowire to at least partially surround the corresponding nanowire, wherein the semiconductor layer(s) formed around the respective nanowire(s) are separated from each other; an isolation layer formed on the substrate, exposing the at least one semiconductor layer; and a gate stack formed on the isolation layer and intersecting the at least one semiconductor layer, wherein the gate stack includes a gate dielectric layer at least partially surrounding a periphery of respective one of the at least one semiconductor layer and a gate conductor layer. | 2020-01-23 |
20200027996 | SEMICONDUCTOR DEVICE AND A METHOD OF MANUFACTURING THE SAME - A memory cell, which is a nonvolatile memory cell, includes a gate dielectric film having charge storage layer capable of holding charges, and a memory gate electrode formed on the gate dielectric film. The charge storage layer includes an insulating film containing hafnium, silicon, and oxygen, an insertion layer formed on the insulating film and containing aluminum, and an insulating film formed on the insertion layer and containing hafnium, silicon, and oxygen. | 2020-01-23 |
20200027997 | BIDIRECTIONAL ZENER DIODE AND METHOD FOR MANUFACTURING BIDIRECTIONAL ZENER DIODE - A bidirectional Zener diode includes a substrate, a first conductivity type base region formed at a front surface portion of the substrate, a second conductivity type first impurity region formed at the base region, a second conductivity type second impurity region formed at the base region away from the first impurity region, an insulating layer formed on a front surface of the substrate, a first electrode film formed on the insulating layer and electrically connected to the first impurity region, and a second electrode film formed on the insulating layer and electrically connected to the second impurity region, and a first region formed on the insulating layer, the first region being sandwiched between the first electrode film and the second electrode film, and the first region including a portion having an aspect ratio of 1 or larger. | 2020-01-23 |
20200027998 | Method of Mounting an Electrical Component on a Base Part - A method of mounting an electrical component on a base part having an inclined support surface is provided, in which method a first wedge surface of a wedge element is arranged on the support surface and a lateral force is exerted on the wedge element so that the first wedge surface moves on the support surface until a second wedge surface of the wedge element remote from the support surface reaches a desired position, and wherein the electrical component is arranged on the second wedge surface. In this respect, a first fastening element of the wedge element is fixed to the base part and the lateral force is afterward no longer exerted. | 2020-01-23 |
20200027999 | MULTIJUNCTION SOLAR CELL AND SOLAR CELL ASSEMBLIES FOR SPACE APPLICATIONS - A multijunction solar cell having an upper first solar subcell composed of a semiconductor material having a first band gap; a second solar subcell adjacent to said first solar subcell and composed of a semiconductor material having a second band gap smaller than the first band gap and being lattice matched with the upper first solar subcell; a third solar subcell adjacent to said second solar subcell and composed of a semiconductor material having a third band gap smaller than the second band gap and being lattice matched with the second solar subcell; a fourth solar subcell adjacent to and lattice mismatched from said third solar subcell and composed of germanium grown on a growth substrate. In some embodiments of a five junction solar cell, the growth substrate forms a bottom solar subcell and is composed of germanium. | 2020-01-23 |
20200028000 | MICROSTRUCTURE ENHANCED ABSORPTION PHOTOSENSITIVE DEVICES - Lateral and vertical microstructure enhanced photodetectors and avalanche photodetectors are monolithically integrated with CMOS/BiCMOS ASICs and can also be integrated with laser devices using fluidic assembly techniques. Photodetectors can be configured in a vertical PIN arrangement or lateral metal-semiconductor-metal arrangement where electrodes are in an inter-digitated pattern. Microstructures, such as holes and protrusions, can improve quantum efficiency in silicon, germanium and III-V materials and can also reduce avalanche voltages for avalanche photodiodes. Applications include optical communications within and between datacenters, telecommunications, LIDAR, and free space data communication. | 2020-01-23 |
20200028001 | LOW POWER OPTICAL SENSOR FOR CONSUMER, INDUSTRIAL, AND AUTOMOTIVE APPLICATIONS - An optical sensor includes a light-emitter device formed in a body of solid-state material with wide band gap having a surface. The light-emitter device includes a cathode region having a first conductivity type and an anode region having a second conductivity type. The anode region extends into the cathode region from the surface of the body. The anode region and the cathode region define a junction, and the cathode region has, near the junction, a peak defectiveness area accommodating vacancies in the crystalline structure due to non-bound ions or atoms of Group IV or VIII of the periodic table, which may include carbon, silicon, helium, argon, or neon. The vacancies are at a higher concentration with respect to mean values of vacancies in the anode region and in the cathode region. For example, the vacancies in the peak defectiveness area have a concentration of at least 10 | 2020-01-23 |
20200028002 | SILICON-BASED VISIBLE AND NEAR-INFRARED OPTOELECTRIC DEVICES - In one aspect, the present invention provides a silicon photodetector having a surface layer that is doped with sulfur inclusions with an average concentration in a range of about 0.5 atom percent to about 1.5 atom percent. The surface layer forms a diode junction with an underlying portion of the substrate. A plurality of electrical contacts allow application of a reverse bias voltage to the junction in order to facilitate generation of an electrical signal, e.g., a photocurrent, in response to irradiation of the surface layer. The photodetector exhibits a responsivity greater than about 1 A/W for incident wavelengths in a range of about 250 nm to about 1050 nm, and a responsivity greater than about 0.1 A/W for longer wavelengths, e.g., up to about 3.5 microns. | 2020-01-23 |
20200028003 | SOLAR CELL, SOLAR CELL MODULE, AND SOLAR CELL MANUFACTURING METHOD - A solar cell includes a crystal substrate which has a major surface on a light reception side provided with a first texture surface and a major surface on a non-light reception side provided with a second texture surface. The second texture surface occupies 20% or more of the area of the major surface on the non-light reception side. | 2020-01-23 |
20200028004 | PHOTOELECTRIC CONVERTER, PHOTOELECTRIC CONVERSION MODULE, AND ELECTRONIC INSTRUMENT - A photoelectric converter including a crystalline silicon substrate having a light receiving surface including a smooth section and a rough surface section having surface roughness greater than the surface roughness of the smooth section and a light transmissive inorganic film so provided as to overlap with the smooth section and the rough surface section, and the film thickness t | 2020-01-23 |
20200028005 | Bifacial Solar Modules Incorporating Effectively Transparent Contacts - Bifacial solar cells have been gaining momentum due to their promise of reducing the price of photovoltaic generated electricity by increasing power output. In addition to front side illumination, bifacial solar cells can also accept photons incident on the rear side. In many embodiments, increased power output values of up to and around 50% can be achieved. In some circumstances, other values can be achieved. For example, ˜40-70% under cloudy conditions and between ˜13-35% under sunny conditions, depending on the height of the ground clearance, can be achieved. Other factors such as but not limited to the (spectral) albedo of the surroundings as well as the geometry in which the cells are mounted can strongly influence the power output. As can readily be appreciated, the exact amount of increased power output can vary widely depending on the configuration and operating conditions of the bifacial solar cell. | 2020-01-23 |
20200028006 | ALUMINUM PASTE USED FOR LOCAL BACK SURFACE FIELD SOLAR CELL AND LOCAL BACK SURFACE FIELD SOLAR CELL USING THE ALUMINUM PASTE - An aluminum paste used for local back surface field solar cells is introduced. The aluminum paste which has large-sized aluminum powder; an organic vehicle including a solvent and a resin or cellulose; wherein a ratio of a median particle size (μm) to an oxygen content (%) (median particle size (μm)/oxygen content (%)) of the large-sized aluminum powder ranges from 10 to 15. The aluminum paste used for local back surface field solar cell and the local back surface field solar cell using the aluminum paste eliminate the powder extraction of aluminum powder, the aluminum beads, the adhesion of the aluminum layer to the SiN | 2020-01-23 |
20200028007 | Optically Activated Transistor, Switch, and Photodiode - An optically activated device that includes an active material on a substrate with two electrodes electrically connected to the active material, the active material conducts current in the presence of light and does not conduct appreciable current in the absence of light. The optically activated device functions as a photodiode, a switch, and an optically gated transistor. The optically activated device conducts current in the presences of light. The active material may be layers of germanium selenide and germanium selenide and an element. Germanium selenide may be sputtered onto a substrate to create layers of material separated by layers of co-sputtered germanium selenide with the element. The active material may be deposited onto a flexible substrate. | 2020-01-23 |
20200028008 | METAL-CONTACT-FREE PHOTODETECTOR - A Ge-on-Si photodetector constructed without doping or contacting Germanium by metal is described. Despite the simplified fabrication process, the device has responsivity of 1.24 A/W, corresponding to 99.2% quantum efficiency. Dark current is 40 nA at −4 V reverse bias. 3-dB bandwidth is 30 GHz. | 2020-01-23 |
20200028009 | SOLAR BATTERY - To provide a solar battery that is not affected or substantially not easily affected by an irradiation history of UV light, and thus does not or substantially does not suffer degradation of service life. The above-described problem is solved by a solar battery ( | 2020-01-23 |