04th week of 2015 patent applcation highlights part 14 |
Patent application number | Title | Published |
20150021584 | Integrated Touch Screen - In one embodiment, an apparatus includes a display stack for a touch-sensitive screen. The display stack comprises a plurality of layers in which a top layer comprises a substantially transparent cover layer. The display stack is configured to display a color image. The apparatus also includes a touch sensor provided within the display stack. The touch sensor comprises a plurality of first conductive electrodes contacting a layer of a subset of the plurality of layers of the display stack. The subset of the plurality of layers is below the substantially transparent cover layer. The touch sensor also includes a plurality of second conductive electrodes contacting a layer of the subset of the plurality of layers. | 2015-01-22 |
20150021585 | COMPOSITION FOR ORGANIC LIGHT-EMITTING DIODE, ORGANIC LIGHT-EMITTING LAYER INCLUDING SAME, AND ORGANIC LIGHT-EMITTING DIODE - Provided is a composition for an organic light emitting diode comprising a compound for an organic optoelectric device represented by Chemical Formula S-1; and a compound for an organic optoelectric device represented by Chemical Formula X-1, and an organic emission layer and organic light emitting diode. | 2015-01-22 |
20150021586 | DEUTERATED COMPOUNDS FOR ELECTRONIC APPLICATIONS - This invention relates to deuterated aryl-anthracene compounds that are useful in electronic applications. It also relates to electronic devices in which the active layer includes such a deuterated compound. | 2015-01-22 |
20150021587 | COMPOSITION FOR ORGANIC ELECTROLUMINESCENT ELEMENTS ANDORGANIC ELECTROLUMINESCENT ELEMENT - The objection of invention is to provide a composition for organic electroluminescent element having a smaller amount of foreign substance. The invention is a composition for organic electroluminescent element, which is for forming at least one layer selected from the group consisting of a light emitting layer, a hole injection layer and a hole transportation layer, wherein the composition comprises an aromatic amine polymer having a weight average molecular weight of 3,000 to 1,000,000 and a solvent, and a Zn concentration in the composition is less than 0.5 ppm. | 2015-01-22 |
20150021588 | LIGHT EMITTING DEVICE AND METHOD OF MANUFACTURING THE SAME - A high-quality light emitting device is provided which has a long-lasting light emitting element free from the problems of conventional ones because of a structure that allows less degradation, and a method of manufacturing the light emitting device is provided. After a bank is formed, an exposed anode surface is wiped using a PVA (polyvinyl alcohol)-based porous substance or the like to level the surface and remove dusts from the surface. An insulating film is formed between an interlayer insulating film on a TFT and the anode. Alternatively, plasma treatment is performed on the surface of the interlayer insulating film on the TFT for surface modification. | 2015-01-22 |
20150021589 | ORGANIC LIGHT-EMITTING DISPLAY DEVICE - Embodiments may disclose an organic light-emitting display device including a first substrate including a pixel area emitting light in a first direction, and a transmittance area that is adjacent to the pixel area and transmits external light; a second substrate facing the first substrate and encapsulating a pixel on the first substrate; an optical pattern array on the first substrate or the second substrate to correspond to the transmittance area, the optical pattern array being configured to transmit or block external light depending on the transmittance area according to a coded pattern; and a sensor array corresponding to the optical pattern array, the sensor array being arranged in a second direction that is opposite to the first direction in which the light is emitted, the second array receiving the external light passing through the optical pattern array. | 2015-01-22 |
20150021590 | ORGANIC ELECTROLUMINESCENT MATERIALS AND DEVICES - Organometallic compounds comprising an imidazole carbene ligand having a N-containing ring fused to the imidazole ring are provided. In particular, the N-containing ring fused to the imidazole ring may contain one nitrogen atom or more than one nitrogen atom. These compounds may demonstrate high photoluminescent (PL) efficiency, Gaussian emission spectra, and/or short excited state lifetimes. These materials may be especially useful as blue phosphorescent emitters. | 2015-01-22 |
20150021591 | THIN FILM TRANSISTOR AND THIN FILM TRANSISTOR ARRAY PANEL INCLUDING THE SAME - A thin film transistor is disclosed. In one aspect, the thin film transistor includes a substrate, a semiconductor layer formed on the substrate, and a first gate electrode substantially overlapping the semiconductor layer with a gate insulating layer interposed therebetween. The thin film transistor also includes a second gate electrode substantially overlapping the first gate electrode with an interlayer insulating layer interposed therebetween, and a source electrode and a drain electrode electrically connected to the semiconductor layer, wherein the first gate electrode is electrically connected to the second gate electrode. | 2015-01-22 |
20150021592 | DISPLAY SUBSTRATE INCLUDING A THIN FILM TRANSISTOR AND METHOD OF MANUFACTURING THE SAME - A method of manufacturing a display substrate includes forming a gate electrode on a base substrate, forming an active pattern which includes an oxide semiconductor and overlaps with the gate electrode, forming an etch stopper which partially covers the active pattern, and performing a plasma treatment process to promote a reduction reaction to portions of the active pattern exposed by the etch stopper, thereby forming a source electrode and a drain electrode. | 2015-01-22 |
20150021593 | OXIDE SEMICONDUCTOR FILM, METHOD FOR FORMING OXIDE SEMICONDUCTOR FILM, AND SEMICONDUCTOR DEVICE - A crystalline oxide semiconductor film and a semiconductor device including the oxide semiconductor film are provided. One embodiment of the present invention is an oxide semiconductor film including a plurality of flat-plate particles each having a structure in which layers including a gallium atom, a zinc atom, and an oxygen atom are provided over and under a layer including an indium atom and an oxygen atom. In the semiconductor film, the plurality of flat-plate particles face in random directions, and a crystal boundary is not observed using a transmission electron microscope. | 2015-01-22 |
20150021594 | RADIATION IMAGE-PICKUP DEVICE AND RADIATION IMAGE-PICKUP DISPLAY SYSTEM - A radiation image-pickup device includes: a plurality of pixels configured to generate signal charge based on radiation; and a field effect transistor used to read out the signal charge from the plurality of pixels. The transistor includes a first silicon oxide film, a semiconductor layer, and a second silicon oxide film laminated in order from a substrate side, the semiconductor layer including an active layer, and a first gate electrode disposed to face the semiconductor layer, with the first or the second silicon oxide film interposed therebetween, and the first or the second silicon oxide film or both include an impurity element. | 2015-01-22 |
20150021595 | ELECTRO STATIC DISCHARGE PROTECTION CIRCUIT AND ELECTRONIC DEVICE HAVING THE SAME - An electro static discharge (ESD) protection circuit including a signal transmission line coupled to an external input terminal, the ESD protection circuit including: a first power line coupled to a high voltage power supply; a second power line coupled to a low voltage power supply; a plurality of first oxide thin film transistors coupled in parallel between the first power line and the signal transmission line, the first oxide thin film transistors being diode-connected; and a plurality of second oxide thin film transistors coupled in parallel between the signal transmission line and the second power line, the second oxide thin film transistors being diode-connected. | 2015-01-22 |
20150021596 | Semiconductor Device - A semiconductor device is provided with a first oxide semiconductor film over an insulating surface; a second oxide semiconductor film over the first oxide semiconductor film; a third oxide semiconductor film in contact with a top surface of the insulating surface, a side surface of the first oxide semiconductor film, and side and top surfaces of the second oxide semiconductor film; a gate insulating film over the third oxide semiconductor film; and a gate electrode in contact with the gate insulating film and faces the top and side surfaces a of the second oxide semiconductor film. A thickness of the first oxide semiconductor film is larger than a sum of a thickness of the third oxide semiconductor film and a thickness of the gate insulating film, and the difference is larger than or equal to 20 nm. | 2015-01-22 |
20150021597 | Photopatternable Materials and Related Electronic Devices and Methods - The present polymeric materials can be patterned with relatively low photo-exposure energies and are thermally stable, mechanically robust, resist water penetration, and show good adhesion to metal oxides, metals, metal alloys, as well as organic materials. In addition, these polymeric materials can be solution-processed (e.g., by spin-coating), and can exhibit good chemical (e.g., solvent and etchant) resistance in the cured form. | 2015-01-22 |
20150021598 | SOLID-STATE IMAGING DEVICE AND SEMICONDUCTOR DISPLAY DEVICE - A solid-state imaging device increases the SN ratio of a signal even when external light intensity is low. The solid-state imaging device includes a sensor circuit that includes a light-receiving element, a first transistor that controls connection between a first wiring and a node in which the amount of accumulated charge is determined by the amount of exposure to the light-receiving element, a second transistor whose on or off state is selected in accordance with the potential of the node, and a third transistor that controls connection between a second wiring and a third wiring together with the second transistor; a central processing unit that selects a first driving method or a second driving method in accordance with external light intensity; and a controller that controls a potential supplied to the gate of the first transistor in accordance with the first driving method or the second driving method. | 2015-01-22 |
20150021599 | BARRIER MATERIALS FOR DISPLAY DEVICES - Described herein are apparatus comprising one or more silicon-containing layers and a metal oxide layer. Also described herein are methods for forming one or more silicon-containing layers to be used, for example, as passivation layers in a display device. In one particular aspect, the apparatus comprises a transparent metal oxide layer, a silicon oxide layer and a silicon nitride layer. In this or other aspects, the apparatus is deposited at a temperature of 350° C. or below. The silicon-containing layers described herein comprise one or more of the following properties: a density of about 1.9 g/cm | 2015-01-22 |
20150021600 | DISPLAY DEVICE AND ELECTRONIC DEVICE INCLUDING THE SAME - One embodiment of the present invention provides a highly reliably display device in which a high mobility is achieved in an oxide semiconductor. A first oxide component is formed over a base component. Crystal growth proceeds from a surface toward an inside of the first oxide component by a first heat treatment, so that a first oxide crystal component is formed in contact with at least part of the base component. A second oxide component is formed over the first oxide crystal component. Crystal growth is performed by a second heat treatment using the first oxide crystal component as a seed, so that a second oxide crystal component is formed. Thus, a stacked oxide material is formed. A transistor with a high mobility is formed using the stacked oxide material and a driver circuit is formed using the transistor. | 2015-01-22 |
20150021601 | SEMICONDUCTOR DEVICE AND ELECTRONIC DEVICE - An object is to improve the drive capability of a semiconductor device. The semiconductor device includes a first transistor and a second transistor. A first terminal of the first transistor is electrically connected to a first wiring. A second terminal of the first transistor is electrically connected to a second wiring. A gate of the second transistor is electrically connected to a third wiring. A first terminal of the second transistor is electrically connected to the third wiring. A second terminal of the second transistor is electrically connected to a gate of the first transistor. A channel region is formed using an oxide semiconductor layer in each of the first transistor and the second transistor. The off-state current of each of the first transistor and the second transistor per channel width of 1 μm is 1 aA or less. | 2015-01-22 |
20150021602 | THIN FILM TRANSISTOR DISPLAY PANEL AND MANUFACTURING METHOD THEREOF - A thin film transistor array panel and a manufacturing method capable of forming an insulating layer made of different materials for a portion contacting an oxide semiconductor and a second portion without an additional process. Source and drain electrodes of the thin film transistor each include a lower layer and an upper layer. A first passivation layer contacts the lower layer of the source and drain electrodes but does not contact the upper layer of the source and drain electrodes, and a second passivation layer is disposed on the upper layer of the source and drain electrodes. The first passivation layer may be made of silicon oxide, and the second passivation may be made of silicon nitride. | 2015-01-22 |
20150021603 | SEMICONDUCTOR ELEMENT, METHOD FOR MANUFACTURING THE SEMICONDUCTOR ELEMENT, AND SEMICONDUCTOR DEVICE INCLUDING THE SEMICONDUCTOR ELEMENT - A structure including an oxide semiconductor layer which is provided over an insulating surface and includes a channel formation region and a pair of low-resistance regions between which the channel formation region is positioned, a gate insulating film covering a top surface and a side surface of the oxide semiconductor layer, a gate electrode covering a top surface and a side surface of the channel formation region with the gate insulating film positioned therebetween, and electrodes electrically connected to the low-resistance regions is employed. The electrodes are electrically connected to at least side surfaces of the low-resistance regions, so that contact resistance with the source electrode and the drain electrode is reduced. | 2015-01-22 |
20150021604 | CMOS IMAGE SENSOR HAVING OPTICAL BLOCK AREA - A CMOS image sensor includes an active pixel structure suitable for sensing light incident from outside and converting a sensed light into an electrical signal, and an optical block structure suitable for blocking a visible light and passing a UV light to check and evaluate an electrical characteristic of the active pixel area. The UV pass filter includes first and second insulation layers comprising an insulator, and a metal layer formed between the first and second insulation layers. | 2015-01-22 |
20150021605 | MAPPING DENSITY AND TEMPERATURE OF A CHIP, IN SITU - A method and system to map density and temperature of a chip, in situ, is disclosed. The method includes measuring a propagation time that a mechanical propagation wave travels along at least one predefined path in a substrate. The method further includes calculating an average substrate density and temperature along the at least one predefined path as a function of the propagation time and distance. The method further includes determining a defect or unauthorized modification in the substrate based on the average substrate density being different than a baseline substrate density. | 2015-01-22 |
20150021606 | MRAM SYNTHETIC ANITFEROMAGNET STRUCTURE - An MRAM bit ( | 2015-01-22 |
20150021607 | THIN FILM TRANSISTOR SUBSTRATE, METHOD OF MANUFACTURING THE SAME, AND ORGANIC LIGHT EMITTING DIODE DISPLAY USING THE SAME - A thin film transistor substrate includes: a polymer substrate, an oxide transparent electrode layer (TCO) formed on the polymer substrate, a barrier layer formed on the oxide transparent electrode layer, and a semiconductor layer formed on the barrier layer, in which the semiconductor layer is polysilicon. The polysilicon thin film transistor provides an oxide transparent electrode layer (TCO) which absorbs heat energy and light generated during a process of manufacturing the polysilicon thin film transistor to prevent a damage of the substrate using a polymer material. | 2015-01-22 |
20150021608 | ARRAY SUBSTRATE AND METHOD FOR MANUFACTURING THE SAME - An array substrate having a wiring of a pad region formed without an insulating film or without an insulating film and an organic film to reduce abnormal operations due to an increase in resistance caused by a contact margin at a high temperature, and a method for manufacturing the same are provided. The array substrate includes: an insulating substrate including a pad region and a thin film transistor (TFT) formation region; a first electrode layer formed in the pad region of the substrate; and a second electrode formed on the first electrode layer in an overlapping manner. | 2015-01-22 |
20150021609 | SEMICONDUCTOR APPARATUS WITH MULTIPLE TIERS, AND METHODS - Apparatus and methods are disclosed, including an apparatus that includes a number of tiers of a first semiconductor material, each tier including at least one access line of at least one memory cell and at least one source, channel and/or drain of at least one peripheral transistor, such as one used in an access line decoder circuit or a data line multiplexing circuit. The apparatus can also include a number of pillars of a second semiconductor material extending through the tiers of the first semiconductor material, each pillar including either a source, channel and/or drain of at least one of the memory cells, or a gate of at least one of the peripheral transistors. Methods of forming such apparatus are also described, along with other embodiments. | 2015-01-22 |
20150021610 | SEMICONDUCTOR STRUCTURES WITH DEEP TRENCH CAPACITOR AND METHODS OF MANUFACTURE - An integrated FinFET and deep trench capacitor structure and methods of manufacture are disclosed. The method includes forming at least one deep trench capacitor in a silicon on insulator (SOI) substrate. The method further includes simultaneously forming polysilicon fins from material of the at least one deep trench capacitor and SOI fins from the SOI substrate. The method further includes forming an insulator layer on the polysilicon fins. The method further includes forming gate structures over the SOI fins and the insulator layer on the polysilicon fins. | 2015-01-22 |
20150021611 | ARRAY SUBSTRATE AND MANUFACTURING METHOD THEREOF - An array substrate of an LCD includes a substrate, a first wiring layer, a semiconductor film, an insulating layer, a second wiring layer, a passivation layer, a conductive film, and a spacer. The first wiring layer is patterned to a gate line, a gate electrode, and a first laminating layer. The semiconductor film is patterned to a channel layer and a second laminating layer. The second wiring layer is patterned to a source line, a source electrode, a drain electrode, and a third laminating layer. The conductive film is patterned to a pixel electrode and a fourth laminating layer. The spacer is a laminating structure at least includes the first, second, third, fourth laminating layers. A portion of insulating layer overlaps with the first laminating layer, and a portion of passivation layer overlaps with the third laminating layer. | 2015-01-22 |
20150021612 | ARRAY SUBSTRATE, DISPLAY DEVICE AND MANUFACTURING METHOD OF ARRAY SUBSTRATE - An array substrate, a display device and a method of producing the array substrate are provided, and the array substrate includes a substrate and a thin film field effect transistor and a data line formed on the substrate, and the thin film field effect transistor includes a gate electrode, an active layer, a source electrode and a drain electrode, a gate insulating layer is formed between the gate electrode and the active layer, and the array substrate includes: a protection layer formed between the gate insulating layer and the data line and being in direct contact with the data line; and the protection layer is provided on the same layer with and has the same material with the active layer. | 2015-01-22 |
20150021613 | PHOTOSENSOR - For a photosensor, an array substrate is provided, wherein the edge of a photodiode is enclosed by the opening edge of a contact hole formed on a drain electrode. | 2015-01-22 |
20150021614 | CONTROLLED ON AND OFF TIME SCHEME FOR MONOLITHIC CASCODED POWER TRANSISTORS - A semiconductor device includes a depletion mode GaN FET cascoded with an enhancement mode NMOS transistor. A gate of the GaN FET is electrically coupled to a source of the NMOS transistor through a gate network. The gate network controls at least one of a turn-on time and a turn-off time of the GaN FET. The gate network may be controlled by an input signal to a gate of the NMOS transistor. | 2015-01-22 |
20150021615 | JUNCTION BARRIER SCHOTTKY DIODE AND MANUFACTURING METHOD THEREOF - The present invention discloses a junction barrier Schottky (JBS) diode and a manufacturing method thereof. The JBS diode includes: an N-type gallium nitride (GaN) substrate; an aluminum gallium nitride (AlGaN) barrier layer, which is formed on the N-type GaN substrate; a P-type gallium nitride (GaN) layer, which is formed on or above the N-type GaN substrate; an anode conductive layer, which is formed at least partially on the AlGaN barrier layer, wherein a Schottky contact is formed between part of the anode conductive layer and the AlGaN barrier layer; and a cathode conductive layer, which is formed on the N-type GaN substrate, wherein an ohmic contact is formed between the cathode conductive layer and the N-type GaN substrate, and the cathode conductive layer is not directly connected to the anode conductive layer. | 2015-01-22 |
20150021616 | NITRIDE-BASED SEMICONDUCTOR DEVICES - A nitride-based semiconductor device includes a barrier structure on a substrate, a nitride semiconductor layer on the barrier structure, and a source electrode, a drain electrode, and a gate electrode on the nitride semiconductor layer to be separated from each other. The barrier structure includes a first semiconductor layer having a first conductivity, a second semiconductor layer having a second conductivity on the first semiconductor layer, a third semiconductor layer having the first conductivity on the second semiconductor layer, and a fourth semiconductor layer having the second conductivity on the third semiconductor layer. A two-dimensional electrode gas (2DEG) channel is formed in the nitride semiconductor layer. | 2015-01-22 |
20150021617 | SEMICONDUCTOR DEVICE - A semiconductor device includes; a semiconductor layer mainly made of GaN; a protective film provided to have electrical insulation property and configured to coat the semiconductor layer; and an electrode provided to have electrical conductivity and configured to form a Schottky junction with the semiconductor layer. Tthe protective film includes: a first layer made of Al | 2015-01-22 |
20150021618 | SEMICONDUCTOR DEVICE - A semiconductor device includes: a p-type semiconductor layer mainly made of GaN; an n-type semiconductor layer mainly made of GaN and joined with the p-type semiconductor layer; a protective film arranged to coat the p-type semiconductor layer and the n-type semiconductor layer; a gate insulating film arranged to coat the p-type semiconductor layer and the n-type semiconductor layer; and a gate electrode joined with the gate insulating film. The protective film includes: a first layer made of Al | 2015-01-22 |
20150021619 | III-Nitride Semiconductor Device with Reduced Electric Field Between Gate and Drain - A conductive field plate is formed between the drain electrode and gate of each cell of a III-Nitride semiconductor and is connected to the source electrode to reduce the electric field between the gate and the drain. The electrodes may be supported on N | 2015-01-22 |
20150021620 | LIGHT EMITTING DEVICE - The light emitting device includes a first semiconductor layer, a second semiconductor layer and an active layer provided between the first semiconductor layer and the second semiconductor layer. A first light extraction layer is provided on the first semiconductor layer and includes a nitride semiconductor layer. The first light extraction layer includes a plurality of first layers. The refractive indexes of the first layers decrease with increasing distance from the first semiconductor layer. | 2015-01-22 |
20150021621 | SELF-ALIGNED GATE BURIED CHANNEL FIELD EFFECT TRANSISTOR - This disclosure provides a transistor device formed on a wide band gap substrate. The transistor device includes a channel layer and a gate structure physically coupled to the channel layer. The gate structure can be formed on the channel layer using an epitaxial process instead of a lithographic process, thereby providing a mechanism to build small semiconductor features that are smaller than a resolution of the state-of-the-art lithographic process and reducing the amount of impurities between the channel layer and the gate structure. | 2015-01-22 |
20150021622 | LIGHT-EMITTING ELEMENT AND METHOD FOR MANUFACTURING SAME - In a light emitting element, a semiconductor layer including a light emitting layer is stacked on a GaN substrate | 2015-01-22 |
20150021623 | ENHANCED GATE DIELECTRIC FOR A FIELD EFFECT DEVICE WITH A TRENCHED GATE - The present disclosure relates to a silicon carbide (SiC) field effect device that has a gate assembly formed in a trench. The gate assembly includes a gate dielectric that is an dielectric layer, which is deposited along the inside surface of the trench and a gate dielectric formed over the gate dielectric. The trench extends into the body of the device from a top surface and has a bottom and side walls that extend from the top surface of the body to the bottom of the trench. The thickness of the dielectric layer on the bottom of the trench is approximately equal to or greater than the thickness of the dielectric layer on the side walls of the trench. | 2015-01-22 |
20150021624 | LIFT-OFF OF EPITAXIAL LAYERS FROM SILICON CARBIDE OR COMPOUND SEMICONDUCTOR SUBSTRATES - A method to remove epitaxial semiconductor layers from a substrate by growing an epitaxial sacrificial layer on the substrate where the sacrificial layer is a transition metal nitride (TMN) or a TMN ternary compound, growing one or more epitaxial device layers on the sacrificial layer, and separating the device layers from the substrate by etching the sacrificial layer to completely remove the sacrificial layer without damaging or consuming the substrate or any device layer. Also disclosed are the related semiconductor materials made by this method. | 2015-01-22 |
20150021625 | SEMICONDUCTOR FIN ISOLATION BY A WELL TRAPPING FIN PORTION - A bulk semiconductor substrate including a first semiconductor material is provided. A well trapping layer including a second semiconductor material and a dopant is formed on a top surface of the bulk semiconductor substrate. The combination of the second semiconductor material and the dopant within the well trapping layer is selected such that diffusion of the dopant is limited within the well trapping layer. A device semiconductor material layer including a third semiconductor material can be epitaxially grown on the top surface of the well trapping layer. The device semiconductor material layer, the well trapping layer, and an upper portion of the bulk semiconductor substrate are patterned to form at least one semiconductor fin. Semiconductor devices formed in each semiconductor fin can be electrically isolated from the bulk semiconductor substrate by the remaining portions of the well trapping layer. | 2015-01-22 |
20150021626 | LIGHT-EMITTING DEVICE - A light-emitting device includes: a layered semiconductor body including an n-type layer, a light-emitting layer, and a p-type layer stacked in sequence; an n-side electrode formed on part of the n-type layer exposed in a via formed in the layered semiconductor body to be non-conductive with the light-emitting layer and the p-type layer; and a p-side electrode formed on the p-type layer. The n-side electrode has an annular shape on a principal surface of the n-type layer. | 2015-01-22 |
20150021627 | LIGHT EMITTING APPARATUS, MANUFACTURING METHOD OF LIGHT EMITTING APPARATUS, LIGHT RECEIVING AND EMITTING APPARATUS, AND ELECTRONIC EQUIPMENT - A light emitting apparatus includes a translucent substrate, and a light emitting section and an optical filter section arranged in a first region of the substrate when viewed in a normal direction of a first surface of the substrate. The light emitting section has a laminate structure that includes, on the first surface of the substrate, a dielectric multilayer film, a first electrode, a functional layer with a light emitting layer, and a second electrode having semi-transmissive reflectivity. The optical filter section has a laminate structure that includes, on the first surface of the substrate, the dielectric multilayer film, the functional layer, and the second electrode. The dielectric multilayer film and the functional layer extend over the first region. | 2015-01-22 |
20150021628 | SOLID STATE LIGHTING DEVICES AND FABRICATION METHODS INCLUDING DEPOSITED LIGHT-AFFECTING ELEMENTS - Solid state light emitting devices include one or more light affecting elements (e.g., of one or more light-transmissive, light-absorptive, light-reflective, and/or lumiphoric materials) formed on, over, or around at least one solid state light emitter, with the light affecting elements including multiple fused elements embodying plurality of dots, rods, or layers such as may be formed by three-dimensional (3D) printing. At least one electrically conductive path in electrical communication with a solid state light emitter may be formed by selective material deposition such as 3D printing. Light affecting elements may be individually tailored to individual solid state light emitters, such as to yield different optical distributions for interactions between each specific emitter and its corresponding light affecting element. | 2015-01-22 |
20150021629 | Using An LED Die To Measure Temperature Inside Silicone That Encapsulates An LED Array - An LAM/ICM assembly comprises an integrated control module (ICM) and an LED array member (LAM). The ICM includes interconnect through which power from outside the assembly is received. In a first novel aspect, active circuitry is embedded in the ICM. In one example, the circuitry monitors LED operation, controls and supplies power to the LEDs, and communicates information into and out of the assembly. In a second novel aspect, a lighting system comprises an AC-to-DC converter and a LAM/ICM assembly. The AC-to-DC converter outputs a substantially constant current or voltage. The magnitude of the current or voltage is adjusted by a signal output from the LAM/ICM. In a third novel aspect, the ICM includes a switching DC-to-DC converter. An AC-to-DC power supply supplies a roughly regulated supply voltage. The switching converter within the LAM/ICM receives the roughly regulated voltage and supplies a regulated LED drive current to its LEDs. | 2015-01-22 |
20150021630 | DISPLAY DEVICE AND MANUFACTURING METHOD THEREOF - The present invention relates to a display device, and a manufacturing method thereof. The display device includes a first insulation substrate; gate lines and data lines positioned on the first insulating substrate. The gate lines and data lines are insulated from each other and crossed each other. A first passivation layer positioned on the gate lines and the data lines, and including a first contact opening. A color filter positioned on the first passivation layer, and including an opening. An organic insulation layer positioned on the color filter, and including a contact hole, in which the first contact opening is larger than the opening. The organic insulation layer covers the color filter and the contact opening. | 2015-01-22 |
20150021631 | FLEXIBLE DISPLAY APPARATUS AND METHOD OF MANUFACTURING SAME - A method of manufacturing a flexible display apparatus includes: preparing a support substrate; forming a first graphene oxide layer having a first electrical charge on the support substrate; forming a second graphene oxide layer having a second electrical charge on the first graphene oxide layer; forming a flexible substrate on the second graphene oxide layer; forming a display unit on the flexible substrate; and separating the support substrate and the flexible substrate from each other. | 2015-01-22 |
20150021632 | LED WITH MULTIPLE BONDING METHODS ON FLEXIBLE TRANSPARENT SUBSTRATE - Inventive aspects disclosed herein include a flexible device. The flexible device includes a flexible transparent substrate and an adhesive adhered to the flexible transparent substrate, covering a portion of the substrate. The device also includes two or more bare LED dies adhered to the adhesive, the two or more LED dies spaced as little as 0.22 inches (5.4 mm), or less, apart. The device additionally includes a pair of conductive traces on or in the substrate and positioned on opposing sides of the bare LED dies; a pair of conductive pads positioned on opposing surfaces of the bare LED die; and an interconnect that interconnects the pads and the traces. | 2015-01-22 |
20150021633 | LIGHT-EMITTING DIODE PACKAGE AND LIGHT-EMITTING DEVICE - An LED package is disclosed, which includes a heat dissipation plate, a composite structure, an LED chip, and an encapsulant. The heat dissipation plate has a chip bonding area, a circuit area, and a first dam disposed at the boundary between the chip bonding area and the circuit area, wherein the first dam is formed by punching or bending the heat dissipation plate. The composite structure is disposed on the circuit area. The LED chip which is disposed on the chip bonding area is electrically connected to the composite structure and covered by the encapsulant. Also a light-emitting device using the LED package is disclosed. | 2015-01-22 |
20150021634 | DISPLAY UNIT USING LED LIGHT SOURCES - A display unit includes a substrate, a plurality of LED light sources arranged in a matrix on the substrate, and a light blocking layer that blocks at least part of light emitted from the LED light sources. The light blocking layer includes an area that overlaps a region between two adjacent LED light sources among the plurality of LED light sources as viewed in a thickness direction Z of the substrate. | 2015-01-22 |
20150021635 | White Light Emitting LED Device - A white light emitting LED device comprises: base, blue light LED chips, light reflector and transparent substrate covered with a phosphor coating; two ends of the light reflector connect the base and the transparent substrate, respectively, the inner surface of the light reflector is covered with a light-reflecting coating; blue light LED chips are set on the surface of the base pointing to the transparent substrate, and the electrode leads of blue light LED chips pass through the base; blue light LED chip is a single chip, or a group of chips connected in series, or in parallel, or in a mixed manner; the transparent substrate has the shape of a plane, or a convex, or a semi-cylinder. The present invention gets the white light by utilizing the blue lights emitted by the blue light LED chips to irradiate the transparent substrate which is covered with a phosphor coating. | 2015-01-22 |
20150021636 | Optoelectronic Semiconductor Chip - An optoelectronic semiconductor chip includes a number active regions that are arranged at a distance from each other and a substrate that is arranged on an underside of the active regions. One of the active regions has a main extension direction. The active region has a core region that is formed using a first semiconductor material. The active region has an active layer that covers the core region at least in directions perpendicular to the main extension direction of the active region. The active region has a cover layer that is formed using a second semiconductor material and covers the active layer at least in directions perpendicular to the main extension direction of the active region. | 2015-01-22 |
20150021637 | DISPLAY PANEL AND METHOD OF MANUFACTURING THE SAME - A display panel includes a plurality of unit pixels, where each of the unit pixels has a hexagonal-shape and includes: a first sub-pixel configured to emit a first color light, where the first sub-pixel has a rhombus-shape; a second sub-pixel configured to emit a second color light, where the second sub-pixel has the rhombus-shape; and a third sub-pixel configured to emit a third color light, where the third sub-pixel has the rhombus-shape, where first sub-pixels, second sub-pixels or third sub-pixels of neighboring unit pixels in a same row are arranged to adjoin each other. | 2015-01-22 |
20150021638 | LIGHT EMITTING DEVICE - Disclosed is a light emitting device comprising a plurality of light emitting cells, and a bridge electrode electrically connecting two adjacent light emitting cells, and the plurality of light emitting cells comprise a light emitting structure including a first conductive semiconductor layer, a second conductive semiconductor layer and an active layer between the first conductive semiconductor layer and the second conductive semiconductor layer, a first electrode on the first conductive semiconductor layer and a second electrode on the second conductive semiconductor layer, wherein the bridge electrode has a part thicker than the first electrode and the second electrode. | 2015-01-22 |
20150021639 | LIGHT EMITTING DIODE STRUCTURE - A light emitting diode structure including a substrate, a semiconductor epitaxial layer and a reflective conductive structure layer is provided. The semiconductor epitaxial layer is disposed on the substrate and exposes a portion of the substrate. The reflective conductive structure layer covers a part of the semiconductor epitaxial layer and the portion of the substrate exposed by the semiconductor epitaxial layer. | 2015-01-22 |
20150021640 | LIGHT-EMITTING DEVICE - A light-emitting device includes a lead frame, a white resist, a light-emitting element, and a wire. The white resist is provided on the lead frame to be in contact with the lead frame. The white resist has an opening to expose the lead frame. The light-emitting element is disposed on the white resist and includes a transparent substrate and a semiconductor layer. The transparent substrate is bonded to the white resist via a bonding member. The semiconductor layer is provided on the transparent substrate. The wire connects the light-emitting element and the lead frame at the opening. | 2015-01-22 |
20150021641 | LIGHT EMITTING DEVICE - A light emitting device includes a substrate member, a light emitting element, a resin member, an insulating layer and a fluorescent material layer. The light emitting element is arranged on the substrate member. The resin member surrounds sides of the light emitting element, and has a top portion located higher than a light emission surface of the light emitting element. The insulating layer covers the light emission surface of the light emitting element and an outer wall surface and an inner wall surface of the top portion of the resin member. The fluorescent material layer covers a surface of the insulating layer. | 2015-01-22 |
20150021642 | LIGHT EMITTING DEVICE AND METHOD OF MANUFACTURING THE SAME - A light emitting device has a substrate including a pair of connection terminals at least on a first main surface of the substrate a light emitting element connected to the connection terminals by a molten material, and a light reflecting member covering the light emitting element, at least one of the connection terminals including a protruding portion configured to project from a first main surface of the connection terminal at a region which is connected with the light emitting element, the protruding portion and the molten material being embedded into the light reflecting member. | 2015-01-22 |
20150021643 | SURFACE-MODIFIED-METAL-OXIDE-PARTICLE MATERIAL, COMPOSITION FOR SEALING OPTICAL SEMICONDUCTOR ELEMENT, AND OPTICAL SEMICONDUCTOR DEVICE - There is provided a surface-modified-metal-oxide-particle material including surface-modified-metal-oxide-particles obtained by performing surface modification on metal oxide particles with a surface-modifying material, in which the surface-modifying material includes a predetermined silicone compound, an average primary particle diameter of the metal oxide particles is 3 nm to nm, viscosity at 25° C. is 1000 Pa·s or less, and transmittance of light at a wavelength of 400 nm to 800 nm and a thickness of 1 mm is 60% or greater, a composition for sealing optical semiconductor element, and an optical semiconductor device using the same. | 2015-01-22 |
20150021644 | LIGHT EMITTING DEVICE PACKAGE AND LIGHT UNIT HAVING THE SAME - Disclosed is a light emitting device package. The light emitting device package includes a package body having a first cavity and a second cavity; a plurality of reflective frames comprising a first reflective frame and a second reflective frame on the first cavity and the second cavity, respectively, and each of the first reflective frame and the second reflective frame comprises a bottom frame and at least two side wall frames extending from the bottom frame; and a light emitting device on the first reflective frame, wherein the first reflective frame and the second reflective frame are electrically separated from each other. | 2015-01-22 |
20150021645 | LIGHT EMITTING PACKAGE HAVING A GUIDING MEMBER GUIDING AN OPTICAL MEMBER - A light emitting package, includes a base; a light emitting device on the base; an electrical circuit layer electrically connected to the light emitting device; an optical member formed of a light transmissive material; and a guiding member guiding the optical member, the guiding member including an opening, a first portion disposed on the uppermost surface of the base, and a second portion connected to an edge portion of the optical member. The first portion of the guiding member is positioned higher than a bottom surface of the optical member, an uppermost surface of the base is closer to the first portion of the guiding member than the second portion of the guiding member, and the edge portion of the optical member is closer to the second portion of the guiding member than the first portion of the guiding member. | 2015-01-22 |
20150021646 | LIGHT EMITTING DEVICE PACKAGE INCLUDING A SUBSTRATE HAVING AT LEAST TWO RECESSED SURFACES - A light emitting device package is disclosed, which includes a first via hole and a second via hole disposed lower than a light emitting part, the first via hole and the second via hole are disposed at an outer area of the light emitting part, a bottom metal includes a first bottom metal, a second bottom metal, and a third bottom metal between the first bottom metal and the second bottom metal, a first conductive metal electrically connected to the first bottom metal through the first via hole and a second conductive metal electrically connected to the second bottom metal through the second via hole. Further, the first bottom metal, the second bottom metal are apart from the third bottom metal at a bottom surface of the substrate, and the third bottom metal is not electrically connected to the second conductive type metal layer. | 2015-01-22 |
20150021647 | LUMINOUS ELEMENT - A light emitting device according to the embodiment includes a first conductive semiconductor layer; an active layer over the first conductive semiconductor layer; a second conductive semiconductor layer over the active layer; a bonding layer over the second conductive semiconductor layer; a schottky diode layer over the bonding layer; an insulating layer for partially exposing the bonding layer, the schottky diode layer, and the first conductive semiconductor layer; a first electrode layer electrically connected to both of the first conductive semiconductor layer and the schottky diode layer; and a second electrode layer electrically connected to the bonding layer. | 2015-01-22 |
20150021648 | COMPOSITE LED PACKAGE AND ITS APPLICATION TO LIGHT TUBES - A light emitting diode package includes a first lead frame, a second lead frame and an encapsulant. The first lead frame has a die deposition area on the top thereof for disposing LED die. The second lead frame has a contacting face on the top thereof for wire bonding. The die deposition area of the first lead frame has a first adhesion area such that the encapsulant is held by the first adhesion area when enclosing the top and bottom of the first and second lead frames. The light is emitted in all directions. | 2015-01-22 |
20150021649 | PIXEL STRUCTURE - A pixel structure having a first region and a second region adjacent to each other is provided. The pixel structure includes a first pixel electrode and a second pixel electrode. The first pixel electrode forms a plurality of first V-shaped electrode patterns. A tip of the first V-shaped electrode patterns is located at a boundary of the first region and the second region. The second pixel electrode includes a plurality of second V-shaped electrode patterns and a first protrusion electrode pattern. The first protrusion electrode pattern is connected to one of the second V-shaped electrode patterns and protrudes towards an adjacent first V-shaped electrode pattern from the tip of the second V-shaped electrode pattern. | 2015-01-22 |
20150021650 | SUBSTRATE, LIGHT-EMITTING DEVICE, ILLUMINATING LIGHT SOURCE, AND LIGHTING APPARATUS - A lighting apparatus includes a substrate and a semiconductor light-emitting element mounted on the substrate. The substrate includes a plate-like base member and a copper foil layer formed on part of the base member. The substrate includes a first area and a second area. The first area is an area that is provided so as to surround an element mounting area where a semiconductor light-emitting element is mounted thereon when viewed from the top of the substrate and does not include with the copper foil layer. The second area is an area that includes a part provided so as to surround the first area and the element mounting area; and where the copper foil layer formed. The substrate has a white resist layer disposed thereon that covers the first and second areas and is formed thicker on the first area than on the second area. | 2015-01-22 |
20150021651 | LIGHT EMITTING DEVICE PACKAGE AND LIGHT UNIT HAVING THE SAME - Disclosed is a light emitting device package. The light emitting device package includes a package body having a first cavity and a second cavity; a plurality of reflective frames comprising a first reflective frame and a second reflective frame on the first cavity and the second cavity, respectively, and each of the first reflective frame and the second reflective frame comprises a bottom frame and at least two side wall frames extending from the bottom frame; and a light emitting device on the first reflective frame, wherein the first reflective frame and the second reflective frame are electrically separated from each other. | 2015-01-22 |
20150021652 | NITRIDE SEMICONDUCTOR LIGHT-EMITTING ELEMENT - The present invention improves luminous efficiency of a nitride semiconductor light-emitting element. In the nitride semiconductor light-emitting element, a non-polar or semi-polar Al | 2015-01-22 |
20150021653 | NITRIDE SEMICONDUCTOR LIGHT-EMITTING ELEMENT AND METHOD FOR FABRICATING THE SAME - Provided is a nitride semiconductor light-emitting element having a low contact resistance between an n-type nitride semiconductor layer and an n-side electrode. A portion of the n-type nitride semiconductor layer is removed by a plasma etching process using a gas containing halogen to expose a surface region | 2015-01-22 |
20150021654 | TUNNELING TRANSISTOR WITH ASYMMETRIC GATE - An asymmetric gate tunneling transistor includes a substrate, a first-polarity portion, a second-polarity portion, a channel portion, a gate structure and an insulation body. The first-polarity portion and the second-polarity portion are disposed on the substrate. The channel portion is connected with the first-polarity portion and the second-polarity portion, and includes a first section and a second section. The gate structure includes an enveloping portion surrounding the first section, and a flat portion covering one side of the second section away from the substrate. The insulation body includes a first insulation portion disposed between the first section and the enveloping portion, and a second insulation portion disposed between the second section and the flat portion. Through the asymmetric design of the gate structure, the tunneling transistor is offered with features of a high ON current and a low OFF current. | 2015-01-22 |
20150021655 | SEMICONDUCTOR DEVICE - A semiconductor device includes a first semiconductor region of a first conductivity type, a second semiconductor region of a second conductivity type on the first semiconductor region, a third semiconductor region of the first conductivity type on the second semiconductor region, a control electrode disposed within and insulated from the first, second, and third semiconductor regions, a first electrode electrically connected with the second and third semiconductor regions, a second electrode, and a fourth semiconductor region of the second conductivity type between the second electrode and the first semiconductor region. The fourth semiconductor region includes a first portion having a first dopant concentration and a second portion having a second dopant concentration higher than the first dopant concentration, and a contact area of the first portion with the second electrode is larger than a contact area of the second area with the second electrode. | 2015-01-22 |
20150021656 | SEMICONDUCTOR DEVICE - According to one embodiment, a semiconductor device includes a first semiconductor region of a first conductivity type, a first control electrode, a first electrode, a second control electrode, a second semiconductor region of a second conductivity type, a third semiconductor region of the first conductivity type, and a first insulating film. The first control electrode is provided on or above the first semiconductor region. The first electrode is provided on the first control electrode. The second control electrode is provided on or above the first semiconductor region and includes a first portion which is beside the first control electrode and a second portion which is provided on the first portion and beside the first electrode. The second semiconductor region is provided on the first semiconductor region. A boundary between the first semiconductor region and the second semiconductor region is above the lower end of the first electrode. | 2015-01-22 |
20150021657 | SEMICONDUCTOR DEVICE - According to one embodiment, a semiconductor device includes: first and second electrodes; a first semiconductor region being in ohmic contact with the first electrode; a second semiconductor region being in contact with the first semiconductor region and the first electrode, and the second semiconductor region having a lower impurity concentration than the first semiconductor region; a first semiconductor layer; a second semiconductor layer; a third semiconductor region; a fourth semiconductor region being in contact with the second electrode; and a third electrode in contact with the second semiconductor layer, the third semiconductor region, and the fourth semiconductor region via an insulating film. A peak of impurity concentration profile of the first semiconductor layer in a direction from the first electrode toward the second electrode is located between the first semiconductor region and the second semiconductor layer and located between the second semiconductor region and the second semiconductor layer. | 2015-01-22 |
20150021658 | SEMICONDUCTOR DEVICE AND METHOD FOR FABRICATING THE SAME - A semiconductor device includes an emitter electrode and a first field plate disposed on one surface of a substrate and spaced apart from each other, a collector electrode disposed on the other surface of the substrate, a trench gate disposed in the substrate, a field diffusion junction disposed in the substrate, and a first contact connecting the trench gate and the first field plate. The first field plate has a first part extending toward the emitter electrode with respect to the first contact and having a first width, and a second part extending toward the field diffusion junction with respect to the first contact and having a second width. The second width is greater than the first width. | 2015-01-22 |
20150021659 | PROGRAMMABLE SCR FOR ESD PROTECTION - A programmable semiconductor controlled rectifier (SCR) circuit is disclosed. The SCR includes a first terminal ( | 2015-01-22 |
20150021660 | TRANSISTOR HAVING A BACK-BARRIER LAYER AND METHOD OF MAKING THE SAME - A transistor includes a substrate and a buffer layer on the substrate, wherein the buffer layer comprises p-type dopants. The transistor further includes a channel layer on the buffer layer and a back-barrier layer between a first portion of the channel layer and a second portion of the channel layer. The back-barrier layer has a band gap discontinuity with the channel layer. The transistor further includes an active layer on the second portion of the channel layer, wherein the active layer has a band gap discontinuity with the second portion of the channel layer. The transistor further includes a two dimensional electron gas (2-DEG) in the channel layer adjacent an interface between the channel layer and the active layer. | 2015-01-22 |
20150021661 | TRANSISTOR HAVING HIGH BREAKDOWN VOLTAGE AND METHOD OF MAKING THE SAME - A transistor includes a substrate and a graded layer on the substrate, wherein the graded layer is doped with p-type dopants. The transistor further includes a superlattice layer (SLS) on the graded layer, wherein the SLS has a p-type dopant concentration equal to or greater than 1×10 | 2015-01-22 |
20150021662 | III-V SEMICONDUCTOR DEVICE HAVING SELF-ALIGNED CONTACTS - A method including forming a III-V compound semiconductor-containing heterostructure, forming a gate dielectric having a dielectric constant greater than 4.0 positioned within a gate trench, the gate trench formed within the III-V compound semiconductor-containing heterostructure, and forming a gate conductor within the gate trench on top of the gate dielectric, the gate conductor extending above the III-V compound semiconductor heterostructure. The method further including forming a pair of sidewall spacers along opposite sides of a portion of the gate conductor extending above the III-V compound semiconductor-containing heterostructure and forming a pair of source-drain contacts self-aligned to the pair of sidewall spacers. | 2015-01-22 |
20150021663 | FINFET WITH INSULATOR UNDER CHANNEL - A FinFET has a structure including a semiconductor substrate, semiconductor fins and a gate spanning the fins. The fins each have a bottom region coupled to the substrate and a top active region. Between the bottom and top fin regions is a middle stack situated between a vertically elongated source and a vertically elongated drain. The stack includes a top channel region and a dielectric region immediately below the channel region, providing electrical isolation of the channel. The partial isolation structure can be used with both gate first and gate last fabrication processes. | 2015-01-22 |
20150021664 | Lateral/Vertical Semiconductor Device with Embedded Isolator - A lateral/vertical device is provided. The device includes a device structure including a device channel having a lateral portion and a vertical portion. The lateral portion of the device channel can be located adjacent to a first surface of the device structure, and one or more contacts and/or a gate can be formed on the first surface. The device structure also includes a set of insulating layers located in the device structure between the lateral portion of the device channel and a second surface of the device structure opposite the first surface. An opening in the set of insulating layers defines a transition region between the lateral portion of the device channel and a vertical portion of the device channel. A contact to the vertical portion of the device channel can be located on the second surface. | 2015-01-22 |
20150021665 | TRANSISTOR HAVING BACK-BARRIER LAYER AND METHOD OF MAKING THE SAME - A transistor includes a substrate, a channel layer over the substrate, a back-barrier layer over the channel layer, and an active layer over the back-barrier layer. The back-barrier layer has a band gap discontinuity with the channel layer. The band gap of the active layer is less than the band gap of the back-barrier layer. A two dimensional electron gas (2-DEG) is formed in the channel layer adjacent an interface between the channel layer and the back-barrier layer. | 2015-01-22 |
20150021666 | TRANSISTOR HAVING PARTIALLY OR WHOLLY REPLACED SUBSTRATE AND METHOD OF MAKING THE SAME - A transistor includes a substrate, a channel layer over the substrate, an active structure over the channel layer, a gate electrode over the channel layer, and a drain electrode over the channel layer. The active structure is configured to cause a two dimensional electron gas (2DEG) to be formed in the channel layer along an interface between the channel layer and the active structure. The gate electrode and the drain electrode define a first space therebetween. The substrate has a first portion directly under the first space defined between the gate electrode and the drain electrode, and the first portion has a first electrical conductivity value less than that of intrinsic silicon and a thermal conductivity value greater than that of intrinsic silicon. | 2015-01-22 |
20150021667 | High Electron Mobility Transistor and Method of Forming the Same - A semiconductor structure includes a first III-V compound layer. A second III-V compound layer is disposed on the first III-V compound layer and is different from the first III-V compound layer in composition. A carrier channel is located between the first III-V compound layer and the second III-V compound layer. A source feature and a drain feature are disposed on the second III-V compound layer. A gate electrode is disposed over the second III-V compound layer between the source feature and the drain feature. A fluorine region is embedded in the second III-V compound layer under the gate electrode. A diffusion barrier layer is disposed on top of the second III-V compound layer. A gate dielectric layer is disposed over the second III-V compound layer. The gate dielectric layer has a fluorine segment on the fluorine region and under at least a portion of the gate electrode. | 2015-01-22 |
20150021668 | PHOTOSENSITIVE CELL OF AN IMAGE SENSOR - An image sensor cell formed inside and on top of a substrate of a first conductivity type includes: a storage region of the second conductivity type; a read region of the second conductivity type; a transfer region located between the storage region and the read region; and a transfer gate topping the transfer region and which does not or does not totally top the storage region. The transfer region comprises a first area of the first conductivity type in the vicinity of the storage region, and a second area of the second conductivity type extending between the first area and the read region. | 2015-01-22 |
20150021669 | SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD THEREOF - A non-planar JFET device having a thin fin structure is provided. A fin is formed projecting upwardly from or through a top surface of a substrate, where the fin has a first semiconductor layer portion formed from a first semiconductor material of a first conductivity type. The first semiconductor layer portion has a source region and a drain region, a channel region extending between the source region and the drain region. Two or more channel control regions are formed adjoining the channel region for generating charge depletion zones at and extending into the channel region for thereby controlling current conduction through the channel region. A gate is provided so as to adjoin and short together the at least two channel control regions from the outer sides of the channel control regions. | 2015-01-22 |
20150021670 | Charge Compensation Semiconductor Devices - A field-effect semiconductor device includes a semiconductor body having a first surface and an edge, an active area, and a peripheral area between the active area and the edge, a source metallization on the first surface and a drain metallization. In the active area, first conductivity type drift portions alternate with second conductivity type compensation regions. The drift portions contact the drain metallization and have a first maximum doping concentration. The compensation regions are in Ohmic contact with the source metallization. The peripheral area includes a first edge termination region and a second semiconductor region in Ohmic contact with the drift portions having a second maximum doping of the first conductivity type which lower than the first maximum doping concentration by a factor of ten. The first edge termination region of the second conductivity type adjoins the second semiconductor region and is in Ohmic contact with the source metallization. | 2015-01-22 |
20150021671 | FIELD-EFFECT TRANSISTOR AND METHOD OF MANUFACTURING THEREOF - According to this GaN-based HFET, resistivity ρ of a semi-insulating film forming a gate insulating film is 3.9×10 | 2015-01-22 |
20150021672 | CONTACT FOR HIGH-K METAL GATE DEVICE - An integrated circuit having an improved gate contact and a method of making the circuit are provided. In an exemplary embodiment, the method includes receiving a substrate. The substrate includes a gate stack disposed on the substrate and an interlayer dielectric disposed on the gate stack. The interlayer dielectric is first etched to expose a portion of the gate electrode, and then the exposed portion of the gate electrode is etched to form a cavity. The cavity is shaped such that a portion of the gate electrode overhangs the electrode. A conductive material is deposited within the cavity and in electrical contact with the gate electrode. In some such embodiments, the etching of the gate electrode forms a curvilinear surface of the gate electrode that defines the cavity. | 2015-01-22 |
20150021673 | SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD THEREOF - A semiconductor device includes a substrate that has a surface. The semiconductor further includes a fin disposed on the surface and including a semiconductor member. The semiconductor further includes a spacer disposed on the surface, having a type of stress, and overlapping the semiconductor member in a direction parallel to the surface. A thickness of the spacer in a direction perpendicular to the surface is less than a height of the semiconductor member in the direction perpendicular to the surface. | 2015-01-22 |
20150021674 | RADIATION IMAGE PICKUP UNIT AND RADIATION IMAGE PICKUP DISPLAY SYSTEM - A radiation image pickup unit includes: a plurality of pixels each configured to generate a signal charge based on a radiation; and a field effect transistor to readout the signal charges from the plurality of pixels. The transistor includes a semiconductor layer including an active layer, a first gate electrode disposed to face the semiconductor layer, a first gate insulating film provided between the semiconductor layer and the first gate electrode, and including a first silicon oxide film, a source electrode and a drain electrode that are electrically connected to the semiconductor layer, and a second silicon oxide film provided in a layer different from the first gate insulating film. The first silicon oxide film of the first gate insulating film is a porous film lower in film density than the second silicon oxide film. | 2015-01-22 |
20150021675 | THREE-DIMENSIONAL MAGNETIC MEMORY ELEMENT - The disclosed technology relates to a magnetic memory device. In one aspect, the device includes a first electrode comprising a conductive pillar formed over the substrate and elongated in a vertical direction crossing a lateral surface of the substrate. The device additionally includes a second electrode extending in a lateral direction crossing the first direction, where the second electrode intersects the first electrode. The device additionally includes a magnetic tunnel junction (MTJ) formed at an intersection between the first electrode and the second electrode, where the MTJ continuously surrounding the first electrode. The MTJ includes a reference layer continuously surrounding the pillar of the first electrode, a free layer continuously surrounding the free layer, and a dielectric tunnel barrier interposed between the reference layer and the free layer. | 2015-01-22 |
20150021676 | HIGH VOLTAGE METAL-OXIDE-METAL (HV-MOM) DEVICE, HV-MOM LAYOUT AND METHOD OF MAKING THE HV-MOM DEVICE - A high voltage metal-oxide-metal (HV-MOM) device includes a substrate, a deep well in the substrate and at least one high voltage well in the substrate over the deep well. The HV-MOM device further includes a dielectric layer over each high voltage well of the at least one high voltage well and a gate structure over the dielectric layer. The HV-MOM device further includes an inter-layer dielectric (ILD) layer over the substrate, the ILD layer surrounding the gate structure. The HV-MOM device further includes a first inter-metal dielectric (IMD) layer over the ILD layer and a first metal feature in the first IMD layer, wherein the first metal feature is part of a MOM capacitor. | 2015-01-22 |
20150021677 | Embedded Transistor - An embedded transistor for an electrical device, such as a DRAM memory cell, and a method of manufacture thereof is provided. A trench is formed in a substrate and a gate dielectric and a gate electrode formed in the trench of the substrate. Source/drain regions are formed in the substrate on opposing sides of the trench. In an embodiment, one of the source/drain regions is coupled to a storage node and the other source/drain region is coupled to a bit line. In this embodiment, the gate electrode may be coupled to a word line to form a DRAM memory cell. | 2015-01-22 |
20150021678 | NONVOLATILE SEMICONDUCTOR MEMORY DEVICE AND METHOD OF MANUFACTURING THE SAME - According to one embodiment, a nonvolatile semiconductor memory device includes a first memory cell on the first fin-type active area, and a second memory cell on the second fin-type active area. Each of widths of charge storage layers of the first and second memory cells becomes narrower upward from below. Each of inter-electrode insulating layers of the first and second memory cells has a contact portion through which both are in contact with each other. | 2015-01-22 |
20150021679 | Architecture to Improve Cell Size for Compact Array of Split Gate Flash Cell with Buried Common Source Structure - Some embodiments of the present disclosure relates to an architecture to create split gate flash memory cell that has lower common source (CS) resistance and a reduced cell size by utilizing a buried conductive common source structure. A two-step etch process is carried out to create a recessed path between two split gate flash memory cells. A single ion implantation to form the common source also forms a conductive path beneath the STI region that connects two split gate flash memory cells and provide potential coupling during programming and erasing and thus electrically connect the common sources of memory cells along a direction that forms a CS line. The architecture contains no OD along the source line between the cells, thus eliminating the effects of CS rounding and CS resistance, resulting in a reduced space between cells in an array. Hence, this particular architecture reduces the resistance and the buried conductive path between several cells in an array suppresses the area over head. | 2015-01-22 |
20150021680 | FIELD EFFECT TRANSISTOR INCORPORATING A SCHOTTKY DIODE - A FET incorporating a Schottky diode has a structure allowing the ratio of an area in which the Schottky diode is formed and an area in which the FET is formed to be freely adjusted. A trench extending for a long distance is utilized. Schottky electrodes are interposed at positions appearing intermittently in the longitudinal direction of the trench. By taking advantage of the growth rate of a thermal oxide film formed on SiC being slower, and the growth rate of a thermal oxide film formed on polysilicon being faster, a structure can be obtained in which insulating film is formed between gate electrodes and Schottky electrodes, between the gate electrodes and a source region, between the gate electrodes and a body region, and between the gate electrodes and a drain region, and in which insulating film is not formed between the Schottky electrodes and the drain region. | 2015-01-22 |
20150021681 | SEMICONDUCTOR DEVICE HAVING METAL GATE AND MANUFACTURING METHOD THEREOF - A manufacturing method of a semiconductor device having metal gate includes providing a substrate having a first semiconductor device formed thereon, and the first semiconductor device includes a first dummy gate. Next, the dummy gate is removed to form a first gate trench in the first semiconductor device, and the substrate is exposed in a bottom of the first gate trench. Subsequently, an epitaxial channel layer is formed in the first gate trench. | 2015-01-22 |
20150021682 | NORMALLY ON HIGH VOLTAGE SWITCH - In some embodiments, a normally on high voltage switch device (“normally on switch device”) incorporates a trench gate terminal and buried doped gate region. In other embodiments, a surface gate controlled normally on high voltage switch device is formed with trench structures and incorporates a surface channel controlled by a surface gate electrode. The surface gate controlled normally on switch device may further incorporate a trench gate electrode and a buried doped gate region to deplete the conducting channel to aid in the turning off of the normally on switch device. The normally on switch devices thus constructed can be readily integrated with MOSFET devices and formed using existing high voltage MOSFET fabrication technologies. | 2015-01-22 |
20150021683 | METHODS OF FORMING SEMICONDUCTOR DEVICE WITH SELF-ALIGNED CONTACT ELEMENTS AND THE RESULTING DEVICES - One method disclosed herein includes forming a sacrificial etch stop material in a recess above a replacement gate structure, with the sacrificial etch stop material in position, forming a self-aligned contact that is conductively coupled to the source/drain region, after forming the self-aligned contact, performing at least one process operation to expose and remove the sacrificial etch stop material in the recess so as to thereby re-expose the recess, and forming a third layer of insulating material in at least the re-exposed recess. | 2015-01-22 |