04th week of 2009 patent applcation highlights part 13 |
Patent application number | Title | Published |
20090020812 | METAL-OXIDE-SEMICONDUCTOR DEVICE - A MOS device includes a semiconductor substrate having a first conductive type, a source region, a gate structure, and a drain region having a second conductive type. The gate structure is formed on the semiconductor substrate and substantially parallel to a first direction. The source region and the drain region are both disposed in the semiconductor substrate, and on two opposite sides of the gate structure. The source region includes at least a source doped region having the second conductive type, and at least a source contact region having the first conductive type, and the source doped region and the source contact region are alternately arranged along the first direction. | 2009-01-22 |
20090020813 | FORMATION OF LATERAL TRENCH FETS (FIELD EFFECT TRANSISTORS) USING STEPS OF LDMOS (LATERAL DOUBLE-DIFFUSED METAL OXIDE SEMICONDUCTOR) TECHNOLOGY - A semiconductor structure and a method forming the same. The method includes providing a semiconductor structure which includes a semiconductor substrate. The semiconductor substrate includes a top substrate surface which defines a reference direction perpendicular to the top substrate surface. The method further includes simultaneously forming a first doped transistor region of a first transistor and a first doped Source/Drain portion of a second transistor on the semiconductor substrate. The first doped transistor region is not a portion of a Source/Drain region of the first transistor. The first doped transistor region and the first doped Source/Drain portion comprise dopants of a first doping polarity. The method further includes forming a second gate dielectric layer and a second gate electrode region of the second transistor on the semiconductor substrate. The second gate dielectric layer is sandwiched between and electrically insulates the second gate electrode region and the semiconductor substrate. | 2009-01-22 |
20090020814 | High Voltage Semiconductor Device with Floating Regions for Reducing Electric Field Concentration - A high voltage semiconductor device includes a source region of a first conductivity type having an elongated projection with two sides and a rounded tip in a semiconductor substrate. A drain region of the first conductivity type is laterally spaced from the source region in the semiconductor substrate. A gate electrode extends along the projection of the source region on the semiconductor substrate between the source and drain regions. Top floating regions of a second conductivity type are disposed between the source and drain regions in the shape of arched stripes extending along the rounded tip of the projection of the source region. The top floating regions are laterally spaced from one another by regions of the first conductivity type to thereby form alternating P-N regions along the lateral dimension. | 2009-01-22 |
20090020815 | Semiconductor device and manufacturing method of the same - An object of the present invention is to provide a semiconductor device having a structure which can realize not only suppressing a punch-through current but also reusing a silicon wafer which is used for bonding, in manufacturing a semiconductor device using an SOI technique, and a manufacturing method thereof. The semiconductor device can suppress the punch-through current by forming a semiconductor film in which an impurity imparting a conductivity type opposite to that of a source region and a drain region is implanted over a substrate having an insulating surface, and forming a channel formation region using a semiconductor film of stacked layers obtained by bonding a single crystal semiconductor film to the semiconductor film by an SOI technique. | 2009-01-22 |
20090020816 | SEMICONDUCTOR DEVICE AND METHOD OF FORMING THE SAME - One embodiment generally described herein can be characterized as a semiconductor device. The semiconductor device can include a first transistor on a semiconductor substrate. A first interlayer insulating layer may be disposed over the first transistor and includes a first recess region. A single-crystalline semiconductor pattern may be disposed in the first recess region. A single-crystalline semiconductor plug may connect the semiconductor substrate to the single-crystalline semiconductor pattern. A second transistor may be disposed on the single-crystalline semiconductor pattern. | 2009-01-22 |
20090020817 | Semiconductor device having a plurality of stacked transistors and method of fabricating the same - A semiconductor device according to example embodiments may have a plurality of stacked transistors. The semiconductor device may have a lower insulating layer formed on a semiconductor substrate and an upper channel body pattern formed on the lower insulating layer. A source region and a drain region may be formed within the upper channel body pattern, and a non-metal transfer gate electrode may be disposed on the upper channel body pattern between the source and drain regions. The non-metal transfer gate electrode, the upper channel body pattern, and the lower insulating layer may be covered by an intermediate insulating layer. A metal word line may be disposed within the intermediate insulating layer to contact at least an upper surface of the non-metal transfer gate electrode. An insulating spacer may be disposed on a sidewall of the metal word line. A metal node plug may be disposed within the intermediate insulating layer and the lower insulating layer to contact the source region of the upper channel body pattern. Example embodiments also relate to a method of fabricating the above semiconductor device. | 2009-01-22 |
20090020818 | SEMICONDUCTOR DIODE STRUCTURES - A semiconductor structure and a method for operating the same. The method includes providing a semiconductor structure. The semiconductor structure includes first, second, third, and fourth doped semiconductor regions. The second doped semiconductor region is in direct physical contact with the first and third doped semiconductor regions. The fourth doped semiconductor region is in direct physical contact with the third doped semiconductor region. The first and second doped semiconductor regions are doped with a first doping polarity. The third and fourth doped semiconductor regions are doped with a second doping polarity. The method further includes (i) electrically coupling the first and fourth doped semiconductor regions to a first node and a second node of the semiconductor structure, respectively, and (ii) electrically charging the first and second nodes to first and second electric potentials, respectively. The first electric potential is different from the second electric potential. | 2009-01-22 |
20090020819 | FIN-TYPE FIELD EFFECT TRANSISTOR STRUCTURE WITH MERGED SOURCE/DRAIN SILICIDE AND METHOD OF FORMING THE STRUCTURE - Disclosed herein are embodiments of a multiple fin fin-type field effect transistor (i.e., a multiple fin dual-gate or tri-gate field effect transistor) in which the multiple fins are partially or completely merged by a highly conductive material (e.g., a metal silicide). Merging the fins in this manner allow series resistance to be minimized with little, if any, increase in the parasitic capacitance between the gate and source/drain regions. Merging the semiconductor fins in this manner also allows each of the source/drain regions to be contacted by a single contact via as well as more flexible placement of that contact via. | 2009-01-22 |
20090020820 | CHANNEL-STRESSED SEMICONDUCTOR DEVICES AND METHODS OF FABRICATION - In one aspect, a method of fabricating a semiconductor device is provided. The method includes forming at least one capping layer over epitaxial source/drain regions of a PMOS device, forming a stress memorization (SM) layer over the PMOS device including the at least one capping layer and over an adjacent NMOS device, and treating the SM layer formed over the NMOS and PMOS devices to induce tensile stress in a channel region of the NMOS device. | 2009-01-22 |
20090020821 | DUAL WORKFUNCTION SEMICONDUCTOR DEVICE - A dual workfunction semiconductor device which comprises a first and second control electrode comprising a metal-semiconductor compound, e.g. a silicide or a germanide, and a dual workfunction semiconductor device thus obtained are disclosed. In one aspect, the method comprises forming a blocking region for preventing diffusion of metal from the metal-semiconductor compound of the first control electrode to the metal-semiconductor compound of the second control electrode, the blocking region being formed at a location where an interface between the first and second control electrodes is to be formed or is formed. By preventing metal to diffuse from the one to the other control electrode the constitution of the metal-semiconductor compounds of the first and second control electrodes may remain substantially unchanged during e.g. thermal steps in further processing of the device. | 2009-01-22 |
20090020822 | SEMICONDUCTOR DEVICE AND METHOD FOR FABRICATING THE SAME - A semiconductor device includes an n-type MIS transistor and a p-type MIS transistor. The n-type MIS transistor includes a first gate electrode formed on a first active region and a first sidewall formed on the side face of the first gate electrode. The p-type MIS transistor includes a second gate electrode formed on a second active region, a second sidewall formed on the side face of the second gate electrode and strain layers formed in the second active region. The second sidewall has a smaller thickness than the first sidewall. | 2009-01-22 |
20090020823 | SEMICONDUCTOR DEVICE AND METHOD FOR MANUFACTURING THE SAME - A semiconductor device of the present invention includes a first transistor, a first stress-inducing film, a first insulating film, and a second insulating film. The first transistor is formed in a first active region of a semiconductor substrate, and includes a first gate electrode. The first stress-inducing film is formed so as to cover the first gate electrode, and applies a stress to the channel region of the first transistor. The first insulating film is formed on the first stress-inducing film and has a planarized upper surface. The second insulating film is formed on the first insulating film. | 2009-01-22 |
20090020824 | SEMICONDUCTOR DEVICE AND METHOD FOR PRODUCING THE SAME - A complementary semiconductor device comprising an n-channel transistor and a p-channel transistor, including: the n-channel transistor including a gate insulating film and a first metal gate electrode formed on the gate insulating film and having a first compound layer including a first metal (M | 2009-01-22 |
20090020825 | Forming dual metal complementary metal oxide semiconductor integrated circuits - Complementary metal oxide semiconductor metal gate transistors may be formed by depositing a metal layer in trenches formerly inhabited by patterned gate structures. The patterned gate structures may have been formed of polysilicon in one embodiment. The metal layer may have a workfunction most suitable for forming one type of transistor, but is used to form both the n and p-type transistors. The workfunction of the metal layer may be converted, for example, by ion implantation to make it more suitable for use in forming transistors of the opposite type. | 2009-01-22 |
20090020826 | Integrated Schottky Diode and Power MOSFET - A semiconductor structure includes a semiconductor substrate; a first well region of a first conductivity type in the semiconductor substrate; a metal-containing layer on the first well region, wherein the metal-containing layer and the first well region form a Schottky barrier; and a first heavily doped region of the first conductivity type in the first well region, wherein the first heavily doped region is horizontally spaced apart from the metal-containing layer. | 2009-01-22 |
20090020827 | THIN GATE ELECTRODE CMOS DEVICES AND METHODS OF FABRICATING SAME - A CMOS device and method of forming the CMOS device. The device including a source and a drain formed in a semiconductor substrate, the source and the drain and separated by a channel region of the substrate; a gate dielectric formed on a top surface of the substrate and a very thin metal or metal alloy gate electrode formed on a top surface of the gate dielectric layer, a polysilicon line abutting and in electrical contact with the gate electrode, the polysilicon line thicker than the gate electrode. The method including, forming the gate electrode by forming a trench above the channel region and depositing metal into the trench. | 2009-01-22 |
20090020828 | SEMICONDUCTOR DEVICE AND ITS MANUFACTURING METHOD - A first MIS transistor includes a first source/drain region formed outside a first sidewall spacer in a first active region, a first silicide film formed on the first source/drain region, and a stressor insulating film formed on a first gate electrode, the first sidewall spacer, and the first silicide film. A second MIS transistor includes a second source/drain region formed outside a second sidewall spacer in a second active region, a first protection film formed, extending over a second gate electrode, the second sidewall spacer, and a portion of the second source/drain region, and including a first protection insulating film and a second protection insulating film, a second silicide film formed outside the first protection film on the second source/drain region, and the stressor insulating film formed on the first protection film and the second silicide film. | 2009-01-22 |
20090020829 | PRINTING OF CONTACT METAL AND INTERCONNECT METAL VIA SEED PRINTING AND PLATING - Methods of forming contacts (and optionally, local interconnects) using an ink comprising a silicide-forming metal, electrical devices such as diodes and/or transistors including such contacts and (optional) local interconnects, and methods for forming such devices are disclosed. The method of forming contacts includes depositing an ink of a silicide-forming metal onto an exposed silicon surface, drying the ink to form a silicide-forming metal precursor, and heating the silicide-forming metal precursor and the silicon surface to form a metal silicide contact. Optionally, the metal precursor ink may be selectively deposited onto a dielectric layer adjacent to the exposed silicon surface to form a metal-containing interconnect. Furthermore, one or more bulk conductive metal(s) may be deposited on remaining metal precursor ink and/or the dielectric layer. Electrical devices, such as diodes and transistors may be made using such printed contact and/or local interconnects. A metal ink may be printed for contacts as well as for local interconnects at the same time, or in the alternative, the printed metal can act as a seed for electroless deposition of other metals if different metals are desired for the contact and the interconnect lines. This approach advantageously reduces the number of processing steps and does not necessarily require any etching. | 2009-01-22 |
20090020830 | ASYMMETRIC FIELD EFFECT TRANSISTOR STRUCTURE AND METHOD - Disclosed are embodiments for a design structure of an asymmetric field effect transistor structure and a method of forming the structure in which both series resistance in the source region (R | 2009-01-22 |
20090020831 | Deuterated film encapsulation of nonvolatile charge trap memory device - A nonvolatile charge trap memory device with deuterium passivation of charge traps and method of manufacture. Deuterated gate layer, deuterated gate cap layer and deuterated spacers are employed in various combinations to encapsulate the device with deuterium sources proximate to the interfaces within the gate stack and on the surface of the gate stack where traps may be present. | 2009-01-22 |
20090020832 | Semiconductor Devices and the Manufacture Thereof - A power semiconductor device includes a semiconductor body ( | 2009-01-22 |
20090020833 | SEMICONDUCTOR DEVICE AND METHOD OF FABRICATING THE SAME - A method of fabricating a semiconductor device includes forming first spacers formed of a TEOS layer and second spacers formed of a first nitride layer on sidewalls of a gate electrode formed on a semiconductor substrate, and then forming source/drain regions in the semiconductor substrate using the first and second spacers and the gate electrode as masks, and then removing the second spacers, and then depositing a second nitride layer on an entire surface of the semiconductor substrate, and then implanting ions into the second nitride layer to generate compressive stress, and then etching the second nitride layer to form barrier nitride layers on the side walls of the first spacers. Because the barrier nitride has compressive stress, it is possible to prevent the movement of mobile ions, minimize influence on charge loss and charge gain in a flash memory device, and enhance a retention characteristic. | 2009-01-22 |
20090020834 | SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD THEREOF - In a MOSFET using SiC a p-type channel is formed by epitaxial growth, so that the depletion layer produced in the p-type region right under the channel is reduced, even when the device is formed in a self-aligned manner. Thus, a high breakdown voltage is obtained. Also, since the device is formed in a self-aligned manner, the device size can be reduced so that an increased number of devices can be fabricated in a certain area and the on-state resistance can be reduced. | 2009-01-22 |
20090020835 | INSULATING FILM AND ELECTRONIC DEVICE - An electronic device including a semiconductor layer containing silicon as a major component; and a dielectric film epitaxially grown directly on a major surface of the semiconductor layer, a difference between 2 | 2009-01-22 |
20090020836 | METHOD FOR MAKING A SEMICONDUCTOR DEVICE HAVING A HIGH-K GATE DIELECTRIC - A method for making a semiconductor device is described. That method comprises forming an oxide layer on a substrate, and forming a high-k dielectric layer on the oxide layer. The oxide layer and the high-k dielectric layer are then annealed at a sufficient temperature for a sufficient time to generate a gate dielectric with a graded dielectric constant. | 2009-01-22 |
20090020837 | Semiconductor device and manufacturing method thereof - A long channel semiconductor device and a manufacturing method thereof are provided. The method for forming a long channel semiconductor device includes: providing a substrate; forming a trench in the substrate with a trench bottom defining a first channel length; forming a spacer on a sidewall of the trench; recessing the trench bottom to form a recessed bottom defining a second channel length longer than the first channel length; forming a gate dielectric layer on the recessed bottom; forming a gate conductor on the gate dielectric layer; and forming source/drain regions in the substrate adjacent to the spacer. | 2009-01-22 |
20090020838 | APPARATUS AND METHOD FOR REDUCING OPTICAL CROSS-TALK IN IMAGE SENSORS - An image sensor device includes a semiconductor substrate having a front surface and a back surface; an array of pixels formed on the front surface of the semiconductor substrate, each pixel being adapted for sensing light radiation; an array of color filters formed over the plurality of pixels, each color filter being adapted for allowing a wavelength of light radiation to reach at least one of the plurality of pixels; and an array of micro-lens formed over the array of color filters, each micro-lens being adapted for directing light radiation to at least one of the color filters in the array. The array of color filters includes structure adapted for blocking light radiation that is traveling towards a region between adjacent micro-lens. | 2009-01-22 |
20090020839 | SEMICONDUCTOR LIGHT RECEIVING DEVICE AND METHOD FOR MANUFACTURING SAME - A semiconductor light receiving device includes a light receiving section made of a semiconductor provided on a substrate, an electrode provided on the substrate and configured to apply an electric field to the light receiving section, a resin layer provided above the substrate, the resin layer having an inverted conical opening, the inverted conical opening being located above the light receiving section and having an opening diameter which is smaller than the light receiving section in the vicinity of the light receiving section, is continuously enlarged with the distance from the substrate, and is larger than the light receiving section at a surface of the resin layer, and a light reflecting film made of metal and provided on a bevel of the inverted conical opening, the light reflecting film being electrically isolated from the electrode by a gap formed between the light reflecting film and the electrode. At least a portion of the resin layer located in the gap has a light blocking property. | 2009-01-22 |
20090020840 | SOLID-STATE IMAGING DEVICE, SOLID-STATE IMAGING APPARATUS AND MANUFACTURING METHOD THEREOF - A solid-state imaging apparatus includes a plurality of unit pixels with associated microlenses arranged in a two-dimensional array. Each microlens includes a distributed index lens with a modulated effective refractive index distribution obtained by including a combination of a plurality of patterns having a concentric structure, the plurality of patterns being divided into line widths equal to or shorter than a wavelength of an incident light. At least one of the plurality of patterns includes a lower light-transmitting film having the concentric structure and a first line width and a first film thickness, and an upper light-transmitting film having the concentric structure configured on the lower light-transmitting film having a second line width and a second film thickness. The distributed index lens has a structure in which a refractive index material is dense at a center and becomes sparse gradually toward an outer side in the concentric structure. | 2009-01-22 |
20090020841 | Mesa-Type Photodetectors With Lateral Diffusion Junctions - The present invention relates to a stable mesa-type photodetector with lateral diffusion junctions. The invention has found that without resorting to the complicated regrowth approach, a simple Zn diffusion process can be used to create high-quality semiconductor junction interfaces at the exposed critical surface or to terminate the narrow-bandgap photon absorption layers. The invention converts the epi material layers near or at the vicinity of the etched mesa trench or etched mesa steps into a different dopant type through impurity diffusion process. Preferably the diffused surfaces are treated with a subsequent surface passivation. This invention can be applied to both top-illuminating and bottom-illuminating configurations. | 2009-01-22 |
20090020842 | EMBEDDED BONDING PAD FOR BACKSIDE ILLUMINATED IMAGE SENSOR - The present disclosure provide a microelectronic device. The microelectronic device includes a sensing element formed in the semiconductor substrate; a trench isolation feature formed in the semiconductor substrate; a bonding pad formed at least partially in the trench isolation feature; and interconnect features formed over the sensing element and the trench isolation feature, being coupled to the sensing element and the bonding pad, and isolated from each other by interlayer dielectric. | 2009-01-22 |
20090020843 | Bottom anode Schottky diode structure and method - This invention discloses a bottom-anode Schottky (BAS) diode that includes an anode electrode disposed on a bottom surface of a semiconductor substrate. The bottom-anode Schottky diode further includes a sinker dopant region disposed at a depth in the semiconductor substrate extending substantially to the anode electrode disposed on the bottom surface of the semiconductor and the sinker dopant region covered by a buried Schottky barrier metal functioning as an Schottky anode. The BAS diode further includes a lateral cathode region extended laterally from a cathode electrode near a top surface of the semiconductor substrate opposite the Schottky barrier metal wherein the lateral cathode region doped with an opposite dopant from the sinker dopant region and interfacing the sinker dopant region whereby a current path is formed from the cathode electrode to the anode electrode through the lateral cathode region and the sinker dopant region in applying a forward bias voltage and the sinker dopant region depleting the cathode region in applying a reverse bias voltage for blocking a leakage current. | 2009-01-22 |
20090020844 | Semiconductor device having electrostatic discharge protection circuit and method of manufacturing the same - Semiconductor device having an on-chip type electrostatic discharge (ESD) protection circuit and a method of manufacturing the same are provided. The on-chip type ESD protection circuit may include a first junction diode having a first conductive type region contacting a second conductive type region in a semiconductor substrate, and a first schottky diode having a metallic material layer arranged on and contacting the first conductive type region of the semiconductor substrate. | 2009-01-22 |
20090020845 | SHALLOW TRENCH ISOLATION STRUCTURES FOR SEMICONDUCTOR DEVICES INCLUDING DOPED OXIDE FILM LINERS AND METHODS OF MANUFACTURING THE SAME - A semiconductor device includes a substrate having a trench, a sidewall liner that covers inner walls of the trench, a doped oxide film liner on the sidewall liner in the trench, and a gap-fill insulating film that buries the trench on the doped oxide film liner. In order to form the doped oxide film liner, an oxide film liner is doped with a dopant under a plasma atmosphere. Related methods are also disclosed. | 2009-01-22 |
20090020846 | DIODE FOR ADJUSTING PIN RESISTANCE OF A SEMICONDUCTOR DEVICE - A diode comprises a P-type well formed in a semiconductor substrate, at least one N-type impurity doping area formed in the P-type well, an isolation area formed to surround the N-type impurity doping area, a P-type impurity doping area formed to surround the isolation area, first contacts formed in the N-type impurity doping area in a single row or a plurality of rows, and second contacts formed in the P-type impurity doping area in a single row or a plurality of rows, wherein pin resistance can be adjusted through changing any one of a distance between the N-type impurity doping area and the P-type impurity doping area, a contact pitch between the first contacts, and a contact pitch between the second contacts. | 2009-01-22 |
20090020847 | Semiconductor device having trench isolation region and methods of fabricating the same - A semiconductor device having a trench isolation region and methods of fabricating the same are provided. The method includes forming a first trench region in a substrate, and a second trench region having a larger width than the first trench region in the substrate. A lower material layer may fill the first and second trench regions. The lower material layer may be etched by a first etching process to form a first preliminary lower material layer pattern remaining in the first trench region and form a second preliminary lower material layer pattern that remains in the second trench region. An upper surface of the second preliminary lower material layer pattern may be at a different height than the first preliminary lower material layer pattern. The first and second preliminary lower material layer patterns may be etched by a second etching process to form first and second lower material layer patterns having top surfaces at substantially the same height. First and second upper material layer patterns may be formed on the first and second lower material layer patterns, respectively. | 2009-01-22 |
20090020848 | HIGH-FREQUENCY TRANSISTOR - A high-frequency transistor includes an intrinsic region provided to form an active element on the substrate, plural source and drain fingers alternately located with each other in the intrinsic region in parallel, each including a strip-form interconnect metal layer and contacts formed thereon, plural gate fingers respectively formed between the source and drain fingers and each gate finger including a strip-form gate semiconductor layer, a connecting region provided on the substrate adjacent to and outside of the intrinsic region, plural gate connection semiconductor layers provided in the connecting region according to groups of the gate fingers, each group including some gate fingers adjacent to each other, each gate connection semiconductor layer being connected to end portions of the some gate fingers, and gate connection interconnect metal layers respectively formed on the gate connection semiconductor layers connected thereto through third contacts. | 2009-01-22 |
20090020849 | ELECTRONIC DEVICE INCLUDING A CAPACITOR AND A PROCESS OF FORMING THE SAME - An electronic device can include electronic components and an insulating layer overlying the electronic components. The electronic device can also include a capacitor overlying the insulating layer, wherein the capacitor includes a first electrode and a second electrode. The second electrode can include an opening, wherein from a top view, a defect lies within the opening. In another aspect, a process of forming an electronic device can include forming a first capacitor electrode layer over a substrate, forming a dielectric layer over the first capacitor electrode layer, and forming a second capacitor electrode layer over the dielectric layer. The process can also include detecting a defect and removing a first portion of the second capacitor electrode layer corresponding to the defect, wherein a second portion of the second capacitor electrode layer remains over the dielectric layer. | 2009-01-22 |
20090020850 | SEMICONDUCTOR DESIGN APPARATUS, SEMICONDUCTOR CIRCUIT AND SEMICONDUCTOR DESIGN METHOD - According to an aspect of the present invention, there is provided a semiconductor design apparatus including: a determination section that determines a connection position of a capacitor to suppress a noise on a layout data in which a layout of circuit cells are completed; a calculation section that calculates a capacitance value required to suppress the noise; a generation section that generates the capacitor satisfying the capacitance value; and a wiring section that wires the capacitor to a power wiring and a ground wiring at the connection position. | 2009-01-22 |
20090020851 | BICMOS DEVICES WITH A SELF-ALIGNED EMITTER AND METHODS OF FABRICATING SUCH BICMOS DEVICES - A method of fabricating an heterojunction bipolar transistor (HBT) structure in a bipolar complementary metal-oxide-semiconductor (BiCMOS) process selectively thickens an oxide layer overlying a base region in areas that are not covered by a temporary emitter and spacers such that the temporary emitter can be removed and the base-emitter junction can be exposed without also completely removing the oxide overlying the areas of the base region that are not covered by the temporary emitter or spacers. As a result, a photomask is not required to remove the temporary emitter and to expose the base-emitter junction. | 2009-01-22 |
20090020852 | SEMICONDUCTOR DEVICE - An emitter layer is provided in stripes in a direction orthogonal to an effective gate trench region connected to a gate electrode and a dummy trench region isolated from the gate electrode. A width of the emitter layer is determined to satisfy a predetermined relational expression so as not to cause latch-up in an underlying P base layer. In the predetermined relational expression, an upper limit value of the width W of the emitter layer is (3500/Rspb)·Wso·exp(decimation ratio), where Rspb is a sheet resistance of the P base layer immediately below the emitter layer, Wso is an interval between the trenches, and the decimation ratio is a ratio of the number of the effective gate trench region to the total number of the trench regions. Variations in saturation current in a trench IGBT can be suppressed, and a tolerance of an Reverse Bias Safe Operation Area can be improved. | 2009-01-22 |
20090020853 | STRUCTURES OF AND METHODS FOR FORMING VERTICALLY ALIGNED Si WIRE ARRAYS - A structure consisting of vertically aligned wire arrays on a Si substrate and a method for producing such wire arrays. The wire arrays are fabricated and positioned on a substrate with an orientation and density particularly adapted for conversion of received light to energy. A patterned oxide layer is used to provide for wire arrays that exhibit narrow diameter and length distribution and provide for controlled wire position. | 2009-01-22 |
20090020854 | Process of forming ultra thin wafers having an edge support ring - A process of forming ultra thin wafers having an edge support ring is disclosed. The process provides an edge support ring having an angled inner wall compatible with spin etch processes. | 2009-01-22 |
20090020855 | METHOD FOR STACKING SERIALLY-CONNECTED INTEGRATED CIRCUITS AND MULTI-CHIP DEVICE MADE FROM SAME - A multi-chip device and method of stacking a plurality substantially identical chips to produce the device are provided. The multi-chip device, or circuit, includes at least one through-chip via providing a parallel connection between signal pads from at least two chips, and at least one through-chip via providing a serial or daisy chain connection between signal pads from at least two chips. Common connection signal pads are arranged symmetrically about a center line of the chip with respect to duplicate common signal pads. Input signal pads are symmetrically disposed about the center line of the chip with respect to corresponding output signal pads. The chips in the stack are alternating flipped versions of the substantially identical chip to provide for this arrangement. At least one serial connection is provided between signal pads of stacked and flipped chips when more than two chips are stacked. | 2009-01-22 |
20090020856 | SEMICONDUCTOR DEVICE STRUCTURES AND METHODS FOR SHIELDING A BOND PAD FROM ELECTRICAL NOISE - Semiconductor device structures and methods for shielding a bond pad from electrical noise generated by active circuitry of an integrated circuit carried on a substrate. The structure includes electrically characterized devices placed in a pre-determined arrangement under the bond pad. The pre-determined arrangement of the electrically characterized devices provides for a consistent high frequency environment under the bond pad, which simplifies modeling of the bond pad by a circuit designer. | 2009-01-22 |
20090020857 | SYSTEM AND METHOD FOR ROUTING SUPPLY VOLTAGES OR OTHER SIGNALS BETWEEN SIDE-BY-SIDE DIE AND A LEAD FRAME FOR SYSTEM IN A PACKAGE (SIP) DEVICES - An integrated circuit or chip includes a first die and a second die positioned on a lead frame of a package including a lead frame, such as a QFP, DIP, PLCC, TSOP, or any other type of package including a lead frame. The integrated circuit further includes a redistribution layer formed on the first die to couple selected bond fingers of the lead frame to selected bonding pads of the first and second die. The selected bond fingers may correspond to bond fingers that receive a first supply voltage or the first supply voltage and a second supply voltage. | 2009-01-22 |
20090020858 | TAPE CARRIER SUBSTRATE AND SEMICONDUCTOR DEVICE - The present invention provides a tape carrier substrate that can prevent a conductor wire on the tape carrier substrate from being broken at the boundary portion between the conductor wire and a slit formed in a folding portion of the tape carrier substrate. The slit is formed in the folding portion of the tape carrier substrate so that the width thereof located on an extensional portion side of the tape carrier substrate is larger than that located on a central portion side of the tape carrier substrate. Possible stress resulting from bending of the tape carrier substrate is thus distributed. This prevents the stress from concentrating at the boundary portion between the slit and the conductor wire. | 2009-01-22 |
20090020859 | QUAD FLAT PACKAGE WITH EXPOSED COMMON ELECTRODE BARS - An electronic package is provided. The electronic package comprises a die pad having a die attached thereon. A plurality of leads surrounds the die pad and spaced therefrom to define a ring gap therebetween. At least one first common electrode bar is in the ring gap and substantially coplanar to the die pad, in which at least one of the plurality of leads extends to the first common electrode bar. A molding compound partially encapsulates the die pad and the first common electrode bar, such that the bottom surfaces of the die pad and the first common electrode bar are exposed. An electronic device with the electronic package is also disclosed. | 2009-01-22 |
20090020860 | SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD OF THE SAME - A semiconductor device of a multi-pin structure using a lead frame is provided. The semiconductor device comprises a tab having a chip supporting surface, the chip supporting surface whose dimension is smaller than a back surface of a semiconductor chip, a plurality of leads arranged around the tab, the semiconductor chip mounted over the chip supporting surface of the tab, a plurality of suspending leads for supporting the tab, four bar leads arranged outside the tab so as to surround the tab and coupled to the suspending leads, a plurality of wires for coupling between the semiconductor chip and the leads, and a sealing body for sealing the semiconductor chip and the wires with resin, with first slits being formed respectively in first coupling portions of the bar leads for coupling with the suspending leads. | 2009-01-22 |
20090020861 | SEMICONDUCTOR DEVICE - A module including a carrier and a semiconductor chip applied to the carrier. An external contact element is provided having a first portion and a second portion extending perpendicular to the first portion, wherein a thickness of the second portion is smaller than a thickness of the carrier. | 2009-01-22 |
20090020862 | DEVICE STRUCTURE WITH PREFORMED RING AND METHOD THEREFOR - A device structure with preformed ring includes a sensor chip and a ring disposed and surrounded on periphery of sensitive area of an active surface thereof. The device structure with preformed ring may batchly bind and electrically connect to a carrier by a way of two-dimension array, and then a packaging process is performed. During the packaging process, the top portion of the ring can be used to against the inner side of a packaging mold, so as to stop the packaging material covering the device at outside of the ring and stick with the ring. Therefore, an opening is formed on the sensitive area surface of the device. Depending on the ring, the extra process for eliminating the packaging material on the sensitive area surface can be avoided in the conventional process. | 2009-01-22 |
20090020863 | Stacked semiconductor devices and signal distribution methods thereof - A stacked semiconductor device includes a plurality of stacked chips, each having a plurality of elements to receive a signal. At least one first ladder main signal line for receiving the signal is arranged to pass through the chips. At least one second ladder main signal line is arranged to pass through the chips. A plurality of ladder buffers buffer the signal applied from the first ladder main signal line to the second ladder main signal line. The signal is uniformly distributed to the stacked chips using a ladder type circuit network technique. | 2009-01-22 |
20090020864 | Wafer Level package Structure and Fabrication Methods - A method of forming a package structure with reduced damage to semiconductor dies is provided. The method includes providing a die comprising bond pads on a top surface of the die; forming bumps on the bond pads of the die, wherein the bumps have top surfaces higher than the top surface of the die; mounting the die on a chip carrier, wherein the bumps are attached to the chip carrier; molding the die onto the chip carrier with a molding compound; de-mounting the chip carrier from the die; and forming redistribution traces over, and electrically connected to, the bumps of the die. | 2009-01-22 |
20090020865 | Method for Packaging Semiconductor Dies Having Through-Silicon Vias - An integrated circuit structure is provided. The integrated circuit structure includes a die and an anisotropic conducing film (ACF) adjoining the back surface of the die. The die includes a front surface; a back surface on an opposite side of the die than the front surface; and a through-silicon via (TSV) exposed through the back surface of the die. | 2009-01-22 |
20090020866 | SEMICONDUCTOR DEVICES AND MANUFACTURING METHODS THEREFOR - A semiconductor device includes: a package case in which a semiconductor element is mounted, the package case having a bonding portion; a cap having a bonding portion bonded to the bonding portion of the package case so as to hermetically seal the semiconductor element; and one or more bonding/sealing wires disposed between and in contact with the bonding portion of the package case and the bonding portion of the cap such that the one or more bonding/sealing wires form a closed loop and hermetically seal the semiconductor element. | 2009-01-22 |
20090020867 | SEMICONDUCTOR DEVICE - A semiconductor device, includes: a wiring substrate having a wiring pattern on a front surface thereof; a first semiconductor chip mounted on the front surface of the wiring substrate; a first heat radiator having a first recess housing the first semiconductor chip and making contact with the front surface of the wiring substrate and the first semiconductor chip directly or with a first insulation layer; a second heat radiator making contact with a rear surface of the wiring substrate directly or with a second insulation layer; and a first fixing member passing through the first heat radiator, the wiring substrate, and the second heat radiator, and pressing the first heat radiator and the second heat radiator to the wiring substrate. | 2009-01-22 |
20090020868 | Integrated circuit package and system interface - An apparatus for enhancing the performance of an IC package and media interface. Adding a fissure to a Flip-Chip type package improves the crosstalk performance of the package for both high and low frequencies. The wall of the fissure can be implemented with a heat spreader layer and can be connected to any AC ground such as VSS or VDD package planes. The fissures can also accommodate the ingress of an optical fiber, which allows for a direct interface with the transceivers. The direct optical fiber interface permits the removal of solder balls for high speed signal traces, with their respective vias. On-chip integrated LEDs or other similar light source transceivers can drive the high speed signal media. Selective deposition of low dielectric material can also improve the frequency response of high speed signal package traces. | 2009-01-22 |
20090020869 | INTERCONNECT JOINT - An interconnect joint comprises a substrate ( | 2009-01-22 |
20090020870 | ELECTRONIC DEVICE PROVIDED WITH WIRING BOARD, METHOD FOR MANUFACTURING SUCH ELECTRONIC DEVICE AND WIRING BOARD FOR SUCH ELECTRONIC DEVICE - An electronic device ( | 2009-01-22 |
20090020871 | SEMICONDUCTOR CHIP WITH SOLDER BUMP SUPPRESSING GROWTH OF INTER-METALLIC COMPOUND AND METHOD OF FABRICATING THE SAME - A semiconductor chip having a solder bump and a method of fabricating the same are provided. Conventionally, an inter-metallic compound (IMC) unexpectedly grows at an interface of the solder bump by means of heat generated during operation of the semiconductor chip, thereby weakening mechanical property of the semiconductor chip. To solve this drawback, the semiconductor chip includes at least one metal adhesion layer formed on an electrode pad of the semiconductor chip, an interlayer isolation layer formed on the metal adhesion layer, at least one penetration layer formed on the interlayer isolation layer and penetrating into the solder bump, and the solder bump formed on the penetration layer. Thereby, materials of the penetration layer penetrate into the solder bump to change the solder bump into a multi-component solder bump, so that the growth of the IMC is suppressed, and the reliability of the semiconductor chip can be improved. | 2009-01-22 |
20090020872 | WIRE BONDING METHOD AND SEMICONDUCTOR DEVICE - In order to prevent bonded wires from being damaged during another wire bonding in a semiconductor device, there is provided a wire bonding method for wire-connecting pads on a semiconductor chip and multiple leads corresponding to the pads in a semiconductor device to be manufactured by sealing the semiconductor chip and the leads together in one block, in which bumps and are formed with an ultrasonic vibration on all of the pads on the semiconductor chip and the leads included in the one block, and then wires are provided, with no ultrasonic vibration, for connection between the bumps and on the pads and the leads. | 2009-01-22 |
20090020873 | SEMICONDUCTOR APPARATUS, AND METHOD OF MANUFACTURING SEMICONDUCTOR APPARATUS - A semiconductor apparatus includes a semiconductor chip in which a plurality of electrode pads are provided on a main surface, and a plurality of bump electrodes are provided on the electrode pads of the semiconductor chip. The semiconductor apparatus also includes a wired board which is allocated in a side of the main surface of the semiconductor chip, and is positioned in a central area of the main surface of the semiconductor chip so as to be separated from an edge part of the semiconductor chip by at least 50 μm or more. The semiconductor apparatus also includes a plurality of external terminals which are provided on the wired board, and which are electrically connected to a plurality of bump electrodes through wirings of the wired board, and sealing part which is provided between the semiconductor chip and the wired board, is made of underfill material that covers a connection part between the bump electrode and the wiring. | 2009-01-22 |
20090020874 | SEMICONDUCTOR DEVICE AND METHOD FOR MANUFACTURING SEMICONDUCTOR DEVICE - A semiconductor device according to the present invention is provided with a semiconductor chip in which a plurality of electrode pads is provided on a principal surface, a plurality of bump electrodes provided on the electrode pads of the semiconductor chip, a square-shaped wiring board which is disposed on a side of the principal surface of the semiconductor chip, and in which at least two sides of an outer circumference that face each other are positioned in an area on the principal surface of the semiconductor chip, a plurality of external terminals which is provided on the wiring board, and which are electrically connected to a plurality of the bump electrodes through a wiring of the wiring board, and sealing material which is provided between the semiconductor chip and the wiring board, and which covers a connection part between the bump electrode and the wiring. | 2009-01-22 |
20090020875 | Semiconductor Device and Manufacturing Method Thereof - A semiconductor device is provided. The semiconductor device includes a substrate in which a first interlayer insulation layer having a first via hole and a first trench is formed. The semiconductor device also includes a first via plug and a first metal line respectively formed by filling the first via hole and the first trench with a first metal, a predetermined scratch being formed on the first metal line; and a second via plug a second metal line respectively formed by filling a second via hole and a second trench with a second metal, the second metal lines being separated. | 2009-01-22 |
20090020876 | HIGH TEMPERATURE PACKAGING FOR SEMICONDUCTOR DEVICES - A method of forming multiple bonds on an electronic device includes heating first bonding metals at a predetermined temperature to form a first bond comprising a first melting temperature above the predetermined temperature. The first bond and second bonding metals are then heated at the predetermined temperature to form a second bond comprising a second melting temperature above the predetermined temperature. | 2009-01-22 |
20090020877 | TRANSMISSION LINE STRUCTURE AND SIGNAL TRANSMISSION STRUCTURE - A transmission line structure includes a routing trace, a doped region and a first guard trace. The routing trace is disposed over a substrate. The doped region is disposed in the substrate and the projection of at least the partial routing trace falls within the doped region. The first guard trace is located over the substrate and disposed with a space from the routing trace, wherein the first guard trace is grounded and electrically coupled with the doped region. In addition, the conductivity of the first guard trace is higher than the conductivity of the doped region. | 2009-01-22 |
20090020878 | SEMICONDUCTOR PACKAGES AND METHODS OF FABRICATING THE SAME - A semiconductor package is provided. The semiconductor package includes a semiconductor device having a bonding pad and an interlayer insulating layer disposed on the semiconductor device. The interlayer insulating layer has an opening which exposes the bonding pad and has at least one cavity therein. A redistributed interconnection is disposed on the interlayer insulating layer and electrically connected to the exposed bonding pad. The redistributed interconnection is disposed over the cavity. A method of fabricating the semiconductor package is also provided. | 2009-01-22 |
20090020879 | WIRING STRUCTURE IN SEMICONDUCTOR DEVICE AND METHOD OF FABRICATING WIRING STRUCTURE IN SEMICONDUCTOR DEVICE - A wiring structure in a semiconductor device includes a first insulation layer formed on a substrate having first and second contact regions, and first and second pads extending through the first insulation layer and contacting the first and the second contact regions. The first and the second pads are higher than the first insulation layer. A blocking layer pattern is formed on the first insulation layer between the first and the second pads, the blocking layer pattern being higher than the first and the second pads. A second insulation layer is formed on the blocking layer pattern and the first and the second pads. A bit line structure is formed on the second insulation layer, the bit line structure electrically contacting the second pad. A third insulation layer is formed on the second insulation layer and the bit line structure. A plug extends through the second and the third insulation layers and contacts the first pad. | 2009-01-22 |
20090020880 | WIRING STRUCTURE IN A SEMICONDUCTOR DEVICE AND METHOD OF FORMING A WIRING STRUCTURE IN A SEMICONDUCTOR DEVICE - A wiring structure includes a first insulation layer located on a substrate, and first and second plugs located on the substrate and extending through the first insulation layer. The first plug includes an upper peripheral portion that defines a recess and the second plug is adjacent to the first plug. A second insulation layer is located on the first insulation layer, the first plug and the second plug. A bit line structure is located on the second insulation layer and is electrically connected to the first plug. A protection spacer is located on the recess of the first plug and a sidewall of an opening in the second insulation layer. The opening exposes the recess of the first plug, the second plug and the sidewall of the bit line structure. A pad is located in the opening and contacts the second plug. | 2009-01-22 |
20090020881 | SEMICONDUCTOR DEVICE PACKAGE AND FABRICATING METHOD THEREOF - A semiconductor device package and fabricating method thereof are disclosed, by which heat-dissipation efficiency is enhanced in a system by interconnection (SBI) structure. An exemplary semiconductor device package may include a substrate, at least two chips mounted on the substrate to have a space between one or more of the chips and an edge of the substrate, an insulating layer covering the chips, the insulating layer having via holes exposing portions of the at least two chips and a trench between the via holes, the insulating layer having at least two hole patterns within the space, and a metal layer filling the via holes and the trench. | 2009-01-22 |
20090020882 | Semiconductor device and method of producing the same - A semiconductor device includes a package substrate having a front surface and a backside surface; an electrode pad formed on the front surface; an outer connection pad formed on the backside surface and electrically connected to the electrode pad; a semiconductor chip mounted on the front surface and having an electrode electrically connected to the electrode pad; a sealing resin layer having a through hole formed with a die-molding and reaching the electrode pad for sealing the semiconductor chip; and a through electrode filled in the through hole with a conductive material and having one end portion electrically connected to the electrode pad and the other end portion exposed from the sealing resin layer. | 2009-01-22 |
20090020883 | SEMICONDUCTOR DEVICE AND METHOD FOR FABRICATING SEMICONDUCTOR DEVICE - A semiconductor device includes a first contact plug arranged above a semiconductor substrate and using aluminum (Al) as a material; a second contact plug arranged on and in contact with the first contact plug and using a refractory metal material; a first dielectric film arranged on a flank side of the first and second contact plugs; a wire arranged above the second contact plug and using copper (Cu) as a material; a second dielectric film arranged on a flank side of the wire; and a barrier film arranged at least between the wire and the first dielectric film and between the wire and the second dielectric film. | 2009-01-22 |
20090020884 | SURFACE TREATMENT METHOD, SEMICONDUCTOR DEVICE AND METHOD OF FORMING THE SEMICONDUCTOR DEVICE - Provided are methods of surface treatment, semiconductor devices and methods of forming the semiconductor device. The methods of forming the semiconductor device include forming a first oxide layer and a second oxide layer on a substrate. The first and second oxide layers are patterned to form a contact hole exposing the substrate. A sidewall of the first oxide layer exposed by the contact hole reacts with HF to form a first reaction layer and a sidewall of the second oxide layer exposed by the contact hole reacts with NH | 2009-01-22 |
20090020885 | Semiconductor device and method of manufacturing the same - One embodiment in accordance with the invention can include a semiconductor device that includes a first substrate, a projection portion that has a first semiconductor chip mounted on the first substrate, a second substrate that is provided on the first substrate and is electrically coupled to the first substrate, and a second semiconductor chip that is mounted on the second substrate. An opening portion is formed by the second substrate. The projection portion is arranged in the opening portion. | 2009-01-22 |
20090020886 | SEMICONDUCTOR DEVICE AND METHOD OF FABRICATING THE SAME - Embodiments relate to a semiconductor device, which adopts no wiring or contact for electric connection of a plurality of chips, achieving improved fabrication efficiency and reducing fabrication costs thereof, and a method of fabricating the same. A System In Package (SIP) semiconductor device includes a plurality of first and second semiconductor chips each having a predetermined internal circuit and being bonded opposite each other, wherein the first and second semiconductor chips include, respectively, trenches formed in the centers thereof to have a predetermined depth. First and second metal electrodes are formed in inner bottom surfaces of the respective trenches to apply current to the respective internal circuits of the first and second semiconductor chips. A liquid-phase conductive material fills in a predetermined volume of the trenches for selective conduction of the first and second metal electrodes. A plurality of bonding portions formed in surfaces of the first and second semiconductor chips to correspond to each other for coupling of the first and second semiconductor chips. | 2009-01-22 |
20090020887 | SEMICONDUCTOR APPARATUS AND MANUFACTURING METHOD THEREOF - In a semiconductor apparatus in which plural semiconductor elements are stacked, metal wires whose one ends are connected to electrode terminals of the semiconductor elements are extended to the side surfaces of the semiconductor elements in an abutment state and the metal wires extended to the side surfaces of the semiconductor elements are bonded to a side surface wiring formed on side surfaces of the semiconductor elements by a conductive paste containing conductive particles. | 2009-01-22 |
20090020888 | CIRCUIT MODULE AND ELECTRICAL COMPONENT - In an electrical component including a solid-state circuit portion and a substrate connecting portion, the solid-state circuit portion includes: a supporting surface faced to and supported by the substrate connecting portion; and an opposing surface which is widened outside the supporting surface and which has an area enough to be opposed to another solid-state circuit portion. This structure makes it possible to arrange, on a circuit board, a plurality of the electrical components in a staggered manner in a height direction. | 2009-01-22 |
20090020889 | SEMICONDUCTOR APPARATUS AND MANUFACTURING METHOD THEREOF - A plurality of quadrilateral-shaped semiconductor elements are stacked on the one surface of a circuit substrate. A side surface wiring for making electrical connection between each of the electrode terminals of the semiconductor elements and a pad formed on the circuit substrate is formed by applying a conductive paste containing conductive particles. A metal wire whose one end is connected to the electrode terminal is extended along a tapered surface formed by cutting off an edge of the electrode terminal surface on which the electrode terminal is formed among edges formed along each of the sides of the semiconductor element. At least a part of the metal wire extended from each of the electrode terminals of the semiconductor elements to the tapered surface is electrically connected to the side surface wiring. | 2009-01-22 |
20090020890 | SEMICONDUCTOR DEVICE AND METHOD FOR MANUFACTURING THE SAME - A semiconductor device includes a first semiconductor chip having a pad electrode formed on an upper surface thereof; a resin section sealing the first semiconductor chip with the upper surface and a side surface of the first semiconductor chip being covered and a lower surface of the first semiconductor chip being exposed; a columnar electrode communicating between the upper surface and the lower surface of the resin section with the upper surface and the lower surface of the columnar electrode being exposed on the resin section and at least a part of the side surface of the columnar electrode being covered; and a bonding wire connecting the pad electrode and the columnar electrode with a part of the bonding wire being embedded in the columnar electrode as one end of the bonding wire being exposed on the lower surface of the columnar electrode and the remaining part of the bonding wire being covered with the resin section, and a method for manufacturing the same. | 2009-01-22 |
20090020891 | Methods to Achieve Precision Alignment for Wafter Scale Packages - Methods for manufacturing an integrated wafer scale package that reduces a potential misalignment between a chip and a pocket of a carrier substrate. According to one aspect of the present invention, a method for manufacturing a semiconductor device includes a photoresist layer disposed on a carrier substrate, a chip placed onto a surface of the photoresist layer. The photoresist layer is patterned using the chip as a mask. The chip is removed from the photoresist layer after the patterning step. A pocket is formed in the carrier substrate, and the chip that was removed is placed into the pocket formed in the carrier substrate. | 2009-01-22 |
20090020892 | SELECTIVELY ALTERING A PREDETERMINED PORTION OR AN EXTERNAL MEMBER IN CONTACT WITH THE PREDETERMINED PORTION - A method for selectively altering a predetermined portion of an object or an external member in contact with the predetermined portion of the object is disclosed. The method includes selectively electrically addressing the predetermined portion, thereby locally resistive heating the predetermined portion, and exposing the object, including the predetermined portion, to the external member. | 2009-01-22 |
20090020893 | INTEGRATED CIRCUIT PACKAGE SYSTEM WITH TRIPLE FILM SPACER - An integrated circuit package in package system includes: providing a substrate with a first wire-bonded die mounted thereover, and connected to the substrate with bond wires; mounting a triple film spacer above the first wire-bonded die, the triple film spacer having fillers in a first film and in a third film, and having a second film separating the first film and the third film, and the bond wires connecting the first wire-bonded die to the substrate are embedded in the first film; and encapsulating the first wire-bonded die, the bond wires, and the triple film spacer with an encapsulation. | 2009-01-22 |
20090020894 | Venturi jet structure for fuel delivery module of a fuel tank - A fuel delivery system includes a fuel tank having at least a main chamber. A reservoir is disposed in the main chamber. A fuel pump and venturi jet structure are provided in the reservoir. The venturi jet structure includes a jet inlet having a nozzle for receiving fuel from the fuel pump. A fuel inlet tube structure has a first end associated with the nozzle and a second end extending into a portion of the fuel tank. A mixing tube is in communication with, and downstream of, the jet inlet and the fuel inlet tube structure. An outlet is in communication with, and downstream of, the mixing tube. A length of the fuel inlet tube structure is greater than a length of the outlet, and the mixing tube is mounted so that an axis thereof is generally horizontal ±39.90 degrees with respect to the bottom surface of the reservoir. | 2009-01-22 |
20090020895 | Carburettor - A carburettor for a two stroke engine includes a flow duct comprising rich and lean flow passages separated by a partition, at least one fuel jet communicating with the rich passage, the partition including an aperture towards which the fuel jet is directed, and a substantially planar butterfly valve being received in the aperture so as to be pivotable between a first position, in which the flow duct is substantially closed and the aperture is substantially open, and a second position, in which the flow duct is substantially open and the aperture is substantially closed, the flow duct further comprising a venturi section located substantially upstream of the aperture, and wherein the venturi section extends only partially around a perimeter of the flow duct. | 2009-01-22 |
20090020896 | Packing arranged for an exchange of heat and/or materia... - A stacked packing column for heat and/or mass transfer has individual horizontal layers including a lower layer that has a greater density that initiates an accumulation, in particular flooding, and that is 1.5 to 10, preferably 2 to 3 times, greater than the density of an overlying upper layer. The upper layer forms oblique flow channels having lower sections that are more vertically aligned than respective upper sections. The lower sections of the flow channels have a larger cross section than the upper sections, and the sections of larger cross section open into the lower layer. | 2009-01-22 |
20090020897 | PROCESS FOR THE INCORPORATION OF NANOPHOSPHORS INTO MICRO-OPTICAL STRUCTURES - The invention relates to a process for the incorporation of nanophosphors (phosphors) into micro-optical structures, and to corresponding illuminants. In this impregnation process, a micro-optical system comprising inverse opal powders is filled with a dispersion of a nanophosphor. | 2009-01-22 |
20090020898 | Polymer blends for producing films with a reduced number of defects - The invention relates to selected polymer blends which can be used for production of films or sheets having reduced defects, and also to a process for preparation of the polymer blends. | 2009-01-22 |
20090020899 | Method of manufacturing resin particles - Method of manufacturing resin particles capable of manufacturing resin particles of controlled particle size stably and efficiently by removing bubbles from the surface of a molten kneaded product as the raw material for resin particles thereby sufficiently ensuring action sites for a surfactant on the surface of the molten kneaded product, is provided. The method includes a coarsely-pulverizing step of pressurizing a mixture of a molten kneaded product containing a synthetic resin and an aqueous medium containing a surfactant to 15 MPa to 120 MPa thereby removing bubbles attached to the molten kneaded product containing the synthetic resin, and a finely-granulating step of finely granulating, by a high pressure homogenizer method, an aqueous slurry containing coarse particles of a molten kneaded product passing through a pressure proof nozzle in the coarsely-pulverizing step and in a state where bubbles attached to the surface are removed. | 2009-01-22 |
20090020900 | Process for Producing Resin Microparticles for a Toner Raw Material - An object of the present invention is to provide a resin microparticle for a toner raw material that has a small particle diameter and a narrow particle diameter distribution and has a low odor. | 2009-01-22 |
20090020901 | Process and device for producing a three-dimensional object - A process for producing at least one three-dimensional object by solidifying a solidifyable material, comprising the steps of:
| 2009-01-22 |
20090020902 | SILICON CARBIDE BASED POROUS MATERIAL AND METHOD FOR PRODUCTION THEREOF - A silicon carbide-based porous material characterized by comprising silicon carbide particles as an aggregate, metallic silicon and an oxide phase containing Si, Al and an alkaline earth metal; it is high in porosity and strength and superior in oxidation resistance and thermal shock resistance and, when used as a filter, is very low in risk of having defects such as cuts (which cause leakage of fluid) and the like, as well as in pressure loss. | 2009-01-22 |
20090020903 | METHOD AND DEVICE FOR FEEDING MOLTEN RESIN, AND METHOD FOR MANUFACTURING MOLDED ARTICLE BY USING THE FED MOLTEN RESIN - A method and a device for feeding a molten resin capable of accurately feeding the molten resin without the delay of feed timing by preventing the molten resin from adhering to route members before it seats on a mold to increase the positioning accuracy of the molten metal in the mold, and a method of manufacturing a molded part by using the fed molten resin. Vibration is provided to the route members such as molten resin guide pins ( | 2009-01-22 |
20090020904 | SILICONE-FREE CUTTING OIL AND USE THEREOF - The invention relates to a cutting oil comprising A) at least one polyalkylene glycol and B) optionally solvent and C) optionally further auxiliary materials and additives, and to its use for sawing polyurethane foams. | 2009-01-22 |
20090020905 | Reduced Cycle Time Manufacturing Processes for Thick Film Resistive Devices - A process of forming a resistive device such as s load resistor or a heater is provided that includes forming a dielectric layer onto a substrate, a target, or an adjacent functional layer, wherein the dielectric layer in one form defines a single layer of dielectric tape. The dielectric tape is laminated to the substrate, the target, or the adjacent functional layer through a single predetermined cycle of pressure, temperature and time, and then a resistive layer is farmed on the dielectric layer, and a protective layer is formed over the resistive layer. | 2009-01-22 |
20090020906 | Extruder System for Extruding a Fluid - The invention relates to an extruder system for extruding a fluid with at least one supply device, at least one mixer device and at least one extrusion die. In accordance with the invention at least one device for producing a fluid flow (transport fluid) that completely or partially surrounds the material to be extruded that essentially runs parallel to the outlet direction of the material to be extruded is provided, and whereby the fluid is discharged from the extruder system by suction and/or pressure of the transport fluid flow by means of an expulsion gas. The extruder system allows even product discharge for products well into the nanometre range. | 2009-01-22 |
20090020907 | TENTER CLIP AND SOLUTION CASTING METHOD - A dope is prepared from TAC, solvent and the like. The dope is cast from a casting die ( | 2009-01-22 |
20090020908 | STRUCTURES AND METHODS OF REPLICATING THE SAME - The invention features a method for producing replicas of a desired structure, a master and a mold obtained from it for use in such a method. The master includes a desired structure ( | 2009-01-22 |
20090020909 | Flat Die and Method for Manufacturing Laminated Resin Film or Sheet Using the Same - There is provided a flat die adapted to achieve a desired thickness distribution without a complicated structure even in laminating resins having different viscosities in molding. | 2009-01-22 |
20090020910 | SYSTEM AND METHOD FOR DEPOSITING THIN LAYERS ON NON-PLANAR SUBSTRATES BY STAMPING - An optoelectronic device may be fabricated on a three dimensional surface by transferring a material from an elastomeric stamp to a non-planar substrate. The use of an elastomeric stamp allows for patterned layers to be deposited on a non-planar substrate with reduced chance of damage to the patterned layer. The material may be deposited on the stamp while the stamp is in a planar configuration or after the stamp has been deformed to a shape generally the same as the shape of the non-planar substrate. The material may be transferred by cold welding. The device may include organic layers. | 2009-01-22 |
20090020911 | Method of Treating Rubber Composition with Cure Inihibitor to Create Soft Skin in Golf Ball Core - A method of making a golf ball comprising the steps of providing a preform comprising an uncured polybutadiene composition; coating the preform with a first cure-altering material; curing the coated preform at a predetermined temperature to form a crosslinked golf ball core having an outer surface having a first hardness and a geometric center having a second hardness greater than the first to define a negative hardness gradient; and forming a cover layer about the core to form the golf ball. | 2009-01-22 |