03rd week of 2016 patent applcation highlights part 52 |
Patent application number | Title | Published |
20160020072 | ION ENERGY BIAS CONTROL APPARATUS - This disclosure describes systems, methods, and apparatus for operating a plasma processing chamber. In particular, a periodic voltage function combined with an ion current compensation can be provided as a bias to a substrate support as a modified periodic voltage function. This in turn effects a DC bias on the surface of the substrate that controls an ion energy of ions incident on a surface of the substrate. A peak-to-peak voltage of the periodic voltage function can control the ion energy, while the ion current compensation can control a width of an ion energy distribution function of the ions. Measuring the modified periodic voltage function can provide a means to calculate an ion current in the plasma and a sheath capacitance of the plasma sheath. The ion energy distribution function can be tailored and multiple ion energy peaks can be generated, both via control of the modified periodic voltage function. | 2016-01-21 |
20160020073 | PLASMA GENERATION DEVICE, METHOD OF CONTROLLING CHARACTERISTIC OF PLASMA, AND SUBSTRATE PROCESSING DEVICE USING SAME - Provided are a plasma generation device, a method of controlling a characteristic of plasma, and a substrate processing device using the same. The plasma generation device includes a first radio frequency (RF) power supply supplying a first RF signal; a chamber supplying a space in which plasma is generated; a plasma source installed at the chamber, wherein the plasma source receives the first RF signal and generates plasma; a second RF power supply supplying a second RF signal; a direct current (DC) bias power supply supplying a DC bias signal; and an electrode arranged in the chamber, wherein the electrode receives an overlap signal obtained by overlapping the second RF signal and the DC bias signal and controls a characteristic of the plasma. | 2016-01-21 |
20160020074 | VARIABLE SHOWERHEAD FLOW BY VARYING INTERNAL BAFFLE CONDUCTANCE - Apparatuses and techniques for providing for variable radial flow conductance within a semiconductor processing showerhead are provided. In some cases, the radial flow conductance may be varied dynamically during use. In some cases, the radial flow conductance may be fixed but may vary as a function of radial distance from the showerhead centerline. Both single plenum and dual plenum showerheads are discussed. | 2016-01-21 |
20160020075 | MULTI-RANGE VOLTAGE SENSOR AND METHOD FOR A VOLTAGE CONTROLLED INTERFACE OF A PLASMA PROCESSING SYSTEM - A voltage sensor for a voltage controlled interface of a plasma processing system. The voltage sensor receives a RF signal generated by a pickup device. The RF signal is indicative of a RF voltage provided at a substrate in a plasma chamber. The voltage sensor includes first and second dividers corresponding to first and second channels and having first and second capacitance ratios. The dividers receive the RF signal and respectively generate first and second reduced voltage signals. A first output of the first channel outputs a first output signal based on the first reduced voltage signal and while the RF signal is in a first voltage range. A second output of the second channel outputs a second output signal based on the second reduced voltage signal and while the RF signal is in a second voltage range. | 2016-01-21 |
20160020076 | Collision Cell for Tandem Mass Spectrometry - A method and apparatus for tandem mass spectrometry is disclosed. Precursor ions are fragmented and the fragments are accumulated in parallel, by converting an incoming stream of ions from an ion source ( | 2016-01-21 |
20160020077 | METHOD FOR MONITORING LEVEL OF PARABEN IN COSMETICS - The invention discloses a method for monitoring level of paraben comprising: dissolving a sample in a solvent and obtaining a supernatant containing paraben by ultrasonic vibration and high speed centrifugation; performing a derivatization reaction between a derivatization reagent and paraben by adding the derivatization reagent into the supernatant to obtain a derivatization solution containing a tagged paraben; extracting the derivatization solution by an extractant to obtain an extract containing the tagged paraben; and ionizating the tagged paraben by a laser beam and analyzing mass-to-charge ratio of the tagged paraben by an analyzer to determine molecular weight thereof. | 2016-01-21 |
20160020078 | Device for Transferring Ions from High to Low Pressure Atmosphere, System and Use - Tube-like device ( | 2016-01-21 |
20160020079 | Charging Plate for Enhancing Multiply Charged Ions by Laser Desorption - A sample plate | 2016-01-21 |
20160020080 | SAMPLE PLATE FOR MALDI-TOF MASS SPECTROMETER AND METHOD OF MANUFACTURING THE SAMPLE PLATE AND MASS SPECTROMETRY METHOD USING THE SAMPLE PLATE - The present invention relates to a sample plate to be used for a MALDI-TOF (Matrix Assisted Laser Desorption Ionization Time of Flight) mass spectrometer, and more particularly, to a sample plate for a MALDI-TOF mass spectrometer, which is particularly useful for molecular weight measurement of a high-volatile material, a method of manufacturing the sample plate and a mass spectrometry method using the sample plate. Object of the present invention to provide a method capable of performing a mass spectrometry for a high-volatile material by using a MALDI-TOF mass spectrometer so as to overcome the limits of the gas chromatography method of the related art. According to the present invention, there is provided a sample plate including a target plate, an organic matrix formed on one surface of the target plate, a parylene thin film formed on the target plate having the organic matrix formed thereon and formed to cover the entire organic matrix, and a sample fixing layer formed on the parylene thin film. The sample fixing layer is made of at least one material selected from a group consisting of graphene and carbon nano tube (CNT). | 2016-01-21 |
20160020081 | Method to Perform Beam-Type Collision-Activated Dissociation in the Pre-Existing Ion Injection Pathway of a Mass Spectrometer - Described herein are methods and systems related to the use of the pre-existing ion injection pathway of a mass spectrometer to perform beam-type collision-activated dissociation, as well as other dissociation methods. The methods can be practiced using a wide range of mass spectrometer configurations and allows MS | 2016-01-21 |
20160020082 | MASS SPECTROMETER SYSTEM AND METHOD - An object of the invention is to provide a mass spectrometer system capable of obtaining a mass spectrum with high resolution as the mass number of an ion becomes higher. In the mass spectrometer system of the invention, a control unit | 2016-01-21 |
20160020083 | ADJUSTING PRECURSOR ION POPULATIONS IN MASS SPECTROMETRY USING DYNAMIC ISOLATION WAVEFORMS - A mass spectrometry technique for isolating a plurality of isolated ions from a plurality of injected ions using a dynamic isolation waveform to create at least one isolation notch. Isolating the plurality of isolated ions may include collecting at least a first target ion, but not a second target ion, using the at least one isolation notch for a first period of time; changing at least one property of the at least one isolation notch; and collecting at least the first target ion and the second target ion using the at least one isolation notch for a second period of time. | 2016-01-21 |
20160020084 | SHAPED CATHODE FOR A FIELD EMISSION ARRANGEMENT - The present invention relates to a field emission lighting arrangement, comprising an anode and a cathode, where the shape of the cathode is selected based on the shape of a evacuated envelope in which the anode and cathode is provided. The inventive shape of cathode allows for an improved uniformity of an electric field provided between the anode and cathode during operation of the field emission lighting arrangement. The invention also relates to a corresponding method for selecting a shape of such a cathode. | 2016-01-21 |
20160020085 | SUBSTRATE PROCESSING DEVICE - A substrate processing apparatus includes a processing unit supplying at least one of a plurality of types of chemical liquids to a substrate and a scrubber cleaning an exhaust by bringing the exhaust in contact with a scrubbing liquid. The scrubber includes an exhaust passage that guides the exhaust, generated at the processing unit and containing the chemical liquid, toward an exhaust equipment disposed outside the substrate processing apparatus and a discharger that is able to discharge each of a plurality of types of scrubbing liquids that clean the exhaust individually inside the exhaust passage. A controller selects any one of the plurality of types of scrubbing liquids based on the type of chemical liquid contained in the exhaust and makes the selected scrubbing liquid be discharged from the discharger. | 2016-01-21 |
20160020086 | DOPING CONTROL METHODS AND RELATED SYSTEMS - A system for cleaning dopant contamination in a process chamber is disclosed. The system includes a susceptor and a chamber kit component, a first plurality of lamps configured to heat the susceptor, a second plurality of lamps configured to heat the chamber kit component, and a gas supply configured to provide a chlorine cleaning gas. The system is configured to deposit a layer on a substrate at a deposition temperature and perform an in-situ clean of the process chamber, including the chamber kit component, at the deposition temperature. A method for cleaning dopant contamination includes depositing a layer over a substrate at a deposition temperature, performing an in-situ clean of the process chamber and a process kit component at the deposition temperature, unloading the substrate, and performing a dedicated clean at a clean temperature. In some examples, the clean temperature is about equal to the deposition temperature. | 2016-01-21 |
20160020087 | POST-CMP REMOVAL USING COMPOSITIONS AND METHOD OF USE - An amine-free composition and process for cleaning post-chemical mechanical polishing (CMP) residue and contaminants from a microelectronic device having said residue and contaminants thereon. The amine-free composition preferably includes at least one oxidizing agent, at least one complexing agent, at least one basic compound, and water and has a pH in the range from about 2.5 to about 11.5. The composition achieves highly efficacious cleaning of the post-CMP residue and contaminant material from the surface of the microelectronic device without compromising the low-k dielectric material or the copper interconnect material. | 2016-01-21 |
20160020088 | METHOD OF MAKING A SEMICONDUCTOR DEVICE USING A BARRIER AND ANTIREFLECTIVE COATING (BARC) LAYER - A method of forming a semiconductor device includes forming a dielectric layer over a substrate. The method includes forming a layer set over the dielectric layer, wherein the layer set comprises a plurality of layers. The method further includes forming a bottom antireflective coating (BARC) layer over the layer set. The method further includes etching the layer set to form a tapered opening in the layer set, wherein etching the layer set comprises etching at least one layer comprising a silicon-rich photoresist material layer and a second material layer different from the silicon-rich photoresist material, and the tapered opening has sidewalls at an angle with respect to a top surface of the dielectric layer. The method further includes etching the dielectric layer using the layer set as a mask to form an opening in the dielectric layer, wherein etching the dielectric layer comprises reducing a thickness of the layer set. | 2016-01-21 |
20160020089 | LOW-K DIELECTRIC GAPFILL BY FLOWABLE DEPOSITION - Methods are described for forming a flowable low-k dielectric layer on a patterned substrate. The film may be a silicon-carbon-oxygen (Si—C—O) layer in which the silicon and carbon constituents come from a silicon and carbon containing precursor while the oxygen may come from an oxygen-containing precursor activated in a remote plasma region. A similarly deposited silicon oxide layer may be deposited first to improve the gapfill capabilities. Alternatively, or in combination, the flow of a silicon-and-carbon-containing precursor may be reduced during deposition to change the properties from low-k to high strength roughly following the filling of features of the patterned substrate. | 2016-01-21 |
20160020090 | ENHANCEMENT OF MODULUS AND HARDNESS FOR UV-CURED ULTRA LOW-K DIELECTRIC FILMS - Embodiments described herein generally relate to methods for processing a dielectric film on a substrate with UV energy. In one embodiment, a precursor film is deposited on the substrate, and the precursor film includes a plurality of porogen molecules. The precursor film is first exposed to UV energy at a first temperature to initiate a cross-linking process. After a first predetermined time, the temperature of the precursor film is increased to a second temperature for a second predetermined time to remove porogen molecules and to continue the cross-linking process. The resulting film is a porous low-k dielectric film having improved elastic modulus and hardness. | 2016-01-21 |
20160020091 | Carbon and/or Nitrogen Incorporation in Silicon Based Films Using Silicon Precursors With Organic Co-Reactants by PE-ALD - Methods for the deposition of a silicon-containing film using an organic reactant, a silicon precursor and a plasma. | 2016-01-21 |
20160020092 | METHODS FOR DEPOSITING SILICON OXIDE - The embodiments herein focus on plasma enhanced atomic layer deposition (PEALD) processes. Conventional PEALD techniques result in films having high quality at the bottom and top of a feature, but low quality on the sidewalls. The disclosed embodiments achieve more uniform film quality as evidenced by more uniform wet etch rates and electrical properties throughout the film. The disclosed embodiments may use one or more of a relatively high deposition temperature, a relatively high RF power for generating the plasma, and/or relatively long RF plasma exposure duration during each cycle of the PEALD reaction. | 2016-01-21 |
20160020093 | PROCESS FOR FORMING SILICON-FILLED OPENINGS WITH A REDUCED OCCURRENCE OF VOIDS - In some embodiments, silicon-filled openings are formed having no or a low occurrence of voids in the silicon fill, while maintaining a smooth exposed silicon surface. In some embodiments, an opening in a substrate may be filled with silicon, such as amorphous silicon. The deposited silicon may have interior voids. This deposited silicon is then exposed to a silicon mobility inhibitor, such as an oxygen-containing species and/or a semiconductor dopant. The deposited silicon fill is subsequently annealed. After the anneal, the voids may be reduced in size and, in some embodiments, this reduction in size may occur to such an extent that the voids are eliminated. | 2016-01-21 |
20160020094 | PROCESS FOR FORMING SILICON-FILLED OPENINGS WITH A REDUCED OCCURRENCE OF VOIDS - In some embodiments, silicon-filled openings are formed having no or a low occurrence of voids in the silicon fill, while maintaining a smooth exposed silicon surface. In some embodiments, an opening in a substrate may be filled with silicon, such as amorphous silicon. The deposited silicon may have interior voids. This deposited silicon is then exposed to a silicon mobility inhibitor, such as an oxygen-containing species and/or a semiconductor dopant. The deposited silicon fill is subsequently annealed. After the anneal, the voids may be reduced in size and, in some embodiments, this reduction in size may occur to such an extent that the voids are eliminated. | 2016-01-21 |
20160020095 | METAL-INDUCED CRYSTALLIZATION OF AMORPHOUS SILICON IN AN OXIDIZING ATMOSPHERE - Techniques are provided for forming thin film transistors having a polycrystalline silicon active layer formed by metal-induced crystallization (MIC) of amorphous silicon in an oxidizing atmosphere. In an aspect, a transistor device, is provided that includes a source region and a drain region formed on a substrate, and an active channel region formed on the substrate and electrically connecting the source region and the drain region. The active channel region is formed with a polycrystalline silicon layer having resulted from annealing an amorphous silicon layer formed on the substrate and having a metal layer formed thereon, wherein the annealing of the amorphous silicon layer was at least partially performed in an oxidizing ambience, thereby resulting in crystallization of the amorphous silicon layer to form the polycrystalline silicon layer. | 2016-01-21 |
20160020096 | Manufacture Method Of Low Temperature Poly Silicon, Manufacturing Method Of TFT Substrate Utilizing The Method, And TFT Substrate Structure - The present invention provides a manufacture method of Low Temperature Poly Silicon, a manufacture method of a TFT substrate utilizing the method and a TFT substrate structure. The manufacture method of Low Temperature Poly Silicon comprises steps of: step 1, providing a substrate ( | 2016-01-21 |
20160020097 | LASER ANNEALING APPARATUS AND LASER ANNEALING METHOD USING THE SAME - A laser annealing apparatus includes a beam splitter that splits a laser beam emitted from a laser source into a reflection light beam and a transmission light beam, a beam vibrator that makes an irradiation point of the reflection light beam or the transmission light beam vibrate in a predetermined direction, a beam inverter that inverts the reflection light beam or the transmission light beam, and a light collector that collects the reflection light and the transmission light. | 2016-01-21 |
20160020098 | LITHOGRAPHY USING INTERFACE REACTION - A method of forming a semiconductor structure by; forming a first mask trench in a first mask, where the first mask is on a substrate; forming a second mask in the first mask trench; and forming a third mask between the first mask and the second mask by reacting the first mask with the second mask, where the first mask, the second mask, and the third mask all have different etching properties. | 2016-01-21 |
20160020099 | PATTERN FORMING METHOD AND METHOD OF MANUFACTURING SEMICONDUCTOR DEVICE - According to one embodiment, first, an embedment material is embedded between linear core material patterns in such a manner that a height thereof becomes lower than a height of each of the core material patterns. Then, a shrink agent is supplied and solidified on the embedment material. Subsequently, the solidified shrink agent and the embedment material are removed and a spacer film is formed on an object of processing. Then, the spacer film is etched-back and a spacer pattern is formed by removal of the core material patterns. The solidified shrink agent which is formed in such a manner that a width of the spacer pattern becomes narrow in a region corresponding to a position where the shrink agent, in a sectional surface vertical to an extended direction of the spacer pattern is supplied is removed. | 2016-01-21 |
20160020100 | Self-Aligned Double Patterning - A semiconductor device and a method of forming the same are provided. An embodiment comprises a target layer and masking layers over the target layer. First openings are formed in the uppermost layer of the masking layers. Spacers are formed along sidewalls of the first openings, remaining first openings having a first pattern. Second openings are formed in the uppermost layer of the masking layers, the second openings having a second pattern. The first pattern and the second pattern are partially transferred to the target layer. | 2016-01-21 |
20160020101 | SEMICONDUCTOR DEVICE MANUFACTURING METHOD - Provided is a semiconductor device manufacturing method such that miniaturization of a parallel p-n layer can be achieved, and on-state resistance can be reduced. Firstly, deposition of an n | 2016-01-21 |
20160020102 | CARBON DOPANT GAS AND CO-FLOW FOR IMPLANT BEAM AND SOURCE LIFE PERFORMANCE IMPROVEMENT - Ion implantation processes and systems are described, in which carbon dopant source materials are utilized to effect carbon doping. Various gas mixtures are described, including a carbon dopant source material, as well as co-flow combinations of gases for such carbon doping. Provision of in situ cleaning agents in the carbon dopant source material is described, as well as specific combinations of carbon dopant source gases, hydride gases, fluoride gases, noble gases, oxide gases and other gases. | 2016-01-21 |
20160020103 | BARRIER LAYER, METHOD FOR FABRICATING THE SAME, THIN FILM TRANSISTOR AND ARRAY SUBSTRATE - A barrier layer, a method for fabricating the same, a thin film transistor (TFT) and an array substrate are disclosed and related to display technology field. When the barrier layer ( | 2016-01-21 |
20160020104 | SEMICONDUCTOR STRUCTURE INCLUDING SILICON AND OXYGEN-CONTAINING METAL LAYER AND PROCESS THEREOF - A metal gate process for polishing and oxidizing includes the following steps. A first dielectric layer having a trench is formed on a substrate. A barrier layer and a metal layer are formed sequentially to cover the trench and the first dielectric layer. A first chemical mechanical polishing process including a slurry of H | 2016-01-21 |
20160020105 | METHOD FOR CONTROLLING THE PROFILE OF AN ETCHED METALLIC LAYER - An ashing chemistry employing a combination of Cl | 2016-01-21 |
20160020106 | MASK AND METHOD FOR MANUFACTURING SEMICONDUCTOR DEVICE - A mask may be used in a process for manufacturing a semiconductor device. The semiconductor device may include a source line, a first drain contact terminal, and a second drain contact terminal. The mask may include the following elements: a source-line corresponding light-transmitting portion, which corresponds to the source line; a first-drain-contact-terminal corresponding light-transmitting portion, which corresponds to the first drain contact terminal; a second-drain-contact-terminal corresponding light-transmitting portion, which corresponds to the second drain contact terminal; and a first light-blocking portion, which abuts at least one of the source-line corresponding light-transmitting portion, the first-drain-contact-terminal corresponding light-transmitting portion, and the second-drain-contact-terminal corresponding light-transmitting portion. | 2016-01-21 |
20160020107 | MANUFACTURING METHOD OF SEMICONDUCTOR DEVICE - In MOSFET having SBD as a protection element, a TiW (alloy having tungsten as a main component) film is used as an aluminum-diffusion barrier metal film below an aluminum source electrode in order to secure properties of SBD. The present inventors have found that a tungsten-based barrier metal film is in the form of columnar grains having a lower barrier property than that of a titanium-based barrier metal film such as TiN so that aluminum spikes are generated relatively easily in a silicon substrate. In the present invention, when a tungsten-based barrier metal film is formed by sputtering as a barrier metal layer between an aluminum-based metal layer and a silicon-based semiconductor layer therebelow, the lower layer is formed by ionization sputtering while applying a bias to the wafer side and the upper layer is formed by sputtering without applying a bias to the wafer side. | 2016-01-21 |
20160020108 | METHOD FOR ETCHING HIGH-K DIELECTRIC USING PULSED BIAS POWER - A method of patterning a gate stack on a substrate is described. The method includes preparing a gate stack on a substrate, wherein the gate stack includes a high-k layer and a gate layer formed on the high-k layer. The method further includes transferring a pattern formed in the gate layer to the high-k layer using a pulsed bias plasma etching process, and selecting a process condition for the pulsed bias plasma etching process to achieve a silicon recess formed in the substrate having a depth less than 2 nanometer (nm). | 2016-01-21 |
20160020109 | METHOD OF FABRICATING SEMICONDUCTOR DEVICE - Provided is a method of fabricating a semiconductor device. In the method, a double patterning technology is used to form various patterns with different widths. | 2016-01-21 |
20160020110 | SEMICONDUCTOR DEVICE AND METHOD OF FORMING THE SAME - A method of forming a semiconductor device is provided. At least one stacked structure is provided on a substrate. A first spacer material layer, a second spacer material layer, and a third spacer material layer are sequentially formed on the substrate and cover the stacked structure. The first, second, and third spacer material layers are etched to form a tri-layer spacer structure on the sidewall of the stacked structure. The tri-layer spacer structure includes, from one side of the stacked structure, a first spacer, a second spacer, and a third spacer, and a dielectric constant of the second spacer is less than each of a dielectric constant of the first spacer and a dielectric constant of the third spacer. | 2016-01-21 |
20160020111 | MANUFACTURING METHOD OF SEMICONDUCTOR DEVICE - In a manufacturing method of a semiconductor device according to an embodiment, a mask material comprising at least one layer of a hafnium silicate (HfSiOn (n is a positive number)) film is formed on a processing target film. The processing target material is processed using the mask material as a mask. The hafnium silicate film is located almost at a central portion of the mask material or between the central portion of the mask material and an upper surface thereof. | 2016-01-21 |
20160020112 | APPARATUS AND METHOD FOR ETCHING SUBSTRATE, STAMP FOR ETCHING SUBSTRATE AND METHOD FOR MANUFACTURING THE SAME - The inventive concepts relate to an apparatus and a method for etching a substrate, a stamp for etching a substrate, and a method for manufacturing the stamp. The method for etching a substrate includes bringing a substrate into contact with a stamp including a pattern on which a metal catalyst is formed, and etching the substrate by a chemical reaction between the metal catalyst and an etching solution. | 2016-01-21 |
20160020113 | LIQUID COMPOSITION AND ETCHING METHOD FOR ETCHING SILICON SUBSTRATE - An etching method includes etching a silicon substrate with a liquid composition containing an alkaline organic compound, water, and a boron compound with a content in the range of 1% by mass to 14% by mass. The boron compound is at least one of boron sesquioxide, sodium tetraborate, metaboric acid, sodium perborate, sodium borohydride, zinc borate, and ammonium borate. | 2016-01-21 |
20160020114 | Method for Increasing Oxide Etch Selectivity - Techniques herein include methods for etching an oxide layer with greater selectivity to underlying channel materials. Such an increase in etch selectivity reduces damage to channel materials thereby providing more reliable and better performing semiconductor devices. Techniques herein include using fluorocarbon gas to feed a plasma to create etchants, and also creating a flux of ballistic electrons to treat a given substrate during an etch process. | 2016-01-21 |
20160020115 | Etching Method and Storage Medium - An etching method includes disposing a target substrate within a chamber. The target substrate has a first silicon oxide film formed on a surface of the target substrate by a chemical vapor deposition method or an atomic layer deposition method, a second silicon oxide film that includes a thermally-oxidized film and a silicon nitride film. The second silicon oxide film and the silicon nitride are formed adjacent to the first silicon oxide film. The etching method further includes supplying an HF gas and an alcohol gas or water vapor into the chamber to selectively etch the first silicon oxide film with respect to the second silicon oxide film and the silicon nitride film. | 2016-01-21 |
20160020116 | PLASMA REACTOR WITH CONDUCTIVE MEMBER IN REACTION CHAMBER FOR SHIELDING SUBSTRATE FROM UNDESIRABLE IRRADIATION - Placing a conductive member between a plasma chamber in a remote plasma reactor and a substrate to shield the substrate from irradiation of undesirable electromagnetic radiation, ions or electrons. The conductive member blocks the electromagnetic radiation, neutralizes ions and absorbs the electrons. Radicals generated in the plasma chambers flows to the substrate despite the placement of the conductive member. In this way, the substrate is exposed to the radicals whereas damages to the substrate due to electromagnetic radiations, ions or electrons are reduced or removed. | 2016-01-21 |
20160020117 | SCANNED PULSE ANNEAL APPARATUS AND METHODS - Apparatus, system, and method for thermally treating a substrate. A source of pulsed electromagnetic energy can produce pulses at a rate of at least 100 Hz. A movable substrate support can move a substrate relative to the pulses of electromagnetic energy. An optical system can be disposed between the energy source and the movable substrate support, and can include components to shape the pulses of electromagnetic energy toward a rectangular profile. A controller can command the source of electromagnetic energy to produce pulses of energy at a selected pulse rate. The controller can also command the movable substrate support to scan in a direction parallel to a selected edge of the rectangular profile at a selected speed such that every point along a line parallel to the selected edge receives a predetermined number of pulses of electromagnetic energy. | 2016-01-21 |
20160020118 | SEMICONDUCTOR DEVICE AND METHOD FOR FABRICATING THE SAME - Provided are methods for fabricating semiconductor devices. The methods for fabricating the semiconductor devices may include forming a first interlayer insulation film including a trench on a substrate, forming a high-k layer along an inner sidewall and a bottom surface of the trench, forming a first work function control film including impurities along the high-k layer, removing the impurities from the first work function control film to reduce surface resistance of the first work function control film by about 30% to about 60% and forming a gate metal in the trench. | 2016-01-21 |
20160020119 | Method of Controlling Recess Depth and Bottom ECD in Over-Etching - A semiconductor stack includes a carbon doped/implanted stop layer that reacts with etching plasma to form polymers that maintain bottom etched critical dimension (ECD) and avoid excess recess depth when over-etching in high-aspect-ratio structures. | 2016-01-21 |
20160020120 | APPARATUS AND METHODS FOR MICRO-TRANSFER-PRINTING - In an aspect, a system and method for assembling a semiconductor device on a receiving surface of a destination substrate is disclosed. In another aspect, a system and method for assembling a semiconductor device on a destination substrate with topographic features is disclosed. In another aspect, a gravity-assisted separation system and method for printing semiconductor device is disclosed. In another aspect, various features of a transfer device for printing semiconductor devices are disclosed. | 2016-01-21 |
20160020121 | EMBEDDED PACKAGING WITH PREFORMED VIAS - Microelectronic assemblies and methods of making the same are disclosed. In some embodiments, a microelectronic assembly includes a microelectronic element having edge surfaces bounding a front surface and contacts at the front surface; rigid metal posts disposed between at least one edge surface and a corresponding edge of the assembly, each metal post having a sidewall separating first and second end surfaces, the sidewalls have a root mean square (rms) surface roughness of less than about 1 micron; a encapsulation contacting at least the edge surfaces and the sidewalls; an insulation layer overlying the encapsulation; connection elements extending through the insulation layer, wherein at least some connection elements have cross sections smaller than those of the metal posts; a redistribution structure deposited on the insulation layer and electrically connecting first terminals with corresponding metal posts through the first connection elements, some metal posts electrically coupled with contacts of microelectronic element. | 2016-01-21 |
20160020122 | SUBSTRATE PROCESSING APPARATUS AND SUBSTRATE PROCESSING METHOD - A substrate processing apparatus includes: a chamber that accommodates a processing target substrate therein; a gas supply unit that supplies a gas into the chamber; a gas discharge port that exhausts the chamber; an adjustment mechanism that adjusts an exhaust amount discharged from the gas discharge port; a measuring unit that measures an internal pressure of the chamber; and a controller that executes a series of substrate processings according to recipe information indicating contents of substrate processings. The controller performs a feedback control that controls an opening degree of the adjustment mechanism to maintain the internal pressure within a prescribed range based on a measurement result from the measuring unit. When a predetermined event, estimated to change the internal pressure to a level out of the prescribed range, occurs, the controller switches the feedback control to a non-feedback control that controls the opening degree based on a prescribed control value. | 2016-01-21 |
20160020123 | DATA ANALYSIS METHOD FOR PLASMA PROCESSING APPARATUS, PLASMA PROCESSING METHOD AND PLASMA PROCESSING APPARATUS - A stable etching process is realized at an earlier stage by specifying the combination of wavelength and time interval, which exhibits a minimum prediction error of etching processing result within a short period. For this, the combination of wavelength and time interval is generated from wavelength band of plasma emission generated upon etching of the specimen, the prediction error upon prediction of etching process result is calculated with respect to each combination of wavelength and time interval, the wavelength combination is specified based on the calculated prediction error, the prediction error is further calculated by changing the time interval with respect to the specified wavelength combination, and the combination of wavelength and time interval, which exhibits the minimum value of calculated prediction error is selected as the wavelength and the time interval used for predicting the etching processing process. | 2016-01-21 |
20160020124 | BENDABLE CARRIER MOUNT, DEVICE AND METHOD FOR RELEASING A CARRIER SUBSTRATE - A flexible carrier mount for mounting of a carrier substrate when the carrier substrate is detached from a product substrate, detachment means being provided for debonding the product substrate with bending of the carrier substrate. A device for detaching a carrier substrate from one product substrate in one detachment direction having: a carrier mount flexible in the detachment direction for mounting the carrier substrate, a substrate mount for mounting the product substrate, and detachment means for debonding the carrier substrate from the product substrate with bending of the carrier substrate. A method for detaching a carrier substrate from a product substrate in one detachment direction with the steps: mounting the product substrate with a substrate mount and mounting the carrier substrate with a carrier mount flexible in the detachment direction and debonding the carrier substrate from the product substrate with bending of the carrier substrate. | 2016-01-21 |
20160020125 | SUBSTRATE PROCESSING APPARATUS AND SUBSTRATE PROCESSING METHOD - During a teaching operation regarding a transport mechanism, a hand of the transport mechanism is moved to a tentative target position in a substrate supporter, and a substrate supported at a reference position in the substrate supporter is received by the hand. A positional relationship between the substrate held by the hand and the hand is detected. A deviation between the tentative target position and the reference position is acquired as correction information based on the detected positional relationship. During the teaching operation or during substrate processing, the tentative target position is corrected to a true target position to coincide with the reference position based on the acquired correction information. During the substrate processing, the hand is moved to the true target position, so that the substrate is transferred to the substrate supporter by the hand, or the substrate is received from the substrate supporter by the hand. | 2016-01-21 |
20160020126 | DUAL SCARA ARM - A substrate transport apparatus having a drive section and a scara arm operably connected to the drive section to move the scara arm. The scara arm has an upper arm and at least one forearm. The forearm is movably mounted to the upper arm and capable of holding a substrate thereon. The upper arm is substantially rigid and is adjustable for changing a predetermined dimension of the upper arm. | 2016-01-21 |
20160020127 | APPARATUS AND METHODS FOR MICRO-TRANSFER-PRINTING - In an aspect, a system and method for assembling a semiconductor device on a receiving surface of a destination substrate is disclosed. In another aspect, a system and method for assembling a semiconductor device on a destination substrate with topographic features is disclosed. In another aspect, a gravity-assisted separation system and method for printing semiconductor device is disclosed. In another aspect, various features of a transfer device for printing semiconductor devices are disclosed. | 2016-01-21 |
20160020128 | WAFER CHUCK - A wafer chuck is provided. The wafer chuck includes a main body and a dielectric layer disposed over the main body. The wafer chuck also includes an electrode embedded in the dielectric layer and configured to generate an electrostatic field for retaining a wafer. The wafer chuck further includes a thermal conductive layer embedded in the main body or the dielectric layer. The thermal conductive layer has a lateral thermal conductivity greater than a vertical thermal conductivity. | 2016-01-21 |
20160020129 | METHODS FOR TEMPORARILY BONDING A DEVICE WAFER TO A CARRIER WAFER, AND RELATED ASSEMBLIES - A method of bonding a device wafer to a carrier wafer includes disposing a first adhesive over a central portion of a carrier wafer, the first adhesive having a first glass transition temperature, disposing a second adhesive over a peripheral portion of the carrier wafer, the second adhesive having a second glass transition temperature greater than the first glass transition temperature, and bonding the first adhesive to active front side of the device wafer and the second adhesive to a peripheral portion of the front side of the device wafer. Related assemblies may be used in such methods. | 2016-01-21 |
20160020130 | APPARATUS AND METHODS FOR MICRO-TRANSFER-PRINTING - In an aspect, a system and method for assembling a semiconductor device on a receiving surface of a destination substrate is disclosed. In another aspect, a system and method for assembling a semiconductor device on a destination substrate with topographic features is disclosed. In another aspect, a gravity-assisted separation system and method for printing semiconductor device is disclosed. In another aspect, various features of a transfer device for printing semiconductor devices are disclosed. | 2016-01-21 |
20160020131 | APPARATUS AND METHODS FOR MICRO-TRANSFER-PRINTING - In an aspect, a system and method for assembling a semiconductor device on a receiving surface of a destination substrate is disclosed. In another aspect, a system and method for assembling a semiconductor device on a destination substrate with topographic features is disclosed. In another aspect, a gravity-assisted separation system and method for printing semiconductor device is disclosed. In another aspect, various features of a transfer device for printing semiconductor devices are disclosed. | 2016-01-21 |
20160020132 | Apparatus And Methods For Wafer Chucking On A Susceptor For ALD - Described are apparatus and methods for processing a semiconductor wafer so that the wafer remains in place during processing. The wafer is subjected to a pressure differential between the top surface and bottom surface so that sufficient force prevents the wafer from moving during processing, the pressure differential generated by applying a decreased pressure to the back side of the wafer. | 2016-01-21 |
20160020133 | Carrier Head, Chemical Mechanical Polishing Apparatus and Wafer Polishing Method - Provided is a carrier head. The carrier head includes: a body having a ring shape, wherein a first locking part is formed on an external surface of the body; a support unit surrounding lateral and lower parts of the body to be elevatably coupled to the body, wherein a second locking part vertically facing the first locking part is formed on an internal surface of the support unit; a regulating member located in a space between the first locking part and the second locking part; a retainer ring having a ring shape and located at the external bottom of the support unit; and an elevating unit coupling the retainer ring to the support unit to enable a height to be regulated relative to the support unit. | 2016-01-21 |
20160020134 | APPARATUS AND METHOD FOR REDUCING SUBSTRATE SLIDING IN PROCESS CHAMBERS - Methods and apparatus for processing a substrate are disclosed herein. In some embodiments, an apparatus for processing a substrate includes: a substrate support having a substrate supporting surface including an electrically insulating coating; a substrate lift mechanism including a plurality of lift pins configured to move between a first position disposed beneath the substrate supporting surface and a second position disposed above the substrate supporting surface; and a connector configured to selectively provide an electrical connection between the substrate support and the substrate lift mechanism before the plurality of lift pins reach a plane of the substrate supporting surface. | 2016-01-21 |
20160020135 | PLACING BED STRUCTURE, TREATING APPARATUS USING THE STRUCTURE, AND METHOD FOR USING THE APPARATUS - Provided is a holding stage structure which holds a substrate and disposed in a process chamber that is vacuum-evacuatable and allows a predetermined process to be performed on the substrate therein. The holding stage structure includes: a holding stage body on which the substrate is placed; an elevation pin mechanism lowering the substrate on the holding stage body or raising the substrate from the holding stage body; and a stepped portion formed on the holding stage body so that a peripheral portion of a rear surface of the substrate placed on the holding stage body is exposed to a processing gas supplied into the process chamber. | 2016-01-21 |
20160020136 | RECEPTACLE DEVICE, DEVICE AND METHOD FOR HANDLING SUBSTRATE STACKS - The invention relates to a retaining system for handling substrate stacks, including a retaining surface for retaining a first substrate, and one or more recesses provided relative to the retaining surface, for retaining first magnetic bodies for securing the first substrate relative to a second substrate that is aligned with the first substrate. Second magnetic bodies are applied on a holding side of the second substrate. | 2016-01-21 |
20160020137 | APPARATUS AND METHOD FOR ADJUSTING A PEDESTAL ASSEMBLY FOR A REACTOR - The invention is directed to an alignment assembly for changing the relative position of a plate of a pedestal assembly with respect to a processing chamber of a reactor. The alignment assembly is connected at a first end to a riser shaft of the heating assembly and at a second end to a drive shaft. One or more portions of the alignment assembly may be selectively axially rotated or laterally moved change the relative position of the plate with respect to the processing chamber as desired. | 2016-01-21 |
20160020138 | Techniques for Creating a Local Interconnect Using a SOI Wafer - In one aspect, a method of forming a local interconnect structure includes the steps of: forming a BOX SOI wafer having a fully depleted seed layer between a first BOX layer and a second BOX layer, and an active layer over the second BOX layer; forming at least one STI region in the active layer having an STI oxide; forming at least one trench that extends through the STI oxide and the second BOX layer down to the seed layer, wherein the trench has a footprint and a location such that a portion of the STI oxide remains lining sidewalls of the trench; and growing an epitaxial material in the trench using the seed layer as a template for the growth, wherein the epitaxial material is doped and serves as the local interconnect structure which is buried in the double BOX SOI wafer. | 2016-01-21 |
20160020139 | GAP-FILLING DIELECTRIC LAYER METHOD FOR MANUFACTURING THE SAME AND APPLICATIONS THEREOF - A gap-filling dielectric layer, method for fabricating the same and applications thereof are disclosed. A silicon-containing dielectric layer is firstly deposited on a substrate. The silicon-containing dielectric layer is then subjected to a curing process, an in-situ wetting treatment and an annealing process in sequence, whereby a gap-filling dielectric layer with a nitrogen atom density less than 1×10 | 2016-01-21 |
20160020140 | ANISOTROPIC MATERIAL DAMAGE PROCESS FOR ETCHING LOW-K DIELECTRIC MATERIALS - In one example, a method includes forming a mask layer above or in a dielectric material. The dielectric material is exposed to photon radiation in an ambient atmosphere comprising a carbon gettering agent to generate damaged portions of the dielectric material. The mask layer blocks the photon radiation. The damaged portions of the dielectric material are removed. | 2016-01-21 |
20160020141 | METHOD OF FORMING CONTACT OPENINGS FOR A TRANSISTOR - A method for making contact openings for connecting a transistor from a stack of layers comprising an active layer made of a semi-conductor material, a silicide layer on the top of the active layer, a nitride-based layer on the top of the silicide layer, and an electrically insulating layer on the top of the nitride-based layer, includes opening for forming, in the insulating layer, an exposing opening on the nitride-based layer and delimited by flanks of the insulating layer, and removing the nitride-based layer by modifying the nitride-based layer at the opening using plasma wherein CxHy is introduced where x is the proportion of carbon and y is the proportion of hydrogen ions and comprising ions heavier than hydrogen. The conditions of plasma being so chosen as to modify a portion of the nitride-based layer and to form a protective carbon film on the flanks of the insulating layer. | 2016-01-21 |
20160020142 | CONDUCTIVE STRUCTURE AND METHOD OF FORMING THE SAME - Conductive structures and method of manufacture thereof are disclosed. In some embodiments, a method of forming a conductive structure includes providing a substrate having a recess formed therein, the recess lined with a first seed layer and partially filled with a first conductive material; removing a portion of the first seed layer free from the first conductive material to form an exposed surface of the recess; lining the exposed surface of the recess with a second seed layer; and filling the recess with a second conductive material, the second conductive material covering the first conductive material and the second seed layer. | 2016-01-21 |
20160020143 | Semiconductor Devices and Fabrication Methods With Reduced Topology And Reduced Word Line Stringer Residual Material - Provided are improved semiconductor memory devices and methods for manufacturing such semiconductor memory devices. A method may incorporate the formation of a first dielectric layer over buried oxide regions and the removal of such dielectric layer to prepare a substantially planar substrate for subsequent formation of word lines. The method may allow for the production of semiconductor memory devices of reduced size with reduced word line stringer residual material. | 2016-01-21 |
20160020144 | METHOD FOR FABRICATING SEMICONDUCTOR DEVICE - A method for fabricating semiconductor device is disclosed. The method includes the steps of: providing a substrate having at least a device thereon; forming a dielectric layer on the device and the substrate; forming a first mask layer on the dielectric layer; removing part of the first mask layer and part of the dielectric layer for forming a patterned first mask layer on the dielectric layer; covering a hard mask on the patterned first mask layer and the dielectric layer; partially removing the hard mask for forming a spacer adjacent to the patterned first mask layer and the dielectric layer; forming a contact hole adjacent to the spacer; filling the contact hole with a metal layer; and planarizing the metal layer for forming a contact plug, wherein the contact plug contacts the dielectric layer and the spacer simultaneously. | 2016-01-21 |
20160020145 | METHODS OF FABRICATING SEMICONDUCTOR DEVICES WITH BLOCKING LAYER PATTERNS - A semiconductor device includes a circuit device on a substrate and a first insulating interlayer on the substrate and covering the circuit device. An electrode structure extends through the first insulating interlayer and at least partially through the substrate. An etch-stop layer pattern is disposed on a sidewall of the electrode structure on a side of the first insulating layer opposite the substrate. A blocking layer pattern is disposed on the etch-stop layer pattern. The device further includes an interconnection structure including a via portion passing through the blocking layer pattern to contact the through electrode structure and a wiring portion on the via portion and having a different width than the via portion. The semiconductor device may further include a contact plug electrically connected to the circuit device through the first insulating interlayer. The contact plug and the through electrode structure may include different metals. | 2016-01-21 |
20160020146 | METHOD FOR REDUCING CROSS CONTAMINATION IN INTEGRATED CIRCUIT MANUFACTURING - Systems, apparatuses, and methods related to the design, fabrication, and manufacture of gallium arsenide (GaAs) integrated circuits are disclosed. Copper can be used as the contact material for a GaAs integrated circuit. Metallization of the wafer and through-wafer vias can be achieved through copper plating processes disclosed herein. Various protocols can be employed during processing to avoid cross-contamination between copper-plated and non-copper-plated wafers. GaAs integrated circuits can be singulated, packaged, and incorporated into various electronic devices. | 2016-01-21 |
20160020147 | IMPEDANCE MATCHING CIRCUIT, POWER AMPLIFIER AND MANUFACTURING METHOD FOR VARIABLE CAPACITOR - A manufacturing method for a variable capacitor includes forming a first element of which a capacitance value depends on a voltage applied to both of two terminals of a first area on a substrate, forming a second element having a capacitance value fixed to a second area on the substrate adjacent to the first area, and forming metallic wires for connecting the first element and the second element and connecting the first element and the second element with the outside. The first element maybe a bipolar transistor that may include a diode. The second element maybe a capacitor that includes a dielectric. | 2016-01-21 |
20160020148 | METHOD OF FABRICATING SEMICONDUCTOR DEVICE HAVING A RESISTOR STRUCTURE - Provided is a method of fabricating a semiconductor device. The method includes providing a substrate including a transistor area and a resistor area, forming dummy gate structures on the substrate in the resistor area, and a lower interlayer insulating layer; forming a resistor structure having a buffer insulating pattern, a resistor element and an etch-retard pattern disposed sequentially on the lower interlayer insulating layer; and forming resistor contact structures configured to pass through the etch-retard pattern and to contact with the resistor element. | 2016-01-21 |
20160020149 | SEMICONDUCTOR DEVICE AND METHOD FOR FABRICATING THE SAME - Provided are a semiconductor device and a method for fabricating the same. The semiconductor device includes a substrate including a circuit region and a scribe lane region, an active fin protruding from the substrate in the circuit region, a first gate structure extending over the active fin in the circuit region, and a second gate structure formed in the scribe lane region. | 2016-01-21 |
20160020150 | METHODS OF MANUFACTURING SEMICONDUCTOR DEVICES BY FORMING SOURCE/DRAIN REGIONS BEFORE GATE ELECTRODE SEPARATION - Spaced apart first and second fins are formed on a substrate. An isolation layer is formed on the substrate between the first and second fins. A gate electrode is formed on the isolation layer and crossing the first and second fins. Source/drain regions are formed on the first and second fins adjacent the gate electrode. After forming the source/drain regions, a portion of the gate electrode between the first and second fins is removed to expose the isolation layer. The source/drain regions may be formed by epitaxial growth. | 2016-01-21 |
20160020151 | SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING THE SAME - The present disclosure relates to a semiconductor device and a method of manufacturing the same. The semiconductor device may include a first metal gate electrode provided in a NMOS region of a substrate; and a second metal gate electrode provided in a PMOS region of the substrate, wherein the first and second metal gate electrodes may be formed of TiN material or TiAlN material. Here, the first metal gate electrode may have a higher titanium (Ti) content than the second metal gate electrode, and the second metal gate electrode may have a higher nitrogen (N) content than the first metal gate electrode. | 2016-01-21 |
20160020152 | METHOD OF FORMING SPACERS FOR A GATE OF A TRANSISTOR - A method for forming spacers of a field effect transistor gate, comprising forming a nitride layer covering the gate, modifying the nitride layer by contacting the nitride layer with plasma comprising ions heavier than hydrogen and CxHy so as to form a nitride-based modified layer and a carbon film; with the modifying being so executed that plasma creates an anisotropic bombardment with hydrogen (H)-based ions from CxHy in a favorite direction parallel to flanks of the gate and so as to modify an upper portion of the thickness of the nitride-based layer at the level of the flanks of the gate only, with the anisotropic bombardment with ions heavier than hydrogen enabling the carbon in CxHy to form a carbon film, and removing the nitride-based modified layer, using etching of the nitride-based modified layer to said carbon film and to the non-modified portions which the spacers are made of. | 2016-01-21 |
20160020153 | METHOD TO FABRICATE A TRANSISTOR WHEREIN THE LEVEL OF STRAIN APPLIED TO THE CHANNEL IS ENHANCED - Method of manufacturing a transistor on a layer made of a first crystalline semiconducting material to make a channel, deposited on a dielectric layer, the method including the following steps:
| 2016-01-21 |
20160020154 | SIMPLIFIED MULTI-THRESHOLD VOLTAGE SCHEME FOR FULLY DEPLETED SOI MOSFETS - A method for semiconductor fabrication includes providing channel regions on a substrate including at least one Silicon Germanium (SiGe) channel region, the substrate including a plurality of regions including a first region and a second region. Gate structures are formed for a first n-type field effect transistor (NFET) and a first p-type field effect transistor (PFET) in the first region and a second NFET and a second PFET in the second region, the gate structure for the first PFET being formed on the SiGe channel region. The gate structure for the first NFET includes a gate material having a first work function and the gate structures for the first PFET, second NFET and second PFET include a gate material having a second work function such that multi-threshold voltage devices are provided. | 2016-01-21 |
20160020155 | LIGHT SOURCE TESTING APPARATUS, TESTING METHOD OF LIGHTING SOURCE AND MANUFACTURING METHOD OF LIGHT-EMITTING DEVICE PACKAGE, LIGHT EMITTING MODULE, AND ILLUMINATION APPARATUS USING THE SAME - A method of fabricating a light source includes providing a semiconductor light source emitting light when power is applied thereto, supplying power to the semiconductor light source, receiving light emitted by the semiconductor light source and performing a first measurement of optical properties of the received light, receiving light emitted by the semiconductor light source after a period of time has elapsed from the first measurement and performing a second measurement of optical properties of the received light, determining whether the semiconductor light source is defective or not by comparing the results of the first measurements of optical properties and the second measurements of optical properties, and constructing the light source including the semiconductor light source by providing peripheral parts thereof, wherein the semiconductor light source is determined as being normal as a result of determining whether the semiconductor light source is defective or not. | 2016-01-21 |
20160020156 | METHOD FOR MANUFACTURING SILICON CARBIDE SEMICONDUCTOR DEVICE - The trench has, in a cross-sectional view, a first corner portion which is an intersection between a first sidewall surface and a bottom portion and a second corner portion which is an intersection between a second sidewall surface and the bottom portion. A first layer has a second-conductivity-type region. In a cross-sectional view, the second-conductivity-type region is arranged to intersect with a line which passes through any of the first corner portion and the second corner portion and is in parallel to a <0001> direction of a silicon carbide crystal forming the silicon carbide layer. A ratio calculated by dividing SP by ST is not lower than 20% and not higher than 130%, where ST represents a total area of the trenches in a boundary surface between the first layer and a second layer and SP represents a total area of the second-conductivity-type regions in a plan view. | 2016-01-21 |
20160020157 | POLISHING WITH EDDY CURRENT FEED MEAUREMENT PRIOR TO DEPOSITION OF CONDUCTIVE LAYER - A method of controlling polishing includes storing a base measurement, the base measurement being an eddy current measurement of a substrate after deposition of at least one layer overlying a semiconductor wafer and before deposition of a conductive layer over the at least one layer, after deposition of the conductive layer over the at least one layer and during polishing of the conductive layer on substrate, receiving a sequence of raw measurements of the substrate from an in-situ eddy current monitoring system, normalizing each raw measurement in the sequence of raw measurement to generate a sequence of normalized measurements using the raw measurement and the base measurement, and determining at least one of a polishing endpoint or an adjustment for a polishing rate based on at least the sequence of normalized measurements. | 2016-01-21 |
20160020158 | Systems and Methods for Self Test Circuit Security - The present inventions are related to systems and methods for circuit implementation, and more particularly to systems and methods for securing data in a circuit. | 2016-01-21 |
20160020159 | SEMICONDUCTOR DEVICE HAVING TEST STRUCTURE - A semiconductor device is provided. First and second pads are electrically connected to a plurality of test structures. Each test structure includes an active region, active patterns, gate electrodes and an electrode pattern. The active region includes a rounded corner portion. The active patterns protrudes from the semiconductor substrate and extends in parallel in a first direction. The gate electrodes crosses over the active patterns in a second direction. One gate electrode is electrically connected to the first pad. The electrode pattern is disposed at a side of the gate electrode electrically connected to the first pad. The electrode pattern is electrically connected to the second pad. The electrode pattern crosses over the active patterns. An overlapping area of the electrode pattern and the active patterns in each test structure is different from an overlapping area of the electrode pattern and the active patterns in other test structures. | 2016-01-21 |
20160020160 | DEVICES EMPLOYING SEMICONDUCTOR DIE HAVING HYDROPHOBIC COATINGS, AND RELATED COOLING METHODS - Devices employing semiconductor die having hydrophobic coatings, and related cooling methods are disclosed. A device may include at least one semiconductor die electrically coupled to a substrate by electrical contact elements. During operation the semiconductor die and the electrical contact elements generate heat. By applying hydrophobic coatings to the semiconductor die and the electrical contact elements, a cooling fluid may be used to directly cool the semiconductor die and the electrical contact elements to maintain these components within temperature limits and free from electrical shorting and corrosion. In this manner, the semiconductor die and associated electrical contact elements may be cooled to avoid the creation of damaging localized hot spots and temperature-sensitive semiconductor performance issues. | 2016-01-21 |
20160020161 | SEMICONDUCTOR DEVICE AND SEMICONDUCTOR DEVICE MANUFACTURING METHOD - A semiconductor device includes a semiconductor element; an insulating substrate formed from stacking a rectangular shaped circuit plate, insulating plate, and metal plate, wherein the semiconductor element is fixed to the circuit plate, and the metal plate has at least one first groove portion in four corners thereof; a radiating member made of metal and having a predetermined arrangement area to dispose the insulating substrate, the radiating member having at least one second groove portion provided in four corners of the arrangement area; four positioning members disposed between the four corners of the metal plate and the four corners of the radiating member, each of the four positioning members being fitted to each of the first groove portions and second groove portions; and a solder filling a space between the insulating substrate and the radiating member, and covering the positioning members. | 2016-01-21 |
20160020162 | SEMICONDUCTOR DEVICE - A semiconductor device includes: a semiconductor chip, and a lead frame. The semiconductor chip is mounted over a die pad. Four suspension leads are connected with the die pad and at least one of them is provided between first and second lead groups and is deformed to protrude toward the first lead group. At least one of the leads of the second lead group which is nearer to the deformed suspension lead is deformed to be apart from remaining leads of the second lead group. | 2016-01-21 |
20160020163 | Wiring Substrate and Semiconductor Device - A wiring substrate includes a first wiring structure and a second wiring structure. The first wiring structure includes a first insulating layer, which covers a first wiring layer, and a via wiring. A first through hole of the first insulating layer is filled with the via wiring. The second wiring structure includes a second wiring layer and a second insulating layer. The second wiring layer is formed on an upper surface of the first insulating layer and an upper end surface of the via wiring. The second wiring layer partially includes a roughened surface. The second insulating layer is stacked on the upper surface of the first insulating layer and covers the second wiring layer. The second wiring structure has a higher wiring density than the first wiring structure. The roughened surface of the second wiring layer has a smaller surface roughness than the first wiring layer. | 2016-01-21 |
20160020164 | WIRING SUBSTRATE AND METHOD FOR MANUFACTURING THE SAME - A wiring substrate includes a first outermost conductor layer, a first outermost insulating layer covering the first conductor layer, a second outermost conductor layer formed on opposite side of the first conductor layer, and a second outermost insulating layer covering the second conductor layer. The first insulating layer has first openings such that the first openings are exposing first conductor pads including portions of the first conductor layer, the second insulating layer has second openings such that the second openings are exposing second conductor pads including portions of the second conductor layer, each of the first conductor pads has a first plating layer recessed with respect to outer surface of the first insulating layer, and each of the second conductor pads has a second plating layer formed flush with outer surface of the second insulating layer or having bump shape protruding from the outer surface of the second insulating layer. | 2016-01-21 |
20160020165 | MULTI-LAYER PACKAGE WITH INTEGRATED ANTENNA - Embodiments of the present disclosure describe a multi-layer package with antenna and associated techniques and configurations. In one embodiment, an integrated circuit (IC) package assembly includes a first layer having a first side and a second side disposed opposite to the first side a second layer coupled with the first side of the first layer, one or more antenna elements coupled with the second layer and a third layer coupled with the second side of the first layer, wherein the first layer is a reinforcement layer having a tensile modulus that is greater than a tensile modulus of the second layer and the third layer. Other embodiments may be described and/or claimed. | 2016-01-21 |
20160020166 | TRACE STRUCTURE OF FINE-PITCH PATTERN - A trace structure of fine-pitch pattern includes a connection portion, a first conductive wire portion and a second conductive wire portion, the first conductive wire portion comprises a first section and a second section connected to the first section, the first section connects to the connection portion, the second conductive wire portion comprises a third section and a fourth section connected to the third section, the third section connects to the connection portion, wherein an etching space closed on three sides is formed by the connection portion, the third section and the first section, a first spacing is defined between the third section and the first section, a second spacing is defined between the fourth section and the second section, wherein the first spacing is larger than the second spacing so as to make an metal layer within the etching space completely removed to avoid metal layer residues. | 2016-01-21 |
20160020167 | SEMICONDUCTOR STRUCTURE - A semiconductor structure is provided. The semiconductor structure includes a conductive strip, a conductive layer, a first dielectric layer, and a second dielectric layer. The first dielectric layer is between the conductive strip and the conductive layer arranged in a crisscross manner. The second dielectric layer is different from the first dielectric layer. The second dielectric layer and the first dielectric layer are adjoined with the conductive strip in different positions on the same sidewall of the conductive strip. | 2016-01-21 |
20160020168 | Metal Line Structure and Method - A device comprises a first rounded metal line in a metallization layer over a substrate, a second rounded metal line in the metallization layer, a first air gap between sidewalls of the first rounded metal line and the second metal line, a first metal line in the metallization layer, wherein a top surface of the first metal line is higher than a top surface of the second rounded metal line and a bottom surface of the first metal line is substantially level with a bottom surface of the second rounded metal line and a second air gap between sidewalls of the second rounded metal line and the first metal line. | 2016-01-21 |
20160020169 | SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING THE SAME - A semiconductor device includes a substrate; a stack structure including a plurality of insulating films and a plurality of metal films disposed alternately one above another. The stack structure is provided above the substrate and has a stairway portion including a plurality of terraces located at least at one end portion thereof. A liner film and a stopper film are disposed so as to cover an upper portion the stack structure in the stairway portion formed of the terraces. A plurality of holes are connected to each of the terraces. Each of the terraces is formed of a stack of the insulating films and the metal films. Each of the holes extends through the stopper film and the liner film and connect to the metal films of the terraces. | 2016-01-21 |
20160020170 | STACKED INTEGRATED CIRCUITS WITH REDISTRIBUTION LINES - An integrated circuit structure includes a first and a second semiconductor chip. The first semiconductor chip includes a first substrate and a first plurality of dielectric layers underlying the first substrate. The second semiconductor chip includes a second substrate and a second plurality of dielectric layers over the second substrate, wherein the first and the second plurality of dielectric layers are bonded to each other. A metal pad is in the second plurality of dielectric layers. A redistribution line is over the first substrate. A conductive plug is electrically coupled to the redistribution line. The conductive plug includes a first portion extending from a top surface of the first substrate to a bottom surface of the first substrate, and a second portion extending from the bottom surface of the first substrate to the metal pad. A bottom surface of the second portion contacts a top surface of the metal pad. | 2016-01-21 |
20160020171 | SEMICONDUCTOR PACKAGE AND METHOD OF MANUFACTURING THE SAME - The semiconductor package according to an exemplary embodiment includes: a substrate having a plurality of circuit layers and connection pads which are provided between a plurality of insulating layers; a plated tail part of which one end is electrically connected to the connection pad; a dicing part provided in contact with the other end of the plated tail part; a molded part provided on the substrate; and molded part vias provided on the connection pads and penetrating through the molded part. | 2016-01-21 |