03rd week of 2022 patent applcation highlights part 56 |
Patent application number | Title | Published |
20220020791 | IMAGING SYSTEM INCLUDING ANALOG COMPRESSION FOR SIMULTANEOUS PULSE DETECTION AND IMAGING - An imaging system includes a light sensor, a pulse detection imaging (PDI) circuit, and an image processing unit. The light sensor generates one or both of an image signal and a pulse signal. The pulse PDI circuit includes a first terminal in signal communication with the light sensor to receive one or both of the image signal and the pulse signal and a second terminal in signal communication with a voltage source. The image processing unit is in signal communication with the PDI circuit to receive one or both of the image signal and the pulse signal and to simultaneously perform imagery and pulse detection based on the image signal and the pulse signal, respectively. | 2022-01-20 |
20220020792 | IMAGING ELEMENT AND IMAGING DEVICE - An imaging element and device configured for reduced image quality deterioration are disclosed. In one example, a pixel unit of the imaging element includes a selection transistor and an amplification transistor each constituted by a multigate transistor. The selection transistor and amplification transistor may be a FinFET that includes a silicon channel having a fin shape. Moreover, gates of the selection transistor and the amplification transistor may be formed on an identical silicon channel having a fin shape. Furthermore, for example, an ion having a smaller thermal diffusivity than a thermal diffusivity of boron or phosphorous is injected into the silicon channel of the selection transistor. In addition, for example, a work function of a material of a gate electrode of the selection transistor is different from a work function of a material of a gate electrode of the amplification transistor. | 2022-01-20 |
20220020793 | SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD THEREOF - In a CMOS image sensor in which a plurality of pixels is arranged in a matrix, a transistor in which a channel formation region includes an oxide semiconductor is used for each of a charge accumulation control transistor and a reset transistor which are in a pixel portion. After a reset operation of the signal charge accumulation portion is performed in all the pixels arranged in the matrix, a charge accumulation operation by the photodiode is performed in all the pixels, and a read operation of a signal from the pixel is performed per row. Accordingly, an image can be taken without a distortion. | 2022-01-20 |
20220020794 | IMAGE SENSORS AND ELECTRONIC DEVICES - An image sensor may include a substrate, and a plurality of wavelength separation filters on the substrate and arranged along an in-plane direction of the substrate. The wavelength separation filters include a first wavelength separation filter configured to selectively transmit incident light in the first wavelength spectrum, and photoelectrically convert the incident light in at least one of the second wavelength spectrum or the third wavelength spectrum, a second wavelength separation filter configured to selectively transmit the incident light in the second wavelength spectrum and photoelectrically convert the incident light in at least one of the first wavelength spectrum or the third wavelength spectrum, and a third wavelength separation filter configured to selectively transmit the incident light in the third wavelength spectrum and photoelectrically convert the incident light in at least one of the first wavelength spectrum or the second wavelength spectrum. | 2022-01-20 |
20220020795 | IMAGE SENSING DEVICE - An image sensing device includes a pixel array including a (2x2) array that includes two first pixels, a second pixel, and a third pixel, wherein the first to third pixels have a pixel area and include first to third optical filters that are configured to transmit light of different colors, respectively, and wherein the second pixel or the third pixel includes a grid structure located along a boundary of the second pixel or the third pixel, and wherein the first pixel includes a red optical filter and has a first light reception area that is greater than a second light reception area of the second pixel or a third light reception area of the third pixel. | 2022-01-20 |
20220020796 | SPECTRAL FILTER, AND IMAGE SENSOR AND ELECTRONIC DEVICE INCLUDING THE SPECTRAL FILTER - Provided are a spectral filter, a method of manufacturing the same, and an image sensor and an electronic device each including the spectral filter. The spectral filter includes a plurality of first reflective layers provided spaced apart from each other, and a plurality of cavities provided between the plurality of first reflective layers. The cavities have different thicknesses according to a center wavelength. Each of the cavities includes a plurality of etch stop layers having a constant total thickness according to the center wavelength, and at least one dielectric layer having a total thickness which changes according to the center wavelength, wherein the etch stop layers include materials having etch selectivities different than that of the dielectric layer. | 2022-01-20 |
20220020797 | IMAGE SENSOR - An image sensor includes a substrate having a plurality of pixel regions, a lower layer on the substrate; a plurality of color filters on the lower layer, and a micro-lens layer on or covering top surfaces of the color filters. The micro-lens layer extends to a location between two of the color filters and contacts the lower layer on one of the pixel regions. The color filters are spaced apart from the lower layer. | 2022-01-20 |
20220020798 | MOIRE PATTERN IMAGING DEVICE - A moiré pattern imaging device includes a light-transmissive film and a light-shielding film. The light-transmissive film includes a plurality of imaging units and a light-incident surface and a light-emergent surface opposite to each other. The plurality of imaging units are disposed on the light-incident surface, the light-emergent surface, or a combination thereof and are arranged in two dimensions to form an imaging unit array. The light-shielding film includes a plurality of light-transmissive regions. The light-transmissive regions are arranged in two dimensions to form a light-transmissive array, and the light-shielding film is overlaid on the light-incident surface or the light-emergent surface. The light-transmissive array corresponds to the imaging unit array. The imaging unit array and the light-transmissive array together form a moiré pattern effect to generate an image magnification effect. | 2022-01-20 |
20220020799 | SOLID-STATE IMAGING APPARATUS AND ELECTRONIC APPARATUS - There is provided a imaging device including: an N-type region formed for each pixel and configured to perform photoelectric conversion; an inter-pixel light-shielding wall penetrating a semiconductor substrate in a depth direction and formed between N-type regions configured to perform the photoelectric conversion, the N-type regions each being formed for each of pixels adjacent to each other; a P-type layer formed between the N-type region configured to perform the photoelectric conversion and the inter-pixel light-shielding wall; and a P-type region adjacent to the P-type layer and formed between the N-type region and an interface on a side of a light incident surface of the semiconductor substrate. | 2022-01-20 |
20220020800 | METHOD FOR DEFINING A GAP HEIGHT WITHIN AN IMAGE SENSOR PACKAGE - According to an aspect, a method for fabricating an image sensor package to define a gap height includes coupling an image sensor die to a substrate, forming a plurality of pillar members on the image sensor die, dispensing a bonding material on the image sensor die, contacting a transparent member with the bonding material such that a height of the pillar members defines a gap height between an active region of the image sensor die and the transparent member, and curing the bonding material to couple the transparent member to the image sensor die. | 2022-01-20 |
20220020801 | IMAGE SENSING DEVICE - An image sensing device may include: a variable color filter configured to vary the wavelength range of light transmitted thereby; and a pixel array comprising a plurality of unit pixels each configured to generate a pixel signal corresponding to the intensity of light having penetrated the variable color filter. | 2022-01-20 |
20220020802 | IMAGE SENSOR AND METHOD FOR MANUFACTURING IMAGE SENSOR - There is provided an image sensor including: a light polarizing unit configured to transmit light in a specific light polarization direction out of incident light; a pixel configured to generate an image signal corresponding to the light transmitted through the light polarizing unit; and a signal transfer unit formed simultaneously with the light polarizing unit and configured to transfer either of the image signal and a control signal that controls generation of the image signal. | 2022-01-20 |
20220020803 | SEMICONDUCTOR DEVICE AND METHOD FOR FABRICATING THE SAME - A semiconductor device including: a first substrate including a first surface and a second surface; a first inter-wiring insulating film on the first substrate; a first wiring in the first inter-wiring insulating film; a landing via in the first inter-wiring insulating film, and spaced apart from the first wiring; a second substrate including a third surface and a fourth surface; a second inter-wiring insulating film on the second substrate; a second wiring in the second inter-wiring insulating film; and a through via structure penetrating the second substrate and the second inter-wiring insulating film, and electrically connecting the second wiring to the landing via, wherein with respect to the second surface of the first substrate, a top surface of the landing via is higher than a bottom surface of the first wiring, and a bottom surface of the landing via is lower than the bottom surface of the first wiring. | 2022-01-20 |
20220020804 | IMAGE SENSOR - An image sensor includes a substrate including a pixel region and a pad region and having a first surface and a second surface opposite to the first surface, the pad region of the substrate being provided with a first recess which is recessed to a first depth from the second surface toward the first surface and the pixel region of the substrate being provided with a plurality of unit pixels, an interlayer insulating layer disposed on the first surface, an interconnection line disposed in the interlayer insulating layer, a conductive pad disposed in the first recess of the pad region, and a plurality of penetration structures disposed in the pad region of the substrate and extending from a bottom surface of the first recess to the first surface of the substrate, and electrically connecting the conductive pad to the interconnection line. | 2022-01-20 |
20220020805 | PHOTODETECTOR - In a light detection device | 2022-01-20 |
20220020806 | LIGHT DETECTION DEVICE - In a light detection device, the semiconductor substrate has first and second main surfaces facing each other. The semiconductor substrate includes a plurality of cells. Each of the plurality of cells includes at least one avalanche photodiode. The plurality of pad electrodes are arranged on the first main surface so as to be spaced apart from the plurality of cells. The plurality of wiring portions are arranged on the first main surface. Each of the plurality of wiring portions connects the cell and the pad electrode corresponding to each other. The semiconductor substrate includes a peripheral carrier absorbing portion configured to absorb carriers located at a periphery of the peripheral carrier absorbing portion. The peripheral carrier absorbing portion is provided around each pad electrode and each wiring portion when viewed from a direction perpendicular to the first main surface. | 2022-01-20 |
20220020807 | INTERMEDIATE CONNECTION MEMBER, METHOD FOR MANUFACTURING INTERMEDIATE CONNECTION MEMBER, ELECTRONIC MODULE, METHOD FOR MANUFACTURING ELECTRONIC MODULE, AND ELECTRONIC EQUIPMENT - An intermediate connection member includes a first insulating substrate portion, a second insulating substrate portion, an insulating layer portion provided between the first insulating substrate portion and the second insulating substrate portion and formed from a different material from the first insulating substrate portion and the second insulating substrate portion, a plurality of first wiring portions provided between the first insulating substrate portion and the insulating layer portion so as to extend in a first direction such that both end portions of the plurality of first wiring portions in the first direction are exposed to an outside, and a plurality of second wiring portions provided between the second insulating substrate portion and the insulating layer portion so as to extend in the first direction such that both end portions of the plurality of second wiring portions in the first direction are exposed to the outside. | 2022-01-20 |
20220020808 | SEMICONDUCTOR APPARATUS - A semiconductor apparatus including: a first substrate; a first wiring structure; a second substrate; and a second wiring structure, wherein the first wiring structure has a first wiring layer bonded to wiring of the second wiring structure, a second wiring layer connected to the first wiring layer by a first via, and a third wiring layer connected to the second wiring layer by a second via, at least part of the second via is located at a range distanced, by at least a width of the first via, from an axis of the first via, a thickness of the second wiring layer is less than the width of the first via, a major constituent of the first wiring layer, the second wiring layer and the first via is copper, and a layer that is made from a material different from copper is disposed between the first and second wiring layers. | 2022-01-20 |
20220020809 | PACKAGING STRUCTURE, ELECTRONIC DEVICE, AND METHOD FOR MANUFACTURING THE PACKAGING STRUCTURE - A packaging structure for an image sensor used in an electronic device includes a flexible circuit board, a reinforcing plate, an image sensor, and an adhesive layer. The reinforcing plate is disposed on the flexible circuit board. The image sensor is disposed in the reinforcing plate. The adhesive layer bonds the flexible circuit board, the reinforcing plate, the image sensor and the conductor. | 2022-01-20 |
20220020810 | MULTI-COLOUR ELECTROLUMINESCENT DISPLAY DEVICE AND METHOD FOR MANUFACTURING SUCH A DEVICE - A device including first and second light-emitting cells respectively emitting in first and second wavelength ranges, wherein:
| 2022-01-20 |
20220020811 | OPTOELECTRONIC SEMICONDUCTOR CHIP AND METHOD FOR PRODUCING THE SAME - In at least one embodiment, the optoelectronic semiconductor chip ( | 2022-01-20 |
20220020812 | DISPLAY DEVICE AND METHOD OF MANUFACTURING THE SAME - A display device according to an example of the present disclosure includes a substrate on which a plurality of sub-pixels are defined; a plurality of LEDs including a first LED, a second LED, and a third LED that are disposed in the plurality of respective sub-pixels on the substrate; and at least one buffer layer disposed between the first LED and the substrate, wherein the first LED is in contact with an upper surface of the at least one buffer layer, and the second LED and the third LED are in contact with an upper surface of the substrate. Accordingly, the plurality of LEDs emitting light of different colors using the buffer layer can be respectively formed on one substrate, thereby allow for omission of a transfer process. | 2022-01-20 |
20220020813 | LIGHT EMITTING TRANSDUCER - A light emitting transducer including a flexible sheet having a bottom side and a top side, the flexible sheet including a substrate that is stretchable and compressible, the substrate having a bottom substrate surface at the bottom side, and a top substrate surface facing towards the top side, the top substrate surface comprising a surface pattern of a plurality of raised and depressed micro-scale surface portions which extend in at least one direction; a light emitting diode layer above the substrate and conforming in shape to the top substrate surface, the light emitting diode layer corresponding with the surface pattern of the top substrate surface, wherein the light emitting diode layer has a bottom diode surface facing towards the bottom side, and a top diode surface facing towards the top side, a bottom electrode on the bottom diode surface, and a top electrode on the top diode surface. | 2022-01-20 |
20220020814 | HALL INTEGRATED CIRCUIT AND CORRESPONDING METHOD OF MANUFACTURING OF A HALL INTEGRATED CIRCUIT USING WAFER STACKING - A Hall integrated circuit including a vertical Hall element, having a first wafer and a second wafer, the second wafer including a CMOS substrate integrating a CMOS processing circuit coupled to the vertical Hall element and a stack of dielectric layers, and the first wafer including a Hall-sensor layer having a first surface and a second surface, the first and second wafers being bonded with the interposition of a dielectric layer arranged above the first surface of the Hall-sensor layer. The vertical Hall element has: at least a first Hall terminal; at least a second Hall terminal; a deep trench isolation ring extending through the Hall-sensor layer from the first surface to the second surface and enclosing and isolating a Hall sensor region of the Hall-sensor layer; and a first and a second conductive structures electrically connected to respective contact pads embedded in the stack of the second wafer. | 2022-01-20 |
20220020815 | SILICON OVER INSULATOR TWO-TRANSISTOR ONE-RESISTOR IN-SERIES RESISTIVE MEMORY CELL - A resistive random-access memory (ReRAM) array is provided. The ReRAM array includes a silicon over insulator (SOI) substrate; a first bit line; a first inverted bit line of the first bit line; a second bit line; a second inverted bit line of the second bit line; a first word line; a first inverted word line of the first word line; a first ReRAM cell comprising a first MOSFET, a second MOSFET, and a resistive element; and a second ReRAM cell comprising a first MOSFET, a second MOSFET, and a resistive element connected in series; wherein upon applying a predefined potential on elements of the first ReRAM cell, a state of the first ReRAM cell is adjusted without effecting a state of the second ReRAM. | 2022-01-20 |
20220020816 | INTEGRATED CIRCUIT INCLUDING BIPOLAR TRANSISTORS - The disclosure relates to integrated circuits and methods including one or more rows of transistors. In an embodiment, an integrated circuit includes a row of bipolar transistors including a plurality of first conduction regions, a second conduction region, and a common base between the first conduction regions and the second conduction region. An insulating trench is in contact with each bipolar transistor of the row of bipolar transistors. A conductive layer is on the insulating trench and the common base between the first conduction regions. A spacer layer is between the conductive layer and the first conduction regions. | 2022-01-20 |
20220020817 | SEMICONDUCTOR MEMORY DEVICE - A semiconductor memory device including a substrate; a first conductive line on the substrate and extending in a first direction that is parallel to an upper surface of the substrate; a second conductive line extending in a second direction that intersects the first direction; a memory cell between the conductive lines and including a lower electrode pattern, a data storage element, an intermediate electrode pattern, a switching element, and an upper electrode pattern sequentially stacked on the first conductive line; and a sidewall spacer on a side surface of the memory cell, wherein the side surface of the memory cell includes a first concave portion at a side surface of the switching element, and the sidewall spacer includes a first portion on a side surface of the upper electrode pattern, and a second portion on the first concave portion, the second portion being thicker than the first portion. | 2022-01-20 |
20220020818 | VERTICAL NONVOLATILE MEMORY DEVICE INCLUDING MEMORY CELL STRING - A vertical nonvolatile memory device including memory cell strings using a resistance change material is provided. Each of the memory cell strings of the nonvolatile memory device includes a semiconductor layer extending in a first direction; a plurality of gates and a plurality of insulators alternately arranged in the first direction; a gate insulating layer extending in the first direction between the plurality of gates and the semiconductor layer and between the plurality of insulators and the semiconductor layer; and a resistance change layer extending in the first direction on a surface of the semiconductor layer. The resistance change layer includes a metal-semiconductor oxide including a mixture of a semiconductor material of the semiconductor layer and a transition metal oxide. | 2022-01-20 |
20220020819 | SOLID-STATE IMAGING DEVICE, METHOD OF MANUFACTURING SOLID-STATE IMAGING DEVICE, AND ELECTRONIC EQUIPMENT - A solid-state imaging device ( | 2022-01-20 |
20220020820 | LIGHT EMITTING DISPLAY DEVICE AND MANUFACTURING METHOD THEREOF - A light emitting display device includes a substrate including a display area and a non-display area adjacent to the display area, a lower pad electrode disposed on the substrate in the non-display area, a lower planarization layer disposed on the lower pad electrode and including a via hole exposing an upper surface of the lower pad electrode, an upper pad electrode disposed on the lower pad electrode, the upper pad electrode being electrically connected to the lower pad electrode through the via hole, and a covering layer in contact with a side surface portion of the upper pad electrode, the side surface portion of the upper pad electrode being disposed on the lower planarization layer. | 2022-01-20 |
20220020821 | DISPLAY DEVICE - A display device may include a substrate, a display element portion on a surface of the substrate, the display element portion including a plurality of display pixels, a color conversion portion on the display element portion, the color conversion portion including a plurality of banks and a wavelength conversion pattern between the plurality of banks, and a sensor electrode configured to obtain information of a touch input. The sensor electrode may include a first conductive layer arranged on at least a part of a surface of the plurality of banks. | 2022-01-20 |
20220020822 | COLOR FILTER SUBSTRATE AND METHOD FOR MANUFACTURING THE SAME, DISPLAY DEVICE - The present disclosure provides a color filter substrate and a method for manufacturing the same, and a display device, and the color filter substrate includes a base substrate, a black matrix and a color filter layer located on the base substrate, a quantum dot layer located on a side of the color filter layer away from the base substrate, a barrier layer located on a side of the black matrix away from the base substrate, and a first inorganic layer, and the first inorganic layer at least includes: a first portion located between the color filter layer and the quantum dot layer; a second portion located on the base substrate and between the quantum dot layer and the barrier layer; and a third portion located on a side of the barrier layer away from the base substrate. | 2022-01-20 |
20220020823 | DISPLAY DEVICE AND METHOD FOR MANUFACTURING SAME - A method for manufacturing a display device includes preparing a display panel that includes a first area, a bending area extending from the first area, and a second area extending from the bending area, attaching an anti-reflection layer to the display panel, removing a first removal section of a first releasing film disposed on the anti-reflection layer, the first removal section overlapping the second area of the display panel in a plan view, and providing a cover tape onto a first section of the anti-reflection layer that overlaps the second area of the display panel in a plan view. | 2022-01-20 |
20220020824 | ELECTRONIC DEVICE - An electronic device includes: a display panel configured to display an image; an input sensor on the display panel and comprising a first sensing electrode and a second sensing electrode that is electrically insulated from the first sensing electrode, the input sensor being configured to sense a first input in a first mode and to sense a second input in a second mode; and an input device configured to provide the second input to the input sensor, wherein at least one of the first or second sensing electrodes comprises: a main mesh pattern in a crossing area in which the first and second sensing electrodes cross each other; and a sub mesh pattern in a non-crossing area on which the first and second sensing electrodes do not cross each other and which has a size different from that of the main mesh pattern. | 2022-01-20 |
20220020825 | FLEXIBLE DISPLAY DEVICE - A flexible display device includes a protection member, a first adhesion member, a display member, a second adhesion member, and a window member. A thickness of the display member is less than a sum of thicknesses of the protection member and the window member. The display member includes a display panel layer, a touch sensing layer, and a reflection prevention layer integrated with each other to reduce a thickness of the flexible display device. The reduction in thickness enables the flexible display device to be bent with a relatively small radius of curvature, as well as to be repeatedly bent (or otherwise flexed) with reduced potential for delamination of the first and second adhesion members. | 2022-01-20 |
20220020826 | DISPLAY DEVICE, MASK ASSEMBLY, AND APPARATUS AND METHOD OF MANUFACTURING THE DISPLAY DEVICE - A display device includes a first sub-pixel have a square form, a second sub-pixel positioned to face a first side or a second side of the first sub-pixel and having a rectangular form, and a third sub-pixel positioned to face the first side or the second side of the first sub-pixel spaced from the second sub-pixel and having a rectangular form, wherein the first side and the second side of the first sub-pixel come together at an angle, and wherein the first sub-pixel, the second sub-pixel, and the third sub-pixel are configured to emit lights of different colors. | 2022-01-20 |
20220020827 | DISPLAY SUBSTRATE, METHOD FOR MANUFACTURING THE SAME, AND DISPLAY DEVICE - The present disclosure provides a display substrate, a manufacturing method thereof, and a display device. The display substrate includes a display area and a non-display area located at a periphery of the display area, wherein the display area includes a plurality of pixel opening areas and a pixel spacing area located between the pixel opening areas; the display substrate further includes: a first electrode, wherein at least part of the first electrode is located in the pixel spacing area, an orthographic projection of the first electrode on a substrate of the display substrate does not overlap an orthographic projection of the pixel opening area on the substrate; and a second electrode electrically connected to the first electrode and located in the non-display area. | 2022-01-20 |
20220020828 | LIGHT EMITTING DEVICE AND DISPLAY APPARATUS INCLUDING THE SAME - A light emitting device includes a metal reflective layer including a phase modulation surface on which oblong phase modulation elements are formed; a first electrode provided on the metal reflective layer; an organic emission layer that is provided on the first electrode and that emits light; and a second electrode provided on the organic emission layer, wherein the oblong phase modulation elements are arranged to form a geometric phase lens. | 2022-01-20 |
20220020829 | Display Substrate and Mask Plate Assembly - A display substrate and a mask plate assembly includes a base substrate, a pixel defining layer, a functional layer, a cathode layer, and a covering layer that are sequentially stacked in a direction away from the base substrate, wherein the size of orthographic projection of the functional layer on the base substrate is jointly determined by the size of a display area and a first minimum distance. The first minimum distance is the minimum distance in a direction from the display area to a non-display area and between the boundary of the display area and the boundary of the functional layer, and is determined by a first shadow width of the functional layer extending from the display area to the non-display area. The first shadow width is the maximum width of a shadow area formed within a preset region when the functional layer is vapor deposited in the preset region. | 2022-01-20 |
20220020830 | Patterning of Organic Light Emitting Diode Device and the OLED Displays Manufactured Therefrom - A method for producing ultrahigh resolution (for example, 800˜4000 Pixel Per Inch, PPI) Organic Light Emitting Diode (OLED) displays, with the following characteristics: S1, on top of the driving backplane, deposit the first electrode with designed spacing between one another. After that the Pixel Defining Layer (PDL) is deposited and patterned based on the designs of subpixels of the display; S2, on top of the defined subpixel regions from S1, deposit OLED devices, then fabricate the second electrode with the protection layer; S3, on top of the described second electrode with protection layer, deposit the third electrode. The present invention discloses the patterning method to produce OLED devices without using the conventional Metal Masks. Instead, an ultra-thin organic mask is fabricated using the special photolithographic process, and the OLED device structure that include the protection layer to prevent damages to the OLED device from the chemicals used during the processes. | 2022-01-20 |
20220020831 | DISPLAY DEVICE AND METHOD OF FABRICATING THE SAME - A display device, includes: a substrate including a plurality of pixel areas each having an emission area; and a pixel provided in each of the pixel areas, wherein the pixel comprises: at least one light emitting element on a first surface of the substrate; a first insulating layer on the light emitting element; at least one transistor on the first insulating layer and electrically connected to the light emitting element; a second insulating layer on the transistor; a common electrode on the second insulating layer; and a pixel electrode on a third insulating layer of the common electrode and electrically connected to the transistor, wherein the light emitting element comprises a semiconductor structure on the substrate, and first and second electrodes on the semiconductor structure to be spaced apart from each other. | 2022-01-20 |
20220020832 | DISPLAY DEVICE - A display device includes: a substrate; a TFT layer provided on the substrate; a light-emitting element layer provided on the TFT layer and including a plurality of light-emitting elements; and at least one thermal insulation layer, the thermal insulation layer containing: a cellulosic resin; and a metal oxide or a metal carbonyl compound. | 2022-01-20 |
20220020833 | DISPLAY DEVICE - A display device includes a display area and a peripheral area surrounding the display area, a thin film transistor in the display area, a first insulating layer, the first insulating layer covering the thin film transistor, a signal line on the first insulating layer, the signal line being coupled to the thin film transistor, a second insulating layer on the first insulating layer, the second insulating layer covering the signal line, a power supply line in the peripheral area, the power supply line configured to supply power to a pixel circuit including the thin film transistor, and a first dam including a multilayer structure on the power supply line and overlapping at least a part of the power supply line, in which multilayer structure including a lowermost layer including the same material as the second insulating layer, and the lowermost layer is above the power supply line. | 2022-01-20 |
20220020834 | DISPLAY APPARATUS - A display apparatus includes: a substrate; an insulating layer on the substrate and including a first opening; a plurality of first electrodes on the insulating layer, not overlapping the first opening, and spaced apart from each other; an emission layer on each of the plurality of first electrodes without overlapping the first opening; an intermediate layer including the emission layer; a second electrode on the intermediate layer; an encapsulation layer on the second electrode; and a polarization layer on the encapsulation layer and including a second opening overlapping the first opening. | 2022-01-20 |
20220020835 | DISPLAY DEVICE - A display device including a substrate including a main display area, a component area having a transmission area, and a peripheral area outside the main display area, a first thin film transistor and a first display element arranged over the main display area, a second thin film transistor and a second display element arranged over the component area, a bottom metal layer arranged between the substrate of the component area and the second thin film transistor and including a hole corresponding to the transmission area, and an organic layer arranged in the transmission area and having a hole pattern defined along an edge of the hole of the bottom metal layer. | 2022-01-20 |
20220020836 | DISPLAY PANEL AND DISPLAY DEVICE - The present invention provides a display panel and a display device. A first gate electrode and a first polar plate of a first thin film transistor are used to constitute a storage capacitor. At a same time, the first polar plate and a second gate electrode of a second thin film transistor are disposed in a same layer. Therefore, a gate insulation layer used to separate the first polar plate from the first gate electrode and the second gate electrode in layers can be omitted, so as to reduce a number of film layers in the display panel and a thickness of a film laminated structure, thereby reducing a complexity of a process flow of the display panel, and improving bending ability of the display panel. | 2022-01-20 |
20220020837 | DISPLAY DEVICE - A display device includes a substrate, a corrosion prevention layer on the substrate and including an inorganic material, a first conductive layer on the corrosion prevention layer and including aluminum or an aluminum alloy, a first insulating film on the first conductive layer, a semiconductor layer on the first insulating film and including a channel region of a transistor, a second insulating film on the semiconductor layer, and a second conductive layer on the second insulating film and including a barrier layer, which includes titanium, and a main conductive layer, which includes aluminum or an aluminum alloy, wherein the semiconductor layer includes an oxide semiconductor, and the barrier layer is between the semiconductor layer and the main conductive layer and overlaps the channel region of the transistor. | 2022-01-20 |
20220020838 | DISPLAY APPARATUS AND METHOD OF MANUFACTURING THE SAME - A display apparatus includes: a substrate including a display area, a peripheral area, a pad area, and a bending area, the peripheral area being outside the display area, the pad area being within the peripheral area, and the bending area being between the display area and the pad area; a first organic insulating layer at the bending area; a first conductive line on the first organic insulating layer; a second organic insulating layer on the first conductive line; a third organic insulating layer on the second organic insulating layer; and a metal pattern on the third organic insulating layer, and overlapping with at least a portion of the first conductive line. | 2022-01-20 |
20220020839 | DISPLAY DEVICE - A display device includes a first active pattern disposed on a substrate, a first gate electrode disposed on the first active pattern, a second active pattern disposed on the first gate electrode, being electrically connected to the first gate electrode, and including an extension part extending in a first direction and a protrusion part protruding from the extension part in a second direction crossing the first direction, and a voltage line disposed on the second active pattern, extending in the first direction, and overlapping the protrusion part in an overlapping region. The voltage line contacts the protrusion part through a first contact, and the first contact entirely overlaps the overlapping region on a plane. | 2022-01-20 |
20220020840 | DISPLAY APPARATUS HAVING A TRANSMITTING AREA - A display apparatus includes a substrate including a transmitting area, a display area surrounding the transmitting area, a first non-display area disposed between the transmitting area and the display area, and a second non-display area surrounding the display area. A plurality of pixels is arranged in the display area. A set of 2n connection wirings (where n is a positive integer) is disposed in the first non-display area and each of the 2n connection wirings extends along at least a part of an edge of the transmitting area. Each of a plurality of voltage wirings extends in a first direction and is connected to at least some of pixels disposed in a common row from among the plurality of pixels. Each of the plurality of voltage wirings is connected to one of the 2n connection wirings. | 2022-01-20 |
20220020841 | SEMICONDUCTOR DEVICE - A display device includes a pixel portion in which a pixel is arranged in a matrix, the pixel including an inverted staggered thin film transistor having a combination of at least two kinds of oxide semiconductor layers with different amounts of oxygen and having a channel protective layer over a semiconductor layer to be a channel formation region overlapping a gate electrode layer and a pixel electrode layer electrically connected to the inverted staggered thin film transistor. In the periphery of the pixel portion in this display device, a pad portion including a conductive layer made of the same material as the pixel electrode layer is provided. In addition, the conductive layer is electrically connected to a common electrode layer formed on a counter substrate. | 2022-01-20 |
20220020842 | DISPLAY DEVICE - A display device includes: a substrate; a data line on the substrate; a first insulating layer on the data line; a first transistor on the first insulating layer; a second insulating layer on the first transistor; a pixel electrode on the second insulating layer, the pixel electrode being electrically connected to the first transistor; and an auxiliary data pattern on the second insulating layer as a same layer as the pixel electrode, the auxiliary data pattern being electrically connected to the data line. | 2022-01-20 |
20220020843 | LATERAL CORELESS TRANSFORMER - A multi-voltage domain device includes a semiconductor layer including a first voltage domain, a second voltage domain, and an isolation region that electrically isolates the first voltage domain and the second voltage domain in a lateral direction. The isolation region includes at least one deep trench isolation barrier. A layer stack is arranged on the semiconductor layer and includes a stack insulator layer, a first coil arranged in the stack insulator layer, and a second coil arranged in the stack insulator layer and laterally separated from the first coil in the lateral direction. The first and second coils are magnetically coupled to each other in the lateral direction. The first coil includes terminals arranged vertically over the first region and are electrically coupled to the first voltage domain, and the second coil includes terminals arranged vertically over the second region and are electrically coupled to the second voltage domain. | 2022-01-20 |
20220020844 | TRENCH CAPACITOR HAVING IMPROVED CAPACITANCE AND FABRICATION METHOD THEREOF - A semiconductor memory device includes a substrate; a film stack on the substrate; a silicon device layer on the film stack; and a trench with corrugated sidewall surface extending into the silicon device layer, the film stack, and the substrate. A trench capacitor is located in the trench. The trench capacitor includes an inner electrode and an outer electrode with a node dielectric layer therebetween. The node dielectric layer is in direct with the film stack and the bulk semiconductor substrate. A transistor is disposed on the substrate. The transistor includes a source region and a drain region, a channel region between the source region and the drain region, and a gate over the channel region. The source region is electrically connected to the inner electrode of the trench capacitor. | 2022-01-20 |
20220020845 | SEMICONDUCTOR DEVICE HAVING SUPPORTER PATTERN - A method of manufacturing a semiconductor device includes sequentially stacking a mold layer and a supporter layer on a substrate, forming a plurality of capacitor holes passing through the mold layer and supporter layer, forming a plurality of lower electrodes filling the capacitor holes, forming a supporter mask pattern having a plurality of mask holes on the supporter layer and the lower electrodes, and forming a plurality of supporter holes by patterning the supporter layer. Each of the plurality of lower electrodes has a pillar shape, and each of the mask holes is between four adjacent lower electrodes and has a circular shape. | 2022-01-20 |
20220020846 | SEMICONDUCTOR DEVICE WITH COMPLEMENTARILY DOPED REGIONS AND METHOD OF MANUFACTURING - In an example, a first hard mask is formed on a first surface of a semiconductor body, wherein first openings in the first hard mask expose first surface sections and second openings in the first hard mask expose second surface sections. First dopants of a first conductivity type are implanted selectively through the first openings into the semiconductor body. Second dopants of a second conductivity type are implanted selectively through the second openings into the semiconductor body. The second conductivity type is complementary to the first conductivity type. A second hard mask is formed that covers the first surface sections and the second surface sections, wherein third openings in the second hard mask expose third surface sections and fourth openings in the second hard mask expose fourth surface sections. Third dopants of the first conductivity type are implanted selectively through the third openings into the semiconductor body. Fourth dopants of the second conductivity type are implanted selectively through the fourth openings into the semiconductor body. | 2022-01-20 |
20220020847 | SEMICONDUCTOR STRUCTURE AND MANUFACTURING METHOD THEREOF - A method of manufacturing a semiconductor structure includes the following steps: providing a first semiconductor wafer, wherein the first semiconductor wafer includes a first dielectric layer and at least one first top metallization structure embedded in the first dielectric layer, and a top surface of the first dielectric layer is higher than a top surface of the first top metallization structure by a first distance; providing a second semiconductor wafer, wherein the second semiconductor wafer includes a second dielectric layer and at least one second top metallization structure embedded in the second dielectric layer, and a top surface of the second top metallization structure is higher than a top surface second dielectric layer of the by a second distance; and hybrid-bonding the first semiconductor wafer and the second semiconductor wafer. | 2022-01-20 |
20220020848 | MONOLITHIC SEMICONDUCTOR DEVICE ASSEMBLIES - In a general aspect, a semiconductor device assembly can include a semiconductor substrate that excludes a buried oxide layer. The semiconductor device assembly can also include a first semiconductor device stack disposed on a first portion of the semiconductor substrate, and a second semiconductor device stack disposed on a second portion of the semiconductor substrate. The semiconductor device assembly can further include an isolation trench having a dielectric material disposed therein, the isolation trench being disposed between the first portion of the semiconductor substrate and the second portion of the semiconductor substrate. The isolation trench can electrically isolate the first portion of the semiconductor substrate from the second portion of the semiconductor substrate. | 2022-01-20 |
20220020849 | SEMICONDUCTOR DEVICES AND METHODS OF FABRICATING THE SAME - A semiconductor device includes a gate electrode extending in a first direction, on a substrate, first outer spacers extending along side surfaces of the gate electrode, a first active pattern extending in a second direction, which intersects the first direction, to penetrate the gate electrode and the first outer spacers, epitaxial patterns on the first active pattern and on side surfaces of the first outer spacers, second outer spacers between the first outer spacers and the epitaxial patterns and inner spacers between the substrate and the first active pattern and between the gate electrode and the epitaxial patterns, wherein in a cross section that intersects the second direction, at least parts of the second outer spacers are on side surfaces of the first active pattern and side surfaces of the inner spacers. | 2022-01-20 |
20220020850 | FEEDER DESIGN WITH HIGH CURRENT CAPABILITY - A feeder design is manufactured as a structure in a SIC semiconductor material comprising at least two p-type grids in an n-type SiC material ( | 2022-01-20 |
20220020851 | UP-DIFFUSION SUPPRESSION IN A POWER MOSFET - A substrate for fabricating a MOSFET device includes a first epitaxial layer disposed on a silicon wafer. The silicon wafer is doped with a first dopant. A second epitaxial layer is disposed on the first epitaxial layer. An ion-implanted capping layer is disposed in the first epitaxial layer. The ion-implanted capping layer is doped with a second dopant. The first dopant has a diffusion coefficient in silicon higher than a diffusion coefficient of the second dopant in silicon. The ion-implanted capping layer is configured to limit up-diffusion of the first dopant from the silicon wafer into the second epitaxial layer. | 2022-01-20 |
20220020852 | WAFER AND METHOD OF MANUFACTRURING WAFER - The wafer having a retardation distribution measured with a light having a wavelength of 520 nm, wherein an average value of the retardation is 38 nm or less, wherein the wafer comprises a micropipe, and wherein a density of the micropipe is 1.5/cm | 2022-01-20 |
20220020853 | SEMICONDUCTOR DEVICE - A semiconductor device of embodiments includes a silicon carbide layer having a first face and a second face, a gate electrode, a gate insulating layer on the first face. The silicon carbide layer includes a first silicon carbide region of a first conductive type; a second silicon carbide region of a second conductive type disposed between the first silicon carbide region and the first face; a third silicon carbide region of a second conductive type between the first silicon carbide region and the first face; a fourth silicon carbide region; a fifth silicon carbide region; a sixth silicon carbide region of a second conductive type between the first silicon carbide region and the first face and between the second silicon carbide region and the third silicon carbide region; and a crystal defect. The crystal defect is in the sixth silicon carbide region. | 2022-01-20 |
20220020854 | SEMICONDUCTOR DEVICE AND METHOD FOR MANUFACTURING SAME - A semiconductor device includes: a doped region having a first conductive type in which a source region and/or a drain region having a second conductive type is formed; padding layers having the second conductive type formed on the source region and/or the drain region and in contact with the source region and/or the drain region; an interlayer dielectric layer formed on the doped region and the padding layers; electrodes penetrating through the dielectric layer and extending into the padding layers so as to be electrically connected with the padding layers. | 2022-01-20 |
20220020855 | GATE-LAST FERROELECTRIC FIELD EFFECT TRANSISTOR AND MANUFACTURING METHOD THEREOF - A gate-last ferroelectric field effect transistor includes a substrate, isolation regions, a gate structure, a side wall spacer, source and drain regions, a first metal silicide layer and an interlayer dielectric layer which are sequentially arranged from bottom to top; the present disclosure further provides a manufacturing method of a gate-last ferroelectric field effect transistor; according to structural characteristics of the gate-last ferroelectric field effect transistor and crystalline characteristics of a hafnium oxide-based ferroelectric film, a dummy gate is first introduced in a manufacturing process of the gate-last ferroelectric field effect transistor; afterwards, high-temperature annealing is performed to make sure that an unannealed hafnium oxide-based film is crystallized to form a ferroelectric phase; finally the dummy gate is removed and a gate electrode layer is deposited to meet performance requirements of the gate-last ferroelectric field effect transistor; and the gate-last ferroelectric field effect transistor has an excellent application prospect. | 2022-01-20 |
20220020856 | 3D MEMORY DEVICE INCLUDING SOURCE LINE STRUCTURE COMPRISING COMPOSITE MATERIAL - A semiconductor structure and a method for manufacturing the same are provided. The semiconductor structure includes a source line structure. The source line structure includes a composite material formed in a trench. The composite material includes an oxide portion and a metal portion. | 2022-01-20 |
20220020857 | GATE CONTACT INTERLAYER FOR HEMT DEVICES WITH SELF-ALIGNED ELECTRODES - A HEMT is described in which a gate contact interlayer is included between a surface dielectric and a gate contact. Further, source, drain, and gate contacts may be self-aligned and formed using a single or same metal and metallization process. A gate may be formed in contact with, and covering a portion of, a barrier layer of the HEMT, with a gate contact formed in contact with the gate. The gate contact interlayer may be formed between a surface dielectric formed on the barrier layer and at least a portion of the gate contact. | 2022-01-20 |
20220020858 | TRENCH GATE DEVICE AND METHOD FOR MAKING THE SAME - A method for manufacturing a trench gate device includes: forming a trench in a substrate with a super junction structure; forming a gate dielectric layer in the trench; forming a polysilicon gate by filling a portion of the trench with polysilicon; forming an intermediate dielectric layer in the trench; forming an auxiliary polysilicon layer by filling a gap in the trench with polysilicon; forming a source region of the trench gate device in the substrate; depositing an interlayer dielectric layer, and forming contacts in the interlayer dielectric layer, wherein the polysilicon gate, the auxiliary polysilicon layer, and the source region are led out from the contacts; and connecting the led-out auxiliary polysilicon layer to the led-out source region. | 2022-01-20 |
20220020859 | SEMICONDUCTOR DEVICES - Semiconductor devices and methods of forming the same are disclosed. The semiconductor devices may include a substrate including a first region and a second region, which are spaced apart from each other with a device isolation layer interposed therebetween, a first gate electrode and a second gate electrode on the first and second regions, respectively, an insulating separation pattern separating the first gate electrode and the second gate electrode from each other and extending in a second direction that traverses the first direction, a connection structure electrically connecting the first gate electrode to the second gate electrode, and a first signal line electrically connected to the connection structure. The first and second gate electrodes are extended in a first direction and are aligned to each other in the first direction. The first signal line may extend in the second direction and may vertically overlap the insulating separation pattern. | 2022-01-20 |
20220020860 | SEMICONDUCTOR DEVICE - A semiconductor device including: a substrate that includes a first active region and a second active region; a first source/drain pattern on the first active region; a second source/drain pattern on the second active region; a separation dielectric pattern on the substrate between the first source/drain pattern and the second source/drain pattern; and a first contact pattern on the first source/drain pattern, wherein the first contact pattern includes: a first metal pattern; a first barrier pattern between the first metal pattern and the first source/drain pattern; and a second barrier pattern between the first barrier pattern and the first source/drain pattern, wherein the first barrier pattern contacts the separation dielectric pattern and extends along a sidewall of the first metal pattern adjacent to the separation dielectric pattern. | 2022-01-20 |
20220020861 | Composite Work Function Layer Formation Using Same Work Function Material - A method includes forming a gate dielectric layer on a semiconductor region, and depositing a first aluminum-containing work function layer using a first aluminum-containing precursor. The first aluminum-containing work function layer is over the gate dielectric layer. A second aluminum-containing work function layer is deposited using a second aluminum-containing precursor, which is different from the first aluminum-containing precursor. The second aluminum-containing work function layer is deposited over the first aluminum-containing work function layer. A conductive region is formed over the second aluminum-containing work function layer. | 2022-01-20 |
20220020862 | CARBON-FREE LAMINATED HAFNIUM OXIDE/ZIRCONIUM OXIDE FILMS FOR FERROELECTRIC MEMORIES - Provided are carbon-free (i.e., less than about 0.1 atomic percentage of carbon) Zr doped HfO | 2022-01-20 |
20220020863 | MANUFACTURE METHOD OF LATERAL DOUBLE-DIFFUSED TRANSISTOR - The present disclosure provides a manufacture method of an LDMOS. The manufacture method includes: forming a drift region in a substrate; forming a gate structure on the substrate, the gate structure defining a source region and a drain region which are separated from each other, and the gate structure including a gate oxide layer and a gate conductor layer which are successively stacked on the substrate; forming a first doped region in the source region, wherein the first doped region is surrounded by the drift region; forming a first barrier layer with a first opening on the source region and in connect with sidewall of the gate structure; forming a first implantation region in the source region through self-aligned implantation on the basis of the first opening of the first barrier layer; and forming a second implantation region and a third implantation region respectively. | 2022-01-20 |
20220020864 | THIN FILM TRANSISTOR, METHOD FOR MANUFACTURING THEREOF, ARRAY SUBSTRATE AND DISPLAY DEVICE - The present disclosure discloses a thin film transistor, a method for manufacturing thereof, an array substrate and a display device. The method for manufacturing the thin film transistor includes: forming a nanowire active layer on one side of a base substrate; forming a conductive protective layer on one side of the nanowire active layer away from the base substrate; forming an insulating layer on one side of the protective layer away from the nanowire active layer; etching the insulating layer using a dry etching process to form a first via hole exposing a first region of the protective layer and a second via hole exposing a second region of the protective layer; and forming a source-drain layer on one side of the insulating layer away from the protective layer, wherein the source-drain layer includes a first electrode and a second electrode. | 2022-01-20 |
20220020865 | Multilayer Masking Layer and Method of Forming Same - A method includes forming a semiconductor layer over a substrate; etching a portion of the semiconductor layer to form a first recess and a second recess; forming a first masking layer over the semiconductor layer; performing a first thermal treatment on the first masking layer, the first thermal treatment densifying the first masking layer; etching the first masking layer to expose the first recess; forming a first semiconductor material in the first recess; and removing the first masking layer. | 2022-01-20 |
20220020866 | SEMICONDUCTOR DEVICE AND METHOD OF FORMING THE SAME - A method of forming a semiconductor device includes forming, on a lower structure, a mold structure having interlayer insulating layers and gate layers alternately and repeatedly stacked. Each of the gate layers is formed of a first layer, a second layer, and a third layer sequentially stacked. The first and third layers include a first material, and the second layer includes a second material having an etch selectivity different from an etch selectivity of the first material. A hole formed to pass through the mold structure exposes side surfaces of the interlayer insulating layers and side surfaces of the gate layers. Gate layers exposed by the hole are etched, with an etching speed of the second material differing from an etching speed of the first material, to create recessed regions. | 2022-01-20 |
20220020867 | MANUFACTURING METHOD OF DISPLAY SUBSTRATE, DISPLAY SUBSTRATE AND DISPLAY DEVICE - A manufacturing method of a display substrate, a display substrate, and a display device. The manufacturing method includes: forming an active layer; forming a gate insulation film layer, a gate film layer and a photoresist film layer; exposing the photoresist film layer to a light and developing the exposed photoresist film layer until the developed photoresist film layer has a thickness of 1.8-2.2 μm and a slope angle not less than 70°; over-etching the gate film layer to form a gate electrode, an orthographic projection of the gate electrode being located within a region of an orthographic projection of the developed photoresist film layer; over-etching the gate insulation film layer by a gaseous corrosion method to form a gate insulation layer; peeling off the photoresist film layer remaining on a surface of the gate electrode; and performing a conductive treatment to the active layer. | 2022-01-20 |
20220020868 | BIPOLAR TRANSISTOR AND METHOD FOR FORMING THE SAME - A bipolar transistor includes a substrate, a sub-collector layer, a collector layer, a base layer, an emitter layer, a passivation layer, and a collector electrode. The sub-collector layer is formed over the substrate. The collector layer is formed over the sub-collector layer. The base layer is formed over the collector layer. The emitter layer is formed over the base layer. The passivation layer is formed over the substrate and covering a sidewall of the collector layer. The collector electrode is connected to the sub-collector layer through an opening in the passivation layer. The opening exposes at least a portion of the sub-collector layer. | 2022-01-20 |
20220020869 | SEMICONDUCTOR DEVICE - A first gate wiring layer is a 2-layered structure in which a polysilicon wiring layer and a metal wiring layer containing aluminum are sequentially stacked. The polysilicon wiring layer and the metal wiring layer surround a periphery of an active region. In a portion of a periphery of the first gate wiring layer, the polysilicon wiring layer and the metal wiring layer contact each other via a contact hole of an interlayer insulating film and in remaining portions thereof, are electrically insulated from each other by the interlayer insulating film. The first gate wiring layer, in portion separate from a gate pad, is configured having relatively more of the metal wiring layer with a resistance value lower than that of the polysilicon wiring layer. The resistance value of the first gate wiring layer is adjusted to be relatively high in a portion near the gate pad, as compared to the portion separate from the gate pad. | 2022-01-20 |
20220020870 | SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING SEMICONDUCTOR DEVICE - A semiconductor device according to the present invention includes a substrate, a plurality of semiconductor layers to be overlaid on the substrate and a gate electrode, a drain electrode, and a source electrode provided on the plurality of semiconductor layers, wherein each of the plurality of semiconductor layers includes a channel layer made with GaN and a barrier layer provided in contact with an upper surface of the channel layer and made with Al | 2022-01-20 |
20220020871 | STACKED BUFFER IN TRANSISTORS - The present subject matter provides a High Mobility Electron Transistor (HEMT) comprising: a substrate, a nucleation layer provided on the substrate, a channel layer, and a buffer layer formed between the nucleation layer and the channel layer. The buffer layer comprises a vertical stack of p-n junctions. Each p-n junction of the vertical stack of p-n junctions comprises an n-type layer provided on a p-type layer. The n-type layer and the p-type layer are parallel to the substrate. | 2022-01-20 |
20220020872 | METHOD OF FORMING A SEMICONDUCTOR DEVICE - In an embodiment, a HEMT is formed to have a main transistor having a main active area and a sense transistor having a sense active area. An embodiment may include that the main active area is isolated from the sense active area. | 2022-01-20 |
20220020873 | MONOLITHIC SEMICONDUCTOR DEVICE AND HYBRID SEMICONDUCTOR DEVICE - A monolithic semiconductor device includes: a substrate; a first nitride semiconductor layer disposed on the substrate; a second nitride semiconductor layer disposed on the first nitride semiconductor layer and having a band gap larger than a band gap of the first nitride semiconductor layer; a first transistor disposed on the substrate and including the first nitride semiconductor layer and the second nitride semiconductor layer, the first transistor being of a high-electron-mobility transistor (HEMT) type for power amplification; and a first bias circuit disposed on the substrate and including a second transistor of the HEMT type disposed outside a propagation path of a radio-frequency signal inputted to the first transistor, the first bias circuit applying bias voltage to a gate of the first transistor. | 2022-01-20 |
20220020874 | BYPASSED GATE TRANSISTORS HAVING IMPROVED STABILITY - A transistor device includes a plurality of gate fingers that extend in a first direction and are spaced apart from each other in a second direction, each of the gate fingers comprising at least spaced-apart and generally collinear first and second gate finger segments that are electrically connected to each other. The first gate finger segments are separated from the second gate finger segments in the first direction by a gap region that extends in the second direction. A resistor is disposed in the gap region. | 2022-01-20 |
20220020875 | SEMICONDUCTOR DEVICE - A semiconductor device is provided. The semiconductor may include: a substrate; an N− epitaxial layer disposed on the substrate; P areas positioned on the N− epitaxial layer and spaced apart from each other with a channel therebetween; and N+ areas positioned inside the P areas, wherein the channel includes: a trench area in which the P areas are partially etched so that the N+ areas face each other; and a planar area in which the P areas are not etched to face each other. | 2022-01-20 |
20220020876 | Mesa Contact for a Power Semiconductor Device and Method of Producing a Power Semiconductor Device - A power semiconductor device includes: a semiconductor body with a drift region; a plurality of trenches, wherein two adjacent trenches laterally confine a mesa of the semiconductor body. Each trench extends along a vertical direction and includes a trench electrode, and has a trench width along a first lateral direction and a trench length along a second lateral direction perpendicular to the first lateral direction, the trench length amounting to at least five times the trench width. The device further includes: a semiconductor body region of a second conductivity type in the mesa; a source region in the mesa; an insulation layer above and/or on the source region; a contact plug that extends at least from an upper surface of the insulation layer along the vertical direction so as to contact both the source region and the semiconductor body region. | 2022-01-20 |
20220020877 | SEMICONDUCTOR DEVICE - A semiconductor device includes an output-stage element and a detection element, each of the output-stage element and the detection element including: a channel-formation region deposited at an upper part of a drift region; a main electrode region deposited at an upper part of the channel-formation region; and a gate electrode buried via a gate insulating film in one or more first trenches in contact with the main electrode region, the channel-formation region, and the drift region, wherein the first trenches used in common with the detection element and the output-stage element extend in a planar pattern, and a plurality of second trenches extending in parallel to each other in a direction perpendicular to the first trenches interpose the detection element so as to separate the channel-formation region of the output-stage element and the channel-formation region of the detection element from each other. | 2022-01-20 |
20220020878 | FET DEVICE INSENSITIVE TO NOISE FROM DRIVE PATH - A FET device has a substrate, a plurality of repetitive source stripes, a first layout of drain stripe having a first drift region and a first drain region, a second layout of drain stripe having a second drift region and a second drain region, a first drain contactor contacted with the first drain region and connected to a drain terminal, a second drain contactor contacted with the second drain region and connected to a first gate terminal, a source contactor contacted with a source region in each of the plurality of repetitive source stripes and connected to a source terminal, a first gate region positioned between the source region and the first drain region and connected to the first gate terminal, and a second gate region positioned between the source region and the second drain region and connected to a second gate terminal. | 2022-01-20 |
20220020879 | SEMICONDUCTOR DEVICE, AND METHOD FOR MANUFACTURING SEMICONDUCTOR DEVICE - Noise in a semiconductor device is to be reduced. | 2022-01-20 |
20220020880 | SEMICONDUCTOR DEVICE HAVING UPPER CHANNEL AND LOWER CHANNEL AND METHOD OF MANUFACTURING THE SAME - A semiconductor device and a method of manufacturing a semiconductor device, the device including a first semiconductor pattern on a substrate, the first semiconductor pattern including a lower channel; a second semiconductor pattern on the first semiconductor pattern and spaced apart from the first semiconductor pattern in a vertical direction, the second semiconductor pattern including an upper channel extending in the vertical direction; a gate electrode covering the lower channel and surrounding the upper channel; and source/drain patterns on opposite sides of the upper channel, wherein the substrate and the first semiconductor pattern have a doping concentration of 10 | 2022-01-20 |
20220020881 | SEMICONDUCTOR DEVICE AND METHOD FOR MANUFACTURING SEMICONDUCTOR DEVICE - A semiconductor device having favorable electrical characteristics is provided. The semiconductor device includes a plurality of transistors; each of the plurality of transistors includes a first insulator, a first oxide, a second oxide, a first conductor, a second conductor, a third oxide, a second insulator, and a third conductor; the third oxide included in one of the plurality of transistors and the third oxide included in another of the plurality of transistors, which is adjacent to the one of the plurality of transistors, are provided to be apart from each other in the channel width direction of the plurality of transistors; the second insulator included in one of the plurality of transistors includes a region continuous with the second insulator included in another of the plurality of transistors, which is adjacent to the one of the plurality of transistors; and the third conductor included in one of the plurality of transistors includes a region continuous with the third conductor included in another of the plurality of transistors, which is adjacent to the one of the plurality of transistors. | 2022-01-20 |
20220020882 | STRUCTURE FOR A FIELD EFFECT TRANSISTOR (FET) DEVICE AND METHOD OF PROCESSING A FET DEVICE - The disclosed technology generally relates to a structure for a field effect transistor (FET) device and a method of processing a FET device. In one aspect, the method can include providing a substrate, forming an oxygen passing layer on the substrate, and forming an oxygen blocking layer on the substrate. The oxygen blocking layer can be arranged next to the oxygen passing layer and can delimit the oxygen passing layer on two opposite sides. The method can also include forming an oxide semiconductor layer on the oxygen passing layer and the oxygen blocking layer, forming a gate structure on the oxide semiconductor layer in a region above the oxygen passing layer, and modifying a doping of the oxide semiconductor layer by introducing oxygen into the oxygen passing layer. At least a portion of the introduced oxygen can pass through the oxygen passing layer and into the oxide semiconductor layer. | 2022-01-20 |
20220020883 | SEMICONDUCTOR DEVICE AND METHOD FOR MANUFACTURING SEMICONDUCTOR DEVICE - A semiconductor device with favorable electrical characteristics is provided. The semiconductor device includes a first insulator, a first oxide over the first insulator, a second insulator provided between the first insulator and the first oxide, a second oxide in contact with the first insulator and in contact with a side surface of the first oxide, and a third insulator over the first insulator, the second oxide, and the first oxide. The third insulator includes a region in contact with a top surface of the first oxide. The second insulator and the third insulator include a material which is less likely to pass oxygen than the second oxide. | 2022-01-20 |
20220020884 | WIDE BAND GAP SEMICONDUCTOR ELECTRONIC DEVICE HAVING A JUNCTION-BARRIER SCHOTTKY DIODE - The vertical-conduction electronic power device is formed by a body of wide band gap semiconductor which has a first conductivity type and has a surface, and is formed by a drift region and by a plurality of surface portions delimited by the surface. The electronic device is further formed by a plurality of first implanted regions having a second conductivity type, which extend into the drift region from the surface, and by a plurality of metal portions, which are arranged on the surface. Each metal portion is in Schottky contact with a respective surface portion of the plurality of surface portions so as to form a plurality of Schottky diodes formed by first Schottky diodes and second Schottky diodes, wherein the first Schottky diodes have, at equilibrium, a Schottky barrier having a height different from that of the second Schottky diodes. | 2022-01-20 |
20220020885 | OPTICAL DEVICE AND METHOD OF MANUFACTURING THE SAME - An optical device includes a first circuit layer, a light detector, a first conductive pillar and an encapsulant. The first circuit layer has an interconnection layer and a dielectric layer. The light detector is disposed on the first circuit layer. The light detector has a light detecting area facing away from the first circuit layer and a backside surface facing the first circuit layer. The first conductive pillar is disposed on the first circuit layer and spaced apart from the light detector. The first conductive pillar is electrically connected to the interconnection layer of the first circuit layer. The encapsulant is disposed on the first circuit layer and covers the light detector and the first conductive pillar. The light detector is electrically connected to the interconnection layer of the first circuit layer through the first conductive pillar. The backside surface of the light detector is exposed from the encapsulant. | 2022-01-20 |
20220020886 | PHOTODETECTORS AND PHOTODETECTOR ARRAYS - A dynamic photodiode detector or detector array having a light absorbing region of doped semiconductor material for absorbing photons. Electrons or holes generated by photon absorption are detected with a construction of oppositely heavily doped anode and cathode regions and a heavily doped ground region of the same doping type as the anode region. Photon detection involves switching the device from reverse bias to forward bias to create a depletion region enclosing the anode region. When a photon is then absorbed the electron or hole thereby generated drifts under the electric field induced by the biasing to the depletion region where it causes the anode-to-ground current to increase. Furthermore, the detector is configured such that anode-to-cathode current starts to flow once a threshold number of electrons or holes reaches the depletion region, where the threshold may be one to provide single photon detection. | 2022-01-20 |
20220020887 | Apparatus and Method for Determining an Order of Power Devices in Power Generation Systems - Various implementations described herein are directed to a method for determining an order of power devices connected in a serial string. A command is transmitted, to at least one first power device of a plurality of power devices, to change an output electrical parameter. At least one electrical signal is caused to be transmitted from at least one second power device of the plurality of power devices. At least one measured value responsive to the electrical signal is received from at least one of the plurality of power devices. A determination is made, by analyzing the at least one measured value, which ones of the plurality of power devices are ordered in the serial string between the at least one first power device and the at least one second power device. | 2022-01-20 |
20220020888 | METHOD FOR FABRICATING A SOLAR MODULE OF REAR CONTACT SOLAR CELLS USING LINEAR RIBBON-TYPE CONNECTOR STRIPS AND RESPECTIVE SOLAR MODULE - A solar module and a method for fabricating a solar module comprising a plurality of rear contact solar cells are described. Rear contact solar cells ( | 2022-01-20 |
20220020889 | BLISTER-FREE POLYCRYSTALLINE SILICON FOR SOLAR CELLS - Described herein are methods of fabricating solar cells. In an example, a method of fabricating a solar cell includes forming an amorphous dielectric layer on the back surface of a substrate opposite a light-receiving surface of the substrate. The method also includes forming a microcrystalline silicon layer on the amorphous dielectric layer by plasma enhanced chemical vapor deposition (PECVD). The method also includes forming an amorphous silicon layer on the microcrystalline silicon layer by PECVD. The method also includes annealing the microcrystalline silicon layer and the amorphous silicon layer to form a homogeneous polycrystalline silicon layer from the microcrystalline silicon layer and the amorphous silicon layer. The method also includes forming an emitter region from the homogeneous polycrystalline silicon layer. | 2022-01-20 |
20220020890 | MULTI-JUNCTION LAMINATED LASER PHOTOVOLTAIC CELL - A multi junction laminated laser photovoltaic cell includes a cell unit laminated body and upper and lower electrodes electrically connected with the bottom and top of the cell unit laminated body, respectively, wherein the cell unit laminated body includes more than 6 laminated PN-junction subcells, adjacent two subcells are connected in series via tunnel junctions, wherein each PN-junction subcell uses a semiconductor single crystal material with a specific band gap as the absorption layer, the multiple subcells at least have two different band gaps, and the band gaps of the subcells are arranged in such an order that they decrease successively from the light incidence side to other side of the photovoltaic cell. | 2022-01-20 |