03rd week of 2011 patent applcation highlights part 40 |
Patent application number | Title | Published |
20110014718 | DEVICE AND METHOD FOR PRESSURE AND FLOW CONTROL IN PARALLEL REACTORS - The present invention relates to a method and a device for the parallel study of chemical reactions in at least two spatially separated reaction spaces. In particular, the invention is suitable for reactions which are not constant volume reactions and/or for reactions in which fluid flows through at least two spatially separated reaction spaces are intended to be controlled together for all the reaction spaces, or for related subsets of them, in the most straightforward way possible. | 2011-01-20 |
20110014719 | CARTRIDGE FOR ASSAYS WITH MAGNETIC PARTICLES - The invention relates to a cartridge ( | 2011-01-20 |
20110014720 | METHOD FOR HOMOGENEOUS BIOLOGICAL ASSAY - A method for performing time resolved homogeneous assays using a long-lifetime luminescent dye as a donor. A reaction well containing a sample portion, donor reagent, and acceptor reagent and a matrix well containing a sample portion and donor reagent are excited and the resulting emission from each is measured at a single wavelength associated with the acceptor. The measurement obtained from the matrix well is used to provide a correction for the measurement obtained from the reaction well. The sample may be a biological fluid such as an oral fluid. | 2011-01-20 |
20110014721 | HYDROPHILIC CHEMILUMINESCENT ACRIDINIUM LABELING REAGENTS - In accordance with the present invention, it has been discovered that introduction of hydrophilic sulfoalkyl substituents and/or hydrophilic linkers derived from homocysteic acid, cysteic acid, glycine peptides, tetraethylene oxide, and the like, offset the hydrophobicity of the acridinium ring system to produce a more soluble label which can be attached to an antibody at higher loading before precipitation and aggregation problems are encountered. Additional compounds described herein contain linkers derived from short peptides and tetraethylene oxide which increase aqueous solubility due to hydrogen bonding with water molecules. The present invention also embraces reagents for multiple acridinium labeling for signal amplification composed of a peptide bearing several acridinium esters with sulfonate groups at regularly spaced intervals for increased solubility. The invention also embraces assays employing the above-described compounds. | 2011-01-20 |
20110014722 | SPIN COLUMN SYSTEM AND METHODS - The present invention provides a low bed-volume spin column system and methods of use. The system includes various combinations of spin columns with packed beds, a rack for holding the spin columns, a receiver plate that attaches to the rack and that has wells in registration with the spin columns held in the rack, a lid that attaches to the receiver plate and seals the spin columns, and an incubator block configured for accepting the wells of the receiver plate and for incubating the packed bed. The lid, spin columns, rack, receiver plate, and incubator block are preferably capable of being assembled in a nested configuration. In preferred versions of the invention, the rack is compatible with and attachable to conventional 96-well microplates. Further provided are methods of using the spin column system that include quantitatively purifying and analyzing an analyte, removing and preventing air entrainment within the packed bed, and incubating the packed bed while preventing drying thereof. | 2011-01-20 |
20110014723 | COMPOSITIONS AND PROCESSES RELATING TO HUMAN BOCAVIRUS - Non-replicating, antigenic, human bocavirus virus-like particles (HBoV VLPs) are provided by the present invention along with assays using the HBoV VLPs to detect anti-HBoV antibodies in a biological sample. Pharmaceutical compositions including HBoV VLPs and/or anti-HBoV antibodies are described herein along with novel antibodies generated using HBoV VLPs as an antigen. A recombinant baculovirus is provided including a DNA sequence encoding an expressible human bocavirus VP2 with or without a DNA sequence encoding an expressible human bocavirus VP1 polypeptide, and/or a non-HBoV peptide or protein, and culturing the cells to form the VP1 and/or VP2 proteins that self assemble to form the HBoV VLPs which are then amenable to isolation. | 2011-01-20 |
20110014724 | METHOD OF DETECTING BIOPRODUCTS USING LOCALIZED SURFACE PLASMON RESONANCE SENSOR OF GOLD NANOPARTICLES - Disclosed is a method of detecting bioproducts using Localized Surface Plasmon Resonance (LSPR) of gold nanoparticles, which can diagnose bioproducts based on changes in the maximum wavelength occurred by an antigen-antibody reaction after immobilization of the gold nanoparticles onto a glass panel. A sensor using such method exhibits high sensitivity, is low in price, and makes quick diagnosis possible, thereby being applicable to various biological fields associated with environmental contaminants, pathogens and the like, as well as diagnosis of diseases. Further, it provides a technology for manufacturing a sensor having higher sensitivity, low price and quick performance, as compared to conventional methods using SPR. | 2011-01-20 |
20110014725 | METHOD FOR MANUFACTURING SOLAR CELL MODULE - Disclosed is a method for manufacturing a solar cell module in which a wiring substrate having a base material and a wiring formed on the base material, and a plurality of solar cells electrically connected by being placed on the wiring of the wiring substrate are sealed with a sealant, including a first step of placing at least one of the solar cells on the wiring of the wiring substrate, and a second step of sealing the wiring substrate and the solar cells with the sealant, the method including the step of conducting an inspection of the solar cells after the first step and before the second step. | 2011-01-20 |
20110014726 | METHOD OF FORMING SHALLOW TRENCH ISOLATION STRUCTURE - A method for forming a shallow trench isolation (STI) structure with a predetermined target height is provided. A substrate having a pad oxide layer formed on the substrate is provided. A nitride-containing layer with a thickness is formed on the pad oxide. A STI structure is formed and extends through the nitride-containing layer, the pad oxide layer, into the substrate. The thickness of the nitride-containing layer is measured to calculate the height of STI structure according to a correlation between the thickness of the nitride-containing layer and the height of STI structure. A thickness of the top portion STI structure to be removed is determined according to the difference between the height of the STI structure and the predetermined target height and is removed in a first etching process. The nitride-containing layer is removed without etching the STI structure or the pad oxide layer in a second etching process. | 2011-01-20 |
20110014727 | THIN FILM PROBE SHEET AND SEMICONDUCTOR CHIP INSPECTION SYSTEM - In the highly accurate thin film probe sheet which is used for the contact to electrode pads disposed in high density with narrow pitches resulting from the increase in integration degree of semiconductor chips and for the inspection of semiconductor chips, a large spatial region in which a metal film selectively removable relative to terminal metal is formed in advance is formed in the peripheral region around minute contact terminals having sharp tips and disposed in high density with narrow pitches equivalent to those of the electrode pads. Thus, occurrence of damage in an inspection process is significantly reduced, and an inspection device simultaneously achieving the miniaturization and the durability can be provided. | 2011-01-20 |
20110014728 | ELECTRONIC DEVICE AND MANUFACTURING METHOD THEREOF - An object of the invention is to provide an electronic device which can be easily manufactured using a wet method. One of electronic devices according to the invention has a first layer and a second layer. The first layer contains a first compound including a conjugated double bond. Here, the first compound preferably has a molecular weight of 100 to 1000. The second layer contains a second compound having a cyclic structure which is formed by an addition reaction between two molecules of the first compound. Here, a light emitting element or an element such as a transistor can be given as the electronic device. | 2011-01-20 |
20110014729 | DONOR FILM FOR LASER INDUCED THERMAL IMAGING METHOD, LIGHT EMITTING DEVICE USING THE SAME, AND METHOD OF MANUFACTURING LIGHT EMITTING DEVICE - A donor film for a laser induced thermal imaging method capable of improving the optical efficiency of an emission layer, a light emitting device using the same, and a method of manufacturing the light emitting device are provided. The donor film for a laser induced thermal imaging method includes a base substrate, a light to heat conversion layer (LTHC) provided on the base substrate and having a pattern with a predetermined step difference, and a transfer layer provided on the LTHC. It is possible to improve the optical efficiency of the emission layer by patterning the transfer layer using the LTHC having the pattern with a predetermined step difference. | 2011-01-20 |
20110014730 | Method for Manufacturing Light Emitting Device - An object of the present invention is to provide a new light emitting element with little initial deterioration, and a display device in which initial deterioration is reduced and variation in deterioration over time is reduced by a new method for driving a display device having the light emitting element. One feature of the invention is that a display device comprising a light emitting element including a first electrode, a second electrode opposed to the first electrode, and a mixed layer of metal oxide and an organic compound provided between the first electrode and the second electrode is subjected to aging drive. | 2011-01-20 |
20110014731 | METHOD FOR SEALING A PHOTONIC DEVICE - Methods for sealing a photonic device are disclosed. The photonic device may, for example, comprise a display device, a lighting device or a photovoltaic device. The device is sealed with a glass frit that is heated with a laser from both sides of the device (through both glass substrate plates), either sequentially or simultaneously. The methods can facilitate wider seal widths, and wider overall frit wall widths for increased device strength. | 2011-01-20 |
20110014732 | LIGHT-EMITTING MODULE FABRICATION METHOD - A light-emitting module fabrication method includes the steps of (a) forming component contacts and positive-bonding and negative-bonding contacts on a circuit layout on a substrate, (b) electrically bonding the pins of electronic components to the component contacts and P-electrode bonding pads and N-electrode bonding pads of light-emitting chips to the positive-bonding and negative-bonding contacts at the substrate, (c) employing a coating technique to cover light-emitting surfaces of each of the light-emitting chips with a respective phosphor layer, and (d) employing a curing technique to cure the phosphor layers. | 2011-01-20 |
20110014733 | OPTICAL INTERCONNECT DEVICE AND METHOD FOR MANUFACTURING THE SAME - An optical interconnect device includes a first substrate, a second substrate, an optical waveguide, an electrical wiring and a switching device. The first substrate has an electrical wiring circuit, an electrical-optical converter for converting an electrical signal to an optical signal, and a light emitting device for emitting a light. The second substrate has an electrical wiring circuit, an optical-electrical converter for converting the optical signal to the electrical signal, and a light receiving device for receiving the light from the light emitted device. The optical waveguide optically connects the light emitting and light receiving devices. The electrical wiring electrically connects the electrical wiring circuits of the first and second substrates. The switching device determines a fast signal of data to be transmitted via the optical substrate and a slow signal of data to be transmitted via the electrical wiring. | 2011-01-20 |
20110014734 | METHOD FOR FABRICATING FLIP CHIP GALLIUM NITRIDE LIGHT EMITTING DIODE - The present invention discloses a method for fabricating a flip chip GaN LED, which has a predetermined region on an epitaxial layer for forming a first groove to expose a portion of the substrate, and another predetermined region on the epitaxial layer for forming a second groove to expose a portion of N type GaN Ohm contacting layer. On a side of the first groove, there are a translucent conducting layer, an N type electrode pad, a first isolation protection layer, a metallic reflection layer and a second isolation protection layer sequentially formed on the surface of a P type GaN Ohm contacting layer. On another side of the first groove, a translucent conducting layer, an N type electrode pad, a first isolation protection layer and a second isolation protection layer are sequentially formed on the surface of an N type GaN Ohm contacting layer. The above structure not only can provide a flat surface for electrical connection of the P type and N type electrode pads with the circuit board, but also to keep the metallic reflection layer from conducting electricity to avoid increasing the forward voltage and the power consumption, and accordingly to promote the light emitting performance of the LED. | 2011-01-20 |
20110014735 | Dual Panel Type Organic Electroluminescent Display Device and Method of Fabricating the Same - An organic electroluminescent device includes: a switching element and a driving element connected to each other on a substrate including a pixel region; a planarization layer on the switching element and the driving element, the planarization layer having a substantially flat top surface; a cathode on the planarization layer, the cathode connected to the driving element; an emitting layer on the cathode; and an anode on the emitting layer. | 2011-01-20 |
20110014736 | ORGANIC THIN FILM TRANSISTOR ARRAY PANEL AND METHOD OF MANUFACTURING THE SAME - An organic thin film transistor (“TFT”) array panel includes a substrate, a gate line extending in a first direction, a data line extending in a second direction, intersecting with and insulated from the gate line, a source electrode connected to the data line, a drain electrode facing the source electrode, a pixel electrode connected to the drain electrode, and an organic semiconductor connected to the source electrode and the drain electrode, the organic semiconductor made of an organic material with photosensitivity. | 2011-01-20 |
20110014737 | THIN FILM TRANSISTOR ARRAY AND METHOD OF MANUFACTURING THE SAME - A thin film transistor array and method of manufacturing the same include a pixel electrode formed of a transparent conductive layer on a substrate, a gate line formed of the transparent conductive layer and an opaque conductive layer on the substrate, a gate electrode connected to the gate line and formed of the transparent conductive layer and an opaque conductive layer on the substrate, a gate insulating layer which covers the gate line and the gate electrode, a semiconductor layer formed on the gate insulating layer to overlap the gate electrode, a data line which intersects the gate line, a source electrode connected to the data line to overlap a part of the semiconductor layer, and a drain electrode connected to the pixel electrode to overlap a part of the semiconductor layer. | 2011-01-20 |
20110014738 | LCD TFT array plate and fabricating method thereof - Lift-off method and half-tone photolithography are used to fabricate LCD TFT array plate. Only two photo masks are used to respectively define a first and a second metal layers to accomplish the LCD TFT array plate. | 2011-01-20 |
20110014739 | MAKING AN EMISSIVE LAYER FOR MULTICOLORED OLEDS - A method of making an electroluminescent device having a substrate, and at least one blue light emitting layer and at least one non-emissive layer containing an emissive material that emits light longer in wavelength than blue light, these two layers being directly separated by and in direct contact with a non-emissive buffer layer; and heating the electroluminescent device after fabrication to cause the long wavelength emissive material to diffuse from the non-emissive layer into at least the buffer layer such that the long wavelength emissive material comes into contact with the blue light-emitting layer such that the recombination energy in the emitting layer is preferentially transferred to the diffused emissive material compared to the blue emissive material and the light emitted is longer in wavelength than blue light. | 2011-01-20 |
20110014740 | DUAL PANEL TYPE ORGANIC ELECTROLUMINESCENT DISPLAY DEVICE AND METHOD OF FABRICATING THE SAME - An organic electroluminescent device includes a switching element and a driving element connected to the switching element on a substrate in a pixel region, an overcoat layer on the switching element and the driving element, a first contact layer on the overcoat layer, the first contact layer being made of one of molybdenum and indium tin oxide, a cathode on the first contact layer, the cathode connected to the driving element through the first contact layer, an emitting layer on the cathode, and an anode on the emitting layer. | 2011-01-20 |
20110014741 | THREE DIMENSIONAL STRUCTURE AND ITS MANUFACTURING METHOD - A plurality of micro three-dimensional structure elements each having a movable structure fixed on a sacrifice layer, and fixation portions of the micro three-dimensional structure elements for the sacrifice layer are arranged into a film-like elastic body, and then the sacrifice layer is removed. Thus, a three-dimensional structure in which the individual micro three-dimensional structure elements are arranged independently of one another within the elastic body is manufactured. | 2011-01-20 |
20110014742 | METHOD OF CREATING REUSABLE TEMPLATE FOR DETACHABLE THIN FILM SUBSTRATE - A structure and method operable to create a reusable template for detachable thin semiconductor substrates is provided. The template has a shape such that the 3-D shape is substantially retained after each substrate release. Prior art reusable templates may have a tendency to change shape after each subsequent reuse; the present disclosure aims to address this and other deficiencies from the prior art, therefore increasing the reuse life of the template. | 2011-01-20 |
20110014743 | ALUMINUM THICK FILM COMPOSITION(S), ELECTRODE(S), SEMICONDUCTOR DEVICE(S), AND METHODS OF MAKING THEREOF - The present invention is directed to a thick film conductor composition comprised of (a) aluminum-containing powder; (b) one or more glass frit compositions; dispersed in (c) organic medium wherein at least one of said glass frit compositions has a softening point of less than 400° C. | 2011-01-20 |
20110014744 | Organic memory devices and methods of fabricating such devices - Disclosed herein are organic memory devices and methods for fabricating such devices. The organic memory devices comprise a first electrode, a second electrode and an organic active layer extending between the first and second electrodes wherein the organic active layer is formed from one or more electrically conductive organic materials that contain heteroatoms and which are configured in such a manner as that the heteroatoms are available for linking or complexing metal atoms within the organic active layer. The metal ions may then be reduced to form metal filaments within the organic active layer to form a low resistance state and the metal filaments may, in turn, be oxidized to form a high resistance state and thereby function as memory devices. | 2011-01-20 |
20110014745 | METHOD OF MANUFACTURING SEMICONDUCTOR DEVICE - An object is to provide a method for manufacturing a highly reliable semiconductor device including a transistor with stable electric characteristics. A method for manufacturing a semiconductor device includes the steps of: forming a gate electrode over a substrate having an insulating surface; forming a gate insulating film over the gate electrode; forming an oxide semiconductor film over the gate insulating film; irradiating the oxide semiconductor film with an electromagnetic wave such as a microwave or a high frequency; forming a source electrode and a drain electrode over the oxide semiconductor film irradiated with the electromagnetic wave; and forming an oxide insulating film, which is in contact with part of the oxide semiconductor film, over the gate insulating film, the oxide semiconductor film, the source electrode, and the drain electrode. | 2011-01-20 |
20110014746 | Semiconductor Device and Method of Forming Conductive TSV in Peripheral Region of Die Prior to Wafer Singulaton - A semiconductor device is made by providing a semiconductor wafer having semiconductor die separated by a peripheral region. An opening is formed in the peripheral region having a depth less than a thickness of the wafer. A conductive material is deposited in the opening of the peripheral region of the wafer to form a conductive via extending partially through the wafer. The wafer is singulated through the conductive via in the peripheral region to provide a plurality of semiconductor die each having the conductive via. A semiconductor die is mounted on a sacrificial carrier. An encapsulant is deposited over the carrier around the semiconductor die. A portion of the encapsulant and semiconductor die is removed to expose the conductive via. A first and second interconnect structure are formed over the encapsulant and semiconductor die. The first and second interconnect structures are electrically connected to the conductive via. | 2011-01-20 |
20110014747 | STACKABLE PACKAGES FOR THREE-DIMENSIONAL PACKAGING OF SEMICONDUCTOR DICE - An apparatus and a method for packaging semiconductor devices. The apparatus includes a substrate strip component of a leadless three-dimensional stackable semiconductor package having mounting contacts on, for example, four peripheral edges. The substrate strip may either be fabricated for mounting a single electrical component (e.g., an integrated circuit die) or a plurality of substrate strips may be laid out in an X-Y matrix pattern which may later be singulated into individual package strip for leadless packages. three-dimensional stacking is achieved by a bonding area on an uppermost portion of the sidewall. The sidewall of the strip is high enough to enclose an encapsulant covering a later mounted integrated circuit die and associated bonding wires. | 2011-01-20 |
20110014748 | Semiconductor packages, stacked semiconductor packages, and methods of manufacturing the semiconductor packages and the stacked semiconductor packages - A semiconductor package may include a semiconductor pattern, a bonding pad, and a polymer insulation member. The semiconductor pattern may include a semiconductor device and first hole. The bonding pad may include a wiring pattern and plug. The wiring pattern may be formed on an upper face of the semiconductor pattern. The plug may extend from the wiring pattern to fill the first hole. The polymer insulation member may be formed on a lower face of the semiconductor pattern and may include a second hole exposing a lower end of the plug. A method of manufacturing a semiconductor package may include forming a first hole through a semiconductor substrate; forming a bonding pad and plug; attaching a supporting member to the upper face of the substrate; reducing a thickness of the substrate; forming a polymer insulation member on the lower face of the substrate; and cutting the substrate. | 2011-01-20 |
20110014749 | Method for Packaging Semiconductor Dies Having Through-Silicon Vias - An integrated circuit structure is provided. The integrated circuit structure includes a die and an anisotropic conducing film (ACF) adjoining the back surface of the die. The die includes a front surface; a back surface on an opposite side of the die than the front surface; and a through-silicon via (TSV) exposed through the back surface of the die. | 2011-01-20 |
20110014750 | CAP AND SUBSTRATE ELECTRICAL CONNECTION AT WAFER LEVEL - A cap and substrate having an electrical connection at a wafer level includes providing a substrate and forming an electrically conductive ground structure in the substrate and electrically coupled to the substrate. An electrically conductive path to the ground structure is formed in the substrate. A top cap is then provided, wherein the top cap includes an electrically conductive surface. The top cap is bonded to the substrate so that the electrically conductive surface of the top cap is electrically coupled to the path to the ground structure. | 2011-01-20 |
20110014751 | MANUFACTURING PROCESS FOR EMBEDDED SEMICONDUCTOR DEVICE - A manufacturing process for an embedded semiconductor device is provided. In the manufacturing process, at least one insulation layer and a substrate are stacked to each other, and a third metal layer is laminated on the insulation layer to embed a semiconductor device in the insulation layer. The substrate has a base, a first circuit layer, a second circuit layer, and at least a first conductive structure passing through the base and electrically connected to the first circuit layer and the second circuit layer. In addition, the third metal layer is patterned to form a third circuit layer having a plurality of third pads. | 2011-01-20 |
20110014752 | SUBSTRATE FOR SEMICONDUCTOR DEVICE, RESIN-SEALED SEMICONDUCTOR DEVICE, METHOD FOR MANUFACTURING SAID SUBSTRATE FOR SEMICONDUCTOR DEVICE AND METHOD FOR MANUFACTURING SAID RESIN-SEALED SEMICONDUCTOR DEVICE - A substrate for a semiconductor device includes: a base plate, a plurality of external terminal portions respectively arranged in a plane on the base plate and having external terminal faces respectively facing the base plate; a plurality of internal terminal portions, respectively arranged in the plane on the base plate and having internal terminal faces respectively facing an opposite side to the base plate. The internal terminal portions are connected with the external terminal portions via wiring portions, respectively. A part of the external terminal portions are located on the base plate in a predetermined arrangement area in which a semiconductor element is arranged. | 2011-01-20 |
20110014753 | METHOD OF FORMING THIN FILM TRANSISTOR ARRAY SUBSTRATE - A method of forming a thin-film transistor array substrate is provided. A first mask is used to define a source, a drain and a channel on a substrate. A dielectric layer is formed to cover the source, the drain, the channel and the substrate. A second mask is used to define a patterned photoresist and the dielectric layer. A transparent conductive layer is formed to cover the patterned photoresist and the substrate. A lift-off process is performed to remove the patterned photoresist and a portion of the transparent conductive layer disposed on the patterned photoresist. A third mask is used to define a gate disposed on the dielectric layer. | 2011-01-20 |
20110014754 | Semiconductor device having a plurality of stacked transistors and method of fabricating the same - A semiconductor device according to example embodiments may have a plurality of stacked transistors. The semiconductor device may have a lower insulating layer formed on a semiconductor substrate and an upper channel body pattern formed on the lower insulating layer. A source region and a drain region may be formed within the upper channel body pattern, and a non-metal transfer gate electrode may be disposed on the upper channel body pattern between the source and drain regions. The non-metal transfer gate electrode, the upper channel body pattern, and the lower insulating layer may be covered by an intermediate insulating layer. A metal word line may be disposed within the intermediate insulating layer to contact at least an upper surface of the non-metal transfer gate electrode. An insulating spacer may be disposed on a sidewall of the metal word line. A metal node plug may be disposed within the intermediate insulating layer and the lower insulating layer to contact the source region of the upper channel body pattern. Example embodiments also relate to a method of fabricating the above semiconductor device. | 2011-01-20 |
20110014755 | METHOD OF FABRICATING POLYCRYSTALLINE SILICON, TFT FABRICATED USING THE SAME, METHOD OF FABRICATING THE TFT, AND ORGANIC LIGHT EMITTING DIODE DISPLAY DEVICE INCLUDING THE TFT - A method of fabricating a polycrystalline silicon (poly-Si) layer includes providing a substrate, forming an amorphous silicon (a-Si) layer on the substrate, forming a thermal oxide layer to a thickness of about 10 to 50 Å on the a-Si layer, forming a metal catalyst layer on the thermal oxide layer, and annealing the substrate to crystallize the a-Si layer into the poly-Si layer using a metal catalyst of the metal catalyst layer. Thus, the a-Si layer can be crystallized into a poly-Si layer by a super grain silicon (SGS) crystallization method. Also, the thermal oxide layer may be formed during the dehydrogenation of the a-Si layer so that an additional process of forming a capping layer required for the SGS crystallization method can be omitted, thereby simplifying the fabrication process. | 2011-01-20 |
20110014756 | THIN FILM TRANSISTOR, METHOD OF FABRICATING THE SAME, AND ORGANIC LIGHT EMITTING DIODE DISPLAY DEVICE INCLUDING THE SAME - A thin film transistor includes: a substrate; a semiconductor layer disposed on the substrate, and including a channel region, source and drain regions, and edge regions having a first impurity formed at edges of the source and drain regions, and optionally, in the channel region; a gate insulating layer insulating the semiconductor layer; a gate electrode insulated from the semiconductor layer by the gate insulating layer; and source and drain electrodes electrically connected to the semiconductor layer. | 2011-01-20 |
20110014757 | PROCESS INTEGRATION FOR FLASH STORAGE ELEMENT AND DUAL CONDUCTOR COMPLEMENTARY MOSFETS - A method is provided for simultaneously fabricating a flash storage element, an NFET and a PFET having metal gates with different workfunctions. A first gate metal layer of the NFET having a first workfunction can be deposited simultaneously with a first metal layer for forming the floating gate of the flash storage element. A second gate metal layer of the PFET having a second workfunction different from the first workfunction can be deposited simultaneously with a second metal layer for forming the control gate of the flash storage element. A semiconductor layer can then be deposited over the first and second metal layers and gate metal layers and patterned to form first, second and third gates. Source and drain regions of the flash storage element, the NFET and the PFET can then be formed adjacent to the first, second and third gates, respectively. | 2011-01-20 |
20110014758 | Semiconductor device and method of manufacturing the same - Example embodiments are directed to a method of manufacturing a semiconductor device and a semiconductor device including a substrate including a plurality of active regions and a plurality of isolation regions between adjacent active regions, each active region including a groove, a bottom surface of the groove being below an upper surface of the active region. | 2011-01-20 |
20110014759 | Method of Fabricating Non-volatile Memory Device - A method of fabricating a non-volatile memory device includes: forming a tunnel insulation layer pattern and a floating gate electrode layer pattern over a semiconductor substrate; forming an isolation trench by etching an exposed portion of the semiconductor substrate so that the isolation trench is aligned with the tunnel insulation layer pattern and the floating gate electrode layer pattern; forming an isolation layer by filling the isolation trench with a filling insulation layer; forming a hafnium-rich hafnium silicon oxide layer over the isolation layer and the floating gate electrode layer pattern; forming a hafnium-rich hafnium silicon oxynitride layer by carrying out a first nitridation on the hafnium-rich hafnium silicon oxide layer; forming a silicon-rich hafnium silicon oxide layer over the hafnium-rich hafnium silicon oxynitride layer; forming a silicon-rich hafnium silicon oxynitride layer by carrying out a second nitridation on the silicon-rich hafnium silicon oxide layer; and forming a control gate electrode layer over the silicon-rich hafnium silicon oxynitride layer. | 2011-01-20 |
20110014760 | Method of Forming Lateral Trench Gate FET with Direct Source-Drain Current Path - A method of forming a field effect transistor (FET) includes: forming a drift region comprising a stack of alternating conductivity type silicon layers; forming a drain region of a first conductivity type extending into the stack of alternating conductivity type silicon layers; forming a trench gate extending into the stack of alternating conductivity type silicon layers, the trench gate having a non-active sidewall and an active sidewall being perpendicular to one another; and forming a body region of a second conductivity type adjacent to the active sidewall of the trench gate, wherein the trench gate and the drain region are formed such that the non-active sidewall of the trench gate faces the drain region. | 2011-01-20 |
20110014761 | SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD OF THE SAME - The characteristics of a semiconductor device including a trench-gate power MISFET are improved. The semiconductor device includes a substrate having an active region where the power MISFET is provided and an outer circumferential region which is located circumferentially outside the active region and where a breakdown resistant structure is provided, a pattern formed of a conductive film provided over the substrate in the outer circumferential region with an insulating film interposed therebetween, another pattern isolated from the pattern, and a gate electrode terminal electrically coupled to the gate electrodes of the power MISFET and provided in a layer over the conductive film. The conductive film of the pattern is electrically coupled to the gate electrode terminal, while the conductive film of another pattern is electrically decoupled from the gate electrode terminal. | 2011-01-20 |
20110014762 | SEMICONDUCTOR DEVICE AND METHOD FOR MANUFACTURING THE SAME - A semiconductor device and a method for manufacturing the same are disclosed. The disclosed semiconductor device includes a semiconductor substrate having a device isolation structure for delimiting an active region, the active region being recessed and grooves being defined in channel forming areas of the active region; gates formed in and over the grooves; gate spacers formed on both sidewalls of the gates over portions of the recessed active region which are positioned on both sides of the gates; an LDD region formed in the active region under the gate spacers; junction areas formed in the active region on both sides of the gates including the gate spacers; and landing plugs formed on the junction areas. | 2011-01-20 |
20110014763 | Method of Forming Low Resistance Gate for Power MOSFET Applications - A trench gate field effect transistor includes the following steps. A trench is formed in a semiconductor region, followed by a dielectric layer lining sidewalls and bottom of the trench. A recessed polysilicon layer is formed in the trench. A highly conductive cap layer is formed over and in contact with the recessed polysilicon layer. Rapid thermal processing is performed to cause the recessed polysilicon layer and the highly conductive cap layer to react. | 2011-01-20 |
20110014764 | METHOD OF FORMING A DUAL-TRENCH FIELD EFFECT TRANSISTOR - A method of forming a field effect transistor includes forming a well region in a semiconductor region of a first conductivity type. The well region may be of a second conductivity type and have an upper surface and a lower surface. The method also includes forming a plurality of gate trenches extending into the semiconductor region to a depth below the lower surface of the well region, and forming a plurality of stripe trenches extending through the well region and into the semiconductor region to a depth below the plurality of gate trenches. The plurality of stripe trenches may be laterally spaced from the plurality of gate trenches. The method also includes at least partially filling the plurality of stripe trenches with a semiconductor material of the second conductivity type. The semiconductor material of the second conductivity type may form a PN junction with a portion of the semiconductor region. | 2011-01-20 |
20110014765 | SEMICONDUCTOR DEVICE MANUFACTURING METHOD - A method of manufacturing a semiconductor device including forming a gate insulating film and a gate electrode over a Si substrate; forming a recess in the Si substrate at both sides of the gate electrode; forming a first Si layer including Ge in the recess; forming an interlayer over the first Si layer; forming a second Si layer including Ge over the interlayer; wherein the interlayer is composed of Si or Si including Ge, and a Ge concentration of the interlayer is less than a Ge concentration of the first Si layer and a Ge concentration of the second Si layer. | 2011-01-20 |
20110014766 | BOTTOM-DRAIN LDMOS POWER MOSFET STRUCTURE HAVING A TOP DRAIN STRAP - Lateral DMOS devices having improved drain contact structures and methods for making the devices are disclosed. A semiconductor device comprises a semiconductor substrate; an epitaxial layer on top of the substrate; a drift region at a top surface of the epitaxial layer; a source region at a top surface of the epitaxial layer; a channel region between the source and drift regions; a gate positioned over a gate dielectric on top of the channel region; and a drain contact trench that electrically connects the drift layer and substrate. The contact trench includes a trench formed vertically from the drift region, through the epitaxial layer to the substrate and filled with an electrically conductive drain plug; electrically insulating spacers along sidewalls of the trench; and an electrically conductive drain strap on top of the drain contact trench that electrically connects the drain contact trench to the drift region. | 2011-01-20 |
20110014767 | LOW-TEMPERATURE GROWN HIGH QUALITY ULTRA-THIN CoTiO3 GATE DIELECTRICS - A gate oxide and method of fabricating a gate oxide that produces a more reliable and thinner equivalent oxide thickness than conventional SiO | 2011-01-20 |
20110014768 | METHOD AND SYSTEM FOR IMPROVED NICKEL SILICIDE - According to one embodiment of the invention, a method for nickel silicidation includes providing a substrate having a source region, a gate region, and a drain region, forming a source in the source region and a drain in the drain region, annealing the source and the drain, implanting, after the annealing the source and the drain, a heavy ion in the source region and the drain region, depositing a nickel layer in each of the source and drain regions, and heating the substrate to form a nickel silicide region in each of the source and drain regions by heating the substrate. | 2011-01-20 |
20110014769 | MANUFACTURING METHOD FOR PLANAR INDEPENDENT-GATE OR GATE-ALL-AROUND TRANSISTORS - The present invention relates to a method for fabricating a planar independent-double-gate FET or a planar gate-all-around FET on a bulk semiconductor substrate. The method comprises refilling a surface recess in an active semiconductor region with a buried sacrificial layer, and, after preparing a pre-processing a gate stack by respective deposition and patterning, the formation of a recess in the isolation regions so as to cause the recess to extend, in a depth direction that points towards the inner substrate, to a depth level that allows removing the buried sacrificial layer and so as to cause the recess to undercut portions of gate stack in the channel direction. | 2011-01-20 |
20110014770 | Methods of forming a dielectric thin film of a semiconductor device and methods of manufacturing a capacitor having the same - A method of forming a dielectric thin film of a semiconductor device, the method including supplying a first nuclear atom precursor source and a second nuclear atom precursor source having different thermal decomposition temperatures to a substrate and forming a chemical adsorption layer including first nuclear atoms and second nuclear atoms on the substrate. A reactant including oxygen atoms may be supplied to the substrate on which the chemical adsorption layer is formed. An atomic layer including an oxide of the first nuclear atoms and the second nuclear atoms may be formed on the chemical adsorption layer. | 2011-01-20 |
20110014771 | Method of making damascene diodes using selective etching methods - A method of making a semiconductor device includes providing an insulating layer containing a plurality of openings, forming a first conductivity type semiconductor layer in the plurality of openings, forming a second conductivity type semiconductor layer over the first conductivity type semiconductor layer in the plurality of openings, and selectively etching the second conductivity type semiconductor layer using an upper surface of the first conductivity type semiconductor layer as a stop to form a recess in the plurality of openings. | 2011-01-20 |
20110014772 | ALIGNING METHOD OF PATTERNED ELECTRODE IN A SELECTIVE EMITTER STRUCTURE - An aligning method of patterned electrode in a selective emitter structure includes the following steps. A substrate is provided. A barrier layer is then formed on the substrate. The barrier layer is patterned, and thus the substrate is partially exposed to form a patterned electrode region. Thereafter, the surface property of the substrate located in the patterned electrode region is changed, so as to form a visible patterned mark. Subsequently, the barrier layer is removed, and the visible patterned mark is used as alignment mark. | 2011-01-20 |
20110014773 | METHOD FOR FABRICATING A METAL GATE STRUCTURE - A method of fabricating a metal gate structure is provided. The method includes providing a semiconductor substrate with a planarized polysilicon material; patterned the planarized polysilicon material to form at least a first gate and a second gate, wherein the first gate is located on the active region and the second gate at least partially overlaps with the isolation region; forming an inter-layer dielectric material covering the gates; planarizing the inter-layer dielectric material until exposing the gates and forming an inter layer-dielectric layer; performing an etching process to remove the gates to form a first recess and a second recess within the inter-layer dielectric layer; forming a gate dielectric material on a surface of each of the recesses; forming at least a metal material within the recesses; and performing a planarization process. | 2011-01-20 |
20110014774 | APPARATUS FOR TEMPORARY WAFER BONDING AND DEBONDING - An improved apparatus for temporary wafer bonding includes a temporary bonder cluster and a debonder cluster. The temporary bonder cluster includes temporary bonder modules that perform electronic wafer bonding processes including adhesive layer bonding, combination of an adhesive layer with a release layer bonding and a combination of a UV-light curable adhesive layer with a laser absorbing release layer bonding. The debonder cluster includes a thermal slide debonder, a mechanical debonder and a radiation debonder. | 2011-01-20 |
20110014775 | METHOD FOR PRODUCING SILICON FILM TRANSFERRED INSULATOR WAFTER - [PROBLEM] Provided is a method for producing an SOI wafer which the method can prevent occurrence of thermal strain, detachment, crack and the like attributed to a difference in thermal expansion coefficients between the insulating substrate and the SOI layer and also improve the uniformity of film thickness of the SOI layer. | 2011-01-20 |
20110014776 | METHOD FOR PRODUCING SOI SUBSTRATE - A method for easily manufacturing a transparent SOI substrate having: a main surface with a silicon film formed thereon; and a rough main surface located on a side opposite to a side where the silicon film is formed. A method for manufacturing transparent SOI substrate, having a silicon film formed on a first main surface of the transparent insulating substrate, while a second main surface of the transparent insulating substrate, an opposite to the first main surface, is roughened. The method includes at least the steps of: roughening the first main surface with an RMS surface roughness lower than 0.7 nm and the second main surface with an RMS surface roughness higher than the surface roughness of the first main surface to prepare the transparent insulating substrate; and forming the silicon film on the first main surface of the transparent insulating substrate. | 2011-01-20 |
20110014777 | METHOD FOR PROCESSING A SUBSTRATE, METHOD FOR MANUFACTURING A SEMICONDUCTOR CHIP, AND METHOD FOR MANUFACTURING A SEMICONDUCTOR CHIP HAVING A RESIN ADHESIVE LAYER - A mask used when a semiconductor wafer is diced into individual semiconductor chips by plasma etching is formed as follows. First, a pattern of a liquid-repellent film is formed by printing a liquid-repellent liquid on the area to be etched on the rear surface of the semiconductor wafer. Next, a resin film thicker than the liquid-repellent film is formed in the area not having the liquid-repellent film by supplying a liquid resin to the rear surface on which the liquid-repellent pattern has been formed. Then, the resin film is cured to form the mask covering the area other than the area to be removed by the etching. This method allows the formation of an etching mask without using a high-cost method such as photolithography. | 2011-01-20 |
20110014778 | Boron-10 coating process for neutron detector integrated circuit with high aspect ratio trenches - A coating process to infill high aspect-ratio vias and trenches in semiconductor substrates with dense boron for the production of neutron detectors and other devices uses a vacuum cathodic arc or other source of fully ionized boron plasma. Biasing of the substrate is used to impart energies to the plasma ions directing them toward the substrate, while repulsing the electrons. The full ionization produced by the source allows control of the energies of the boron ions by means of the bias voltage. The bias is alternated between coating deposition at low ion energies and sputtering of already coated material by energetic ions. Most of the sputtered material comes off the substrate top surface and between the trenches or vias and much of it is redeposited, thereby contributing to the infill. The process is suitable for carbon, boron or similar light elements, and is of particular interest for | 2011-01-20 |
20110014779 | Method of making damascene diodes using sacrificial material - A method of making a semiconductor device includes forming a first layer comprising a seed material over an underlying layer, forming a second layer comprising a sacrificial material over the first layer, the sacrificial material being different from the seed material, patterning the first layer and the second layer into a plurality of separate features, forming an insulating filling material between the plurality of the separate features, removing the sacrificial material from the separate features to form a plurality of openings in the insulating filling material such that the seed material is exposed in the plurality of openings, and growing a semiconductor material on the exposed seed material in the plurality of openings. | 2011-01-20 |
20110014780 | METHOD FOR MANUFACTURING SEMICONDUCTOR DEVICE - A layer including a semiconductor film is formed over a glass substrate and is heated. A thermal expansion coefficient of the glass substrate is greater than 6×10 | 2011-01-20 |
20110014781 | METHOD OF FABRICATING SEMICONDUCTOR DEVICE - According to one embodiment, a method of fabricating a semiconductor device includes forming a first insulator on a semiconductor substrate, forming a first groove on the insulator to expose at least a part of the semiconductor substrate at a bottom of the first groove, forming a first embedding film including at least germanium in the groove, melting the first embedding film by heat treatment, and crystallizing the first embedding film being melted to a single-crystalline film using the semiconductor substrate as a seed. | 2011-01-20 |
20110014782 | Apparatus and Method for Growing a Microcrystalline Silicon Film - Disclosed is a method for growing a microcrystalline silicon film on a substrate. The method includes the step of disposing the substrate in a chamber, the step of vacuuming the chamber and heating the substrate, the step of introducing reacting gas into the chamber as a precursor and keeping the pressure in the chamber at a predetermined value and the step of using RF energy in the chamber to dissociate the reacting gas to form plasma for growing the microcrystalline silicon film on the substrate. The reacting gas includes SiH | 2011-01-20 |
20110014783 | SEMICONDUCTOR DEVICE HAVING ELECTRODE AND MANUFACTURING METHOD THEREOF - A manufacturing method of a semiconductor device includes a first electrode formation step of forming a control gate electrode above a surface of a semiconductor substrate with a control gate insulating film interposed between the control gate electrode and the semiconductor substrate, a step of forming a storage node insulating film on the surface of the semiconductor substrate, and a second electrode formation step of forming a memory gate electrode on a surface of the storage node insulating film. The second electrode formation step includes a step of forming a memory gate electrode layer on the surface of the storage node insulating film, a step of forming an auxiliary film, having an etching rate slower than that of the memory gate electrode layer, on a surface of the memory gate electrode layer, and a step of performing anisotropic etching on the memory gate electrode layer and the auxiliary film. | 2011-01-20 |
20110014784 | SEMICONDUCTOR PROCESS - A semiconductor process is provided. First, a substrate having a dielectric layer formed thereon is provided. Thereafter, an interconnection structure including copper is formed in the dielectric layer. Afterwards, a metal layer is formed on the dielectric layer. The metal layer is then patterned to form a pad. An annealing process is performed, wherein the gas source for the annealing process includes hydrogen in a concentration of 50% to 90%. | 2011-01-20 |
20110014785 | Method for manufacturing semiconductor device, and semiconductor manufacturing apparatus used in said method - This method includes an electrode pad forming process for forming an electrode pad on a substrate, a solder bump forming process for forming a solder bump on the electrode pad, at least part of the surface of the solder bump being covered with a flux, and an oxygen exposure process for supplying an oxygen gas having reactive properties, such as an ozone (O | 2011-01-20 |
20110014786 | METHOD, SYSTEM, AND PROGRAM PRODUCT FOR ROUTING AN INTEGRATED CIRCUIT TO BE MANUFACTURED BY DOUBLED PATTERNING - Disclosed are a method, apparatus, and program product for routing an electronic design using double patenting that is correct by construction. The layout that has been routed will by construction be designed to allow successful manufacturing with double patenting, since the router will not allow a routing configuration in the layout that cannot be successfully manufactured with double patterning. | 2011-01-20 |
20110014787 | Method of Forming Contacts for a Memory Device - The present invention is generally directed to a method of forming contacts for a memory device. In one illustrative embodiment, the method includes forming a layer of insulating material above an active area of a dual bit memory cell, forming a hard mask layer above the layer of insulating material, the hard mask layer having an original thickness, performing at least two partial etching processes on the hard mask layer to thereby define a patterned hard mask layer above the layer of insulating material, wherein each of the partial etching processes is designed to etch through less than the original thickness of the hard mask layer, the hard mask layer having openings formed therein that correspond to a digitline contact and a plurality of storage node contacts for the dual bit memory cell, and performing at least one etching process to form openings in the layer of insulating material for the digitline contact and the plurality of storage node contacts using the patterned hard mask layer as an etch mask. | 2011-01-20 |
20110014788 | Display panel structure and manufacture method thereof - A display panel structure having a circuit element disposed thereon and method of manufacture are provided. The display panel includes a substrate and the circuit element disposed on the substrate. The circuit element has a first interface layer and a first conductive layer. Both the first interface layer and the first conductive layer have cooper materials. The material which makes the first interface layer includes a reactant or a compound of the material which makes the first conductive layer. The method for manufacturing includes the following steps: forming a first interface layer on the substrate; forming a first conductive layer on the first interface layer; and etching the first conductive and interface layers to form a pattern. The existence of the first interface reduces the penetration of the first conductive layer on the substrate and improves the adhesive force between the first conductive layer and the substrate. | 2011-01-20 |
20110014789 | MANUFACTURING APPARATUS AND METHOD FOR SEMICONDUCTOR DEVICE - There is provided an apparatus for manufacturing a semiconductor device including a chamber in which a wafer is loaded; a gas supply mechanism for supplying process gas into the chamber; a gas discharge mechanism for discharging gas from the chamber; a heater having a slit and for heating the wafer to a predetermined temperature; a push-up base on which the wafer is mounted in an lifted state and housed in the slit in a lower state; a vertical rotation drive control mechanism for moving the push-up base up/down and rotating the push-up base in an lifted state; and a rotating member for rotating the wafer in a predetermined position and a rotation drive control mechanism connected to the rotating member. | 2011-01-20 |
20110014790 | METHODS FOR FABRICATING SEMICONDUCTOR DEVICES - Methods are provided for fabricating a semiconductor device on and in a semiconductor substrate. In one embodiment, a method comprises the steps of forming etch masking features overlying the semiconductor substrate, the etch masking features having a first thickness, and forming an etch barrier layer overlying the substrate, the etch barrier layer having a second thickness less than or substantially equal to the first thickness. The method also comprises removing the etch masking features to expose the substrate, and etching the substrate using the etch barrier layer as an etch mask. | 2011-01-20 |
20110014791 | METHODS FOR FABRICATING FINFET STRUCTURES HAVING DIFFERENT CHANNEL LENGTHS - Methods for fabricating FinFET structures having gate structures of different gate widths are provided. The methods include the formation of sidewall spacers of different thicknesses to define gate structures of the FinFET structures with different gate widths. The width of a sidewall spacer is defined by the height of the structure about which the sidewall spacer is formed, the thickness of the sidewall spacer material layer from which the spacer is formed, and the etch parameters used to etch the sidewall spacer material layer. By forming structures of varying height, forming the sidewall spacer material layer of varying thickness, or a combination of these, sidewall spacers of varying width can be fabricated and subsequently used as an etch mask so that gate structures of varying widths can be formed simultaneously. | 2011-01-20 |
20110014792 | FIN MASK AND METHOD FOR FABRICATING SADDLE TYPE FIN USING THE SAME - A fin mask for forming saddle type fins in each of active regions formed in an island shape having a certain size with a major axis and a minor axis includes a first fin mask of a line type, and a second fin mask of an island type, wherein the first fin mask and the second fin mask in combination expose saddle type fin regions and cover ends of the neighboring active regions along the major axis. | 2011-01-20 |
20110014793 | Post-dry etching cleaning liquid composition and process for fabricating semiconductor device - A post-dry etching cleaning liquid composition for cleaning a substrate after dry etching is provided, the cleaning liquid composition containing at least one type of fluorine compound, glyoxylic acid, at least one type of organic acid salt, and water. With regard to the fluorine compound, ammonium fluoride may be used. With regard to the organic acid salt, at least one of ammonium oxalate, ammonium tartarate, ammonium citrate, and ammonium acetate may be used. | 2011-01-20 |
20110014794 | DEVICE MADE OF SINGLE-CRYSTAL SILICON - A device made of single-crystal silicon having a first side, a second side which is situated opposite to the first side, and a third side which extends from the first side to the second side, the first side and the second side each extending in a 100 plane of the single-crystal silicon, the third side extending in a first area in a 111 plane of the single-crystal silicon. The third side extends in a second area in a 110 plane of the single-crystal silicon. Furthermore, a production method for producing a device made of single-crystal silicon is described. | 2011-01-20 |
20110014795 | Method of Forming Stress-Tuned Dielectric Film Having Si-N Bonds by Modified PEALD - A method of forming stress-tuned dielectric films having Si—N bonds on a semiconductor substrate by modified plasma enhanced atomic layer deposition (PEALD), includes: introducing a nitrogen-and hydrogen-containing reactive gas and an additive gas into a reaction space inside which a semiconductor substrate is placed; applying RF power to the reaction space using a high frequency RF power source and a low frequency RF power source; and introducing a hydrogen-containing silicon precursor in pulses into the reaction space wherein a plasma is excited, thereby forming a stress-tuned dielectric film having Si—N bonds on the substrate. | 2011-01-20 |
20110014796 | DIPPING SOLUTION FOR USE IN PRODUCTION OF SILICEOUS FILM AND PROCESS FOR PRODUCING SILICEOUS FILM USING THE DIPPING SOLUTION - This invention relates to a dipping solution used in a process for producing a siliceous film. The present invention provides a dipping solution and a siliceous film-production process employing the solution. The dipping solution enables to form a homogeneous siliceous film even in concave portions of a substrate having concave portions and convex portions. The substrate is coated with a polysilazane composition, and then dipped in the solution before fire. The dipping solution comprises hydrogen peroxide, a foam-deposit inhibitor, and a solvent. | 2011-01-20 |
20110014797 | METHOD FOR Sr-Ti-O-BASED FILM FORMATION AND STORAGE MEDIUM - A film is formed so that the atomic numbers ratio of Sr to Ti, i.e., Sr/Ti, in the film is not less than 1.2 and not more than 3. The film is then annealed in an atmosphere containing not less than 0.001% and not more than 80% of O | 2011-01-20 |
20110014798 | HIGH QUALITY SILICON OXIDE FILMS BY REMOTE PLASMA CVD FROM DISILANE PRECURSORS - A method of depositing a silicon and nitrogen containing film on a substrate. The method includes introducing silicon-containing precursor to a deposition chamber that contains the substrate, wherein the silicon-containing precursor comprises at least two silicon atoms. The method further includes generating at least one radical nitrogen precursor with a remote plasma system located outside the deposition chamber. Moreover, the method includes introducing the radical nitrogen precursor to the deposition chamber, wherein the radical nitrogen and silicon-containing precursors react and deposit the silicon and nitrogen containing film on the substrate. Furthermore, the method includes annealing the silicon and nitrogen containing film in a steam environment to form a silicon oxide film, wherein the steam environment includes water and acidic vapor. | 2011-01-20 |
20110014799 | PROJECTION ILLUMINATION SYSTEM FOR EUV MICROLITHOGRAPHY - A projection illumination installation for EUV microlithography includes an EUV synchrotron light source for producing EUV used light. An object field is illuminated with the used light using illumination optics. The object field is mapped into an image field using projection optics. A scanning device is used to illuminate the object field by deflecting the used light in sync with a projection illumination period. The result is a projection illumination installation in which the output power from an EUV synchrotron light source can be used as efficiently as possible for EUV projection illumination. | 2011-01-20 |
20110014800 | MINIATURIZED CONNECTORS AND METHODS - Improved miniaturized interconnect connector apparatus and methods for their manufacture. These miniaturized interconnect connectors minimize overall size, while at the same time offering acceptable and even improved electrical performance over prior art interconnect connector designs. In one exemplary embodiment, the interconnect connector comprises a plug and corresponding receptacle manufactured from a laser direct structuring (LDS) polymer material. In another embodiment, the interconnect connector comprises a composite structure which takes advantages of the properties of multiple selected materials. In yet another embodiment of the invention, precisely plated polymers such as the aforementioned LDS polymer are utilized in conjunction with known technologies such as flexible printed circuits (FPC) to produce miniaturized interconnect connectors. | 2011-01-20 |
20110014801 | SOCKET CONNECTOR BRIDGING MOTHERBOARDS ARRANGED AT DIFFERENT LEVELS - An electrical socket comprises a socket body and a plurality of contacts. The socket body comprises a first section and a second section, the first section and the second section each having a plurality of contacts received therein, the first section defining an upper face being spaced away from a top face of the second section in a vertical direction. | 2011-01-20 |
20110014802 | Vertically Stackable Sockets for Chip Modules - The socket system comprises a set of vertically-stackable sockets. A first socket mounts on a printed circuit board to receive a first chip module, and a second socket stacks on the first socket to receive a second chip module. The first socket includes a first set of embedded contacts to electrically connect the first chip module to the printed circuit board, and a second set of embedded contacts to electrically connect the second socket to the printed circuit board. The second socket includes a third set of embedded contacts to electrically connect the second chip module to the printed circuit board. System upgrades are enabled by replacing the chip modules. | 2011-01-20 |
20110014803 | CONNECTOR AND ELECTRICAL TRACKS ASSEMBLY - A connector and electrical tracks assembly comprises a connector with a plurality of electrical contacts; said connector being connectable to a further connector at a first extremity; said connector being connectable at a second extremity to a circuit board portion with a plurality of electrical tracks; wherein a circuit board portion is located between a first layer of plastic thermosetting composite material of fibre and filler and a second layer of plastic thermosetting composite material of fibre and filler. | 2011-01-20 |
20110014804 | Lever-Type Connector - A lever-type connector capable of preventing a worker from damaging a lever when removing the lever from a housing is provided. The lever-type connector includes a housing containing a contact, a wire cover and a lever. The wire cover includes a main body, stopper and a first tapered section formed between the main body and the stopper. The wire cover is attached to a rear side of the housing. The lever includes a pair of side plates and a connecting part that connects the pair of side plates to each other. The lever rotatably attaches to the housing by bridging over the rear side of the wire cover with the wire cover inserted between the pair of side plates in a thickness direction. The main body has a smaller thickness than a distance between the pair of side plates and the stopper has a greater thickness than the distance between the pair of side plates. | 2011-01-20 |
20110014805 | Lever-Type Connector - A lever-type connector capable of simplifying a release operation for a lock of a lever locked by a lock while preventing the lock of the lever locked by the lock from unintentionally being released is provided. The lever-type connector includes a housing, a wire cover, a lever, and a lock. The housing includes a contact, while the wire cover attaches to a rear side of the housing. The lever includes a pair of side plates and a connecting part for connecting both of the side plates to each other. The lever bridges over the rear side of the wire cover and is rotatably attached to the housing between a release position and a mating position. The lock includes a cantilever plate-spring form and is positioned on the rear side of the wire cover in order to prevent rotation of the lever when set to the mating position. | 2011-01-20 |
20110014806 | LAMP CONNECTOR, BACKLIGHT DEVICE AND LIQUID CRYSTAL DISPLAY DEVICE - A valve holding portion including a pair of elastic deformation portions which is arranged opposite each other, whose gap is elastically opened and which sandwiches the valve and a feed portion that is coupled to at least one of the elastic deformation portions and that feeds electric power to the lead wire are included. The feed portion includes a lead contact portion formed such that, when the pair of elastic deformation portions holds the valve, comes into contact with the lead wire. | 2011-01-20 |
20110014807 | CONNECTOR ASSEMBLY WITH INTERNAL SEALS AND MANUFACTURING METHOD - An implantable medical device connector assembly and method of manufacture include a molded, insulative shell having a first inner surface forming a connector bore, an outer surface defining a fill port for receiving an adhesive, and a second inner surface defining a channel extending from the fill port to the first inner surface forming the connector bore; one or more conductive members positioned along the connector bore; and sealing members positioned between the conductive members. An adhesive is disposed in the channel and seals the outer surface of the sealing member to the inner surface forming the connector bore. | 2011-01-20 |
20110014808 | JUMPER AND STRUCTURAL UNIT COMPRISING AT LEAST TWO ELECTRICAL MODULAR TERMINALS AND ONE JUMPER - A jumper that has a housing and is used for bridging two modular electric terminals which are arranged next to one another and are each equipped with a busbar. At least one opening is formed in the busbars. In order to be able to easily actuate the jumper according to the invention and flexibly and easily insert the same into multiple modular terminals, two mutually insulated contact elements are arranged in the housing so as to engage into an opening in a respective busbar, and a jumper rail is movably retained in the housing. The jumper rail, which has two contact zones and a connection zone that connects the contact zones, can be moved from a first final position in which the contact zones do not contact the contact elements into a second final position in which the contact elements are interconnected in an electrically conducting manner via the jumper rail. | 2011-01-20 |
20110014809 | CONNECTOR WITH KEYING MEMBER - A connector is provided for terminating an end portion of a cable that includes a conductor. The connector includes a housing and a contact held by the housing. The contact is configured to be connected to the conductor of the cable. A keying member is rotatably held by the housing. The keying member is configured to cooperate with a keying element of a mating connector that mates with the connector. The keying member is movable about the housing such that the keying member is rotatably positioned to align with the keying element of the mating connector. | 2011-01-20 |
20110014810 | CONNECTOR FRAME - A connector frame is provided. The connector frame can be a generally rectangular member having a bore formed therethrough. The rectangular member can be at least partially formed by a first wall, and a second wall, connected by two side walls. The first, second and side walls can form at least a portion of an interior surface and an exterior surface. At least a portion of the interior surface can include a plurality of raised features adapted to detachably attach to a cable connector. A plurality of projections adapted to provide a grip for one or more fingers on each of the two side walls can be disposed on the exterior surface of the two side walls. | 2011-01-20 |
20110014811 | Shielded insertion and connection structure of flat cable connector - A shielded insertion and connection structure is provided for a flat cable connector, including a receiving housing and a hold-down member. The receiving housing forms a receiving compartment and two side walls formed at opposite ends of the receiving compartment. The hold-down member has opposite ends that respectively form pivot structures for pivotally coupling the hold-down member to the side walls and rotating between an open position and a holding position. The hold-down member is made of metal and the receiving housing is at least partly made of metal to form a conduction section, which is connected to a grounding terminal. When the hold-down member is at the open position and a circuit flat cable is inserted into the receiving compartment, the hold-down member is operated to depress down and hold the circuit flat cable and the hold-down member is put in electrical connection with the grounding terminal through the conduction section. | 2011-01-20 |
20110014812 | THERMAL IMAGING DEVICE WITH A BATTERY PACK WITH A SHOCK ABSORBER - A thermal imaging device includes a replaceable battery pack, which may include a shock absorbing and/or seal member. A battery portion of the battery pack includes an electrical contact and a sidewall that contains at least one battery cell, which is electrically coupled to the contact. An attachment mechanism of the battery pack is configured to engage a portion of a housing of the device, such that a portion of the battery pack forms a terminal end of the device, the battery portion is held within the portion of the housing, and the electrical contact of the battery portion is operably connected to the imaging assembly of the device. The attachment mechanism is releasable from engagement with the housing, such that an entirety of the battery pack can be completely separated from the thermal imaging device. | 2011-01-20 |
20110014813 | BOOSTER CABLE - The present invention provides a booster cable capable of reliably being connected to a terminal that is provided in a limited space. Specifically, a connecting clip | 2011-01-20 |
20110014814 | ELECTRICAL CONNECTOR WITH SHIELDING MEANS FOR GROUNDING AND IMPEDANCE METCHING - An electrical connector ( | 2011-01-20 |
20110014815 | AUDIO JACK CONNECTOR WITH AN IMPROVED CONTACT ARRANGEMENT - An audio jack connector includes an insulative housing ( | 2011-01-20 |
20110014816 | ELECTRICAL CONNECTOR HAVING FLOATABLY ARRANGED CONTACT - An electrical connector includes a number of contacts and an insulative housing. Each contact includes a main body, a spring portion extending upwardly from the main body, and a tail portion defining a receiving space in a vertical plane. The insulative housing has a plurality of passageways retaining the contacts. An inner sidewall of each passageway has a protrusion extending into the receiving space to limit a movement of the contact, such that the contact can float upwardly and downwardly in the vertical direction without being drawn out of the passageway. | 2011-01-20 |
20110014817 | ELECTRICAL CONNECTOR ASSEMBLY AND ADAPTER MODULE - An electrical connector assembly includes a first connector having a plurality of first terminals; a main element for coupling to the first connector, and formed with a terminal recess for reception of the first terminals therein; and an adapter element for coupling to the main element, and including a plurality of adapter terminals. Each adapter terminal has a connecting section that is received in the terminal recess and that is electrically connected to a respective one of the first terminals. | 2011-01-20 |