03rd week of 2011 patent applcation highlights part 14 |
Patent application number | Title | Published |
20110012115 | DISPLAY DEVICE WITH IMPROVED SENSING MECHANISM - A display panel that includes: a substrate, a sensing transistor disposed on the substrate, and a readout transistor connected to the sensing transistor and transmitting a detecting signal is presented. The sensing transistor includes a semiconductor layer disposed on the upper substrate, a source electrode and a drain electrode disposed on the semiconductor layer, and a gate electrode overlapping the semiconductor layer on the source electrode and the drain electrode. Accordingly, in a display device and a manufacturing method thereof, an infrared sensing transistor, a visible light sensing transistor, and a readout transistor are simultaneously formed with a top gate structure such that the number of manufacturing processes and the manufacturing cost may be reduced. | 2011-01-20 |
20110012116 | SEMICONDUCTOR DEVICE AND METHOD FOR MANUFACTURING THE SAME - A highly reliable display device which has high aperture ratio and includes a transistor with stable electrical characteristics is manufactured. The display device includes a driver circuit portion and a display portion over the same substrate. The driver circuit portion includes a driver circuit transistor and a driver circuit wiring. A source electrode and a drain electrode of the driver circuit transistor are formed using a metal. A channel layer of the driver circuit transistor is formed using an oxide semiconductor. The driver circuit wiring is formed using a metal. The display portion includes a pixel transistor and a display portion wiring. A source electrode and a drain electrode of the pixel transistor are formed using a transparent oxide conductor. A semiconductor layer of the pixel transistor is formed using the oxide semiconductor. The display portion wiring is formed using a transparent oxide conductor. | 2011-01-20 |
20110012117 | SEMICONDUCTOR DEVICE AND METHOD FOR MANUFACTURING SEMICONDUCTOR DEVICE - An object is to reduce the manufacturing cost of a semiconductor device. An object is to improve the aperture ratio of a semiconductor device. An object is to make a display portion of a semiconductor device display a higher-definition image. An object is to provide a semiconductor device which can be operated at high speed. The semiconductor device includes a driver circuit portion and a display portion over one substrate. The driver circuit portion includes: a driver circuit TFT in which source and drain electrodes are formed using a metal and a channel layer is formed using an oxide semiconductor; and a driver circuit wiring formed using a metal. The display portion includes: a pixel TFT in which source and drain electrodes are formed using an oxide conductor and a semiconductor layer is formed using an oxide semiconductor; and a display wiring formed using an oxide conductor. | 2011-01-20 |
20110012118 | SEMICONDUCTOR DEVICE AND METHOD FOR MANUFACTURING THE SAME - An object is to improve the aperture ratio of a semiconductor device. The semiconductor device includes a driver circuit portion and a display portion (also referred to as a pixel portion) over the same substrate. The driver circuit includes a channel-etched thin film transistor for driver circuit and a driver circuit wiring formed using metal. Source and drain electrodes of the thin film transistor for the driver circuit are formed using a metal. A channel layer of the thin film transistor for the driver circuit is formed using an oxide semiconductor. The display portion includes a bottom-contact thin film transistor for a pixel and a display portion wiring formed using an oxide conductor. Source and drain electrode layers of the thin film transistor for the pixel are formed using an oxide conductor. A semiconductor layer of the thin film transistor for the pixel is formed using an oxide semiconductor. | 2011-01-20 |
20110012119 | Semiconductor Device and Method for Fabricating the Same - The invention primarily provides gate electrodes and gate wirings permitting large-sized screens for active matrix-type display devices, wherein, in order to achieve this object, the construction of the invention is a semiconductor device having, on the same substrate, a pixel TFT provided in a display region and a driver circuit TFT provided around the display region, wherein the gate electrodes of the pixel TFT and the driver circuit TFT are formed from a first conductive layer, the gate electrodes are in electrical contact through connectors with gate wirings formed from a second conductive layer, and the connectors are provided outside the channel-forming regions of the pixel TFT and the driver circuit | 2011-01-20 |
20110012120 | ARRAY SUBSTRATE FOR LIQUID CRYSTAL DISPLAY DEVICE AND FABRICATION METHOD THEREOF - Provided is a liquid crystal display (LCD) device and a fabrication method thereof. An array substrate for the LCD includes a gate line formed on a substrate, and a gate electrode extending from the gate line; a data line intersected with the gate line, wherein the data line is configured with a gate insulating layer, a semiconductor layer and a data metal layer; a pixel electrode formed of a first transparent metal layer at a pixel which is defined by an intersection of the gate line and the data line; a source electrode extending from the data line, and a drain electrode spaced apart from the source electrode by a predetermined distance to expose a channel; and a second transparent metal layer pattern formed on the data line, the source electrode and the drain electrode, wherein the second transparent metal layer connects the drain electrode and the pixel electrode to each other. | 2011-01-20 |
20110012121 | THIN FILM TRANSISTOR IN WHICH AN INTERLAYER INSULATING FILM COMPRISES TWO DISTINCT LAYERS OF INSULATING MATERIAL - A display apparatus including a TFT array substrate on which TFTs are formed in an array, a counter substrate disposed so as to face the TFT array substrate, and a sealing pattern for adhering the TFT array substrate and the counter substrate to each other, wherein the counter substrate has a counter electrode, and the TFT array substrate has a first conductive layer, a first insulating film formed on the first conductive layer, a second conductive layer disposed so as to intersect the first conductive layer via the first insulating film, a second insulating film formed on the second conductive layer and having at least two layers, and common electrode wiring provided below the sealing pattern and electrically connected to the counter electrode by the sealing pattern, and the sealing pattern overlaps the second conductive layer via the second insulating film. | 2011-01-20 |
20110012122 | ELECTRO-OPTICAL DEVICE AND METHOD FOR MANUFACTURING THE SAME - Using thin film transistors (TFTs), an active matrix circuit, a driver circuit for driving the active matrix circuit or the like are formed on one substrate. Circuits such as a central processing unit (CPU) and a memory, necessary to drive an electric device, are formed using single crystalline semiconductor integrated circuit chips. After the semiconductor integrated circuit chips are adhered to the substrate, the chips are connected with wirings formed on the substrate by a chip on glass (COG) method, a wire bonding method or the like, to manufacture the electric device having a liquid crystal display (LCD) on one substrate. | 2011-01-20 |
20110012123 | THIN FILM TRANSISTOR SUBSTRATE AND FABRICATING METHOD THEREOF - A thin film transistor substrate and fabricating method thereof by which the size of the thin film transistor substrate is reduced by constructing data signal supply lines, each of which supplies a pixel data voltage to a data line, with different metal lines, respectively includes gate and data lines crossing each other on a substrate, with a gate insulating layer disposed therebetween, a thin film transistor formed on each intersection between the gate and data lines, a display area on which a pixel electrode connected to the thin film transistor is formed, a first data signal supply line comprising a first conductive layer connected to the data line in a non-display area located at a periphery of the display area, and a second data signal supply line alternating with the first data signal supply line, with the gate insulating layer disposed therebetween, the second data signal supply line comprising a second conductive layer connected to the data line. | 2011-01-20 |
20110012124 | Metal-Induced Crystallization of Amorphous Silicon in Thin Film Transistors - The invention provides a method for forming thin film transistors including a polycrystalline semiconducting film. The method comprises depositing a first layer of amorphous semiconducting thin film on to a substrate; depositing a second layer of thin film on to the first layer of amorphous semiconducting thin film; patterning the second layer of thin film so that the first layer of amorphous semiconducting thin film is exposed at selected locations; exposing the first and second layers of thin film to a nickel containing compound in either a solution or a vapor phase ; removing the second layer of thin film; and annealing the first layer of amorphous semiconducting thin film at an elevated temperature so the first layer of amorphous semiconducting thin film converts into a polycrystalline semiconducting thin film. | 2011-01-20 |
20110012125 | THIN FILM TRANSISTOR AND ACTIVE MATRIX DISPLAY - A thin film transistor is formed in a semiconductor island on an insulating substrate. The transistor comprises a source ( | 2011-01-20 |
20110012126 | NITRIDE-BASED SEMICONDUCTOR LIGHT EMITTING DEVICE - An object is to provide a nitride-based semiconductor light emitting device capable of preventing a Schottky barrier from being formed at an interface between a contact layer and an electrode. LD | 2011-01-20 |
20110012127 | GaN CRYSTAL SUBSTRATE AND METHOD OF MANUFACTURING THE SAME, AND METHOD OF MANUFACTURING SEMICONDUCTOR DEVICE - In a GaN crystal substrate, a rear surface opposite to a crystal growth surface can have a warpage w | 2011-01-20 |
20110012128 | METHOD FOR MANUFACTURING A LAYER OF GALLIUM NITRIDE OR GALLIUM AND ALUMINUM NITRIDE - The present invention relates to a method for manufacturing a crack free monocrystalline nitride layer having the composition Al | 2011-01-20 |
20110012129 | High-Gain Wide Bandgap Darlington Transistors and Related Methods of Fabrication - A packaged power electronic device includes a wide bandgap bipolar driver transistor having a base, a collector, and an emitter terminal, and a wide bandgap bipolar output transistor having a base, a collector, and an emitter terminal. The collector terminal of the output transistor is coupled to the collector terminal of the driver transistor, and the base terminal of the output transistor is coupled to the emitter terminal of the driver transistor to provide a Darlington pair. An area of the output transistor is at least 3 times greater than an area of the driver transistor in plan view. For example, an area ratio of the output transistor to the driver transistor may be between about 3:1 to about 5:1. Related devices and methods of fabrication are also discussed. | 2011-01-20 |
20110012130 | High Breakdown Voltage Wide Band-Gap MOS-Gated Bipolar Junction Transistors with Avalanche Capability - High power wide band-gap MOSFET-gated bipolar junction transistors (“MGT”) are provided that include a first wide band-gap bipolar junction transistor (“BJT”) having a first collector, a first emitter and a first base, a wide band-gap MOSFET having a source region that is configured to provide a current to the base of the first wide band-gap BJT and a second wide band-gap BJT having a second collector that is electrically connected to the first collector, a second emitter that is electrically connected to the first emitter, and a second base that is electrically connected to the first base. | 2011-01-20 |
20110012131 | METHOD FOR MANUFACTURING SEMICONDUCTOR SUBSTRATE, AND SEMICONDUCTOR DEVICE - An object is to provide a novel manufacturing method of a semiconductor substrate containing silicon carbide, and another object is to provide a semiconductor device using silicon carbide. A semiconductor substrate is manufactured through the steps of: adding ions to a silicon carbide substrate to form an embrittlement region in the silicon carbide substrate; bonding the silicon carbide substrate to a base substrate with insulating layers interposed therebetween; heating the silicon carbide substrate and separating the silicon carbide substrate at the embrittlement region to form a silicon carbide layer over the base substrate with the insulating layers interposed between therebetween; and performing heat treatment on the silicon carbide layer at a temperature of 1000° C. to 1300° C. to reduce defects of the silicon carbide layer. A semiconductor device is manufactured using the semiconductor substrate formed as described above. | 2011-01-20 |
20110012132 | Semiconductor Device - Provided is a semiconductor device which has improved withstand voltage and can be manufactured by simpler manufacturing process. The semiconductor device according to the present invention includes: a SiC-containing n-type epitaxial layer | 2011-01-20 |
20110012133 | SILICON CARBIDE SEMICONDUCTOR DEVICE AND METHOD FOR MANUFACTURING THE SAME - A silicon carbide MOSFET that exhibits a high source-to-drain withstand voltage and that involves a smaller difference between gate-to-drain capacitance achieved in an activated state and gate-to-drain capacitance achieved in a deactivated state. A silicon carbide drift layer of a first conductivity type is provided on a silicon carbide substrate of a first conductivity type; a pair of base regions are provided in a surface layer portion of the silicon carbide drift layer and exhibit a second conductivity type; a pair of source regions are provided in interiors of surface layer portions of the pair of base regions and exhibit a first conductivity type; and semi-insulating regions are provided between the silicon carbide substrate and the pair of base regions. | 2011-01-20 |
20110012134 | IMAGE READING APPARATUS AND MULTILAYER SUBSTRATE - An image reading apparatus includes a light source that irradiates a document with light, the light source including a multilayer substrate and light emitting elements linearly arranged on a first surface of the multilayer substrate; and a light receiver that receives reflected light reflected from the document. The multilayer substrate has at least a pair of through holes each having an inner surface on which a reinforcement member is formed, the at least a pair of through holes being formed so that one of the light emitting elements is interposed therebetween. The reinforcement members contact wiring formed on the first surface of the multilayer substrate and wiring formed on a second surface of the multilayer substrate opposite the first surface. | 2011-01-20 |
20110012135 | LIGHT-EMITTING DEVICE AND REPAIRING METHOD THEREOF - A light-emitting device including a plurality of light-emitting units is provided. Each of the light-emitting units includes a first common electrode layer, a plurality of light-emitting layers, and a second common electrode layer. The first common electrode layer includes a bridge conductive line and a plurality of first electrode patterns electrically insulated from each other, in which the first electrode patterns cover a portion of the bridge conductive line and are electrically connected to each other through the bridge conductive line. Each of the light-emitting layers is disposed on one of the first electrode patterns. The second common electrode layer is disposed on the light-emitting layers, in which the first common electrode layer of each of the light-emitting units is electrically connected to the second common electrode layer of an adjacent light-emitting unit. | 2011-01-20 |
20110012136 | DISPLAY APPARATUS - Provided is a display apparatus whose light extraction efficiency is not reduced even when a film thickness error of an image display device is caused. The display apparatus includes a plurality of image display devices. Each of the image display devices includes at least: a stack ( | 2011-01-20 |
20110012137 | STRUCTURE OF AC LIGHT-EMITTING DIODE DIES - A structure of light-emitting diode (LED) dies having an AC loop (a structure of AC LED dies), which is formed with at least one unit of AC LED micro-dies disposed on a chip. The unit of AC LED micro-dies comprises two LED micro-dies arranged in mutually reverse orientations and connected with each other in parallel, to which an AC power supply may be applied so that the LED unit may continuously emit light in response to a positive-half wave voltage and a negative-half wave voltage in the AC power supply. Since each AC LED micro-die is operated forwardly, the structure of AC LED dies also provides protection from electrical static charge (ESD) and may operate under a high voltage. | 2011-01-20 |
20110012138 | Light-Emitting Diode Die Packages and Methods for Producing Same - The present invention relates to a light-emitting diode die package. The LED die package includes a semiconductor base, at least two electrodes disposed on an electrode mounting surface of the semiconductor base, an insulation layer formed on the electrode-mounting surface and provided with two through holes for exposing the electrodes, a conductor-forming layer formed on the insulation layer and provided with two conductor-mounting holes in communication with the through holes, and conductor units formed within the through holes and the conductor-mounting holes in a manner electrically connected to the corresponding electrodes. The LED die package further includes a covering layer formed on a surface of the LED die opposite to the electrode-mounting surface and extending to an outer surface of the LED die. The covering layer is made of transparent material doped with phosphor powder. | 2011-01-20 |
20110012139 | ORGANIC ELECTROLUMINESCENT DEVICE - An organic electroluminescent device with a configuration in which a functional layer, a transparent first electrode, alight emitting layer, and a second electrode are disposed in layer in this order, wherein a surface of the functional layer has a plurality of depressions and projections having a height of 0.5 μm to 100 μm, the surface being located on a side opposite to a side where the first electrode is, and the refractive index n | 2011-01-20 |
20110012140 | LIGHT EMITTING DIODE ARRANGEMENT - The invention relates to a light emitting diode arrangement comprising a first light emitting diode ( | 2011-01-20 |
20110012141 | SINGLE-COLOR WAVELENGTH-CONVERTED LIGHT EMITTING DEVICES - A packaged light emitting device (LED) includes an LED chip configured to emit light within a first wavelength range, and a wavelength conversion material on the LED chip. The wavelength conversion material is configured to receive the light within the first wavelength range and responsively emit light within a second wavelength range different than the first wavelength range such that a light output of the packaged LED does not substantially include the light within the first wavelength range and provides an appearance of substantially monochromatic light of a color of the visible spectrum corresponding to the second wavelength range. The packaged LED may include a color filter on the wavelength conversion material that is configured to prevent passage of the light within the first wavelength range therethrough, and/or may include a thickness of the wavelength conversion material configured to completely absorb the light within the first wavelength range. | 2011-01-20 |
20110012142 | Method for Producing a Luminous Device and Luminous Device - A method for producing a luminous device is specified. A number of light emitting diodes each have a radiation-transmissive carrier and at least two semiconductor bodies spatially separated from one another. Each semiconductor body is provided for generating electromagnetic radiation. The semiconductor bodies can be driven separately from one another and the semiconductor bodies are arranged at the top side of the radiation-transmissive carrier on the radiation-transmissive carrier. A chip assemblage is composed of CMOS chips each of which has at least two connection locations at its top side. At least one of the light emitting diodes is connected to one of the CMOS chips. The light emitting diode is arranged, at the top side of the radiation-transmissive carrier, at the top side of the CMOS chip and each semiconductor body of the light emitting diode is connected to a connection location of the CMOS chip. | 2011-01-20 |
20110012143 | SOLID STATE LIGHTING COMPONENT - An LED component comprising an array of LED chips mounted on a planar surface of a submount with the LED chips capable of emitting light in response to an electrical signal. The LED chips comprise respective groups emitting at different colors of light, with each of the groups interconnected in a series circuit. A lens is included over the LED chips. Other embodiments can comprise thermal spreading structures included integral to the submount and arranged to dissipate heat from the LED chips. | 2011-01-20 |
20110012144 | LIGHT EMITTING DEVICE PACKAGE - Provided is a light emitting device package. The light emitting device package comprises a package body, a light emitting device, and a transient voltage suppress diode. The package body comprises a plurality of electrodes. The light emitting device is electrically connected to the plurality of electrodes. The transient voltage suppress diode is electrically connected to the plurality of electrodes. | 2011-01-20 |
20110012145 | GaN-BASED SEMICONDUCTOR LIGHT EMITTING DEVICE - There is provided a GaN-based semiconductor light emitting device including: a substrate; and an n-type GaN-based semiconductor layer, an active layer and a p-type GaN-based semiconductor layer sequentially deposited on the substrate, wherein the active layer includes: a first barrier layer including Al | 2011-01-20 |
20110012146 | SEMICONDUCTOR LIGHT-EMITTING DEVICE AND METHOD FOR MANUFACTURING THE SAME - There is provided a light-emitting device including a second electrode which exhibits a stable behavior in a process for manufacturing a light-emitting device or during an operation of a light-emitting device. A light-emitting device includes a first compound semiconductor layer | 2011-01-20 |
20110012147 | WAVELENGTH-CONVERTED SEMICONDUCTOR LIGHT EMITTING DEVICE INCLUDING A FILTER AND A SCATTERING STRUCTURE - A semiconductor structure comprises a light emitting layer disposed between an n-type region and a p-type region. A wavelength converting material is disposed over the semiconductor structure. The wavelength converting material is configured to absorb light emitted by the semiconductor structure and emit light of a different wavelength. A filter configured to reflect blue ambient light is disposed over the wavelength converting material. A scattering structure is disposed over the wavelength converting layer. The scattering structure is configured to scatter light. In some embodiments, the scattering structure is a transparent material having a rough surface, containing non-wavelength-converting particles that appear substantially white in ambient light, or including both a rough surface and white particles. | 2011-01-20 |
20110012148 | LIGHTING DEVICE WITH LIGHT SOURCES POSITIONED NEAR THE BOTTOM SURFACE OF A WAVEGUIDE - A device according to embodiments of the invention includes a waveguide, typically formed from a first section of transparent material. A light source is disposed proximate a bottom surface of the waveguide. The light source comprises a semiconductor light emitting diode and a second section of transparent material disposed between the semiconductor light emitting diode and the waveguide. Sidewalls of the second section of transparent material are reflective. A surface to be illuminated is disposed proximate a top surface of the waveguide. In some embodiments, an edge of the waveguide is curved. | 2011-01-20 |
20110012149 | REFLECTIVE SUBSTRATEFOR LEDS - An underfill formation technique for LEDs molds a reflective underfill material to encapsulate LED dies mounted on a submount wafer while forming a reflective layer of the underfill material over the submount wafer. The underfill material is then hardened, such as by curing. The cured underfill material over the top of the LED dies is removed using microbead blasting while leaving the reflective layer over the submount surface. The exposed growth substrate is then removed from all the LED dies, and a phosphor layer is molded over the exposed LED surface. A lens is then molded over the LEDs and over a portion of the reflective layer. The submount wafer is then singulated. The reflective layer increases the efficiency of the LED device by reducing light absorption by the submount without any additional processing steps. | 2011-01-20 |
20110012150 | LIGHT EMITTING DEVICE AND METHOD FOR FABRICATING THE SAME - A light-emitting device comprises a second conductive type semiconductor layer, an active layer on the second conductive type semiconductor layer, a first conductive type semiconductor layer on the active layer, and a nonconductive semiconductor layer on the first conductive type semiconductor layer, the nonconductive semiconductor layer comprising a light extraction structure. | 2011-01-20 |
20110012151 | LIGHT EMITTING DEVICE - A light emitting device includes: a mounting member including a recess; a light emitting element provided in the recess and made of a semiconductor; an electrostatic discharge protection element provided in the recess and connected parallel to the light emitting element; and a translucent resin layer mixed with a filler capable of reflecting emitted light from the light emitting element, covering the electrostatic discharge protection element and not covering the light emitting element. | 2011-01-20 |
20110012152 | LIGHT EMITTING DEVICE AND LIGHT EMITTING DEVICE PACKAGE HAVING THE SAME - Disclosed are a light emitting device and a light emitting device package having the same. The light emitting device includes a light emitting structure that includes a first conductive type semiconductor layer, an active layer on the first conductive type semiconductor layer, and a second conductive type semiconductor layer on the active layer, a first electrode including at least one arm shape and contacted with a portion of the first conductive type semiconductor layer, an insulating layer covering the first electrode, and a second electrode including on at least one arm shape, wherein the second electrode disposes on at least one of the insulating layer and the second conductive type semiconductor layer. | 2011-01-20 |
20110012153 | Light emitting package and methods of fabricating the same - Example embodiments are directed to a light emitting package having a structure that prevents variance in a depth of a cavity in which a chip is mounted and a method of fabricating the same. A light emitting package includes a package body including a first body including the cavity and a second body bonded to the first body. The cavity penetrates the first body. A first electrode and a second electrode separate from each other are on the package body. A first dielectric layer is between the package body and the first electrode and between the package body and the second electrode. A light emitting element is placed in the cavity and electrically connected to the first electrode and the second electrode. A method of fabricating the light emitting package includes forming the first body and the second body bonded to the first body through a dielectric layer, forming the cavity in the first body and forming the light emitting element in the cavity. | 2011-01-20 |
20110012154 | LED ELEMENT AND METHOD FOR MANUFACTURING LED ELEMENT - Provided is a GaN-based LED element having a novel structure for improving output by increasing light extraction efficiency. A GaN-based LED element comprising: a semiconductor laminated structure in which an n-type GaN-based semiconductor layer is arranged on the side of a lower surface of a p-type GaN-based semiconductor layer having an upper surface and the lower surface, and a light emitting part comprising a GaN-based semiconductor is interposed between the layers; a p-side electrode formed on the upper surface of the p-type GaN-based semiconductor layer; and an n-side electrode electrically connected to the n-type GaN-based semiconductor layer, wherein the p-side electrode comprises a transparent conductive film comprising a window region serving as a window for extracting light generated in the light emitting part, and a flat section and a rough surface section formed by a roughening treatment are arranged to form a predetermined mixed pattern on the upper surface of the p-type GaN-based semiconductor layer covered with the window region of the transparent conductive film. | 2011-01-20 |
20110012155 | Semiconductor Optoelectronics Structure with Increased Light Extraction Efficiency and Fabrication Method Thereof - A semiconductor optoelectronic structure with increased light extraction efficiency and a fabrication method thereof are presented. The semiconductor optoelectronic structure includes continuous grooves formed under an active layer of the semiconductor optoelectronic structure to reflect light from the active layer and thereby direct more light through a light output surface so as to increase the light intensity from the semiconductor optoelectronic structure. | 2011-01-20 |
20110012156 | LIGHT EMITTING DEVICES INCLUDING WAVELENGTH CONVERTING MATERIAL - Light-emitting devices and associated methods are provided. The light emitting devices can have a wavelength converting material-coated emission surface. | 2011-01-20 |
20110012157 | TRANSPARENT HEAT SPREADER FOR LEDS - A heat spreader for an LED can include a thermally conductive and optically transparent member. The bottom side of the heat spreader can be configured to attach to a light emitting side of the LED. The top and/or bottom surface of the heat spreader can have a phosphor layer formed thereon. The heat spreader can be configured to conduct heat from the LED to a package. The heat spreader can be configured to conduct heat from the phosphors to the package. By facilitating the removal of heat from the LED and phosphors, more current can be used to drive the LED. The use of more current facilitates the construction of a brighter LED, which can be used in applications such as flashlights, displays, and general illumination. By facilitating the removal of heat from the phosphors, desired colors can be better provided. | 2011-01-20 |
20110012158 | MANUFACTURING METHOD AND INTEGRATED CIRCUIT HAVING A LIGHT PATH TO A PIXILATED ELEMENT - The present invention relates to a manufacturing method of an integrated circuit (IC) comprising a substrate ( | 2011-01-20 |
20110012159 | PACKAGE FOR OPTICAL SEMICONDUCTOR DEVICE, OPTICAL SEMICONDUCTOR DEVICE USING THE PACKAGE, AND METHODS FOR PRODUCING SAME - The present invention is a package for optical semiconductor devices, and an optical semiconductor device using the package, which can prevent discoloration of a plating layer formed on a lead frame even when a silicone resin is used as a sealing resin for an optical semiconductor device, and which enables high luminous efficiency for a long time. | 2011-01-20 |
20110012160 | SEMICONDUCTOR LIGHT-EMITTING DEVICE AND METHOD FOR MANUFACTURING SEMICONDUCTOR LIGHT-EMITTING DEVICE - A semiconductor light-emitting device | 2011-01-20 |
20110012161 | MANUFACTURING METHODS AND INSTALLATION PROCEDURES WHICH CONFORMING TO THE INTERNATIONAL SAFETY CODES AND REGULATIONS FOR AC LED LAMP - An alternating-current (AC) light-emitting diode (LED) lamp conforming to international safety regulations and a method for making the same are provided, wherein the core technique involves a circuit board made of a thermally conductive insulation material on which traces are provided, a chip is soldered, and an LED lighting unit is encapsulated. After the LED lighting unit is encapsulated on the circuit board, exposed and electrically conductive portions of the traces or solder points on the circuit board are encapsulated with a thermally resistant insulation material. Furthermore, a thermally conductive insulation plate is provided between the circuit board and a metal housing, and the circuit board is secured in position by fasteners made of an insulation material. Thus, electric shock is effectively prevented which may otherwise result from high-voltage current passing from electrically conductive ends of the circuit board to a heat dissipation mechanism (the metal housing). | 2011-01-20 |
20110012162 | LED PACKAGE WITH TOP-BOTTOM ELECTRODE - An LED package with an extended top electrode and an extended bottom electrode is made from a single metal sheet, one manufacturing process embodiment includes: preparing a piece of single metal sheet, forming a first metal and a coplanar second metal, mounting an LED on an inner end of the first metal, wire-bonding top electrode to an inner end of the second metal, encapsulating at least the LED and the bonding wire with a protection glue, bending an outer end of the first metal upward twice 90 degrees to form a top flat as an extended top electrode of the package, and bending an outer end of the second metal downward twice 90 degrees to form a bottom flat as an extended bottom electrode of the package. | 2011-01-20 |
20110012163 | DEVICE HAVING A MULTILAYERED STRUCTURE AND METHOD OF FABRICATING THEREOF - The invention provides a multilayered device and the method for fabricating the same. The multilayered device comprises a substrate, a first layer deposited on the substrate, a second layer deposited on the first layer, and a third layer deposited on the second layer. The coverage of the second layer is determined by a rate of crystallization of the third layer. The rate of crystallization of the third layer is determined by measuring X-ray diffraction of the device. | 2011-01-20 |
20110012164 | LIGHT-EMITTING ELEMENT AND METHOD OF FABRICATING THE SAME - Provided are a light-emitting element and a method of fabricating the same. The light-emitting element includes: a first pattern including conductive regions and non-conductive regions. The non-conductive regions are defined by the conductive regions. The light-emitting element also include an insulating pattern including insulating regions and non-insulating regions which correspond respectively to the conductive regions and non-conductive regions. The non-insulating regions are defined by the insulating regions. The light-emitting element further includes a light-emitting structure interposed between the first pattern and the insulating pattern. The light-emitting structure includes a first semiconductor pattern of a first conductivity type, a light-emitting pattern, and a second semiconductor pattern of a second conductivity type which are stacked sequentially. The light-emitting element also includes a second pattern formed in the non-insulating regions. | 2011-01-20 |
20110012165 | LIGHT-EMITTING DIODE LIGHT BAR - In a light-emitting diode light bar of a light-emitting device, a first lead and a second lead are juxtaposed with a distance. A light-emitting diode crystal has a first electrode and a second electrode. Then, the first electrode is electrically fixed to the first lead. The second electrode is electrically connected to the second lead via a metallic lead. A light-transmitting body is used to package the light-emitting diode crystal and the metallic lead. Finally, via a hot pressing process, an insulating layer covers the first lead and the second lead. In this way, a light-emitting diode light bar is formed. | 2011-01-20 |
20110012166 | METHOD AND DEVICE FOR WAFER SCALE PACKAGING OF OPTICAL DEVICES USING A SCRIBE AND BREAK PROCESS - A multilayered integrated optical and circuit device. The device has a first substrate comprising at least one integrated circuit chip thereon, which has a cell region and a peripheral region. Preferably, the peripheral region has a bonding pad region, which has one or more bonding pads and an antistiction region surrounding each of the one or more bonding pads. The device has a second substrate with at least one or more deflection devices thereon coupled to the first substrate. At least one or more bonding pads are exposed on the first substrate. The device has a transparent member overlying the second substrate while forming a cavity region to allow the one or more deflection devices to move within a portion of the cavity region to form a sandwich structure including at least a portion of the first substrate, a portion of the second substrate, and a portion of the transparent member. The one or more bonding pads and the antistiction region are exposed while the one or more deflection devices is maintained within the portion of the cavity region. | 2011-01-20 |
20110012167 | LIGHT EMITTING ELEMENT - A light emitting device includes a pair of electrodes facing to each other and a phosphor layer which is sandwiched between the pair of electrodes and includes phosphor particles placed therein. The phosphor particles include an n-type nitride semiconductor part and a p-type nitride semiconductor part, the n-type nitride semiconductor part and the p-type nitride semiconductor part are made of respective single crystals having wurtzite-type crystal structures having c axes parallel with each other, and the phosphor particles include an insulation layer provided to overlie one end surface out of their end surfaces perpendicular to the c axes. | 2011-01-20 |
20110012168 | COMPOUND SEMICONDUCTOR LIGHT-EMITTING ELEMENT AND ILLUMINATION DEVICE USING THE SAME, AND METHOD FOR MANUFACTURING COMPOUND SEMICONDUCTOR LIGHT-EMITTING ELEMENT - A compound semiconductor light-emitting element includes: a substrate; a first electrode provided on one face of the substrate; a plurality of nanoscale columnar crystalline structures in which an n-type semiconductor layer, a light-emitting layer and a p-type semiconductor layer are stacked in order on the other face of the substrate; a second electrode connected to top portions of the plurality of columnar crystalline structures; and a foundation layer, provided on the side of the other face, in a first region being a partial region of the substrate; wherein a level difference is provided, on the other face, between the first region and a second region being at least part of a remaining region of the substrate excluding the first region. | 2011-01-20 |
20110012169 | NITRIDE SEMICONDUCTOR LIGHT-EMITTING DEVICE - A nitride semiconductor light-emitting device includes a substrate ( | 2011-01-20 |
20110012170 | SEMICONDUCTOR DEVICE USED IN STEP-UP DC-DC CONVERTER, AND STEP-UP DC-DC CONVERTER - A power supply device is disclosed that is able to satisfy the power requirements of a device in service and has high efficiency. | 2011-01-20 |
20110012171 | SEMICONDUCTOR DEVICE - According to one embodiment, a semiconductor device includes a first semiconductor layer of a first conductivity type, a second semiconductor layer of a second conductivity type, a third semiconductor layer of the first conductivity type, and a first main electrode. The second semiconductor layer is provided on the first semiconductor layer. The third semiconductor layer is provided on the first semiconductor layer in contact with the second semiconductor layer and has an impurity concentration higher than an impurity concentration of the first semiconductor layer. The first main electrode includes a first metal layer and a second metal layer made of a metal different from a metal of the first metal layer. The first metal layer is connected to the second semiconductor layer. The second metal layer is connected to the third semiconductor layer. | 2011-01-20 |
20110012172 | Semiconductor Heterostructures Having Reduced Dislocation Pile-Ups and Related Methods - Dislocation pile-ups in compositionally graded semiconductor layers are reduced or eliminated, thereby leading to increased semiconductor device yield and manufacturability. This is accomplished by introducing a semiconductor layer having a plurality of threading dislocations distributed substantially uniformly across its surface as a starting layer and/or at least one intermediate layer during growth and relaxation of the compositionally graded layer. The semiconductor layer may include a seed layer disposed proximal to the surface of the semiconductor layer and having the threading dislocations uniformly distributed therein. | 2011-01-20 |
20110012173 | SEMICONDUCTOR DEVICE - A semiconductor device includes an undoped GaN layer ( | 2011-01-20 |
20110012174 | Structure and Method for Forming Field Effect Transistor with Low Resistance Channel Region - A trench-gate field effect transistor includes trenches extending into a silicon region of a first conductivity type, and a gate electrodes in each trench. Body regions of second conductivity type extend over the silicon region between adjacent trenches. Each body region forms a PN junction with the silicon region. A gate dielectric layer lines at least upper sidewalls of each trench, and insulates the gate electrode from the body region. Source regions of the first conductivity flank the trenches. A silicon-germanium region vertically extends through each source region and through a corresponding body region, and terminates within the corresponding body region before reaching the PN junction. | 2011-01-20 |
20110012175 | SEMICONDUCTOR WAFER, SEMICONDUCTOR WAFER MANUFACTURING METHOD, AND ELECTRONIC DEVICE - A high-quality GaAs-type crystal thin film using an inexpensive Si wafer with good thermal release characteristics is achieved. Provided is a semiconductor wafer comprising an Si wafer; a Ge layer that is crystal-grown on the wafer and shaped as an isolated island; and a functional layer that is crystal-grown on the Ge layer. The Ge layer may be shaped as an island having a size that docs not exceed double a distance moved by crystal defects as a result of annealing the Ge layer at a certain temperature for a certain time. The Ge layer may be shaped as an island having a size for which stress due to a difference relative to a thermal expansion coefficient of Si, which is material of the wafer, does not cause crystal dejects when the Ge layer is annealed at a certain temperature. | 2011-01-20 |
20110012176 | Multiple Orientation Nanowires With Gate Stack Stressors - An electronic device includes a conductive channel defining a crystal structure and having a length and a thickness t | 2011-01-20 |
20110012177 | Nanostructure For Changing Electric Mobility - A structure and a method for a semiconductor including a nanostructure semiconductor channel. The semiconductor may include a dielectric and an electrode, the electrode attached to the dielectric, a semiconductor channel may be disposed proximate to the dielectric, wherein the semiconductor channel has an electric mobility and is configured to have at least one dimension, and wherein the dielectric may be configured to apply a force at the at least one dimension. | 2011-01-20 |
20110012178 | SEMICONDUCTOR WAFER, METHOD OF MANUFACTURING A SEMICONDUCTOR WAFER, AND SEMICONDUCTOR DEVICE - Provided is a semiconductor wafer having decreased interface state density at the semiconductor-insulator interface, a method of manufacturing this semiconductor wafer, and a semiconductor device. | 2011-01-20 |
20110012179 | MAGNETORESISTIVE RANDOM ACCESS MEMORY DEVICE - An aspect of the present disclosure, there is provided a magnetoresistive random access memory device, including, an active area formed on a semiconductor substrate in a first direction, a magnetoresistive effect element formed on the active area and storing data by a change in resistance value, a gate electrode of a cell transistor formed on each side of the magnetoresistive effect element on the active area in a second direction, a bit line contact formed on the active area and arranged alternately with the magnetoresistive effect element, a first bit line connected to the magnetoresistive effect, and a second bit line connected to the bit line contact. | 2011-01-20 |
20110012180 | METHOD OF FORMING A CMOS STRUCTURE HAVING GATE INSULATION FILMS OF DIFFERENT THICKNESSES - The semiconductor integrated circuit device employs on the same silicon substrate a plurality of kinds of MOS transistors with different magnitudes of tunnel current flowing either between the source and gate or between the drain and gate thereof. These MOS transistors include tunnel-current increased MOS transistors at least one of which is for use in constituting a main circuit of the device. The plurality of kinds of MOS transistors also include tunnel-current reduced or depleted MOS transistors at least one of which is for use with a control circuit. This control circuit is inserted between the main circuit and at least one of the two power supply units. | 2011-01-20 |
20110012181 | METHOD OF MANUFACTURING SEMICONDUCTOR INTEGRATED CIRCUIT DEVCIE HAVING CAPACITOR ELEMENT - In a complete CMOS SRAM having a memory cell composed of six MISFETs formed over a substrate, a capacitor element having a stack structure is formed of a lower electrode covering the memory cell, an upper electrode, and a capacitor insulating film (dielectric film) interposed between the lower electrode and the upper electrode. One electrode (the lower electrode) of the capacitor element is connected to one storage node of a flip-flop circuit, and the other electrode (the upper electrode) is connected to the other storage node. As a result, the storage node capacitance of the memory cell of the SRAM is increased to improve the soft error resistance. | 2011-01-20 |
20110012182 | Semiconductor Constructions and Transistors, and Methods of Forming Semiconductor Constructions and Transistors - The invention includes a transistor device having a semiconductor substrate with an upper surface. A pair of source/drain regions are formed within the semiconductor substrate and a channel region is formed within the semiconductor substrate and extends generally perpendicularly relative to the upper surface of the semiconductor substrate. A gate is formed within the semiconductor substrate between the pair of the source/drain regions. | 2011-01-20 |
20110012183 | WIRELESS CHIP - An ID tag capable of communicating data wirelessly, the size of which is reduced, and where the size of an IC chip is reduced, a limited area of the chip is effectively used, current consumption is reduced, and communication distance is prevented from decreasing. The ID tag of the invention includes an IC chip having an integrated circuit, a resonance capacitor portion and a storage capacitor portion, and an antenna formed over the IC chip so as to overlap at least partially with an insulating film interposed therebetween. The antenna, the insulating film and wirings or semiconductor films forming the integrated circuit are stacked, and one or both of capacitors in the resonance capacitor portion and the storage capacitor portion are formed by this stacked structure. | 2011-01-20 |
20110012184 | SEMICONDUCTOR MEMORY DEVICE - A semiconductor memory device including: word lines extending in a Y direction on a semiconductor substrate, the word lines being arranged in an X direction perpendicular to the Y direction and being parallel to one another; active regions each elongating and intersecting with two of the word lines, the active regions being arranged in the Y direction and being parallel to one another on the semiconductor substrate; a capacitance contact plug connected to each end of each of the active regions in the longitudinal direction thereof; a stack lower electrode including a first lower electrode formed on the capacitance contact plug and a second lower electrode formed on the first lower electrode; a capacitance insulating film; and an upper electrode, wherein the center position of the second lower electrode is shifted in a predetermined direction from the center position of the first lower electrode. | 2011-01-20 |
20110012185 | SEMICONDUCTOR MEMORY DEVICE AND WRITE METHOD OF THE SAME - A write and erase method of a semiconductor memory device includes a floating gate type transistor having a semiconductor substrate, a gate insulating film formed on the semiconductor substrate, a floating gate electrode formed on the gate insulating film, and a control gate electrode opposing the floating gate electrode with a hollow portion being sandwiched therebetween. A capacitance between the semiconductor substrate and the control gate electrode is controlled by one of an operation of forming, in the hollow portion, an electrical path which electrically connects the floating gate electrode and the control gate electrode, and an operation of eliminating the electrical path. | 2011-01-20 |
20110012186 | ISOLATION TRENCHES FOR MEMORY DEVICES - A first dielectric plug is formed in a portion of a trench that extends into a substrate of a memory device so that an upper surface of the first dielectric plug is recessed below an upper surface of the substrate. The first dielectric plug has a layer of a first dielectric material and a layer of a second dielectric material formed on the layer of the first dielectric material. A second dielectric plug of a third dielectric material is formed on the upper surface of the first dielectric plug. | 2011-01-20 |
20110012187 | NON-VOLATILE SEMICONDUCTOR MEMORY DEVICE AND METHOD OF MANUFACTURING THE SAME - A semiconductor memory device includes: a semiconductor substrate; an element isolation insulating film dividing the semiconductor substrate into a plurality of element regions; tunnel insulating films formed respectively on the plurality of element regions; floating gate electrodes formed respectively on the tunnel insulating films; a first control-gate electrode formed, on the floating gate electrodes and between each two floating gate electrodes adjacent to each other in a channel-width direction, with a laminated insulating film interposed therebetween; assist insulating films formed on side surface facing in the channel-width direction of the plurality of element regions; and a second control-gate electrode formed between the plurality of element regions with the assist insulating films interposed therebetween. | 2011-01-20 |
20110012188 | SEMICONDUCTOR MEMORY DEVICE - A semiconductor memory device includes: a stacked body formed of a plurality of inter-layer insulating films and a plurality of electrode films alternately stacked and having a through-hole formed in the stacking direction; an electrode-side insulating film of a film thickness of 4 nm or more provided on an inner surface of the through-hole; a charge storage film provided on the electrode-side insulating film; a semiconductor-side insulating film of a film thickness of 4 nm or more provided on the charge storage film; and a semiconductor pillar buried in the through-hole. | 2011-01-20 |
20110012189 | SEMICONDUCTOR DEVICE AND METHOD OF FORMING THE SAME - A semiconductor device includes stacked-gate structures including a plurality of cell gate patterns and insulating patterns alternately stacked on a semiconductor substrate and extending in a first direction. Active patterns and gate dielectric patterns are disposed in the stacked-gate structures. The active patterns penetrate the stacked-gate structures and are spaced apart from each other in a second direction intersecting the first direction, and the gate dielectric patterns are interposed between the cell gate patterns and the active patterns and extend onto upper and lower surfaces of the cell gate patterns. The active patterns share the cell gate patterns in the stacked-gate structures. | 2011-01-20 |
20110012190 | SEMICONDUCTOR DEVICE AND METHOD FOR MANUFACTURING THE SAME - A semiconductor device includes a semiconductor substrate, a first insulating film formed on the semiconductor substrate, a charge storage layer formed on the first insulating film, a second insulating film formed on the charge storage layer, and a control electrode formed on the second insulating film, the second insulating film including a lower silicon nitride film, a lower silicon oxide film formed on the lower silicon nitride film, an intermediate insulating film formed on the lower silicon oxide film and containing a metal element, the intermediate insulating film having a relative dielectric constant of greater than 7, an upper silicon oxide film formed on the intermediate insulating film, and an upper silicon nitride film formed on the upper silicon oxide film. | 2011-01-20 |
20110012191 | SELF-ALIGNED PATTERNING METHOD BY USING NON-CONFORMAL FILM AND ETCH BACK FOR FLASH MEMORY AND OTHER SEMICONDUCTUR APPLICATIONS - A method for fabricating a memory device with a self-aligned trap layer which is optimized for scaling is disclosed. In the present invention, a non-conformal oxide is deposited over the charge trapping layer to form a thick oxide on top of the core source/drain region and a pinch off and a void at the top of the STI trench. An etch is performed on the pinch-off oxide and the thin oxide on the trapping layer on the STI oxide. The trapping layer is then partially etched between the core cells. A dip-off of the oxide on the trapping layer is performed. And a top oxide is formed. The top oxide converts the remaining trap layer to oxide and thus isolate the trap layer. | 2011-01-20 |
20110012192 | Vertical Channel Transistor Structure and Manufacturing Method Thereof - A vertical channel transistor structure is provided. The structure includes a substrate, a channel, a cap layer, a charge trapping layer, a source and a drain. The channel is formed in a fin-shaped structure protruding from the substrate. The cap layer is deposited on the fin-shaped structure. The cap layer and the fin-shaped structure have substantially the same width. The charge trapping layer is deposited on the cap layer and on two vertical surfaces of the fin-shaped structure. The gate is deposited on the charge trapping layer and on two vertical surfaces of the fin-shaped structure. The source and the drain are respectively positioned on two sides of the fin-shaped structure and opposite the gate. | 2011-01-20 |
20110012193 | SEMICONDUCTOR DEVICE HAVING VERTICAL TRANSISTOR, MANUFACTURING METHOD THEREOF, AND DATA PROCESSING SYSTEM - A semiconductor device includes: a semiconductor substrate; a silicon pillar provided perpendicularly to a main surface of the semiconductor substrate; a gate dielectric film that covers a portion of a side surface of the silicon pillar; an insulator pillar that covers remaining portions of the side surface of the silicon pillar; a gate electrode that covers the silicon pillar via the gate dielectric film and the insulator pillar; an interlayer dielectric film provided above the silicon pillar, the gate dielectric film, the insulator pillar, and the gate electrode; and a gate contact plug embedded in a contact hole provided in the interlayer dielectric film, and in contact with the gate electrode and the insulator pillar. A film thickness of the insulator pillar in a lateral direction is thicker than a film thickness of the gate dielectric film in a lateral direction. | 2011-01-20 |
20110012194 | Multi-die DC-DC Buck Power Converter with Efficient Packaging - A DC-DC buck converter in multi-die package is proposed having an output inductor, a low-side Schottky diode and a high-side vertical MOSFET controlled by a power regulating controller (PRC). The multi-die package includes a first die pad with the Schottky diode placed there on side by side with the vertical MOSFET. The PRC die is attached atop the first die pad via an insulating die bond. Alternatively, the first die pad is grounded. The vertical MOSFET is a top drain N-channel FET, the substrate of Schottky diode die is its anode. The Schottky diode and the vertical MOSFET are stacked atop the first die pad. The PRC is attached atop the first die pad via a conductive die bond. The Schottky diode die can be supplied in a flip-chip configuration with cathode being its substrate. Alternatively, the Schottky diode is supplied with anode being its substrate without the flip-chip configuration. | 2011-01-20 |
20110012195 | SEMICONDUCTOR DEVICE - Between a source electrode ( | 2011-01-20 |
20110012196 | Isolated drain-centric lateral MOSFET - A lateral MOSFET formed in a substrate of a first conductivity type includes a gate formed atop a gate dielectric layer over a surface of the substrate, a drain region of a second conductivity type, a source region of a second conductivity type, and a body region of the first conductivity type which extends under the gate. The body region may have a non-monotonic vertical doping profile with a portion located deeper in the substrate having a higher doping concentration than a portion located shallower in the substrate. The lateral MOSFET is drain-centric, with the source region and a dielectric-filled trench surrounding the drain region. | 2011-01-20 |
20110012197 | METHOD OF FABRICATING TRANSISTORS AND A TRANSISTOR STRUCTURE FOR IMPROVING SHORT CHANNEL EFFECT AND DRAIN INDUCED BARRIER LOWERING - A method of fabricating transistors includes: providing a substrate including an N-type well and P-type well; forming a first gate on the N-type well and a second gate on the P-type well, respectively; forming a third spacer on the first gate; forming an epitaxial layer in the substrate at two sides of the first gate; forming a fourth spacer on the second gate; forming a silicon cap layer covering the surface of the epitaxial layer and the surface of the substrate at two sides of the fourth spacer; and forming a first source/drain doping region and a second source/drain doping region at two sides of the first gate and the second gate respectively. | 2011-01-20 |
20110012198 | SEMICONDUCTOR DEVICE, METHOD FOR MANUFACTURING SEMICONDUCTOR DEVICE, DISPLAY DEVICE, AND METHOD FOR MANUFACTURING DISPLAY DEVICE - A semiconductor device | 2011-01-20 |
20110012199 | SEMICONDUCTOR-ON-INSULATOR WITH BACK SIDE HEAT DISSIPATION - Embodiments of the present invention provide for the dissipation of heat from semiconductor-on-insulator (SOI) structures. In one embodiment, a method for fabricating an integrated circuit is disclosed. In a first step, active circuitry is formed in an active layer of a SOI wafer. In a second step, substrate material is removed from a substrate layer disposed on a back side of the SOI wafer. In a third step, insulator material is removed from the back side of the SOI wafer to form an excavated insulator region. In a fourth step, a thermal dissipation layer is deposited on said excavated insulator region. The thermal dissipation layer is thermally conductive and electrically insulating. | 2011-01-20 |
20110012200 | SUBSTRATE HAVING A CHARGED ZONE IN AN INSULATING BURIED LAYER - Embodiments of the invention relate to substrates comprising a base wafer, an insulating layer and a top semiconductor layer, wherein the insulating layer comprises at least a zone wherein a density of charges is in absolute value higher than 10 | 2011-01-20 |
20110012201 | Semiconductor device having fins FET and manufacturing method thereof - A line-form insulator is formed on a substrate and then the substrate is etched with the insulator used as a mask to form first trenches on both sides of the insulator. Side wall insulators are formed on the side walls of the first trenches, the substrate is etched with the insulator and side wall insulators used as a mask to form second trenches in the bottom of the first trenches. After, the substrate is oxidized with the insulator and side wall insulators used as an anti-oxidation mask to cause oxide regions formed on the adjacent side walls of the second trenches lying on both sides of the substrate to make contact with each other and the insulator and side wall insulators are removed. Then, a fin FET having a semiconductor region as a line-form fin is formed in the substrate. | 2011-01-20 |
20110012202 | Selective Floating Body SRAM Cell - A memory cell has N≧6 transistors, in which two are access transistors, at least one pair [say (N−2)/2] are pull-up transistors, and at least another pair [say (N−2)/2] are pull-down transistors. The pull-up and pull-down transistors are all coupled between the two access transistors. Each of the access transistors and the pull-up transistors are the same type, p-type or n-type. Each of the pull-down transistors is the other type, p-type or n-type. The access transistors are floating body devices. The pull-down transistors are non-floating body devices. The pull-up transistors may be floating or non-floating body devices. Various specific implementations and methods of making the memory cell are also detailed. | 2011-01-20 |
20110012203 | THIN FILM TRANSISTOR PANEL AND FABRICATING METHOD THEREOF - A thin film transistor panel includes; an insulating substrate, a gate line including a gate electrode disposed on the insulating substrate, a gate insulating layer disposed on the gate electrode, a semiconductor layer disposed on the gate insulating layer, the semiconductor layer including a sidewall, a data line including a source electrode disposed on the semiconductor layer, a drain electrode disposed substantially opposite to and spaced apart from the source electrode, a first protective film disposed on the data line, the first protective film including a sidewall, a second protective film disposed on the first protective film and including a sidewall, and a pixel electrode electrically connected to the drain electrode, wherein the sidewall of the second protective film is disposed inside an area where the sidewall of the first protective film is disposed, and the source electrode and the drain electrode cover the sidewall of the semiconductor layer. | 2011-01-20 |
20110012204 | TRIG MODULATION ELECTROSTATIC DISCHARGE (ESD) PROTECTION DEVICES - Trig modulation electrostatic discharge (ESD) protection devices are presented. An ESD protection device includes a semiconductor substrate. A high voltage N-well (HVNW) region is formed in the semiconductor substrate. An NDD region, a first P-body region and a second P-body region are formed in the HVNW region, wherein the first P-body region is separated from the second P-body region with a predetermined distance, and wherein the NDD region is isolated from the first P-body region with an isolation region. An N | 2011-01-20 |
20110012205 | METHOD FOR FABRICATING A METAL GATE STRUCTURE - A metal gate structure is disclosed. The metal gate structure includes: a semiconductor substrate having an active region and an isolation region; an isolation structure disposed in the isolation region; a first gate structure disposed on the active region; and a second gate structure disposed on the isolation structure, wherein the height of the second gate structure is different from the height of the first gate structure. | 2011-01-20 |
20110012206 | SEMICONDUCTOR MEMORY DEVICE - When threshold voltages of constituent transistors are reduced in order to operate an SRAM circuit at a low voltage, there is a problem in that a leakage current of the transistors is increased and, as a result, electric power consumption when the SRAM circuit is not operated while storing data is increased. Therefore, there is provided a technique for reducing the leakage current of MOS transistors in SRAM memory cells MC by controlling a potential of a source line ssl of the driver MOS transistors in the memory cells. | 2011-01-20 |
20110012207 | SEMICONDUCTOR DEVICE AND METHOD FOR MANUFACTURING THE SAME - A semiconductor device includes a PMOS transistor of a peripheral circuit region. The PMOS transistor is formed over a silicon germanium layer to have a compressive strain structure, thereby increasing hole mobility of a channel region in operation of the device. The semiconductor device may include a second active region including a silicon layer connected to a first active region of a semiconductor substrate, a silicon germanium layer formed over the silicon layer expected to be a PMOS region, and a PMOS gate formed over the silicon germanium layer. | 2011-01-20 |
20110012208 | FIELD-EFFECT TRANSISTOR WITH LOCAL SOURCE/DRAIN INSULATION AND ASSOCIATED METHOD OF PRODUCTION - A method for fabricating a field-effect transistor with local source/drain insulation. The method includes forming and patterning a gate stack with a gate layer and a gate dielectric on a semiconductor substrate; forming source and drain depressions at the gate stack in the semiconductor substrate; forming a depression insulation layer at least in a bottom region of the source and drain depressions; and filling the at least partially insulated source and drain depressions with a filling layer for realizing source and drain regions. | 2011-01-20 |
20110012209 | GATE STRUCTURE AND METHOD OF MAKING THE SAME - A method of making a gate structure includes the following steps. First, a gate is formed. Then, a first silicon oxide layer, a silicon nitride layer, and a second silicon oxide layer are formed to cover the gate from bottom to top. Later, a dry etching is performed to etch the second silicon oxide layer. After that, a wet etching is performed to etch the silicon nitride layer and the first silicon oxide layer. The aforesaid wet etching is performed by utilizing an RCA cleaning solution. Furthermore, the silicon nitride layer is formed by the SINGEN process. Therefore, the first and second silicon oxide layer and the silicon nitride layer can be etched together by the RCA cleaning solution. | 2011-01-20 |
20110012210 | Scaling EOT by Eliminating Interfacial Layers from High-K/Metal Gates of MOS Devices - An integrated circuit structure includes a semiconductor substrate, and a phonon-screening layer over the semiconductor substrate. Substantially no silicon oxide interfacial layer exists between the semiconductor substrate and the phonon-screening layer. A high-K dielectric layer is located over the phonon-screening layer. A metal gate layer is located over the high-K dielectric layer. | 2011-01-20 |
20110012211 | SEMICONDUCTOR DEVICE AND METHOD - Disclosed is a semiconductor device comprising a stack of patterned metal layers ( | 2011-01-20 |
20110012212 | MEMS SENSOR AND PRODUCTION METHOD OF MEMS SENSOR - An MEMS sensor of the present invention includes a substrate, a lower thin film provided on a surface of the substrate, an upper thin film opposed to the lower thin film at an interval on the side opposite to the substrate, and a wall portion surrounding the lower thin film and the upper thin film and protruding on the side opposite to the lower thin film with respect to the upper thin film. | 2011-01-20 |
20110012213 | VERTICAL SENSOR ASSEMBLY METHOD - A method to vertically bond a chip to a substrate is provided. The method includes forming a metal bar having a linear aspect on the substrate, forming a solder paste layer over the metal bar to form a solder bar, forming a plurality of metal pads on the substrate, and forming a solder paste layer over the plurality of metal pads to form a plurality of solder pads on the substrate. Each of the plurality of solder pads is offset from a long edge the solder bar by an offset-spacing. The chip to be vertically bonded to the substrate has a vertical-chip thickness fractionally less than the offset-spacing. The chip to be vertically bonded fits between the plurality of solder pads and the solder bar. The solder bar enables alignment of the chip to be vertically bonded. | 2011-01-20 |
20110012214 | MICROELECTROMECHANICAL SEMICONDUCTOR COMPONENT WITH CAVITY STRUCTURE AND METHOD FOR PRODUCING THE SAME - One aspect of the invention relates to a semiconductor component with cavity structure and a method for producing the same. The semiconductor component has an active semiconductor chip with the microelectromechanical structure and a wiring structure on its top side. The microelectromechanical structure is surrounded by walls of at least one cavity. A covering, which covers the cavity, is arranged on the walls. The walls have a photolithographically patterned polymer. The covering has a layer with a polymer of identical type. In one case, the molecular chains of the polymer of the walls are crosslinked with the molecular chains of the polymer layer of the covering layer to form a dimensionally stable cavity housing. | 2011-01-20 |