03rd week of 2013 patent applcation highlights part 34 |
Patent application number | Title | Published |
20130017612 | pH-Sensitive Microparticles with Matrix-Dispersed Active Agent - Methods to produce pH-sensitive microparticles that have an active agent dispersed in a polymer matrix have certain advantages over microcapsules with an active agent encapsulated in an interior compartment/core inside of a polymer wall. The current invention relates to pH-sensitive microparticles that have a corrosion-detecting or corrosion-inhibiting active agent or active agents dispersed within a polymer matrix of the microparticles. The pH-sensitive microparticles can be used in various coating compositions on metal objects for corrosion detecting and/or inhibiting. | 2013-01-17 |
20130017613 | METHOD AND APPARATUS FOR EXTRACTION OF STRONTIUM FROM URINEAANM KAMINSKI; Michael D.AACI LockportAAST ILAACO USAAGP KAMINSKI; Michael D. Lockport IL USAANM MERTZ; Carol J.AACI Downers GroveAAST ILAACO USAAGP MERTZ; Carol J. Downers Grove IL USAANM SHKROB; Ilya A.AACI ChicagoAAST ILAACO USAAGP SHKROB; Ilya A. Chicago IL USAANM DIETZ; Mark L.AACI EvanstonAAST ILAACO USAAGP DIETZ; Mark L. Evanston IL USAANM HAWKINS; Cory A.AACI ShorewoodAAST WIAACO USAAGP HAWKINS; Cory A. Shorewood WI US - The present invention provides an apparatus and rapid methods for extracting strontium ions from urine to provide a concentrated and purified strontium-90 extract suitable for scintillation measurements. The methods remove organic compounds, pigments, and alkali metal ions that can interfere with quantitative determination of strontium-90 in urine. A method of the invention comprises acidifying urine and removing organic pigments therefrom, loading a known quantity of so-treated urine onto a diphosphonic acid-based ion-exchange resin; flowing aqueous methanesulfonic acid through the diphosphonic acid-based ion-exchange resin to elute alkali metal ions therefrom; eluting strontium ions off of the diphosphonic acid-based resin and on to a strontium extraction chromatographic resin with a concentrated aqueous nitric acid solution; subsequently flowing water or a dilute acid stripping solution through the strontium extraction resin to strip the strontium from the strontium extraction resin; and collecting the strontium-containing stripping solution eluting from the strontium extraction resin. | 2013-01-17 |
20130017614 | METHODS AND KIT FOR ENDOMETRIOSIS DIAGNOSIS - An endometriosis diagnostic in which a biological sample of a female mammal having had a menstrual cycle within 90 days of the biological sample having been obtained from the female mammal is subjected to an in vitro diagnostic procedure in which the biological sample is contacted with an apatite compound for an effective time to provide a responsive visual appearance. Based on the visual appearance, a determination is made whether the female mammal has endometriosis. | 2013-01-17 |
20130017615 | PEPTIDE PROBE FOR RAPID AND SPECIFIC DETECTION OF AMYLOID AGGREGATION - A method for use of a peptide probe that generates fluorescence signals rapidly upon recognition of various Aβ aggregates without significant perturbation of samples. The present peptide probes display an increase in fluorescence signals upon coincubation with Aβ oligomers, but neither monomeric/dimeric species nor fibrils. The detection can occur within an hour or two without any additional sample preparation and incubation steps. | 2013-01-17 |
20130017616 | Methods For Treating Inflammation - The present invention provides methods for treating or limiting development of inflammatory disorders. | 2013-01-17 |
20130017617 | Incorporation of Chemochromic Pigment into a Variety of Articles as an Indicator for the Presence of Hypergolic Fuels - A chemochromic indicator is provided that includes a hypergolic fuel sensing chemochromic pigment that change from a first color to a second color in the presence of a hypergolic fuel. In a first embodiment, a chemochromic indicator is provided for detecting the presence of a hypergolic fuel such that the irreversible hypergolic fuel sensing chemochromic pigment includes potassium tetrachloroaurate (KAuCl | 2013-01-17 |
20130017618 | CHEMICAL EXPLOSIVE DETECTOR - A method and device for detecting explosive compounds in an air sample in which the air sample is filtered with activated carbon treated with a weakly basic solution, after which the air sample is divided into two parts, with one part being heated at lower temperatures to decompose non-explosive nitrogenous compounds and the second part being heated at higher temperatures to decompose explosive nitrogenous compounds. Nitrogen dioxide is measured in both portions of the air sample with a spectrographic detector, and the presence or absence of explosive nitrogenous compounds in the air sample is determined. | 2013-01-17 |
20130017619 | ANIONIC SURFACTANT DETECTION - Disclosed herein are methods for the detection and/or quantification of anionic surfactants. Also disclosed herein are test kits, which utilize the disclosed methods, to estimate the anionic surfactant concentration in samples, such as environmentally-derived samples. In some specific embodiments, the method and the test kit may be used to detect, among other things, aqueous film forming foams that comprise anionic surfactants. | 2013-01-17 |
20130017620 | All-In-One Sample Preparation Device And Method - Sample preparation device that allows for a complete bind, wash, elute, buffer-exchange and concentration process to be carried out without sample transfer between multiple devices. The device includes a reservoir, a column for holding chromatography media, a holder region for holding a filtration device, and an outlet. The filtration device plugs into the holder region of the centrifugal device, and the assembly can be placed in an optional holder. The assembly, with or without the optional holder, can be placed in a conventional centrifuge tube for centrifugation. The entire bind, wash, elute, buffer exchange and concentration steps can be carried out with the apparatus without any pipette transfers (and the associated sample losses. The sample preparation device also can be used for binding and washing steps, in which case the filtration device is not needed, and for buffer exchange and concentration steps, in which case the media is not needed. | 2013-01-17 |
20130017621 | METHODS AND SYSTEMS PROVIDING REAGENT MIXING - Disclosed are methods and systems adapted to provide mixing of a liquid reagent in an automated clinical analyzer. The methods include aspirating an air separator (e.g., an air slug) into the interior of a probe. A relatively small volume of reagent liquid is also aspirated into the probe adjacent to the air separator; the volume of liquid reagent being entirely contained within the probe. The volume of liquid reagent may be repeatedly aspirated and dispensed at a relatively high frequency to accomplish reagent mixing in the reagent container. Improved sample and reagent mixing may be promoted using a similar method. Systems carrying out the methods are provided, as are other aspects. | 2013-01-17 |
20130017622 | METHOD AND SYSTEM FOR ANALYTE MONITORING USING SURFACE PLASMONS WITH A REFRESHABLE SURFACEAANM Rahn; John RichardAACI SammamishAAST WAAACO USAAGP Rahn; John Richard Sammamish WA US - The present technology provides an illustrative method for analyte monitoring using surface plasmons with a refreshable surface. The method includes placing a solution to be monitored in contact with a working surface of a surface plasmon resonance (SPR) generation system. The working surface includes a metal surface disposed on a glass surface, and the metal surface includes a first binding substance that provides binding sites for an analyte. The method further includes applying light to the metal surface at a plurality of angles over a period of time, measuring a reflectance of the light at each of the plurality of angles to determine an SPR angle, and monitoring changes to the SPR angle over the period of time. The working surface of the SPR generation system is refreshed by depositing a new layer of the first binding substance on the working surface of the SPR generation system. | 2013-01-17 |
20130017623 | Fluid sample collecting and analyzing apparatus and method - A spongy swab ( | 2013-01-17 |
20130017624 | METHOD FOR DETERMINATION OF BINDING STOICHIOMETRYAANM Karlsson; RobertAACI UppsalaAACO SEAAGP Karlsson; Robert Uppsala SE - A method is provided for determining binding stoichiometry for the interaction between a first molecule and a second molecule forming a complex between them. Either (i) a solution having a fixed initial active concentration of the first molecule is titrated with solutions of varying active concentrations of the second molecule, and the free active concentrations of the second molecule are measured; or (ii) a solution with fixed initial concentrations of the first molecule and the second molecule is incubated, and the free active concentrations of both molecules are measured. In the first case, the binding stoichiometry can be determined from the initial concentration values of both molecules and the free concentration value(s) of the second molecule at saturation; and in the second case from the initial concentration values of both molecules and the free concentration values of both molecules. Active concentration measurements are typically performed by an interaction analysis sensor, using a calibration-free analytical format at least for the determination of active initial concentrations. | 2013-01-17 |
20130017625 | SEMICONDUCTOR FABRICATING DEVICE AND METHOD FOR DRIVING THE SAME, AND METHOD FOR FABRICATING MAGNETIC TUNNEL JUNCTION USING THE SAMEAANM CHOI; Won JoonAACI SeoulAACO KRAAGP CHOI; Won Joon Seoul KR - In a method for fabricating a magnetic tunnel junction, a first magnetic layer is formed on a substrate, and a tunnel insulating layer is formed on the first magnetic layer. Subsequently, a second magnetic layer is formed on the tunnel insulating layer. In the method, the first magnetic layer is formed by periodically sputtering a magnetic target while a metal target is continuously sputtered. | 2013-01-17 |
20130017626 | ETCHING APPARATUS AND METHOD OF MANUFACTURING SEMICONDUCTOR DEVICEAANM TOMIOKA; KazuhiroAACI Yokohama-shiAACO JPAAGP TOMIOKA; Kazuhiro Yokohama-shi JP - According to one embodiment, an etching apparatus includes a stage having an upper surface and a lower surface, and being capable of mounting a substrate on the upper surface, a chamber covering above the upper surface, a lower electrode having an opening portion, and provided under the lower surface, a gas supplying portion supplying an etching gas in the chamber, a high-frequency power source portion executing a plasma gasification of the etching gas by applying a high-frequency to the lower electrode, a micro wave generating portion setting a temperature of the substrate within an optimum range by applying a micro wave to the substrate through the opening portion, and a control portion controlling the gas supplying portion, the high-frequency power source portion and the micro wave generating portion. | 2013-01-17 |
20130017627 | Embedded Magnetic Random Access Memory (MRAM) - A magnetic random access memory (MRAM) cell includes an embedded MRAM and an access transistor. The embedded MRAM is formed on a number of metal-interposed-in-interlayer dielectric (ILD) layers, which each include metal dispersed therethrough and are formed on top of the access transistor. An magneto tunnel junction (MTJ) is formed on top of a metal formed in the ILD layers that is in close proximity to a bit line. An MTJ mask is used to pattern the MTJ and is etched to expose the MTJ. Ultimately, metal is formed on top of the bit line and extended to contact the MTJ. | 2013-01-17 |
20130017628 | TEMPERATURE DETECTING APPARATUS, SUBSTRATE PROCESSING APPARATUS AND METHOD OF MANUFACTURING SEMICONDUCTOR DEVICEAANM KOSUGI; TetsuyaAACI ToyamaAACO JPAAGP KOSUGI; Tetsuya Toyama JPAANM UENO; MasaakiAACI ToyamaAACO JPAAGP UENO; Masaaki Toyama JPAANM YAMAGUCHI; HidetoAACI ToyamaAACO JPAAGP YAMAGUCHI; Hideto Toyama JP - A temperature detecting apparatus is provided which is capable of suppressing disconnection of a thermocouple wire or positional deviation of a thermocouple junction portion caused by change over time. The temperature detecting apparatus includes: an insulation rod installed to extend in a vertical direction and including a through-hole in vertical direction; a thermocouple wire inserted in the through-hole of the insulation rod, the thermocouple wire including a thermocouple junction portion at an upper end thereof and an angled portion at a lower end of the insulation rod; and a buffer area installed below the insulation rod and configured to suppress a restriction of a horizontal portion of the angled portion upon heat expansion, wherein an upper portion of the thermocouple wire or a middle portion in the vertical direction are supported by the insulation rod. | 2013-01-17 |
20130017629 | METHODS OF MANUFACTURING THREE-DIMENSIONAL SEMICONDUCTOR DEVICESAANM Pyo; MyungjungAACI Hwaseong-siAACO KRAAGP Pyo; Myungjung Hwaseong-si KRAANM Kim; Hyo-JungAACI SeoulAACO KRAAGP Kim; Hyo-Jung Seoul KRAANM Lim; JongHeunAACI Hwaseong-siAACO KRAAGP Lim; JongHeun Hwaseong-si KRAANM Kim; KyunghyunAACI SeoulAACO KRAAGP Kim; Kyunghyun Seoul KRAANM Yoon; ByoungmoonAACI Suwon-siAACO KRAAGP Yoon; Byoungmoon Suwon-si KRAANM Han; JaHyungAACI Suwon-siAACO KRAAGP Han; JaHyung Suwon-si KR - According to example embodiments, a methods includes forming a peripheral structure including peripheral circuits on a peripheral circuits region of a substrate, recessing a cell array region of the substrate to form a concave region having a bottom surface lower than a top surface of the peripheral structure, forming a stacked layer structure conformally covering the concave region, the stacked layer structure including a plurality of layers sequentially stacked and having a lowest top surface in the cell array region and a highest top surface in the peripheral circuits region, forming a planarization stop layer that conformally covers the stacked layer structure, and planarizing the stacked layer structure using the planarization stop layer in the cell array region as a planarization end point to expose top surfaces of the thin layers between the cell array region and the peripheral circuits region simultaneously with a top surface of the peripheral structure. | 2013-01-17 |
20130017630 | CRYSTALLIZATION APPARATUS, CRYSTALLIZATION METHOD, METHOD OF MANUFACTURING THIN FILM TRANSISTOR AND METHOD OF MANUFACTURING ORGANIC LIGHT EMITTING DISPLAY APPARATUS - Provided are a crystallization apparatus and method, which prevent cracks from being generated, a method of manufacturing a thin film transistor (TFT), and a method of manufacturing an organic light emitting display apparatus. The crystallization apparatus includes a chamber for receiving a substrate, a first flash lamp and a second flash lamp, which are disposed facing each other within the chamber, wherein amorphous silicon layers are disposed on a first surface of the substrate facing the first flash lamp and a second surface of the substrate facing the second flash lamp, respectively. | 2013-01-17 |
20130017631 | METHOD OF MANUFACTURING LIGHT-EMITTING DEVICEAANM TAKEDA; ShigeoAACI Kiyosu-shiAACO JPAAGP TAKEDA; Shigeo Kiyosu-shi JPAANM ISHIDA; MakotoAACI Kiyosu-shiAACO JPAAGP ISHIDA; Makoto Kiyosu-shi JPAANM TERAKAMI; MitsushiAACI Kiyosu-shiAACO JPAAGP TERAKAMI; Mitsushi Kiyosu-shi JPAANM YAMAMORI; ShotaAACI Kiyosu-shiAACO JPAAGP YAMAMORI; Shota Kiyosu-shi JP - A method of manufacturing a light-emitting device includes providing a plate-shaped substrate, forming a lattice frame on a light-emitting element mounting surface of the plate-shaped substrate, mounting a light-emitting device in an opening of the lattice frame on the light-emitting element mounting surface, sealing the light-emitting element by supplying a sealing material into the opening of the lattice frame, and cutting the lattice frame and the plate-shaped substrate so as to split the lattice flame to obtain a plurality of light-emitting devices with a sidewall. | 2013-01-17 |
20130017632 | METHOD FOR MANUFACTURING LIGHT EMITTING DIODEAANM CHEN; PIN-CHUANAACI HukouAACO TWAAGP CHEN; PIN-CHUAN Hukou TW - A method for manufacturing LEDs (light emitting diodes) includes steps: providing a substrate; attaching an adhesive layer on the substrate; forming a blocking layer on the adhesive layer, the blocking layer having a plurality of first holes and second holes alternating with and spaced from the first holes; forming a conductive layer including first leads and second leads in the first holes and the second holes; removing the blocking layer; forming a housing layer on the adhesive layer, the housing layer having a plurality of cavities to expose the first leads and second leads; fixing chips on the first leads and electrically connecting the chips with the first and second leads; forming encapsulants in the cavities to seal the chips; and removing the substrate and adhesive layer from the housing layer and the conductive layer. | 2013-01-17 |
20130017633 | VAPOR DEPOSITION APPARATUS AND METHOD, AND METHOD OF MANUFACTURING ORGANIC LIGHT EMITTING DISPLAY APPARATUSAANM Seo; Sang-JoonAACI Yongin-cityAACO KRAAGP Seo; Sang-Joon Yongin-city KRAANM Kim; Seung-HunAACI Yongin-cityAACO KRAAGP Kim; Seung-Hun Yongin-city KRAANM Kim; Jin-KwangAACI Yongin-cityAACO KRAAGP Kim; Jin-Kwang Yongin-city KRAANM Song; Seung-YongAACI Yongin-cityAACO KRAAGP Song; Seung-Yong Yongin-city KR - A vapor deposition apparatus, which is capable of performing a thin film deposition process and improving characteristics of a formed thin film, includes a chamber having an exhaust opening; a stage located in the chamber, and including a plurality of mounting surfaces on which the plurality of substrates may be mounted; and an injection unit having at least one injection opening for injecting a gas into the chamber in a direction parallel with surfaces of the plurality of substrates. | 2013-01-17 |
20130017634 | WAVELENGTH CONVERTING LIGHT-EMITTING DEVICES AND METHODS OF MAKING THE SAME - Wavelength converting light-emitting devices and methods of making the same are provided. In some embodiments, the devices include a phosphor material region designed to convert the wavelength of emitted light. | 2013-01-17 |
20130017635 | Techniques of Forming Ohmic Contacts on GaN Light Emitting Diodes - A method of forming ohmic contacts on a light emitting diode that features a surface treatment of a substrate includes exposing a surface of a p-type gallium nitride layer to an acid-containing solution and a buffered oxide etch process. A quantum well is formed in a gallium nitride substrate and a layer of p-type gallium nitride is deposited over the quantum well. The surface of the p-type gallium nitride is exposed to an acid-containing solution and then a buffered oxide etch process is performed to provide an etched surface. A metal stack including a layer of silver disposed between layers of platinum is then deposited. | 2013-01-17 |
20130017636 | COMPOSITION FOR REMOVING A PHOTORESIST AND METHOD OF MANUFACTURING A THIN-FILM TRANSISTOR SUBSTRATE USING THE COMPOSITIONAANM KIM; Bong-KyunAACI Hwaseong-siAACO KRAAGP KIM; Bong-Kyun Hwaseong-si KRAANM CHOI; Shin-IlAACI Hwaseong-siAACO KRAAGP CHOI; Shin-Il Hwaseong-si KRAANM PARK; Hong-SickAACI Suwon-siAACO KRAAGP PARK; Hong-Sick Suwon-si KRAANM LEE; Wang-WooAACI Suwon-siAACO KRAAGP LEE; Wang-Woo Suwon-si KRAANM JANG; Seok-JunAACI Asan-siAACO KRAAGP JANG; Seok-Jun Asan-si KRAANM KIM; Byung-UkAACI Hwaseong-siAACO KRAAGP KIM; Byung-Uk Hwaseong-si KRAANM PARK; Sun-JooAACI Pyeongtaek-siAACO KRAAGP PARK; Sun-Joo Pyeongtaek-si KRAANM YOON; Suk-IlAACI Suwon-siAACO KRAAGP YOON; Suk-Il Suwon-si KRAANM JEONG; Jong-HyunAACI SeoulAACO KRAAGP JEONG; Jong-Hyun Seoul KRAANM HUR; Soon-BeomAACI Anyang-siAACO KRAAGP HUR; Soon-Beom Anyang-si KR - A composition for removing a photoresist, the composition including about 1% by weight to about 10% by weight of tetramethyl ammonium hydroxide (“TMAH”), about 1% by weight to about 10% by weight of an alkanol amine, about 50% by weight to about 70% by weight of a glycol ether compound, about 0.01% by weight to about 1% by weight of a triazole compound, about 20% by weight to about 40% by weight of a polar solvent, and water, each based on a total weight of the composition. | 2013-01-17 |
20130017637 | METHOD FOR FORMING PATTERN AND METHOD FOR MANUFACTURING DISPLAY DEVICE BY USING THE SAMEAANM JEON; Woo-SeokAACI SeoulAACO KRAAGP JEON; Woo-Seok Seoul KRAANM LEE; Jong KwangAACI DaejeonAACO KRAAGP LEE; Jong Kwang Daejeon KRAANM JU; Jin HoAACI SeoulAACO KRAAGP JU; Jin Ho Seoul KRAANM KANG; MinAACI SeoulAACO KRAAGP KANG; Min Seoul KRAANM KANG; HoonAACI Suwon-siAACO KRAAGP KANG; Hoon Suwon-si KRAANM SHIM; Seung BoAACI Asan-siAACO KRAAGP SHIM; Seung Bo Asan-si KRAANM PARK; Gwui-HyunAACI Osan-siAACO KRAAGP PARK; Gwui-Hyun Osan-si KRAANM KIM; Bong-YeonAACI SeoulAACO KRAAGP KIM; Bong-Yeon Seoul KR - A method for forming a fine exposure pattern where a width and an interval of the pattern are each 1CD, by first exposing a photoresist by using an exposure mask where an interval ratio of a light shielding part and a light transmission part is 2CD:1CD to 4CD:1CD, and then second exposing the photoresist after the exposure mask is shifted at a predetermined interval, or second exposing the photoresist by using an exposure mask formed at a position where a light transmission part is shifted at a predetermined interval, and developing the photoresist, such that it is possible to form a display device having a pixel electrode including a plurality of fine branch electrodes having a smaller width and interval than a resolution of an exposure apparatus. | 2013-01-17 |
20130017638 | PROCESS FOR MANUFACTURING BURIED HETERO-STRUCTURE LASER DIODESAANM TSUJI; YukihiroAACI Yokohama-shiAACO JPAAGP TSUJI; Yukihiro Yokohama-shi JP - A process for manufacturing buried hetero-structure laser diodes includes the steps of forming a stacked semiconductor layer on a substrate; forming a mask layer on the stacked semiconductor layer; forming a semiconductor mesa by etching the stacked semiconductor layer through the mask layer; forming an overhang of the mask layer by selectively etching the stacked semiconductor layer of the semiconductor mesa; selectively growing a buried layer on a side surface of the semiconductor mesa while leaving the mask layer on the semiconductor mesa; forming a lateral portion of the buried layer, the lateral portion having a side surface adjacent to the side surface of the semiconductor mesa; after forming the lateral portion of the buried layer, removing the mask layer on the semiconductor mesa; and forming an electrode on a top surface of the semiconductor mesa and on the side surface of the lateral portion of the buried layer. | 2013-01-17 |
20130017639 | METHOD FOR PRODUCING A GROUP III NITRIDE SEMICONDUCTOR LIGHT-EMITTING DEVICEAANM BOYAMA; ShinyaAACI Kiyosu-shiAACO JPAAGP BOYAMA; Shinya Kiyosu-shi JPAANM Ushida; YasuhisaAACI Kiyosu-shiAACO JPAAGP Ushida; Yasuhisa Kiyosu-shi JP - The present invention is a method for producing a light- emitting device whose p contact layer has a p-type conduction and a reduced contact resistance with an electrode. On a p cladding layer, by MOCVD, a first p contact layer of GaN doped with Mg is formed. Subsequently, after lowering the temperature to a growth temperature of a second p contact layer being formed in the subsequent process, which is 700° C., the supply of ammonia is stopped and the carrier gas is switched from hydrogen to nitrogen. Thereby, Mg is activated in the first p contact layer, and the first p contact layer has a p-type conduction. Next, the second p contact layer of InGaN doped with Mg is formed on the first p contact layer by MOCVD using nitrogen as a carrier gas while maintaining the temperature at 700° C. which is the temperature of the previous process. | 2013-01-17 |
20130017640 | METHOD OF PROCESSING OPTICAL DEVICE WAFERAANM Morikazu; HiroshiAACI Ota-KuAACO JPAAGP Morikazu; Hiroshi Ota-Ku JPAANM Nishino; YokoAACI Ota-kuAACO JPAAGP Nishino; Yoko Ota-ku JP - A method of processing an optical device wafer having an optical device layer including an n-type semiconductor layer and a p-type semiconductor layer stacked over a sapphire substrate, a buffer layer therebetween, allowing peeling of the sapphire substrate. The method includes joining a transfer substrate to the optical device layer, breaking the buffer layer by irradiation with a pulsed laser beam from the sapphire substrate side of the wafer with the transfer substrate joined to the optical device layer, and peeling the sapphire substrate from the optical device wafer with the buffer layer broken, transferring the optical device layer onto the transfer substrate. The pulsed laser beam has a wavelength longer than an absorption edge of the sapphire substrate and shorter than an absorption edge of the buffer layer, and a pulse width set so that a thermal diffusion length will be not more than 200 nm. | 2013-01-17 |
20130017641 | METHOD FOR MANUFACTURING A LIGHT-EMITTING DEVICEAANM Goda; TadashiAACI Tsukuba-shiAACO JPAAGP Goda; Tadashi Tsukuba-shi JP - Provided is a method for manufacturing a light-emitting device ( | 2013-01-17 |
20130017642 | CHEMICALLY-SENSITIVE FIELD EFFECT TRANSISTOR BASED PIXEL ARRAY WITH PROTECTION DIODES - Methods and apparatus relating to FET arrays for monitoring chemical and/or biological reactions such as nucleic acid sequencing-by-synthesis reactions. Some methods provided herein relate to improving signal (and also signal to noise ratio) from released hydrogen ions during nucleic acid sequencing reactions. | 2013-01-17 |
20130017643 | METHOD FOR FABRICATING PACKAGE STRUCTURE HAVING MEMS ELEMENTSAANM LIN; Chen-HanAACI Taichung HsienAACO TWAAGP LIN; Chen-Han Taichung Hsien TWAANM CHANG; Hong-DaAACI Taichung HsienAACO TWAAGP CHANG; Hong-Da Taichung Hsien TWAANM LIU; Cheng-HsiangAACI Taichung HsienAACO TWAAGP LIU; Cheng-Hsiang Taichung Hsien TWAANM LIAO; Hsin-YiAACI Taichung HsienAACO TWAAGP LIAO; Hsin-Yi Taichung Hsien TWAANM CHIU; Shih-KuangAACI Taichung HsienAACO TWAAGP CHIU; Shih-Kuang Taichung Hsien TW - A fabrication method of a package structure having MEMS elements includes: disposing a plate on top of a wafer having MEMS elements and second alignment keys; cutting the plate to form therein a plurality of openings exposing the second alignment keys; performing a wire bonding process and disposing block bodies corresponding to the second alignment keys, respectively; forming an encapsulant and partially removing the encapsulant and the block bodies from the top of the encapsulant; and aligning through the second alignment keys so as to form on the encapsulant a plurality of metal traces. The present invention eliminates the need to form through holes in a silicon substrate as in the prior art so as to reduce the fabrication costs. Further, since the plate only covers the MEMS elements and the encapsulant is partially removed, the overall thickness and size of the package structure are reduced. | 2013-01-17 |
20130017644 | Fluorine Based Chamber Clean With Nitrogen Trifluoride Backup - The present invention is a process for cleaning a reaction chamber comprising the steps of;
| 2013-01-17 |
20130017645 | PHOTOELECTRIC CONVERSION DEVICE AND METHOD OF PRODUCING THE SAME - A photoelectric conversion device which can improve photoelectric conversion efficiency is provided. The photoelectric conversion device has at least one p-i-n type photoelectric conversion part which includes a first conductivity type layer, a first i-type layer, a second i-type layer and a second conductivity type layer stacked in this order, and it is characterized in that a crystallization ratio of the first i-type layer is lower than that of the second i-type layer and a change rate of a crystallization ratio in a film-thickness direction at an interface between the first i-type layer and the second i-type layer is 0.013 to 0.24 nm | 2013-01-17 |
20130017646 | METHOD OF MANUFACTURING IMAGE SENSOR HAVING BACKSIDE ILLUMINATION STRUCTUREAANM KIM; Sang-hoonAACI Seongnam-siAACO KRAAGP KIM; Sang-hoon Seongnam-si KRAANM PARK; Byung-junAACI Yongin-siAACO KRAAGP PARK; Byung-jun Yongin-si KRAANM AN; Hee-chulAACI Yongin-siAACO KRAAGP AN; Hee-chul Yongin-si KR - A method of manufacturing an image sensor having a backside illumination (BSI) structure includes forming a wiring unit on a front side of a semiconductor substrate, forming an anti-reflective layer in an active pixel sensor (APS) region on a back side of the semiconductor substrate, a photodiode being between the back and front sides of the semiconductor substrate, forming an etch stopping layer on the anti-reflective layer, forming an interlayer insulating layer on the etch stopping layer, the interlayer insulating layer having an etch selectivity with respect to the etch stopping layer, and etching the interlayer insulating layer in the APS region using the etch stopping layer as an etch stopping point. | 2013-01-17 |
20130017647 | SURFACE-MODIFIED NANOPARTICLE INK FOR PHOTOVOLTAIC APPLICATIONS - Described herein is a novel material that easily penetrates silicon nitride-based anti-reflective coatings, forming a high quality electrical contact. A method for metallization on a solar cell includes depositing a passivation layer on a silicon substrate of a solar cell, depositing derivatized metal particles onto the passive layer, heating the substrate of the solar cell to migrate surface coatings from the derivatized metal particles onto the passivation layer creating a diffusion Channel through passivation layer to the silicon substrate, and as the metal particles melt due to the heating on the substrate, the melted metal diffuses through the diffusion channel forming a metallic content with the silicon substrate. | 2013-01-17 |
20130017648 | METHODS OF MANUFACTURING THIN FILM TRANSISTOR DEVICES - Embodiments of the disclosure provide methods of fabricating a thin film transistor device with good profile control of peripheral sidewall of an active layer formed in the thin film transistor devices. In one embodiment, a method for manufacturing a thin film transistor device includes providing a substrate having a source-drain metal electrode layer disposed on an active layer formed thereon, wherein the active layer is a metal oxide layer, performing a back-channel-etching process to form a channel in the source-drain metal electrode layer, and performing an active layer patterning process after the back-channel-etching process. | 2013-01-17 |
20130017649 | PACKAGING FOR CLIP-ASSEMBLED ELECTRONIC COMPONENTSAANM Touzet; DominiqueAACI Savigne Sous le LudeAACO FRAAGP Touzet; Dominique Savigne Sous le Lude FRAANM Coirault; PascalAACI Ballan-MireAACO FRAAGP Coirault; Pascal Ballan-Mire FR - A system for assembling electronic chips in a package, including a first lead frame defining chip reception areas; and a second lead frame defining chip coverage areas, the frames including, at least at their periphery, pairs of mutually-cooperating elements for maintaining the frames together. | 2013-01-17 |
20130017650 | COATING FOR A MICROELECTRONIC DEVICE, TREATMENT COMPRISING SAME,AND METHOD OF MANAGING A THERMAL PROFILE OF A MICROELECTRONIC DIE - A coating for a microelectronic device comprises a polymer film ( | 2013-01-17 |
20130017651 | METHOD FOR MANUFACTURING A SEMICONDUCTOR PACKAGEAANM Standing; MartinAACI VillachAACO ATAAGP Standing; Martin Villach ATAANM Ganitzer; PaulAACI VillachAACO ATAAGP Ganitzer; Paul Villach AT - A method for manufacturing a semiconductor package, the method comprising providing a substrate having opposite first and second surfaces and having one or more through openings formed therethrough from the first to the second surfaces at predefined positions; providing at least one first die having first and second opposite surfaces and having one or more first contact terminals on the first surface of the at least one first die; placing the at least one first die with the first surface thereof on the first surface of the substrate, with an adhesive applied therebetween outside the one or more through openings, such that the one or more through openings are aligned to the one or more first contact terminals, whereby a die assembly having correspondingly opposite first and second surfaces is formed; providing the first surface of the die assembly with a first plating layer of an electrically conductive plating material to electrically contact the one or more first contact terminals, wherein the plating material of the first plating layer extends in the through openings to electrically contact the one or more first contact terminals therethrough. | 2013-01-17 |
20130017652 | METHOD OF MANUFACTURING A SEMICONDUCTOR DEVICE PACKAGE WITH A HEATSINK - Embodiments of the present invention relate to forming semiconductor device package with a heat sink. In one embodiment, a subassembly comprising a die attached to a lead frame is formed, a heat sink is provided in a molding cavity, and the subassembly is coupled to the heat sink while the heat sink is in the molding cavity. In certain embodiments, a second component of the lead frame can be substituted for the heat sink. Such techniques can simplify the manufacturing process for semiconductor packages having a heat sink or lead frame with a second component. | 2013-01-17 |
20130017653 | Integrated Antennas in Wafer Level Package - A semiconductor module comprises components in one wafer level package. The module comprises an integrated circuit (IC) chip embedded within a package molding compound. The package comprises a molding compound package layer coupled to an interface layer for integrating an antenna structure and a bonding interconnect structure to the IC chip. The bonding interconnect structure comprises three dimensional interconnects. The antenna structure and bonding interconnect structure are coupled to the IC chip and integrated within the interface layer in the same wafer fabrication process. | 2013-01-17 |
20130017654 | FABRICATION METHOD FOR SURROUNDING GATE SILICON NANOWIRE TRANSISTOR WITH AIR AS SPACERSAANM Huang; RuAACI BeijingAACO CNAAGP Huang; Ru Beijing CNAANM Zhuge; JingAACI BeijingAACO CNAAGP Zhuge; Jing Beijing CNAANM Fan; JiewenAACI BeijingAACO CNAAGP Fan; Jiewen Beijing CNAANM Ai; YujieAACI BeijingAACO CNAAGP Ai; Yujie Beijing CNAANM Wang; RunshengAACI BeijingAACO CNAAGP Wang; Runsheng Beijing CNAANM Huang; XinAACI BeijingAACO CNAAGP Huang; Xin Beijing CN - The invention discloses a fabrication method for a surrounding gate silicon nanowire transistor with air as spacers. The method comprises: performing isolation, and depositing a material A which has a higher etch selectivity ratio with respect to Si; performing photolithography to define a Fin hard mask; etching the material A to form the Fin hard mask; performing source and drain implantation; performing photolithography to define a channel region and large source/drain regions; forming the Si Fin and the large source/drains; removing the hard mask of the material A; forming a nanowire; etching the SiO | 2013-01-17 |
20130017655 | DEVICES WITH NANOCRYSTALS AND METHODS OF FORMATION - Devices can be fabricated using a method of growing nanoscale structures on a semiconductor substrate. According to various embodiments, nucleation sites can be created on a surface of the substrate. The creation of the nucleation sites may include implanting ions with an energy and a dose selected to provide a controllable distribution of the nucleation sites across the surface of the substrate. Nanoscale structures may be grown using the controllable distribution of nucleation sites to seed the growth of the nanoscale structures. According to various embodiments, the nanoscale structures may include at least one of nanocrystals, nanowires, or nanotubes. According to various nanocrystal embodiments, the nanocrystals can be positioned within a gate stack and function as a floating gate for a nonvolatile device. Other embodiments are provided herein. | 2013-01-17 |
20130017656 | METHOD OF FABRICATING A SEMICONDUCTOR DEVICEAANM Wei; QingsongAACI BeijingAACO CNAAGP Wei; Qingsong Beijing CNAANM Lu; WeiAACI BeijingAACO CNAAGP Lu; Wei Beijing CNAANM Liu; WupingAACI BeijingAACO CNAAGP Liu; Wuping Beijing CNAANM He; YonggenAACI BeijingAACO CNAAGP He; Yonggen Beijing CN - A method of fabricating semiconductor device is provided. First, a recess having a substantially rectangular cross section is formed in a substrate. Then, oxide layers are formed on sidewalls and bottom of the recess by oxygen ion implantation process, wherein oxide layer on sidewalls of recess is thinner than oxide layer on bottom of recess. Thereafter, oxide layer on sidewalls of recess is completely removed, and only a portion of oxide layer on bottom of recess remains. Then, sidewalls of recess are shaped into Σ form by orientation selective wet etching using oxide layer remained on bottom of recess as a stop layer. Finally, oxide layer on bottom of recess is removed. By forming oxide layer on bottom of recess and using it as stop layer in subsequent orientation selective wet etching, the disclosed method can prevent a Σ-shaped recess with a cuspate bottom. | 2013-01-17 |
20130017657 | METHOD OF MANUFACTURING POWER DEVICEAANM LEE; Jae HoonAACI Suwon-siAACO KRAAGP LEE; Jae Hoon Suwon-si KR - A power device manufacturing method is provided. The power device manufacturing method may perform patterning of regions on which a source electrode and a drain electrode are to be formed, may regrow n | 2013-01-17 |
20130017658 | Method for Fabricating a MOS Transistor with Reduced Channel Length Variation - According to an exemplary embodiment, a method for fabricating a MOS transistor, such as an LDMOS transistor, includes forming a self-aligned lightly doped region in a first well underlying a first sidewall of a gate. The method further includes forming a self-aligned extension region under a second sidewall of the gate, where the self-aligned extension region extends into the first well from a second well. The method further includes forming a drain region spaced apart from the second sidewall of the gate. The method further includes forming a source region in the self-aligned lightly doped region and the first well. The self-aligned lightly doped region and the self-aligned extension region define a channel length of the MOS transistor, such as an LDMOS transistor. | 2013-01-17 |
20130017659 | FABRICATING METHOD OF SEMICONDUCTOR DEVICEAANM LIU; An-ChiAACI Tainan CityAACO TWAAGP LIU; An-Chi Tainan City TW - A fabricating method of a semiconductor device includes the following actions. A substrate having a silicon gate structure formed thereon is provided, and then a modification process is performed on a surface of the silicon gate structure to render the surface from being hydrophobic to be hydrophilic. After that, a mask is formed on the substrate. In succession, a dopant implantation process is performed using the silicon gate structure after the modification process and the mask. After the dopant implantation process, a cleaning process which includes a wet cleaning process is performed to remove the mask. In the above fabricating method, because the surface of the silicon gate structure is modified into a hydrophilic surface, therefore it is easy to remove the residues after the dopant implantation process using the wet cleaning process. | 2013-01-17 |
20130017660 | SELF-ALIGNED SOURCE AND DRAIN STRUCTURES AND METHOD OF MANUFACTURING SAMEAANM Fang; ZiweiAACI Baoshan TownshipAACO TWAAGP Fang; Ziwei Baoshan Township TWAANM Zhang; YingAACI Hsinchu CityAACO TWAAGP Zhang; Ying Hsinchu City TWAANM Xu; Jeff J.AACI Jhubei CityAACO TWAAGP Xu; Jeff J. Jhubei City TW - An integrated circuit device and method for manufacturing the integrated circuit device are disclosed. In an example, the method includes forming a gate structure over a substrate; forming a doped region in the substrate; performing a first etching process to remove the doped region and form a trench in the substrate; and performing a second etching process that modifies the trench by removing portions of the substrate. | 2013-01-17 |
20130017661 | METHOD FOR FABRICATING A SEMICONDUCTOR DEVICEAANM WEI; QINGSONGAACI BeijingAACO CNAAGP WEI; QINGSONG Beijing CNAANM He; YONGGENAACI BeijingAACO CNAAGP He; YONGGEN Beijing CNAANM Liu; HUANXINAACI BeijingAACO CNAAGP Liu; HUANXIN Beijing CNAANM Liu; JialeiAACI BeijingAACO CNAAGP Liu; Jialei Beijing CNAANM Li; ChaoweiAACI BeijingAACO CNAAGP Li; Chaowei Beijing CN - A method of fabricating semiconductor device includes forming a recess having a substantially rectangular section and forming an oxide layer on sidewalls and an oxide layer on a bottom of the recess by anisotropic oxidation, wherein the oxide layer on the sidewalls is thinner than the oxide layer on the bottom of recess. The method further includes completely removing the oxide layer on the sidewalls and partially removing the oxide layer on the bottom of the recess. The method also includes performing an orientation selective wet etching on the recess using a remaining oxide layer of the recess as a stop layer to shape the sidewalls into a Σ shaped section. The method includes removing the remaining oxide layer using an isotropic wet etching. | 2013-01-17 |
20130017662 | FILLER FOR FILLING A GAP, METHOD OF PREPARING THE SAME AND METHOD OF MANUFACTURING SEMICONDUCTOR CAPACITOR USING THE SAMEAANM PARK; Eun-SuAACI Uiwang-siAACO KRAAGP PARK; Eun-Su Uiwang-si KRAANM Kim; Bong-HwanAACI Uiwang-siAACO KRAAGP Kim; Bong-Hwan Uiwang-si KRAANM Lim; Sang-HakAACI Uiwang-siAACO KRAAGP Lim; Sang-Hak Uiwang-si KRAANM Kwak; Taek-SooAACI Uiwang-siAACO KRAAGP Kwak; Taek-Soo Uiwang-si KRAANM Bae; Jin-HeeAACI Uiwang-siAACO KRAAGP Bae; Jin-Hee Uiwang-si KRAANM Yun; Hui-ChanAACI Uiwang-siAACO KRAAGP Yun; Hui-Chan Uiwang-si KRAANM Kim; Sang-KyunAACI Uiwang-siAACO KRAAGP Kim; Sang-Kyun Uiwang-si KRAANM Lee; Jin-WookAACI Uiwang-siAACO KRAAGP Lee; Jin-Wook Uiwang-si KR - A filler for filling a gap includes a compound represented by the following Chemical Formula 1. | 2013-01-17 |
20130017663 | METHOD OF FORMING A PHASE CHANGE MATERIAL LAYER PATTERN AND METHOD OF MANUFACTURING A PHASE CHANGE MEMORY DEVICEAANM PARK; JEONG-HEEAACI HWASEONG-SIAACO KRAAGP PARK; JEONG-HEE HWASEONG-SI KRAANM PARK; SOON-OHAACI SUWON-SIAACO KRAAGP PARK; SOON-OH SUWON-SI KRAANM PARK; JUNG-HWANAACI SEOULAACO KRAAGP PARK; JUNG-HWAN SEOUL KRAANM OH; JIN-HOAACI SEONGNAM-SOAACO KRAAGP OH; JIN-HO SEONGNAM-SO KR - A method of forming a phase change material layer pattern includes forming a phase change material layer partially filling an opening through an insulating interlayer. A plasma treatment process is performed on the phase change material layer to remove an oxide layer on a surface of the phase change material layer. A heat treatment process is performed on the phase change material layer to remove a void or a seam in the phase change material layer, sufficiently filling the opening. | 2013-01-17 |
20130017664 | METHODS OF FORMING A PHASE CHANGE MATERIAL - Methods of forming a phase change material are disclosed. The method includes forming a chalcogenide compound on a substrate and simultaneously applying a bias voltage to the substrate to alter the stoichiometry of the chalcogenide compound. In another embodiment, the method includes positioning a substrate and a deposition target having a first stoichiometry in a deposition chamber. A plasma is generated in the deposition chamber to form a phase change material on the substrate. The phase change material has a stoichiometry similar to the first stoichiometry. A bias voltage is applied to the substrate to convert the stoichiometry of the phase change material to a second stoichiometry. A phase change material, a phase change random access memory device, and a semiconductor structure are also disclosed. | 2013-01-17 |
20130017665 | METHODS OF FORMING ISOLATION STRUCTURE AND SEMICONDUCTOR STRUCTUREAANM Yin; HaizhouAACI PoughkeepsieAAST NYAACO USAAGP Yin; Haizhou Poughkeepsie NY USAANM Zhu; HuilongAACI PoughkeepsieAAST NYAACO USAAGP Zhu; Huilong Poughkeepsie NY USAANM Luo; ZhijiongAACI PoughkeepsieAAST NYAACO USAAGP Luo; Zhijiong Poughkeepsie NY US - The present invention relates to a method of forming an isolation structure and a semiconductor structure. The method of forming the isolation structure comprises the steps of: providing a silicon substrate having a (110) crystal plane or a (112) crystal plane and determining the [111] direction of the silicon substrate; forming first trenches in the silicon substrate by wet etching the silicon substrate, the extension direction of the first trenches being substantially perpendicular to the [111] direction; filling the first trenches with a first insulating material to form a first isolator; forming second trenches in the silicon substrate by dry etching the silicon substrate, the extension direction of the second trenches being perpendicular to the extension direction of the first trenches; filling the second trenches with a second insulating material to form a second isolator. | 2013-01-17 |
20130017666 | METHOD OF FORMING ISOLATION STRUCTUREAANM Chung; Jui HsuanAACI New Taipei CityAACO TWAAGP Chung; Jui Hsuan New Taipei City TW - A method of forming an isolation structure includes the steps of forming an insulating spacer on the side surfaces of a trench in a substrate, exposing a portion of the substrate, growing an epitaxial silicon layer above a bottom surface of the trench, oxidizing the epitaxial silicon layer to form a thermal oxide layer, and filling a portion of the trench above the thermal oxide layer with a dielectric material. | 2013-01-17 |
20130017667 | SEMICONDUCTOR DEVICE AND METHOD FOR MAKING SAME - A semiconductor device includes a substrate having at least one nitride material lined isolation cavity; and a hafnium containing dielectric fill at least partially contained in and at least partially covering at least a portion of the at least one nitride lined isolation cavity. | 2013-01-17 |
20130017668 | WAFER DICING USING HYBRID SPLIT-BEAM LASER SCRIBING PROCESS WITH PLASMA ETCHAANM Lei; Wei-ShengAACI San JoseAAST CAAACO USAAGP Lei; Wei-Sheng San Jose CA USAANM Eaton; BradAACI Menlo ParkAAST CAAACO USAAGP Eaton; Brad Menlo Park CA USAANM Yalamanchili; Madhava RaoAACI Morgan HillAAST CAAACO USAAGP Yalamanchili; Madhava Rao Morgan Hill CA USAANM Singh; SaravjeetAACI Santa ClaraAAST CAAACO USAAGP Singh; Saravjeet Santa Clara CA USAANM Kumar; AjayAACI CupertinoAAST CAAACO USAAGP Kumar; Ajay Cupertino CA USAANM Iyer; AparnaAACI SunnyvaleAAST CAAACO USAAGP Iyer; Aparna Sunnyvale CA US - Methods of dicing semiconductor wafers, each wafer having a plurality of integrated circuits, are described. A method includes forming a mask above the semiconductor wafer. The mask is composed of a layer covering and protecting the integrated circuits. The mask is patterned with a split-beam laser scribing process to provide a patterned mask with gaps. The patterning exposes regions of the semiconductor wafer between the integrated circuits. The semiconductor wafer is then etched through the gaps in the patterned mask to singulate the integrated circuits. | 2013-01-17 |
20130017669 | MANUFACTURING METHOD OF SEMICONDUCTOR DEVICE AND SEMICONDUCTOR DEVICE - A method to prevent contamination of the principal surface side in a process of grinding the back surface side of a semiconductor wafer. At an intersection of a scribe region of a semiconductor wafer whose back surface side is to be ground, a plurality of insulating layers is laminated over the principal surface in the same manner as an insulating layer constituting a wiring layer laminated over a device region. Moreover, in the same layer as an uppermost wiring disposed at the uppermost layer among a plurality of the wiring layers formed for a device region, a metal pattern is formed. Furthermore, a second insulating layer covering the uppermost wiring is also formed over the metal pattern so as to cover the same. | 2013-01-17 |
20130017670 | LASER PROCESSING METHOD AND LASER PROCESSING APPARATUS - A laser processing method comprising a step of irradiating an object to be processed with laser light elliptically polarized with an ellipticity of other than 1 such that a light-converging point of the laser light is located within the object along the major axis of an ellipse indicative of the elliptical polarization of laser light, along a line which the object is intended to be cut, to form a modified region caused by multiphoton absorption within the object, along the line which the object is intended to be cut. | 2013-01-17 |
20130017671 | METHOD FOR MANUFACTURING SEMICONDUCTOR DEVICE - A method for manufacturing a semiconductor device includes the steps of: preparing a substrate having a region that at least includes one main surface thereof and that is made of single-crystal silicon carbide; forming an active layer on the one main surface; grinding a region including the other main surface of the substrate opposite to the one main surface; removing a damaged layer formed in the step of grinding the region including the other main surface; and forming a backside electrode in contact with the main surface exposed by the removal of the damaged layer. The one main surface has an off angle of not less than 50° and not more than 65° relative to a {0001} plane. | 2013-01-17 |
20130017672 | PLASMA TREATMENT METHOD, PLASMA TREATMENT APPARATUS, AND SEMICONDUCTOR DEVICE MANUFACTURING METHODAANM Kuboi; NobuyukiAACI KanagawaAACO JPAAGP Kuboi; Nobuyuki Kanagawa JPAANM Fukusawa; MasanagaAACI TokyoAACO JPAAGP Fukusawa; Masanaga Tokyo JP - A plasma treatment method includes: creating a plasma from a mixed gas containing carbon and nitrogen to generate CN active species, and treating a surface of a semiconductor substrate with the CN active species. | 2013-01-17 |
20130017673 | GENERATION OF MULTIPLE DIAMETER NANOWIRE FIELD EFFECT TRANSISTORS - A method of modifying a wafer having a semiconductor disposed on an insulator is provided and includes forming first and second nanowire channels connected at each end to semiconductor pads at first and second wafer regions, respectively, with second nanowire channel sidewalls being misaligned relative to a crystallographic plane of the semiconductor more than first nanowire channel sidewalls and displacing the semiconductor toward an alignment condition between the sidewalls and the crystallographic plane such that thickness differences between the first and second nanowire channels reflect the greater misalignment of the second nanowire channel sidewalls. | 2013-01-17 |
20130017674 | CRYOGENIC SILICON ION-IMPLANTATION AND RECRYSTALLIZATION ANNEALINGAANM Itokawa; HiroshiAACI MaltaAAST NYAACO USAAGP Itokawa; Hiroshi Malta NY US - Described herein are methods for forming a semiconductor structure. The methods involve forming a doped semiconductor film, amorphizing the doped semiconductor film through ion implantation; and annealing the doped semiconductor film. The ion implantation and the annealing can increase an activation efficiency of the dopant. The ion implantation and the annealing can also reduce a number of crystalline defects in the doped semiconductor film. | 2013-01-17 |
20130017675 | METHOD FOR MANUFACTURING SEMICONDUCTOR DEVICE - A through portion is formed on a semiconductor substrate. Into the semiconductor substrate, a first ion implantation is performed via the through portion. The through portion is at least partially removed in the thickness direction from a region of at least a portion of the through portion when viewed in a plan view. A second ion implantation is performed into the semiconductor substrate at the region of at least the portion thereof. An implantation energy for the first ion implantation is equal to an implantation energy for the second ion implantation. | 2013-01-17 |
20130017676 | DEEP CONTACTS OF INTEGRATED ELECTRONIC DEVICES BASED ON REGIONS IMPLANTED THROUGH TRENCHES - An embodiment of an integrated circuit includes first and second semiconductor layers and a contact region disposed in the second layer. The first semiconductor layer is of a first conductivity, and the second semiconductor layer is disposed over the first layer and has a surface. The contact region is contiguous with the surface, contacts the first layer, includes a first inner conductive portion, and includes an outer conductive portion of the first conductivity. The contact region may extend deeper than conventional contact regions, because where the inner conductive portion is formed from a trench, doping the outer conductive portion via the trench may allow one to implant the dopants more deeply than conventional techniques allow. | 2013-01-17 |
20130017677 | METHOD FOR MANUFACTURING SEMICONDUCTOR DEVICE - A method for manufacturing a MOSFET includes the steps of: forming a gate oxide film on an active layer, forming a gate electrode on the gate oxide film, forming a source contact electrode in ohmic contact with the active layer, and forming an interlayer insulating film made of silicon dioxide so as to cover the gate electrode after the source contact electrode is formed. The step of forming a source contact electrode includes the steps of forming a metal layer including aluminum so as to be in contact with the active layer, and alloying the metal layer. | 2013-01-17 |
20130017678 | METHODS OF ANNEAL AFTER DEPOSITION OF GATE LAYERSAANM TSAI; Chun HsiungAACI Xinpu TownshipAACO TWAAGP TSAI; Chun Hsiung Xinpu Township TWAANM YU; Xiong-FeiAACI HsinchuAACO TWAAGP YU; Xiong-Fei Hsinchu TWAANM HUANG; Yu-LienAACI Jhubei CityAACO TWAAGP HUANG; Yu-Lien Jhubei City TWAANM LIN; Da-WenAACI Hsinchu CityAACO TWAAGP LIN; Da-Wen Hsinchu City TW - Multi-stage preheat high-temperature anneal processes after the deposition of the gate dielectric layer(s) reduce the number of interfacial sites and improve the negative bias temperature instability (NTBI) performance of a p-type metal-oxide-semiconductor transistor (PMOS). The gate dielectric layers may include an interfacial oxide layer and a high-k dielectric layer. The multi-stage preheat is designed to reduce dopant deactivation and to improve inter-mixing between the interfacial oxide layer and the high-k dielectric layer. The high-temperature anneal is used to reduce the number of interfacial sites at the interface between the silicon substrate and the interfacial oxide layer. | 2013-01-17 |
20130017679 | WORK FUNCTION ADJUSTMENT IN HIGH-K METAL GATE ELECTRODE STRUCTURES BY SELECTIVELY REMOVING A BARRIER LAYER - Generally, the present disclosure is directed work function adjustment in high-k metal gate electrode structures. In one illustrative embodiment, a method is disclosed that includes removing a placeholder material of a first gate electrode structure and a second gate electrode structure, and forming a first work function adjusting material layer in the first and second gate electrode structures, wherein the first work function adjusting material layer includes a tantalum nitride layer. The method further includes removing a portion of the first work function adjusting material layer from the second gate electrode structure by using the tantalum nitride layer as an etch stop layer, removing the tantalum nitride layer by performing a wet chemical etch process, and forming a second work function adjusting material layer in the second gate electrode structure and above a non-removed portion of the first work function adjusting material layer in the first gate electrode structure. | 2013-01-17 |
20130017680 | METHOD OF IMPROVING REPLACEMENT METAL GATE FILLAANM Haran; Balasubramanian S.AACI WatervlietAAST NYAACO USAAGP Haran; Balasubramanian S. Watervliet NY USAANM Demarest; James J.AACI RensselaerAAST NYAACO USAAGP Demarest; James J. Rensselaer NY US - A method of making a gate of a field effect transistor (FET) with improved fill by a replacement gate process using a sacrificial film includes providing a substrate with a dummy gate. It further includes depositing a sacrificial layer and an encapsulating layer over the substrate, and planarizing so that the encapsulating layer, sacrificial layer and dummy gate are co-planar. The encapsulating layer and a portion of the sacrificial film are removed to leave a remaining sacrificial film. The dummy gate is removed to form and opening in the remaining sacrificial film and to expose sidewalls of the film. Spacers are formed on the sidewalls. A high dielectric constant film and metal film are deposited in the opening and planarized to form a gate. The remaining sacrificial film is removed. The method can be used on planar FETs as well non-planar FETs. | 2013-01-17 |
20130017681 | Solder Bump Cleaning Before ReflowAANM Willeke; ReinerAACI DresdenAACO DEAAGP Willeke; Reiner Dresden DEAANM Zenner; SorenAACI DresdenAACO DEAAGP Zenner; Soren Dresden DE - Generally, the subject matter disclosed herein relates to methods for forming modern sophisticated semiconductor devices, and more specifically, methods wherein substantially lead-free solder bumps may be formed above a contact layer of a semiconductor chip. One illustrative method disclosed herein includes forming a solder bump above a metallization layer of a semiconductor device, removing an oxide film from a surface of the solder bump, and, after removing the oxide film, performing a solder bump reflow process in a reducing ambient to reflow the solder bump. | 2013-01-17 |
20130017682 | Overburden Removal For Pore Fill Integration ApproachAANM Bruce; Robert L.AACI White PlainsAAST NYAACO USAAGP Bruce; Robert L. White Plains NY USAANM Dubois; Geraud Jean-MichelAACI San JoseAAST CAAACO USAAGP Dubois; Geraud Jean-Michel San Jose CA USAANM Frot; Theo J.AACI Los GatosAAST CAAACO USAAGP Frot; Theo J. Los Gatos CA USAANM Volksen; WilliAACI San JoseAAST CAAACO USAAGP Volksen; Willi San Jose CA US - In one exemplary embodiment of the invention, a method includes: providing a structure having a first layer overlying a substrate, where the first layer includes a dielectric material having a plurality of pores; applying a filling material to a surface of the first layer; after applying the filling material, heating the structure to enable the filling material to at least partially fill the plurality of pores, where heating the structure results in residual filling material being left on the surface of the first layer; and after heating the structure, removing the residual filling material by applying a solvent wash. | 2013-01-17 |
20130017683 | METHOD OF MANUFACTURING SILICON CARBIDE SUBSTRATE AND METHOD OF MANUFACTURING SILICON CARBIDE SEMICONDUCTOR DEVICE - A silicon carbide substrate is prepared. By exposing the silicon carbide substrate to an atmosphere having a nitrogen dioxide concentration greater than or equal to 2 μg/m | 2013-01-17 |
20130017684 | PROCESS OF FORMING SLIT IN SUBSTRATEAANM Wang; Wen-ChiehAACI Taoyuan CountyAACO TWAAGP Wang; Wen-Chieh Taoyuan County TWAANM Chen; Yi-NanAACI Taipei CityAACO TWAAGP Chen; Yi-Nan Taipei City TWAANM Liu; Hsien-WenAACI Taoyuan CountyAACO TWAAGP Liu; Hsien-Wen Taoyuan County TW - A process of forming a slit in a substrate is provided. A mask layer is formed on a substrate, wherein the mask layer does not include carbon. An etching process is performed to be substrate by using the mask layer as a mask, so as to form a slit in the substrate. The etching gas includes Cl | 2013-01-17 |
20130017685 | METHOD OF MANUFACTURING SEMICONDUCTOR DEVICE AND SUBSTRATE PROCESSING APPARATUSAANM Akae; NaonoriAACI Imizu-shiAACO JPAAGP Akae; Naonori Imizu-shi JPAANM Murakami; KotaroAACI Toyama-shiAACO JPAAGP Murakami; Kotaro Toyama-shi JPAANM Hirose; YoshiroAACI Toyama-shiAACO JPAAGP Hirose; Yoshiro Toyama-shi JPAANM Kameda; KenjiAACI Toyama-shiAACO JPAAGP Kameda; Kenji Toyama-shi JP - To provide a method of manufacturing a semiconductor device, including: forming a thin film different from a silicon oxide film on a substrate by supplying a processing gas into a processing vessel in which the substrate is housed; removing a deposit including the thin film adhered to an inside of the processing vessel by supplying a fluorine-containing gas into the processing vessel after executing forming the thin film prescribed number of times; and forming a silicon oxide film having a prescribed film thickness on the inside of the processing vessel by alternately supplying a silicon-containing gas, and an oxygen-containing gas and a hydrogen-containing gas into the heated processing vessel in which a pressure is set to be less than an atmospheric pressure after removing the deposit. | 2013-01-17 |
20130017686 | PLASMA PROCESSING APPARATUS AND PLASMA PROCESSING METHOD - A plasma processing apparatus for processing an object to be processed using a plasma. The apparatus includes a processing chamber defining a processing cavity for containing an object to be processed and a process gas therein, a microwave radiating antenna having a microwave radiating surface for radiating a microwave in order to excite a plasma in the processing cavity, and a dielectric body provided so as to be opposed to the microwave radiating surface, in which the distance D between the microwave radiating surface and a surface of the dielectric body facing away from the microwave radiating surface, which is represented with the wavelength of the microwave being a distance unit, is determined to be in the range satisfying the inequality | 2013-01-17 |
20130017687 | METHOD FOR FORMING OPENINGS IN SEMICONDUCTOR DEVICEAANM Lin; Chih-ChingAACI Taoyuan CountyAACO TWAAGP Lin; Chih-Ching Taoyuan County TWAANM Chen; Yi-NanAACI Taoyuan CountyAACO TWAAGP Chen; Yi-Nan Taoyuan County TWAANM Liu; Hsien-WenAACI Taoyuan CountyAACO TWAAGP Liu; Hsien-Wen Taoyuan County TW - A method for forming an opening in a semiconductor device is provided, including: providing a semiconductor substrate with a silicon oxide layer, a polysilicon layer and a silicon nitride layer sequentially formed thereover; patterning the silicon nitride layer, forming a first opening in the silicon nitride layer, wherein the first opening exposes a top surface of the polysilicon layer; performing a first etching process, using gasous etchants including hydrogen bromide (HBr), oxygen (O | 2013-01-17 |
20130017688 | Reduction Of Pore Fill Material DewettingAANM Dubois; Geraud Jean-MichelAACI San JoseAAST CAAACO USAAGP Dubois; Geraud Jean-Michel San Jose CA USAANM Frot; Theo J.AACI Los GatosAAST CAAACO USAAGP Frot; Theo J. Los Gatos CA USAANM Magbitang; Teddie P.AACI San JoseAAST CAAACO USAAGP Magbitang; Teddie P. San Jose CA USAANM Volksen; WilliAACI San JoseAAST CAAACO USAAGP Volksen; Willi San Jose CA US - In one exemplary embodiment, a method includes: providing a structure having a first layer overlying a substrate, where the first layer includes a dielectric material having a plurality of pores; applying a filling material to a surface of the first layer, where the filling material includes a polymer and at least one additive, where the at least one additive includes at least one of a surfactant, a high molecular weight polymer and a solvent; and after applying the filling material, heating the structure to enable the filling material to at least partially fill the plurality of pores uniformly across an area of the first layer, where heating the structure results in residual filling material being uniformly left on the surface of the first layer. | 2013-01-17 |
20130017689 | DIGITAL OXIDE DEPOSITION OF SIO2 LAYERS ON WAFERS - Novel silicon dioxide and silicon nitride deposition methods are generally disclosed. In one embodiment, the method includes depositing silicon on the surface of a substrate having a temperature of between about | 2013-01-17 |
20130017690 | PLASMA NITRIDING METHOD AND PLASMA NITRIDING APPARATUSAANM Takatsuki; KoichiAACI YamanashiAACO JPAAGP Takatsuki; Koichi Yamanashi JPAANM Yamazaki; KazuyoshiAACI YamanashiAACO JPAAGP Yamazaki; Kazuyoshi Yamanashi JPAANM Noguchi; HideyukiAACI YamanashiAACO JPAAGP Noguchi; Hideyuki Yamanashi JPAANM Tamura; DaisukeAACI YamanashiAACO JPAAGP Tamura; Daisuke Yamanashi JPAANM Saito; TomohiroAACI YamanashiAACO JPAAGP Saito; Tomohiro Yamanashi JP - In a plasma nitriding method, a processing gas containing nitrogen gas and rare gas is introduced into a processing chamber of a plasma processing apparatus by setting a flow rate thereof as a total flow rate [mL/min(sccm)] of the processing gas per 1 L volume of the processing chamber within a range from 1.5 (mL/min)/L to 13 (mL/min)/L. Further, a nitriding process is performed on oxygen-containing films of target objects to be processed by generating a nitrogen-containing plasma in the processing chamber and while exchanging the target objects. | 2013-01-17 |
20130017691 | Magnetically Enhanced Electrical Signal Conduction Apparatus and Methods - Apparatus and methods for magnetically enhanced electrical signal conduction are disclosed. An embodiment electrical connector comprises a connector body, a first active signal contact mechanically attached to and at least partially disposed within the connector body, a ground contact mechanically attached to the connector body, an insulator mechanically separating and electrically isolating the first active signal contact and the ground contact, and a first permanent magnet electrically connected to the first active signal contact. An embodiment electrical cable comprises an elongated insulating sheath, a first active signal electrical conductor disposed within the sheath, a first connector body mechanically attached to a first end of the sheath, a first active signal contact mechanically attached to the first connector body, and electrically connected to the first active signal electrical conductor, and a first permanent magnet electrically connected to the first active signal electrical conductor. | 2013-01-17 |
20130017692 | CONNECTION STRUCTURE OF A PRINTED CIRCUIT BOARD AND A CONNECTION METHOD THEREOFAANM Que; ChengwenAACI GuangdongAACO CNAAGP Que; Chengwen Guangdong CNAANM Kuo; YichengAACI GuangdongAACO CNAAGP Kuo; Yicheng Guangdong CN - The present invention relates to a technology field of a printed circuit board, and more particularly to a connection structure of a printed circuit board and a connection method thereof. The connection structure of the printed circuit board of the present invention comprises a first and second printed circuit boards. One end of the first printed circuit board disposes a receiving portion. One end of the second printed circuit board disposes a protruding portion. The shape of the protruding portion is corresponding to that of the receiving portion. When connecting the first and second printed circuit boards, the protruding portion is engaged with the receiving portion so that realizing a physical connection. The connection structure and the connection method may reduce the product cost. Moreover, the printed circuit boards connected by the solution of the present invention can be conveniently mounted and dismounted to simplify the operation. | 2013-01-17 |
20130017693 | POWER SUPPLY DEVICE AND POWER SUPPLY SYSTEM FOR SERVER RACKAANM LI; HAN-YUAACI Tu-ChengAACO TWAAGP LI; HAN-YU Tu-Cheng TWAANM ZHANG; NINGAACI Shenzhen CityAACO CNAAGP ZHANG; NING Shenzhen City CNAANM HE; GUANG-DONGAACI Shenzhen CityAACO CNAAGP HE; GUANG-DONG Shenzhen City CN - The power supply device includes a main bus-bar assembly, an assistant bus-bar assembly, and a plurality of connectors being electronically connected to the assistant bus-bar assembly. The main bus-bar assembly includes a first main bus-bar and a second main bus-bar attached to the first main bus-bar. The assistant bus-bar assembly includes a first assistant bus-bar and a second assistant bus-bar attached to the first assistant bus-bar. The first assistant bus-bar is electronically connected to the first main bus-bar, and the second assistant bus-bar is connected to the second main bus-bar. Each of the plurality of connector includes a first pin and a second pin. The first pin is engaged with the first assistant bus-bar, and the second pin is engaged with the second assistant bus-bar. | 2013-01-17 |
20130017694 | SECURITY SHIELD AND TOOLAANM Rodrigues; Julio F.AACI ColliervilleAAST TNAACO USAAGP Rodrigues; Julio F. Collierville TN USAANM Tremba; Timothy NoelAACI CayutaAAST NYAACO USAAGP Tremba; Timothy Noel Cayuta NY US - Security systems, including shields, adapters, and/or tools, for limiting access to a coaxial cable connector are provided. A shield comprises an outer shield configured to limit access to the coaxial cable connector. The coaxial cable connector comprises a fastener portion that is configured to be rotatable with respect to a body portion of the coaxial cable connector. The shield further comprises an adapter configured to be coupled to the outer shield. The adapter is configured to engage a side of the fastener portion of the coaxial cable connector. The adapter is further configured to engage a tool configured to rotate the adapter such that, when engaged with both the tool and the fastener portion of the coaxial cable connector, the adapter is configured to rotate the fastener portion of the coaxial cable connector upon rotation of the adapter by the tool. | 2013-01-17 |
20130017695 | DETACHMENT PREVENTION COMPONENT AND ELECTRONIC DEVICE USING THE SAMEAANM TANAKA; ShintaroAACI OsakaAACO JPAAGP TANAKA; Shintaro Osaka JP - Since a connector device | 2013-01-17 |
20130017696 | MAGNETICALLY ACTIVATED CONNECTOR PORT COVERAANM Alvarez Rivera; Felix J.AACI San JoseAAST CAAACO USAAGP Alvarez Rivera; Felix J. San Jose CA US - A magnetically activated connector port cover or door that provides access through a connector port for a corresponding connector to mate with a receptacle connector behind the door, and closes the door when the connector is not presently proximate to or intending to mate with the receptacle connector. The connector port includes a magnetic element that works in tandem with an actuator to respond to the position of the corresponding connector and bias as well as move the door in an open or closed position accordingly. | 2013-01-17 |
20130017697 | LEVER FITTING-TYPE CONNECTORAANM Furuya; YoshinobuAACI Makinohara-shiAACO JPAAGP Furuya; Yoshinobu Makinohara-shi JPAANM Hasegawa; HirotakaAACI Makinohara-shiAACO JPAAGP Hasegawa; Hirotaka Makinohara-shi JPAANM Fukuda; HiroshiAACI Makinohara-shiAACO JPAAGP Fukuda; Hiroshi Makinohara-shi JP - A lever fitting-type connecter of the present invention has housing having a main body and a pair of projections; a lever having holes into which the projections are inserted, the lever rotated in a state that the projections are inserted into the holes from a non-fitting position before being fitted to another connector to a fitting position fitted to the other connector by rotating around the projection; an engagement receiving portion arranged in the projection so as to sandwich the lever between the main body and the engagement receiving portion; a first overlapping position arranged in the lever and overlapped with the engagement receiving portion at the non-fitting position; a second overlapping position arranged in the lever and overlapped with the engagement receiving portion at the fitting position; and an engaging portion arranged between the first and second overlapping positions and engaged to the engagement receiving portion. | 2013-01-17 |
20130017698 | PORTABLE ELECTRONIC DEVICE AND BATTERY EJECTING STRUCTURE THEREOFAANM CHENG; Wen-ChiehAACI New Taipei CityAACO TWAAGP CHENG; Wen-Chieh New Taipei City TWAANM LEE; Yao-TingAACI New Taipei CityAACO TWAAGP LEE; Yao-Ting New Taipei City TW - A battery ejecting structure is applied to a portable electronic device which comprises a housing and a battery. The battery ejecting structure comprises an ejecting element, a cover, a pushing element and an elastic element. The ejecting element is movably located in the container of the housing; the cover is connected pivotally to the housing and covers the container to be a closed state, and the cover restricts the ejecting element to move via a blocking element; the pushing element is located in the housing, and the fixed member of the ejecting element is connected to the pushing element through the housing. Wherein when the cover is rotated relative to the housing to form an open state, the blocking element disengages from the container, and the pushing element is moved by an elastic restoring force of the elastic element to unlock the battery. | 2013-01-17 |
20130017699 | POWER SUPPLY DEVICE AND POWER SUPPLY SYSTEMAANM LI; HAN-YUAACI Tu-ChengAACO TWAAGP LI; HAN-YU Tu-Cheng TWAANM ZHANG; NINGAACI Shenzhen CityAACO CNAAGP ZHANG; NING Shenzhen City CNAANM WU; HAI-FENGAACI Shenzhen CityAACO CNAAGP WU; HAI-FENG Shenzhen City CN - A power supply device includes a power supply module, a main bus-bar module, an assistant bus-bar module, and a plurality of connectors. The power supply module, for supplying a direct current voltage, includes a positive terminal and a negative terminal for outputting the current voltage. The main bus-bar module includes a first main bus-bar and a second main bus-bar. The first main bus-bar is electronically connected to the positive terminal. The second main bus-bar is electronically connected to the negative terminal. The assistant bus-bar module includes a first assistant bus-bar electronically connected to the second main bus-bar, and a second assistant bus-bar electronically connected to the first main bus-bar. Each connector includes a first pin and a second pin. The first pin is inserted and electronically connected to the first assistant bus-bar. The second pin is inserted and electronically connected to the second assistant bus-bar. | 2013-01-17 |
20130017700 | CIRCUIT BOARD CONNECTOR AND METHOD FOR CONNECTING CIRCUIT BOARDAANM TIAN; XiyongAACI BeijingAACO CNAAGP TIAN; Xiyong Beijing CNAANM LI; LingchangAACI BeijingAACO CNAAGP LI; Lingchang Beijing CNAANM LIU; YinongAACI BeijingAACO CNAAGP LIU; Yinong Beijing CN - A circuit board connector and a method for connecting circuit board. The circuit board connector includes: a housing, including a left side wall and right side wall opposite each other and a bottom wall arranged between the left and right side walls, the bottom wall provided with a plurality of contact pins, and the left and right side walls and the bottom wall forming an accommodation space for accommodating the circuit board; a cover, one end being connected to the housing, so that the cover may be opened or closed relative to the housing; and a locking device arranged on the housing and cover to lock the cover when the cover is closed. Reliable connection of the circuit board can be realized, without a gasket or a film, and also the circuit board can be locked firmly, preventing the rebounding of the hinge of the connector. | 2013-01-17 |
20130017701 | COMMUNICATION PLUGAANM LEE; Ming-HsiAACI New Taipei CityAACO TWAAGP LEE; Ming-Hsi New Taipei City TW - A communication plug for connecting to a communication connector is disclosed, wherein the communication connector has an accommodating slot and the communication plug includes a main body and a fixing portion. The main body can be accommodated in the accommodating slot and the fixing portion is connected to the main body. The fixing portion includes a first part, a second part, and a third part, wherein the third part is connected to the first part and the second part. While the main body is accommodated in the communication connector, the third part is accommodated within the accommodating slot. Consequently, the communication plug is fixed within the communication connector. | 2013-01-17 |
20130017702 | ELECTRONIC DEVICE HAVING CARD EDGE CONNECTORAANM KAMIYA; TakashiAACI Anjyo-cityAACO JPAAGP KAMIYA; Takashi Anjyo-city JPAANM Iida; TakuAACI Nagoya-cityAACO JPAAGP Iida; Taku Nagoya-city JPAANM Watanabe; YujiAACI Nagoya-cityAACO JPAAGP Watanabe; Yuji Nagoya-city JP - In an electronic device, a slider is disposed in an insertion opening of a housing of a card edge connector. The slider is movable with an insertion operation of a circuit board into the insertion opening from an initial position before the circuit board is inserted to an insertion completed position where the insertion operation of the circuit board is completed by being pushed by the circuit board. When the slider is at the initial position, terminal projections are supported on a support surface of the slider in a resiliently deformed condition so that contacts are separated from an electrode-formed surface of the circuit board. When the slider is at the insertion completed position, the terminal projections are completely separated from the slider and in a state of applying a spring back force of resilient deformation to the circuit board through the contacts. | 2013-01-17 |
20130017703 | Releasable Connector System - The preferred embodiments described herein provide a releasable connector system. In one preferred embodiment, a connector plug contains a conical element with a recessed groove. A jack contains features that allow mating with the conical shaped plug. Electrical contacts are embedded within the plug. The jack portion contains spring loaded contacts that are self-centered by the conical shape. The conical shape eases the ability to mate the plug and jack compared to a standard plug with a cylindrical jack. With this preferred embodiment, contact is made in any axial rotation. A lateral force to the jack or cord will dislodge the jack, reducing the likelihood of tripping over a cord, causing a fall, or damaging equipment. | 2013-01-17 |
20130017704 | PROCESSOR LOADING SYSTEM - A component loading system includes a board having a socket. A first base member is secured to the board through a plurality of first heat dissipater coupling posts. A first securing member is moveably coupled to the first base member. A second base member is secured to the board through a plurality of second heat dissipater coupling posts. A second securing member is moveably coupled to the second base member. A loading member is moveably coupled to the first base member. A heat dissipater is operable to be coupled to the plurality of first heat dissipater coupling posts and the plurality of second heat dissipater coupling posts. The loading member is operable to be secured to the board by moving the first securing member into engagement with the second base member and moving the second securing member into engagement with the first base member. | 2013-01-17 |
20130017705 | POWER SUPPLY STRUCTUREAANM LAI; YU-CIAACI Taoyuan CityAACO TWAAGP LAI; YU-CI Taoyuan City TWAANM CIOU; CHUEI-HANGAACI Taoyuan CityAACO TWAAGP CIOU; CHUEI-HANG Taoyuan City TWAANM LEE; DA-WEIAACI Taoyuan CityAACO TWAAGP LEE; DA-WEI Taoyuan City TW - A power supply structure includes a main body and a plug. The main body has a circular containing space, a cylinder and a plurality of conducting plates. The cylinder has a retaining plane and at least one annular groove. The plug has a plug seat and a first cylinder. The first cylinder has a protrusion and at least one elastic device on an inner side of the bottom of the first cylinder. The elastic device has a resilient arm and a pressing member. The annular groove has a stop block and a fixing space. The protrusion is provided and placed into the annular groove, so that the plug can be fixed into the main body. | 2013-01-17 |
20130017706 | ELECTRICAL DEVICEAANM MILLION; Philip StephenAACI DurhamAACO GBAAGP MILLION; Philip Stephen Durham GB - An electrical device comprising a housing for electrical circuitry, the housing defining a cavity opening to the exterior of the device. The cavity includes a first and second fixing arrangement capable of mechanically interlocking with a power connection insert to fix the power connection insert in position. The power connection insert provides a power cable or power connector that couples the electrical circuitry to an external electrical power supply for the device. The use of different power connection inserts allows a wide range of connector types to be provided using a single design of the housing. | 2013-01-17 |
20130017707 | CONNECTOR ASSEMBLYAANM PAN; JIAN-CHUNAACI Shenzhen CityAACO CNAAGP PAN; JIAN-CHUN Shenzhen City CNAANM ZHOU; HAI-QINGAACI Shenzhen CityAACO CNAAGP ZHOU; HAI-QING Shenzhen City CNAANM TU; YI-XINAACI Shenzhen CityAACO CNAAGP TU; YI-XIN Shenzhen City CN - A connector assembly includes a first connector and a second connector. The first connector includes a main body, and a latching member extending out from the main body. The latching member includes a resilient extending portion extending from an outer surface of the main body, and a latching protrusion extending out from the extending portion. The second connector to be connected to the first connector, and includes a base, and a connecting member extending out from an outer surface of the base. The connecting member defining sliding groove and a receiving portion communicating with the sliding groove for latching the latching protrusion. Wherein when the first and second connectors are being connected, the latching member slides through the sliding groove, such that the latching protrusion is latched in the receiving portion. | 2013-01-17 |
20130017708 | Lamp Connector - An improved lamp connector comprises a base, a first cooperating member, a retainer, and a second cooperating member having a bulbous female connector being larger in size than an aperture formed by the a ridge on the retainer. The first and second cooperating members are operatively connected via male and female connectors to energize a UV lamp connected to the distal portion of the first cooperating member. The UV lamp cannot be removed from its housing while energized because the second cooperating member must be detached from the first cooperating member in order for the retainer to be removed. The retainer must be removed in order to remove the first cooperating member to gain access to the UV lamp. | 2013-01-17 |
20130017709 | Electrical ConnectorAANM Mashino; KeitaAACI TokyoAACO JPAAGP Mashino; Keita Tokyo JPAANM Fumikura; TadahiroAACI ChibaAACO JPAAGP Fumikura; Tadahiro Chiba JPAANM Aizawa; MasayukiAACI TokyoAACO JPAAGP Aizawa; Masayuki Tokyo JP - An electrical connector having a first and second housing. The first housing for mating with a mating connector, is provided with a contact being electrically connectable with a mating contact provided in the mating connector. The second housing movably supports the first housing in a mating direction and in an opposite direction and has a lock to be locked with the mating connector. A resilient member is supported by the second housing for biasing the first housing in the mating direction. | 2013-01-17 |
20130017710 | ELECTRICAL CONNECTOR WITH ALIGNMENT MEMBER - An electrical connector includes a connector housing, an organizer configured to be coupled to the connector housing and a plurality of leadframe assemblies supported by the connector housing. One or more of the leadframe assemblies can support respective ones of a plurality of electrical contacts that define respective mounting ends. The electrical connector can further include at least one alignment member disposed between the organizer and a respective one of the plurality of leadframe assemblies. The organizer can define a plurality of openings sized to receive the mounting ends of the plurality of electrical contacts. The organizer and the at least one alignment member can operate to align the plurality of leadframe assemblies along a mating direction, and the plurality of openings can operate to align respective mounting ends of the plurality of electrical contacts along a second direction that is substantially perpendicular with respect to the mating direction. | 2013-01-17 |
20130017711 | ELECTRICAL CONNECTOR HAVING POSITIONING ASSEMBLY - An electrical connector includes a connector housing that supports at least one printed circuit board having a mating end and a mounting end. The connector housing includes a first housing portion and a second housing portion that is configured to attach to the first housing portion. The first housing portion supports the printed circuit board, and the second housing portion includes a positioning member that engages the printed circuit board so as to retain the printed circuit board in a predetermined position. | 2013-01-17 |