03rd week of 2014 patent applcation highlights part 44 |
Patent application number | Title | Published |
20140017780 | MicroRNAs and uses thereof - Described herein are novel polynucleotides associated with prostate and lung cancer. The polynucleotides are miRNAs and miRNA precursors. Related methods and compositions that can be used for diagnosis, prognosis, and treatment of those medical conditions are disclosed. Also described herein are methods that can be used to identify modulators of prostate and lung cancer. | 2014-01-16 |
20140017781 | Methods of Modifying Eukaryotic Cells - A method for engineering and utilizing large DNA vectors to target, via homologous recombination, and modify, in any desirable fashion, endogenous genes and chromosomal loci in eukaryotic cells. These large DNA targeting vectors for eukaryotic cells, termed LTVECs, are derived from fragments of cloned genomic DNA larger than those typically used by other approaches intended to perform homologous targeting in eukaryotic cells. Also provided is a rapid and convenient method of detecting eukaryotic cells in which the LTVEC has correctly targeted and modified the desired endogenous gene(s) or chromosomal locus (loci) as well as the use of these cells to generate organisms bearing the genetic modification. | 2014-01-16 |
20140017782 | Methods for Modifying Eukaryotic Cells - A method for engineering and utilizing large DNA vectors to target, via homologous recombination, and modify, in any desirable fashion, endogenous genes and chromosomal loci in eukaryotic cells. These large DNA targeting vectors for eukaryotic cells, termed LTVECs, are derived from fragments of cloned genomic DNA larger than those typically used by other approaches intended to perform homologous targeting in eukaryotic cells. Also provided is a rapid and convenient method of detecting eukaryotic cells in which the LTVEC has correctly targeted and modified the desired endogenous gene(s) or chromosomal locus (loci) as well as the use of these cells to generate organisms bearing the genetic modification. | 2014-01-16 |
20140017783 | Non-Enzymatic Method for Isolating Human Adipose-Derived Stromal Stem Cells - A simple method was developed to extract adipose-derived stromal stem cells (ASCs) without using enzymatic digestion of the collagen in adipose tissue. The resulting ASCs isolated by the simple wash method have lower levels of CD34 expression, a hematopoietic stem cell marker, as compared to ASCs isolated using conventional enzymatic digestion using collagenase. This characteristic is consistent with non-enzymatically treated stem cells obtained from bone marrow aspirates, which are negative for CD34. Additionally, the washed ASCs have higher levels of CD44 expression, a hyaluronate receptor, and lower levels of contaminating hematopoietic cells, as evidenced by low CD45 expression, as compared to enzymatically digested cells. The cells produced by this simple method can be used therapeutically for allogenic or autologous tissue regeneration, and can be administered using any pharmaceutically acceptable carrier. In addition, the cells can be administered in a matrix, lattice, scaffold, or other biologically compatible materials. | 2014-01-16 |
20140017784 | Methods for Expansion and Analysis of Cultured Hematopoietic Stem Cells - Methods and kits for propagating hematopoietic stem cells are provided. The methods comprise culturing cells in medium comprising one or more angiopoietin-like proteins, under conditions sufficient for expansion of HSCs. Angiopoietin-like proteins include angiopoietin-like protein 2, angiopoietin-like protein 3, angiopoietin-like protein 4, angiopoietin-like protein 5, angiopoietin-like protein 7, and microfibrillar-associated glycoprotein (Mfap4). Methods for identifying hematopoietic stem cells are provided and isolated hematopoietic stem cells are also provided. | 2014-01-16 |
20140017785 | Methods for Collecting and Processing Autografts, Processed Autografts, Kits for Collecting and Transporting Autografts, and Tools for Preparing Autografts - The present invention is directed to methods for collecting and processing autografts, processed autografts, kits for collecting and transporting autografts, and tools for preparing autografts. It is also directed to autologous bone grafts, and methods of preparing them. | 2014-01-16 |
20140017786 | SMALL MOLECULE INHIBITORS OF REPLICATION PROTEIN A THAT ALSO ACT SYNERGISTICALLY WITH CISPLATIN - Replication protein A (RPA) is a single-strand DNA-binding protein with essential roles in DNA replication, recombination and repair. Small molecule inhibitors (SMIs) with the ability to disrupt RPA binding activity to ssDNA have been identified and assessed using both lung and ovarian cancer cell lines. Lung cancer cell lines demonstrated increased apoptotic cell death following treatment with the SMI MCI13E, with IC50 values of ˜5 The A2780 ovarian cancer cell line and the p53-null lung cancer cell line HI 299 were particularly sensitive to MCI13E treatment with IC | 2014-01-16 |
20140017787 | MESENCHYMAL STEM CELLS AND RELATED THERAPIES - Mesenchymal stem cells that selectively promote or suppress inflammation are provided, as well as methods of producing and using the same. | 2014-01-16 |
20140017788 | Mature Dendritic Cell Compositions and Methods for Culturing Same - This invention provides methods to prepare and use immunostimulatory cells for enhancing an immune response. The invention provides a method for preparing mature dendritic cells (DCs), comprising the sequential steps of: (a) signaling isolated immature dendritic cells (iDCs) with a first signal comprising an interferon gamma receptor (IFN-γR) agonist and/or a tumor necrosis factor alpha receptor (TNF-αR) agonist to produce signaled dendritic cells; and (b) signaling said signaled dendritic cells with a second transient signal comprising an effective amount of a CD40 agonist to produce CCR7 | 2014-01-16 |
20140017789 | Brown Fat Cell Compositions and Methods - Methods of developing and using cell lines, such as stem cell lines, for therapeutic or cosmetic use. In one embodiment the cell lines are used to treat a wide range of degenerative and metabolic disorders including, but not limited to, obesity, diabetes, hypertension, and cardiac deficiency. Also described are methods of using such cell lines to screen for compounds that play a role in regulating a variety of processes. | 2014-01-16 |
20140017790 | CONTROL AGENT FOR CONTROLLING UNDIFFERENTIATED STATE AND USE THEREOF - The present invention aims to provide a novel undifferentiated state-control agent that maintains and/or improves an undifferentiated state of undifferentiated cells. CCL2 or a protein containing a functional domain thereof is used as the undifferentiated state-control agent. By culturing undifferentiated cells in the presence of the control agent, it is possible to maintain and/or improve an undifferentiated state of the undifferentiated cells. Examples of the undifferentiated cells include embryonic stem cells (ES cells) and induced pluripotent stem cells (iPS cells). The origin of the cells is not particularly limited, and may be a human, mouse, or the like, for example. | 2014-01-16 |
20140017791 | Combining Biological Micro-Objects - Two or more biological micro-objects can be grouped in a liquid medium in a chamber. Grouping can comprise bringing into and holding in proximity or contact the micro-objects in a group, breaching the membrane of one or more of the micro-objects in a group, subjecting one or more of the micro-objects in a group to electroporation, and/or tethering to each other the micro-objects in a group. The micro-objects in the group can then be combined into a single biological object. | 2014-01-16 |
20140017792 | VECTOR PARTICLES FOR TARGETING CD34+ CELLS - The present invention relates to a vector particle for transferring biological material into cells, wherein said vector particle comprises at least:
| 2014-01-16 |
20140017793 | MASS SPECTROMETRIC DETERMINATION OF EICOSAPENTAENOIC ACID AND DOCOSAHEXAENOIC ACID - The invention relates to the detection of DHA and EPA. In a particular aspect, the invention relates to methods for detecting DHA and EPA by mass spectrometry and kits for carrying out such methods. | 2014-01-16 |
20140017794 | METHOD AND SYSTEM FOR MITIGATING UREA DEPOSITS WITHIN AN SCR CATALYST SYSTEM - A method and system for mitigating a urea deposit within an SCR system that includes determining a mass of an accumulated urea deposit present within the SCR catalyst and SCR piping, comparing the mass of the accumulated urea deposit with a deposit upper threshold limit, and initiating an SCR regeneration event when the mass of the accumulated urea deposit is greater than the deposit upper threshold limit. The method further includes determining an amount of NH | 2014-01-16 |
20140017795 | TEST DEVICE AND CONTROL METHOD THEREOF - A test device to detect a detection object of a microfluidic device and a control method thereof are provided. The test device includes a light emitting element configured to emit light onto the microfluidic device, a light receiving element configured to capture an image of the detection object through light emitted from the light emitting element, and a controller configured to determine a signal value of a predetermined area of the image of the detection object, and adjust an exposure level of the light receiving element according to a difference between the signal value and a predetermined target value. | 2014-01-16 |
20140017796 | Embedded Indicator Dye Monitoring System and Method For An Aquatic Environment - An aquatic environment monitoring system that includes chemical indicators that are dyes immobilized in an immobilizing medium, such as a hydrogel, and supported on a holder such that an optical reader may be used to illuminate the indicator dyes. The chemical indicator dyes include chemical indicator dyes that are sensitive for detecting calcium, magnesium, and carbon dioxide present in the aquatic environment. | 2014-01-16 |
20140017797 | PROTEIN AFFINITY TAG AND USES THEREOF - This invention concerns isotopically coded or non-isotopically coded affinity-tags for analysis of certain target molecules in complex samples, in particular for mass spectrometric analysis of proteomic samples. The affinity-tags have the following general formula X-SPACER-OPO | 2014-01-16 |
20140017798 | ANALYTICAL METHODS FOR ANALYZING AND DETERMINING IMPURITIES IN DIANHYDROGALACTITOL - An improved analytical method for analysis of dianhydrogalactitol preparations provides a method for determining the purity of dianhydrogalactitol and detecting impurities in preparations of dianhydrogalactitol, as well as identifying any such impurities. The method employs high performance liquid chromatography (HPLC), in particular, HPLC with evaporative light scattering detection (ELSD); the HPLC can be followed by tandem mass spectroscopy. The method can further comprise the step of performing preparative HPLC collection of at least one specific substance peak present in a preparation of dianhydrogalactitol. | 2014-01-16 |
20140017799 | SENSING METHOD AND SENSING DEVICE - This invention relates to a sensing method and a sensing device for quantifying the concentration of an analyte by using the property that interaction between an analyte and a labeled compound changes fluorescence intensity. A fluorescence sensor is used to acquire fluorescence intensity at predetermined quantification time points. Then, the concentration of an analyte is quantified in accordance with a non-steady concentration quantification law comprising the relationship between the acquired fluorescence intensity and the time derivative quantity thereof. | 2014-01-16 |
20140017800 | METHOD AND APPARATUS FOR THE IDENTIFICATION OF ALDEHYDES - A method for detecting the presence of an aldehyde in a sample comprises steps of exposing the sample at room temperature to a test medium to catalyze the formation of optically detectable quantities of a product within a time period of no more than 60 minutes and without applying any external heat to the sample or test medium, the test medium comprising a indicator that is a nucleophilic compound having acidic protons at the nucleophilic center and at least one acid, and measuring the optical changes that occur as a result of the catalysis. | 2014-01-16 |
20140017801 | Monitoring of Photo-Aging of Light-Based Chemical Indicators Using Illumination-Brightness Differential Scheme, and Systems, Methods, Apparatuses, and Software Relating Thereto - Photo-aging monitoring of light-based chemical indicators that experience performance degradation as the cumulative amount of light exposure from measurement and/or reference illumination increases from usage. Differing regions on a chemical indicator are illuminated with measurement illumination light of differing exposures, for example, higher brightness, longer exposure times, or both. Readings from the differing regions are compared with known aging information for the chemical indicator at issue to determine a confidence factor for the measurements. The confidence factor can be used to control various actions relating to measurements acquired from the chemical indicators, such as compensating measurement readings for photo-aging, assigning confidence levels to measurement readings, and issuing alerts to users when photo-aging exceeds one or more predetermined thresholds. | 2014-01-16 |
20140017802 | METHOD TO IDENTIFY CHEMICAL COMPOUNDS USING COLORIMETRIC SPOT TESTS - A method to identify a compound of interest includes the step of subjecting a sample to a plurality of colorimetric spot tests to yield a plurality of resultant test colors. The resultant test colors are compared with reference colors to define a set of sample reference colors. Indexed reference color sets indexed for the compound of interest are provided. The indexed reference color sets are searched with one or more of the sample reference colors for a match with the set of sample reference colors. The identity of the sample as the compound of interest is then determined. A device and a system to identify compounds of interest are also disclosed. | 2014-01-16 |
20140017803 | DETECTION OF ANALYTES INCLUDING DRUGS - Embodiments described herein provide materials, devices, and methods relating to the determination of analytes such as drugs, toxins, explosives, other controlled substances and contraband materials, and the like. In some embodiments, the analyte may be detected in vapor phase. Some embodiments may allow for highly sensitive and essentially instantaneous detection of analytes including drugs. | 2014-01-16 |
20140017804 | Container for Selective Transfer of Samples of Biological Material - A container for selective transport of samples of biological material or of biological origin comprising a body ( | 2014-01-16 |
20140017805 | DEVICE AND METHOD FOR ENHANCED COLLECTION AND ASSAY OF CHEMICALS WITH HIGH SURFACE AREA CERAMIC - A method and device for enhanced capture of target analytes is disclosed. This invention relates to collection of chemicals for separations and analysis. More specifically, this invention relates to a solid phase microextraction (SPME) device having better capability for chemical collection and analysis. This includes better physical stability, capacity for chemical collection, flexible surface chemistry and high affinity for target analyte. | 2014-01-16 |
20140017806 | MICROFLUIDIC STRUCTURE, MICROFLUIDIC DEVICE HAVING THE SAME AND METHOD OF CONTROLLING THE MICROFLUIDIC DEVICE - A microfluidic structure in which a plurality of chambers arranged at different positions are connected in parallel and into which a fixed amount of fluid may be efficiently distributed without using a separate driving source, and a microfluidic device having the same. The microfluidic device includes a platform having a center of rotation and including at least one microfluidic structure. The microfluidic structure includes a sample supply chamber configured to accommodate a sample, a plurality of first chambers arranged in a circumferential direction of the platform at different distances from the center of rotation of the platform, and a plurality of siphon channels, each of the siphon channels being connected to a corresponding one of the first chambers. | 2014-01-16 |
20140017807 | NOVEL LUMINESCENT LANTHANIDE CHELATES WITH ENHANCED EXCITATION PROPERTIES - The present application discloses a luminescent lanthanide chelate comprising one or more chromophoric moieties of the formula (I) or of the formula (III) | 2014-01-16 |
20140017808 | PROGNOSIS AND RISK ASSESSMENT IN STROKE PATIENTS BY DETERMINING THE LEVEL OF MARKER PEPTIDES - The present invention relates to a method for prognosis of an outcome or assessing the risk of a patient having suffered a stroke or a transient ischemic attack, comprising the determination of the level of at least one marker peptide in said sample said marker peptide selected from the group comprising ANP, AVP, ADM, ET-1, troponin, CRP, calcitonin and hGH or fragments thereof or its precursor or fragments thereof and attributing the level of said at least one marker peptides its precursor or fragments thereof with the prognosis of an outcome or assessing the risk for said patient. | 2014-01-16 |
20140017809 | OPTICAL FIBER PROBE - A biosensor having an optical fiber having at least one curved portion configured to enhance penetration of evanescent waves; and one or more nanoparticles associated with the optical fiber, and configured to enhance localized surface plasmon resonance. | 2014-01-16 |
20140017810 | BIO-MOLECULE DETECTING DEVICE AND BIO-MOLECULE DETECTING METHOD - A bio-molecule detecting device that enables a high-sensitivity measurement is provided. The orientation direction of third complexes included in blood plasma is switched by switching the vibration direction of an orientation control light. The orientation direction of the third complexes is switched between two directions in which the intensities of an electric field, which is generated between two gold nanoparticles included in the third complexes by surface plasmon resonance, are significantly different. Therefore, the intensity of fluorescence generated from the third complexes is significantly changed by the change in the orientation direction of the third complexes. | 2014-01-16 |
20140017811 | TEST DEVICE AND CONTROL METHOD THEREOF - A test device and a control method thereof are provided. The test device includes a rotary drive unit to rotate the microfluidic device, a light emitting element to emit light onto the microfluidic device, a detection module arranged at a position facing the light emitting element and provided with a light receiving element to receive light emitted from the light emitting element and transmitted through the microfluidic device, a detection module drive unit to move the detection module in a radial direction, and a controller to control the rotary drive unit and the detection module drive unit. | 2014-01-16 |
20140017812 | DIRECT READING DETECTION KITS FOR SURFACE CONTAMINATION BY ANTINEOPLASTIC DRUGS - Methods, kits and devices for detecting antineoplastic drug contamination of a surface are provided according to aspects of the present invention. According to aspects of the invention, methods for detecting antineoplastic drug contamination of a surface include providing a wetting solution compatible with the antineoplastic drug and formulated to promote release of the drug from the surface to be assayed; providing a solid matrix for reversible absorption of the antineoplastic drug; contacting the solid matrix with the wetting solution, generating an assay matrix; contacting the assay matrix and the surface, generating a surface sample; contacting the surface sample with a volume of wetting solution, generating a fluid test sample; and quantifying the antineoplastic drug in the fluid test sample by lateral flow assay to produce an assay result, thereby detecting antineoplastic drug contamination of the surface. | 2014-01-16 |
20140017813 | METHOD AND MEANS FOR SAMPLE PREPARATION - The present invention relates to a method for depletion of undesired molecules and/or enrichment of desired molecules from a sample comprising high abundant as well as low abundant molecules, comprising the following steps: a) providing a separation material comprising a solid phase (beads) comprising an inner porous core material comprising magnetic particles and an outer porous shell with a porosity equal or denser than that of the shell; b) adding the sample to the separation material; c) adsorbing a first fraction of molecules with a molecular weight of 500-50 000 Da in the core and simultaneously excluding a second fraction of molecules from binding to the core and the shell, wherein the molecular weight of the second fraction molecules is at least 5 preferably 10 times higher than the molecular weight of the first fraction and d) eluting the desired molecules from the separation material, wherein step d) and optionally step c) is performed using an oscillating power/field applied over the separation material. | 2014-01-16 |
20140017814 | METHOD FOR PRODUCING AGGLUTINATING REAGENT, AGGLUTINATING REAGENT OR PRODUCT PRODUCED THEREBY, AND METHOD FOR MEASURING ANALYSIS OBJECT USING THE SAME, AND TEST KIT AND ANALYSIS DEVICE - Hemoglobin in a sample solution is quickly and reliably denatured; at the same time, quick and accurate measurement of hemoglobin and a hemoglobin derivative is realized. In a method for measuring hemoglobin and a hemoglobin derivative, and a reagent composition, a measurement kit, an analysis device, and an analysis system used in the method, a sample solution containing a blood component is treated with a nonionic surfactant, an oxidizing agent, and a metal salt to denature hemoglobin in the sample solution to measure the hemoglobin, and thereafter the amount of a hemoglobin derivative in the sample is measured by an immunological method using an antibody specifically binding to a denatured site of the denatured hemoglobin derivative. | 2014-01-16 |
20140017815 | MEASUREMENT OF C-TERMINAL proSP-B - In vitro methods for obtaining an indication of damage in the broncheoalveolar compartment of the lung comprising, measuring C-terminal proSP-B in a bodily fluid sample and comparing the level measured to a reference level of C-terminal proSP-B, wherein an increased level of C-terminal proSP-B is indicative of damage in the broncheoalveolar compartment of the lung. | 2014-01-16 |
20140017816 | WATER RELAXATION-BASED SENSORS - This invention relates to magnetic resonance-based sensors and related methods. | 2014-01-16 |
20140017817 | TECHNIQUES FOR TREATING SIDEWALLS OF PATTERNED STRUCTURES USING ANGLED ION TREATMENT - In one embodiment a method of method of treating a sidewall layer of a patterned feature includes providing the patterned feature as an etched structure comprising one or more layers disposed on a substrate and generally parallel to a plane of the substrate defined by a front surface of the substrate. The sidewall layer comprises material from the one or more etched layers. The method further includes arranging the substrate proximate a sheath modifier that is adjacent a plasma, and providing ions in an ion dose to the substrate by extracting the ions from the plasma through the sheath modifier, the ions impinging upon the substrate at an angle with respect to a perpendicular to the plane of the substrate. | 2014-01-16 |
20140017818 | METHOD FOR MANUFACTURING NON-VOLATILE MAGNETIC MEMORY CELL IN TWO FACILITIES - In accordance with a method of the present invention, a method of manufacturing a magnetic random access memory (MRAM) cell and a corresponding structure thereof are disclosed to include a multi-stage manufacturing process. The multi-stage manufacturing process includes performing a front end on-line (FEOL) stage to manufacture logic and non-magnetic portions of the memory cell by forming an intermediate interlayer dielectric (ILD) layer, forming intermediate metal pillars embedded in the intermediate ILD layer, depositing a conductive metal cap on top of the intermediate ILD layer and the metal pillars, performing magnetic fabrication stage to make a magnetic material portion of the memory cell being manufactured, and performing back end on-line (BEOL) stage to make metal and contacts of the memory cell being manufactured. | 2014-01-16 |
20140017819 | SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING THE SAME - A ferroelectric capacitor is formed above a semiconductor substrate ( | 2014-01-16 |
20140017820 | Co/Ni Multilayers with Improved Out-of-Plane Anisotropy for Magnetic Device Applications - A method for forming a MTJ in a spintronic device is disclosed and includes a thin seed layer that enhances perpendicular magnetic anisotropy (PMA) in an overlying laminated layer with a (Co/Ni) | 2014-01-16 |
20140017821 | On-SOI integrated circuit comprising a triac for protection against electrostatic discharges - An integrated circuit includes four electronic components, a buried UTBOX layer under and plumb with the electronic components, and two pairs of oppositely doped ground planes plumb with corresponding components under the layer. A first isolation trench mutually isolates the ground planes from corresponding wells made plumb and in contact with the ground planes and exhibiting the first doping type. Bias electrodes contact respective wells and ground planes. One pair of electrodes is for connecting to a first bias voltage and the other pair is for connecting to a second bias voltage. Also included are a semiconductor substrate exhibiting the first type of doping and a deeply buried well exhibiting the second type of doping. The deeply buried well contacts the other wells and separates them from the substrate. Finally, a control electrode couples to the deeply buried well. | 2014-01-16 |
20140017822 | METHOD OF MANUFACTURING SEMICONDUCTOR DEVICE - Product management and/or prompt defect analysis of a semiconductor device may be carried out without reducing the throughput in assembly and testing. Unique identification information is attached to a plurality of substrates (lead frames) used in manufacturing a semiconductor device (QFP) and to a transport unit for transporting a plurality of substrates, respectively. Identification information (rack ID) of the transport unit and identification information (substrate ID) of the substrate stored into the transport unit are associated with each other. The substrate is taken out from the transport unit set to a loader unit of each manufacturing apparatus and supplied to a processing unit, of the apparatus and in storing the substrate, the processing of which is complete, into a transport unit of an unloader unit of the apparatus, an association between identification information of the transport unit and the identification information of the substrate is checked. | 2014-01-16 |
20140017823 | SEMICONDUCTOR DIE ASSEMBLIES, SEMICONDUCTOR DEVICES INCLUDING SAME, AND METHODS OF FABRICATION - Methods of fabricating multi-die assemblies including a wafer segment having no integrated circuitry thereon and having a plurality of vertically stacked dice thereon electrically interconnected by conductive through vias, resulting multi-die assemblies, and semiconductor devices comprising such multi-die assemblies. The wafer segment may function as a heat sink to enhance heat transfer from the stacked dice in the resulting multi-die assembly. The die stacks are fabricated at the wafer level on a base wafer, from which the wafer segment and die stacks are singulated after at least peripheral encapsulation. | 2014-01-16 |
20140017824 | POLISHING METHOD - A method of polishing a substrate having a film is provided. The method includes: performing polishing of the substrate in a polishing section; transporting the polished substrate to a wet-type film thickness measuring device prior to cleaning and drying of the substrate; measuring a thickness of the film by the wet-type film thickness measuring device; comparing the thickness with a predetermined target value; and if the thickness has not reached the predetermined target value, performing re-polishing of the substrate in the polishing section prior to cleaning and drying of the substrate. | 2014-01-16 |
20140017825 | ION IMPLANTATION METHOD AND ION IMPLANTATION APPARATUS - The ion implantation method includes setting an ion beam scanning speed and a mechanical scanning speed of an object during ion implantation using hybrid scan in advance and implanting ions based on the set ion beam scanning speed and the set mechanical scanning speed of the object. In the setting in advance, each of the ion beam scanning speeds is set based on each of ion beam scanning amplitudes changing severally according to a surface outline of an object which is irradiated with the ions so that an ion beam scanning frequency is maintained constant for any of ion beam scanning amplitudes, and the mechanical scanning speed of the object corresponding to the ion beam scanning speed is set so that an ion implantation dose per unit area to be implanted into the surface of the object is maintained constant. | 2014-01-16 |
20140017826 | SEMICONDUCTOR WAFER EVALUATION METHOD, SEMICONDUCTOR WAFER EVALUATION DEVICE, AND PROBE FOR SEMICONDUCTOR EVALUATION DEVICE - Provided is a semiconductor wafer evaluation method of performing an evaluation of electrical characteristics of a semiconductor wafer by bringing mercury into contact with a surface of the semiconductor wafer, the method including using a probe constituted of a fixed electrode having a tip end portion and a transparent covering portion that covers a portion other than the tip end portion of the fixed electrode, the fixed electrode being made of a metal having stronger wettability with respect to the mercury than the semiconductor wafer and the covering portion, and measuring the electrical characteristics by attaching the mercury to the tip end portion of the fixed electrode and then bringing the mercury into contact with the surface of the semiconductor wafer. | 2014-01-16 |
20140017827 | APPARATUS AND METHOD FOR MANUFACTURING A LIGHT-EMITTING DEVICE USING A NEUTRAL PARTICLE BEAM - The present invention relates to an apparatus and method for manufacturing a semiconductor light-emitting device using a neutral particle beam. According to the present invention, since the kinetic energy of the neutral particle beam is provided as a portion of the reaction energy for causing a nitride semiconductor single crystal thin film to be formed on a substrate, and the reaction energy is not provided as heat energy by heating a substrate as in the prior art, the substrate may be treated at a relatively low temperature. Furthermore, elements such as Si, Mg, and the like, which are solid elements required for doping are sprayed onto the substrate from a source which generates solid elements for doping together with the neutral particle beam to achieve high doping efficiency at a lower temperature. According to the present invention, since the substrate is treated at a low temperature, the degradation of the substrate and thin film may be prevented, and the undesired diffusion of the doping elements may be prevented to enable the manufacture of the semiconductor light-emitting device having superior light-emitting properties in a relatively easy manner. | 2014-01-16 |
20140017828 | HIGH-REFLECTION SUBMOUNT FOR LIGHT-EMITTING DIODE PACKAGE AND FABRICATION METHOD THEREOF - A method for fabricating a silicon submount for LED packaging. A silicon substrate is provided. A reflection layer is formed on the silicon substrate. Portions of the reflection layer and the silicon substrate are removed to form openings. A wafer backside grinding process is carried out to thin the silicon substrate thereby turning the openings into through silicon vias. An insulating layer is then deposited to cover the reflection layer and the silicon substrate. A seed layer is formed on the insulating layer. A resist pattern is then formed on the seed layer. A metal layer is formed on the seed layer not covered by the resist pattern. The resist pattern is then stripped. The seed layer not covered by the metal layer is then removed. | 2014-01-16 |
20140017829 | LIGHT EMITTING DEVICE PROVIDED WITH LENS FOR CONTROLLING LIGHT DISTRIBUTION CHARACTERISTIC - The light emitting device comprises a substrate ( | 2014-01-16 |
20140017830 | PLANARIZED TCO-BASED ANODE FOR OLED DEVICES, AND/OR METHODS OF MAKING THE SAME - Certain example embodiments relate to organic light emitting diode (OLED)/polymer light emitting diode (PLED) devices, and/or methods of making the same. A first transparent conductive coating (TCC) layer is disposed, directly or indirectly, on a glass substrate. An outermost major surface of the TCC layer is planarized by exposing the outermost major surface thereof to an ion beam. Following said planarizing, the first TCC layer has an arithmetic mean value RMS roughness (Ra) of less than 1.5 nm. A hole transporting layer (HTL) and an electron transporting and emitting layer (ETL) are disposed, directly or indirectly, on the planarized outermost major surface of the first TCC layer. A second TCC layer is disposed, directly or indirectly, on the HTL and the ETL. One or both TCC layers may include ITO. The substrate and/or an optional optical out-coupling layer stack system may be planarized using an ion beam. | 2014-01-16 |
20140017831 | METHOD FOR ENHANCING ELECTRICAL INJECTION EFFICIENCY AND LIGHT EXTRACTION EFFICIENCY OF LIGHT-EMITTING DEVICES - A method for enhancing electrical injection efficiency and light extraction efficiency of a light-emitting device is disclosed. The method includes the steps of: providing a site layer on the light-emitting device; placing a protection layer on the site layer; forming a cavity through the protection layer and the site layer; and growing a window layer in the cavity. The shape of the window layer can be well controlled by adjusting reactive temperature, reactive time, and N | 2014-01-16 |
20140017832 | ORGANIC LIGHT EMITTING DIODE AND METHOD OF FABRICATING THE SAME - Provided are an organic light emitting diode and a method of fabricating the same. The organic light emitting diode may include a light-scattering layer, a first electrode, an organic light-emitting layer, and a second electrode, which are sequentially stacked on a substrate, wherein the light-scattering layer may include uneven shaped nanostructures having irregular width and spacing. The method of fabricating the organic light emitting diode may include sequentially stacking a light-scattering medium layer and a metal alloy layer on a substrate, heat treating the metal alloy layer to form etching mask patterns, etching the light-scattering medium layer by using the etching mask patterns to form a light-scattering layer, removing the etching mask patterns, and forming a planarizing layer on the light-scattering layer. | 2014-01-16 |
20140017833 | MANUFACTURING METHOD FOR LIQUID CRYSTAL DISPLAY DEVICE - A manufacturing method for a liquid crystal display device according to this application is a manufacturing method for a liquid crystal display device having a transparent substrate ( | 2014-01-16 |
20140017834 | LIQUID CRYSTAL DISPLAY DEVICE AND METHOD FOR MANUFACTURING THE SAME - Provided is a method to manufacture a liquid crystal display device in which a contact hole for the electrical connection of the pixel electrode and one of the source and drain electrode of a transistor and a contact hole for the processing of a semiconductor layer are formed simultaneously. The method contributes to the reduction of a photography step. The transistor includes an oxide semiconductor layer where a channel formation region is formed. | 2014-01-16 |
20140017835 | LIQUID CRYSTAL DISPLAY PANEL AND MANUFACTURING METHOD THEREOF - A liquid crystal display panel includes a substrate, a thin film transistor array, a circuit, and a dummy circuit. One surface of the substrate is divided into a display region and a wiring region. The thin film transistor array is formed on the display region. The circuit and the dummy circuit are formed on the wiring region, the dummy circuit is adjacent to the circuit, and the circuit and the dummy circuit protrude from the substrate. | 2014-01-16 |
20140017836 | METHOD FOR MAKING LIGHT EMITTING DIODE - A method of making a LED includes steps of providing a substrate having an epitaxial growth surface. A buffer layer and an intrinsic semiconductor layer are grown thereon in that order. A carbon nanotube layer is placed on the intrinsic semiconductor layer. A first semiconductor layer, an active layer, and a second semiconductor layer are grown in that order on the intrinsic semiconductor layer, the first semiconductor layer covering the carbon nanotube layer. A first electrode is applied to a surface of the second semiconductor layer and the substrate, the buffer layer, and the intrinsic semiconductor layer are removed to expose the carbon nanotube layer. A second electrode is applied to make electrical connections with the carbon nanotube layer. | 2014-01-16 |
20140017837 | METHOD OF CUTTING SILICON SUBSTRATE HAVING LIGHT-EMITTING ELEMENT PACKAGE - Methods of cutting silicon substrates having a light-emitting element package. The method includes preparing a silicon substrate on which a plurality of light-emitting element chips are mounted and a transparent material layer that covers the light-emitting element chips is formed; removing the transparent material layer between the light-emitting element chips along a predetermined cutting line by using a mechanical cutting method; forming a scribing line corresponding to the predetermined cutting line on the silicon substrate by using a laser processing method; and cutting the silicon substrate to form individual light-emitting element packages by applying a mechanical impact to the silicon substrate along the scribing line. The method may enhance productivity of a cutting process of light-emitting element packages, and may prevent damage or transformation of the transparent material layer. | 2014-01-16 |
20140017838 | METHOD OF MANUFACTURING AN ARRAY SUBSTRATE - The present invention provides an array substrate comprising: a substrate, having a thin film transistor (TFT) formed thereupon, the TFT having a gate electrode, a source electrode and a drain electrode; a first metal layer, formed on the substrate, and comprising a gate line and the gate electrode of the TFT; a first insulating layer, covering the first metal layer and the substrate; a semiconductor layer, an ohmic contact layer, and a second metal layer, which are sequentially formed on the first insulating layer; a second insulating layer, covering the semiconductor layer, the ohmic contact layer, and the second metal layer; a pixel electrode, provided on the second insulating layer and is connected to the drain electrode. The second metal layer further comprises an etch-blocking pattern in the peripheral area of the pixel electrode within the overlapping region between the pixel electrode and the first metal layer. | 2014-01-16 |
20140017839 | STRAIN-ENGINEERED BANDGAPS - An optoelectronic device as well as its methods of use and manufacture are disclosed. In one embodiment, the optoelectronic device includes a first optoelectronic material that is inhomogeneously strained. A first charge carrier collector and a second charge carrier collector are each in electrical communication with the first optoelectronic material and are adapted to collect charge carriers from the first optoelectronic material. In another embodiment, a method of photocatalyzing a reaction includes using a strained optoelectronic material. | 2014-01-16 |
20140017840 | NITRIDE-BASED LIGHT-EMITTING DEVICE - A nitride-based light-emitting device includes a substrate and a plurality of layers formed over the substrate in the following sequence: a nitride-based buffer layer formed by nitrogen, a first group III element, and optionally, a second group III element, a first nitride-based semiconductor layer, a light-emitting layer, and a second nitride-based semiconductor layer. | 2014-01-16 |
20140017841 | OPTICAL SEMICONDUCTOR DEVICE HAVING RIDGE STRUCTURE FORMED ON ACTIVE LAYER CONTAINING P-TYPE REGION AND ITS MANUFACTURE METHOD - A p-type cladding layer ( | 2014-01-16 |
20140017842 | METHODS FOR FORMING A SEALED LIQUID METAL DROP - Methods for forming an enclosed liquid metal (LM) drop inside a sealed cavity by formation of LM components as solid LM component layers and reaction of the solid LM component layers to form the LM drop. In some embodiments, the cavity has boundaries defined by layers or features of a microelectronics (e.g. VLSI-CMOS) or MEMS technology. In such embodiments, the methods comprise implementing an initial microelectronics or MEMS process to form the layers or features and the cavity, sequential or side by side formation of solid LM component layers in the cavity, sealing of the cavity to provide a closed space and reaction of the solid LM components to form a LM alloy in the general shape of a drop. In some embodiments, nanometric reaction barriers may be inserted between the solid LM component layers to lower the LM eutectic formation temperature. | 2014-01-16 |
20140017843 | SEMICONDUCTOR PACKAGE AND MANUFACTURING METHOD THEREOF - Various aspects of the present invention, for example and without limitation, comprise a semiconductor device package and/or method for manufacturing a semiconductor device package. Such a device package may, for example, comprise a MEMS device package. | 2014-01-16 |
20140017844 | INTEGRATED CIRCUIT SWITCHES, DESIGN STRUCTURE AND METHODS OF FABRICATING THE SAME - Integrated MEMS switches, design structures and methods of fabricating such switches are provided. The method includes forming at least one tab of sacrificial material on a side of a switching device which is embedded in the sacrificial material. The method further includes stripping the sacrificial material through at least one opening formed on the at least one tab which is on the side of the switching device, and sealing the at least one opening with a capping material. | 2014-01-16 |
20140017845 | Method Of Forming A Photovoltaic Cell Module With A Cell Press - A photovoltaic cell module is formed with the use of a cell press. The cell press has a longitudinal axis, two surfaces disposed opposite each other along the longitudinal axis, and a fluidic mechanism for moving at least one of the two surfaces towards the other of the two surfaces along the longitudinal axis. A method includes the step of disposing a substrate, photovoltaic cell, tie layer or precursor thereof, and superstrate between the two surfaces and spaced from one of the two surfaces. The method also includes the step of moving at least one of the two surfaces along the longitudinal axis towards the other of the two surfaces using the fluidic mechanism to compress the substrate, photovoltaic cell, tie layer or precursor thereof, and superstrate and form the photovoltaic cell module. The precursor has a viscosity of less than about 1,500 cPs measured at 25° C. before curing. | 2014-01-16 |
20140017846 | SYSTEMS AND METHODS FOR ENHANCED LIGHT TRAPPING IN SOLAR CELLS - Methods for improving the light trapping characteristics of crystalline silicon solar cells are provided. In one embodiment, the backside surface of a crystalline silicon solar cell substrate is textured with a pulsed laser beam. The textured backside surface of the crystalline silicon solar cell substrate is then annealed to remove damage from the laser texturization process. | 2014-01-16 |
20140017847 | METHOD FOR MANUFACTURING SOLAR CELL - Provided is a method of manufacturing a solar cell, wherein a solar cell is manufactured by combining a damage removal etching process, a texturing process and an edge isolation process. The method is advantageous in that RIE and DRE are conducted, and then DRE/PSG and/or an edge isolation removal process are simultaneously conducted, so that the movement of a substrate (that is, a wafer) is minimized, thereby reducing the damage rate of the substrate. | 2014-01-16 |
20140017848 | IR Conveyor Furnace Having Single Belt With Multiple Independently Controlled Processing Lanes - Multi-zone IR solar cell processing furnaces using a single, full-width conveyor belt; selected zones are divided into multiple lanes by upper or/and lower longitudinal divider walls, and heated by high intensity radiation IR lamps backed by a flat plate of ultra-high reflectance ceramic material. Lamp numbers and spacing in each zone/lane can be varied. Power to each lamp, or zone/lane lamp array, both upper and lower, is individually and independently controlled to provide infinite number of temperature profiles in each heating zone/lane. In multi-lane zones the IR lamps are folded, the inner ends being supported by the lane dividers. Lamp external power leads are both accessible from one side of the furnace. The lamp internal filaments include non-radiant and radiant sections arranged so that a pair of radiant sections are aligned in the lamp-folded configuration and disposed over the full width of the solar cell wafers. | 2014-01-16 |
20140017849 | METHOD FOR PRODUCING TRANSPARENT CONDUCTIVE FILM AND METHOD FOR MANUFACTURING SOLAR CELL - The purpose of the present invention is to favorably modify a transparent conductive film and provide a transparent conductive film with few grain boundaries. In the manufacturing method for the transparent conductive film of the present invention, a transparent conductive film 3 is formed on a substrate 2 inside a vacuum chamber 10, after which radiant heat is imparted from a surface modifying device 4 arranged near the substrate 2 to modify the transparent conductive film 3, and the substrate 2 having the modified transparent conductive film 3 is removed from the vacuum chamber 10. | 2014-01-16 |
20140017850 | METHOD FOR PRODUCING PHOTOELECTRIC CONVERSION ELEMENT - There is provided a method of producing a photovoltaic element comprising: a first step in which an i-type amorphous silicon layer ( | 2014-01-16 |
20140017851 | SEMICONDUCTOR DEVICE AND METHOD FOR MANUFACTURING THE SAME - A highly reliable semiconductor device is provided. A semiconductor device is manufactured at a high yield, so that high productivity is achieved. In a semiconductor device including a transistor in which a gate electrode layer, a gate insulating film, an oxide semiconductor film containing indium, and an insulating layer provided on and in contact with the oxide semiconductor film so as to overlap with the gate electrode layer are stacked and a source electrode layer and a drain electrode layer are provided in contact with the oxide semiconductor film and the insulating layer, the chlorine concentration and the indium concentration on a surface of the insulating layer are lower than or equal to 1×10 | 2014-01-16 |
20140017852 | METHODS FOR FLIP CHIP STACKING - A method for flip chip stacking includes forming a cavity wafer comprising a plurality of cavities and a pair of corner guides, placing a through-silicon-via (TSV) interposer with solder bumps coupled to a surface of the TSV interposer on the cavity wafer, such that the solder bumps are situated in the plurality of cavities and the TSV interposer is situated between the pair of corner guides, placing an integrated circuit (IC) die on another surface of the TSV interposer, such that the IC die, the TSV interposer, and the solder bumps form a stacked interposer unit, removing the stacked interposer unit from the cavity wafer, and bonding the solder bumps of the stacked interposer unit to an organic substrate such that the stacked interposer unit and the organic substrate form a flip chip. | 2014-01-16 |
20140017853 | STACKED DIGITAL/RF SYSTEM-ON-CHIP WITH INTEGRAL ISOLATION LAYER - An apparatus includes a device package, a first Integrated Circuit (IC) that is packaged in the device package, and a second IC, which is packaged in the device package and is fabricated on a multi-layer interconnection circuit including a plurality of interconnection layers for interconnecting components of the second IC, wherein a selected layer in the plurality is configured to serve as a conductive shield for reducing interference between the first and second ICs. | 2014-01-16 |
20140017854 | CHIP PACKAGE AND FABRICATION METHOD THEREOF - A chip package and a fabrication method thereof are provided according to an embodiment of the invention. The chip package contains a semiconductor substrate having a chip. A packaging layer is disposed over the semiconductor substrate. A spacer is disposed between the semiconductor substrate and the packaging layer, wherein a side surface consisting of the semiconductor substrate, the spacer and the packaging layer has a recess section. The method includes forming a plurality of spacers between a plurality of chips of a semiconductor wafer and a packaging layer, wherein each spacer corresponding to each chip is separated from each other and the spacer is shrunk inward from an edge of the chip to form a recess section and dicing the semiconductor wafer along a scribe line between any two adjacent chips to form a plurality of chip packages. | 2014-01-16 |
20140017855 | METHOD OF MANUFACTURING A BALL GRID ARRAY SUBSTRATE OR A SEMICONDUCTOR CHIP PACKAGE - A method of manufacturing a ball grid array substrate includes: forming a first circuit pattern and a second circuit pattern on a first metal carrier and a second metal carrier, respectively; stacking a first insulating layer and a second insulating layer with a separable material interposed therebetween, wherein each of the first and second insulating layers has first and second surfaces opposing each other, and the first surface contacts the separable material; burying the first and second circuit patterns in the second surfaces of the first and second insulating layers, respectively; removing the first and second metal carriers; removing the separable material to separate the first and second insulating layers from each other; and forming an opening in each of the first and second insulating layers to connect the first and second surfaces with each other. The method may also be part of a process for manufacturing a semiconductor package. | 2014-01-16 |
20140017856 | On-SOI integrated circuit comprising a subjacent protection transistor - An integrated circuit features a FET, an UTBOX layer plumb with the FET, an underlayer ground plane with first doping plumb with the FET's gate and channel, first and second underlayer semiconducting elements, both plumb with the drain or source, electrodes in contact respectively with the ground plane and with the first element, one having first doping and being connected to a first voltage, the other having the first doping and connected to a second bias voltage different from the first, a semiconducting well having the second doping and plumb with the first ground plane and both elements, a first trench isolating the first FET from other components of the integrated circuit and extending through the layer into the well, and second and third trenches isolating the FET from the electrodes, and extending to a depth less than a plane/well interface. | 2014-01-16 |
20140017857 | METHOD FOR PROVIDING LATERAL THERMAL PROCESSING OF THIN FILMS ON LOW-TEMPERATURE SUBSTRATES - A method for thermally processing a minimally absorbing thin film in a selective manner is disclosed. Two closely spaced absorbing traces are patterned in thermal contact with the thin film. A pulsed radiant source is used to heat the two absorbing traces, and the thin film is thermally processed via conduction between the two absorbing traces. This method can be utilized to fabricate a thin film transistor (TFT) in which the thin film is a semiconductor and the absorbers are the source and the drain of the TFT. | 2014-01-16 |
20140017858 | On-SOI integrated circuit comprising a lateral diode for protection against electrostatic discharges - An integrated circuit includes a transistor, an UTBOX buried insulating layer disposed under it, a ground plane disposed under the layer, a well disposed under the plane, a first trench made at a periphery of the transistor and extending through the layer and into the well, a substrate situated under the well, a p-n diode made on a side of the transistor and comprising first and second zones of opposite doping, the first zone being configured for electrical connection to a first electrode of the transistor, wherein first and second zones are coplanar with the plane, a second trench for separating the first and second zones, the second trench extending through the layer into the plane and until a depth less than an interface between the plane and the well, and a third zone under the second trench forming a junction between the zones. | 2014-01-16 |
20140017859 | METHOD FOR FABRICATING TRANSISTOR WITH RECESSED CHANNEL AND RAISED SOURCE/DRAIN - A method is provided for fabricating a transistor. According to the method, a second semiconductor layer is formed on a first semiconductor layer, and a dummy gate structure is formed on the second semiconductor layer. A gate spacer is formed on sidewalls of the dummy gate structure, and the dummy gate structure is removed to form a cavity. The second semiconductor layer beneath the cavity is removed. A gate dielectric is formed on the first portion of the first semiconductor layer and adjacent to the sidewalls of the second semiconductor layer and sidewalls of the gate spacer. A gate conductor is formed on the first portion of the gate dielectric and abutting the second portion of the gate dielectric. Raised source/drain regions are formed in the second semiconductor layer, with at least part of the raised source/drain regions being below the gate spacer. | 2014-01-16 |
20140017860 | SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD THEREOF - A semiconductor device includes an oxide semiconductor layer including a channel formation region which includes an oxide semiconductor having a wide band gap and a carrier concentration which is as low as possible, and a source electrode and a drain electrode which include an oxide conductor containing hydrogen and oxygen vacancy, and a barrier layer which prevents diffusion of hydrogen and oxygen between an oxide conductive layer and the oxide semiconductor layer. The oxide conductive layer and the oxide semiconductor layer are electrically connected to each other through the barrier layer. | 2014-01-16 |
20140017861 | LASER CRYSTALLIZATION APPARATUS AND METHOD - A laser crystallization apparatus includes a laser generator that generates a laser beam, a stage mounted with an object substrate with an object thin film to which the laser beam is firstly incident, the stage is relatively movable such that the laser beam scans the object thin film for crystallization, and a reflection mirror that secondly reflects a second reflection laser beam to the object thin film from a first reflection laser beam that is reflected from the object thin film to the reflection mirror. | 2014-01-16 |
20140017862 | METAL SEMICONDUCTOR ALLOY CONTACT WITH LOW RESISTANCE - A method of forming a semiconductor device is provided that includes forming a gate structure on a channel portion of a semiconductor substrate, forming an interlevel dielectric layer over the gate structure, and forming a opening through the interlevel dielectric layer to an exposed surface of the semiconductor substrate containing at least one of the source region and the drain region. A metal semiconductor alloy contact is formed on the exposed surface of the semiconductor substrate. At least one dielectric sidewall spacer is formed on sidewalls of the opening. An interconnect is formed within the opening in direct contact with the metal semiconductor alloy contact. | 2014-01-16 |
20140017863 | METHODS OF MANUFACTURING SEMICONDUCTOR DEVICES INCLUDING METAL GATES - Methods of manufacturing a semiconductor device including metal gates are provided. The method may include forming a resistor pattern and a dummy gate electrode, which include polysilicon, and forming an impurity region adjacent to the dummy gate electrode. The method may further include replacing the dummy gate electrode with a gate electrode and then forming metal silicide patterns on the resistor pattern and the impurity region. | 2014-01-16 |
20140017864 | METHOD OF FORMING TRENCH GATE MOSFET - A method of forming a trench gate MOSFET is provided. An epitaxial layer is formed on a substrate. A trench is formed in the epitaxial layer. A first insulating layer is conformally formed on surfaces of the epitaxial layer and the trench. A first conductive layer is formed at the bottom of the trench. A portion of the first insulating layer is removed to form a second insulating layer exposing an upper portion of the first conductive layer. An oxidation process is performed to oxidize the first conductive layer to a third insulating layer, wherein a fourth insulating layer is simultaneously formed on the surface of the epitaxial layer and on the sidewall of the trench. A second conductive layer is formed in the trench. Two body layers are formed in the epitaxial layer beside the trench. Two doped regions are formed in the body layers respectively beside the trench. | 2014-01-16 |
20140017865 | Memory Arrays, Semiconductor Constructions, and Methods of Forming Semiconductor Constructions - Some embodiments include memory arrays. The memory arrays may have digit lines under vertically-oriented transistors, with the digit lines interconnecting transistors along columns of the array. Each individual transistor may be directly over only a single digit line, with the single digit line being entirely composed of one or more metal-containing materials. The digit lines can be over a deck, and electrically insulative regions can be directly between the digit lines and the deck. Some embodiments include methods of forming memory arrays. A plurality of linear segments of silicon-containing material may be formed to extend upwardly from a base of the silicon-containing material. The base may be etched to form silicon-containing footings under the linear segments, and the footings may be converted into metal silicide. The linear segments may be patterned into a plurality of vertically-oriented transistor pedestals that extend upwardly from the metal silicide footings. | 2014-01-16 |
20140017866 | Method of Substantially Reducing the Formation of SiGe Abnormal Growths on Polycrystalline Electrodes for Strained-Channel PMOS Transistors - The likelihood of forming silicon germanium abnormal growths, which can be undesirably formed on the gate electrode of a strained-channel PMOS transistor at the same time that silicon germanium source and drain regions are formed, is substantially reduced by using protection materials that reduce the likelihood that the gate electrode is exposed during the formation of the silicon germanium source and drain regions. | 2014-01-16 |
20140017867 | SEMICONDUCTOR DEVICE HAVING METAL GATE AND MANUFACTURING METHOD THEREOF - A method of manufacturing a semiconductor device having metal gate includes providing a substrate having at least a dummy gate, a sacrificial layer covering sidewalls of the dummy gate and a dielectric layer exposing a top of the dummy gate formed thereon, forming a sacrificial layer covering sidewalls of the dummy gate on the substrate, forming a dielectric layer exposing a top of the dummy gate on the substrate, performing a first etching process to remove a portion of the sacrificial layer surrounding the top of the dummy gate to form at least a first recess, and performing a second etching process to remove the dummy gate to form a second recess. The first recess and the second recess construct a T-shaped gate trench. | 2014-01-16 |
20140017868 | INTEGRATED CIRCUIT HAVING MEMORY CELL ARRAY INCLUDING BARRIERS, AND METHOD OF MANUFACTURING SAME - An integrated circuit device having (i) a memory cell array which includes a plurality of memory cells arranged in a matrix of rows and columns, wherein each memory cell includes at least one transistor having a gate, gate dielectric and first, second and body regions, wherein: (i) the body region of each transistor is electrically floating and (ii) the transistors of adjacent memory cells have a common first region and/or a common second region. Each common first region and/or second regions of transistors of adjacent memory cells includes a barrier disposed therein and/or therebetween, wherein each barrier provides a discontinuity in the common regions and/or includes one or more electrical characteristics that are different from one or more corresponding electrical characteristics of the common regions. | 2014-01-16 |
20140017869 | INDIUM, CARBON AND HALOGEN DOPING FOR PMOS TRANSISTORS - A method of forming an integrated circuit (IC) having at least one PMOS transistor includes performing PLDD implantation including co-implanting indium, carbon and a halogen, and a boron specie to establish source/drain extension regions in a substrate having a semiconductor surface on either side of a gate structure including a gate electrode on a gate dielectric formed on the semiconductor surface. Source and drain implantation is performed to establish source/drain regions, wherein the source/drain regions are distanced from the gate structure further than the source/drain extension regions. Source/drain annealing is performed after the source and drain implantation. The co-implants can be selectively provided to only core PMOS transistors, and the method can include a ultra high temperature anneal such as a laser anneal after the PLDD implantation. | 2014-01-16 |
20140017870 | Method for Inhibiting Programming Disturbance of Flash Memory - Disclosed herein is a method for inhibiting a programming disturbance of a flash memory, which relates to a technical field of a non-volatile memory in ultra-large-scale integrated circuit fabrication technologies. In the present invention, an dopant gradient of a PN junction between a substrate and a drain is reduced by adding a step of performing an angled ion implantation of donor dopants into a standard process for a flash memory, so that an electric field of the PN junction between the substrate and the drain is reduced, and consequently the programming disturbance is inhibited. Meanwhile, a dopant gradient of the PN junction between a channel and the drain is maintained, so that an electric field of the PN junction between the channel and the drain, which is necessary for programming, is maintained, and thus the programming efficiency and the programming speed can be ensured. The programming disturbance can be effectively inhibited without increasing numbers of masks used for photolithography according to the invention, thus the present invention is significantly advantageous to the improvement of the flash memory reliability. | 2014-01-16 |
20140017871 | Integrated circuit on SOI comprising a bipolar transistor with isolating trenches of distinct depths - An integrated circuit includes a semiconductor substrate, a silicon layer, a buried isolating layer arranged between the substrate and the layer, a bipolar transistor comprising a collector and emitter having a first doping, and a base and a base contact having a second doping, the base forming a junction with the collector and emitter, the collector, emitter, base contact, and the base being coplanar, a well having the second doping and plumb with the collector, emitter, base contact and base, the well separating the collector, emitter and base contact from the substrate, having the second doping and extending between the base contact and base, a isolating trench plumb with the base and extending beyond the layer but without reaching a bottom of the emitter and collector, and another isolating trench arranged between the base contact, collector, and emitter, the trench extending beyond the buried layer into the well. | 2014-01-16 |
20140017872 | METHOD FOR FABRICATING A METAL-INSULATOR-METAL CAPACITOR - A method for fabricating a metal-insulator-metal capacitor (MIMCap) is disclosed. A first metal layer is provided on top of an oxide layer. A nitride layer is then deposited on the first metal layer. The nitride layer and the first metal layer are etched to form a MIMCap metal layer. The gaps among the MIMCap metal layer are filled with a plasma oxide, and the excess plasma oxide is polished using the nitride layer a polish stop. After removing the nitride layer, a dielectric layer and a second metal layer are deposited on the MIMCap metal layer. Finally, the dielectric layer and the second metal layer are etched to form a set of MIMCap structures. | 2014-01-16 |
20140017873 | METHODS OF FORMING SEMICONDUCTOR STRUCTURES - A method of forming a semiconductor structure includes forming a through-substrate-via (TSV) structure in a substrate. The method includes forming a first etch stop layer over the TSV structure. The method further includes forming a first dielectric layer in contact with the first etch stop layer. The method still further includes forming a second etch stop layer in contact with the first dielectric layer. The method also includes forming a metal-insulator-metal (MIM) capacitor structure in contact with the second etch stop layer. The method further includes forming a first conductive structure through the first etch stop layer and the first dielectric layer, wherein the first conductive structure is electrically coupled with the TSV structure and the TSV structure is substantially wider than the first conductive structure. | 2014-01-16 |
20140017874 | SEMICONDUCTOR BODY WITH A BURIED MATERIAL LAYER AND METHOD - One aspect includes a method for forming a buried material layer in a semiconductor body, including providing a semiconductor body having a first side and having a plurality of first trenches extending from the first surface into the semiconductor body. Each of the plurality of first trenches has a bottom and has at least one sidewall and the plurality of first trenches is separated from one another by semiconductor mesa regions. A first material layer is formed on the bottom of each of the plurality of first trenches such that the first material layer leaves at least one segment of at least one sidewall of each of the plurality of trenches uncovered. Each of the plurality of first trenches is filled by epitaxially growing a semiconductor material from the at least one uncovered sidewall segment. After filling the first trenches, second trenches are formed in the mesa regions. | 2014-01-16 |
20140017875 | NON-VOLATILE SEMICONDUCTOR MEMORY DEVICE AND PROCESS OF MANUFACTURING THE SAME - In device isolation trenches, a first device-isolation insulator film is formed to have recesses thereon and a second device-isolation insulator film is formed in the recesses. The uppermost portions at both ends of the first device-isolation insulator film are located higher than the uppermost portions at both ends of the second device-isolation insulator film. | 2014-01-16 |
20140017876 | System on a Chip with On-Chip RF Shield - Structures of a system on a chip are disclosed. In one embodiment, the system on a chip (SoC) includes an RF component disposed on a first part of a substrate, a semiconductor component disposed on a second part of the substrate, the semiconductor component and the RF component sharing a common boundary, and a conductive cage disposed enclosing the RF component. The conductive cage shields the semiconductor component from electromagnetic radiation originating from the RF circuit. | 2014-01-16 |
20140017877 | METHOD FOR PERMANENTLY BONDING WAFERS - This invention relates to a method for bonding of a first contact surface of a first substrate to a second contact surface of a second substrate with the following steps, especially the following sequence:
| 2014-01-16 |
20140017878 | METHOD OF PROCESSING A DEVICE SUBSTRATE - Methods of processing a device substrate are disclosed herein. In one embodiment, a method of processing a device substrate can include bonding a first surface of a device substrate to a carrier with a polymeric material. The device substrate may have a plurality of first openings extending from the first surface towards a second surface of the device substrate opposite from the first surface. Then, material can be removed at the second surface of the device substrate, wherein at least some of the first openings communicate with the second surface at least one of before or after performing the removal of the material. Then, at least a portion of the polymeric material disposed between the first surface and the carrier substrate can be exposed to a substance through at least some first openings to debond the device substrate from the carrier substrate. | 2014-01-16 |
20140017879 | UNIFORM MASKING FOR WAFER DICING USING LASER AND PLASMA ETCH - Uniform masking for wafer dicing using laser and plasma etch is described. In an example, a method of dicing a semiconductor wafer having a plurality of integrated circuits having bumps or pillars includes uniformly spinning on a mask above the semiconductor wafer, the mask composed of a layer covering and protecting the integrated circuits. The mask is then patterned with a laser scribing process to provide a patterned mask with gaps, exposing regions of the semiconductor wafer between the integrated circuits. The semiconductor wafer is then etched through the gaps in the patterned mask to singulate the integrated circuits. | 2014-01-16 |