03rd week of 2014 patent applcation highlights part 16 |
Patent application number | Title | Published |
20140014979 | LIQUID CRYSTAL DISPLAY DEVICE AND MANUFACTURING METHOD THEREFOR - According to a manufacturing method for a liquid crystal display device according to this application, a first terminal hole ( | 2014-01-16 |
20140014980 | SEMICONDUCTOR LIGHT-EMITTING DEVICE - A reliable semiconductor light-emitting device can include a wavelength converting material in a cavity mounting at least one semiconductor light-emitting chip. The device can also include an encapsulating resin to cover the wavelength converting material so as to emit a wavelength-converted light using light emitted from the chip. The wavelength converting material should include a transparent resin having a large thermal expansion coefficient to maintain a high thermal resistance, and the encapsulating resin is subject to cracks due to a high transparent resin. The semiconductor device can be configured to form a space between the wavelength converting material and the encapsulating resin so that each of the encapsulating resin and the wavelength converting material cannot contact with each other even under a high temperature. Thus, the disclosed subject matter cannot stress in the encapsulating resin when the wavelength converting material expands, and therefore can provide the reliable semiconductor light-emitting device. | 2014-01-16 |
20140014981 | DISPLAY APPARATUS - A display apparatus including a display panel including a pixel electrode and a plurality of first signal lines transmitting a driving signal to the pixel electrode, a conductive member on the first signal lines, the conductive member having a resin, and a second signal line on the conductive member, the second signal line having an opening through which the resin travels to couple the second signal line with one of the first signal lines. | 2014-01-16 |
20140014982 | Liquid Crystal Display Panel and Repair Method Thereof - The present invention provides a LCD panel and a method for repairing the LCD panel. The LCD panel includes a plurality of data lines and a plurality of subpixel areas. Each subpixel area includes a corresponding pixel electrode and thin film transistor. The subpixel area including a spot defect is electrically connected to a neighboring subpixel area having the same color and in normal operation. The connection between the thin film transistor in the subpixel area including the spot defect and the corresponding data line and the connection between the thin film transistor and the corresponding pixel electrode are cut. Consequently, the subpixel area including the bright spot defect is repaired and able to display normally. The display quality of the LCD panel display is improved. Moreover, the present invention repair method is suitable for the repairing of LCD panels without storage capacitors. | 2014-01-16 |
20140014983 | LED-BASED LARGE AREA DISPLAY - An improved approach is described to implement an LED-based large area display which uses an array of single color solid state lighting elements (e.g. LEDs). In some embodiments, the panel comprises an array of blue LEDs, where each pixel of the array comprises three blue LEDs. An overlay is placed over the array of blue LEDs, where the overlay comprises a printed array of phosphor portions. Each pixel on the PCB comprised of three blue LEDs is matched to a corresponding portion of the overlay having the printed phosphor portions. The printed phosphor portions of the overlay includes a number of regions of blue light excitable phosphor materials that are configured to convert, by a process of photoluminescence, blue excitation light generated by the light sources into green or red and colored light. Regions of the overlay associated with generating blue light comprise an aperture/window that allows blue light to pass through the overlay. | 2014-01-16 |
20140014984 | LIGHTING MODULE FOR EMITTING MIXED LIGHT - A lighting module for emitting mixed light comprises at least one first semiconductor element which emits unconverted red light, at least one second semiconductor element which emits converted greenish white light having a first conversion percentage, at least one third semiconductor element which emits greenish white light having a second conversion percentage that is smaller than the first conversion percentage, and at least one resistor element having a temperature-dependent electric resistance, the second semiconductor element being connected in parallel to the third semiconductor element. | 2014-01-16 |
20140014985 | DISPLAY SUBSTRATE, ORGANIC ELECTROLUMINESCENT DISPLAY DEVICE, AND MANUFACTURING METHOD FOR DISPLAY SUBSTRATE AND ORGANIC ELECTROLUMINESCENT DISPLAY DEVICE - TFT substrate ( | 2014-01-16 |
20140014986 | LIGHT-EMITTING-ELEMENT MOUNT SUBSTRATE AND LED DEVICE - A light-emitting-element mount substrate formed by relatively simple manufacturing steps, having a good heat release property, and having a high mechanical strength; and an LED device including the light-emitting-element mount substrate are provided. A substrate body of a light-emitting-element mount substrate is made of a low-resistance semiconductor (e.g., n-type silicon) substrate, and is divided into a first and second individual substrate bodies by an insulating layer. A first front-surface mounting electrode and a first external-connection electrode are formed on respective first and second major surfaces (e.g., front and back surfaces) of the first individual substrate body. A second front-surface mounting electrode and a second external-connection electrode are formed respective first and second major surfaces (e.g., front and back surfaces) of the second individual substrate body. The insulating layer has a shape different from a straight-line shape in plan view. | 2014-01-16 |
20140014987 | METHODS AND APPARATUSES FOR SHIFTING CHROMATICITY OF LIGHT - The present disclosure relates to shifting a chromaticity of light generated from a light-emitting device. A light-emitting device may incorporate an optical element (e.g., filter) so that light emitted from a light-generating surface having an initial chromaticity may be altered. The optical element may shift the chromaticity of emitted light having the initial chromaticity to a final chromaticity that is different from the initial chromaticity. Thus, the chromaticity of emitted light from the manufactured LEDs that would otherwise be unacceptable for having chromaticity coordinates that fall outside of a desired chromaticity bin is shifted so as to have chromaticity coordinates that fall within suitable parameters. Accordingly, a number of the manufactured LEDs that would normally be discarded may be salvaged. | 2014-01-16 |
20140014988 | LIGHTING DEVICES INCLUDING PATTERNED OPTICAL COMPONENTS AND ASSOCIATED DEVICES, SYSTEMS, AND METHODS - Lighting devices including light-emitting diodes and associated devices, systems, and methods are disclosed herein. A lighting device configured in accordance with a particular embodiment includes a lighting-emitting diode and an optical component along a radiation path of the lighting-emitting diode. The optical component includes a color-converting material with walls defining a pattern, the walls extending generally entirely through a thickness of the color-converting material. A total surface area of the walls within a primary zone of the optical component is greater than a total surface area of color-converting features at a major side of the color-converting material. A method for making a lighting device in accordance with a particular embodiment includes combining an optical component and a light-emitting diode, and shaping a color-converting material of the optical component to have a thickness and a pattern of walls selected to control the color of light output from the lighting device. | 2014-01-16 |
20140014989 | Optoelectronic Semiconductor Chip and a Method for the Production Thereof - An optoelectronic semiconductor chip includes a semiconductor layer stack and a mirror. The semiconductor layer stack has an active layer for generating electromagnetic radiation. The mirror is arranged on an underside of the semiconductor layer stack. The mirror has a first region and a second region, the first region containing silver and the second region containing gold. A method of producing such a semiconductor chip is also defined. | 2014-01-16 |
20140014990 | LIGHT-EMITTING DEVICE PACKAGES AND METHODS OF MANUFACTURING THE SAME - Lights-emitting device (LED) packages, and methods of manufacturing the same, include at least one light-emitting structure. The at least one light-emitting structure includes a first compound semiconductor layer, an active layer, and a second compound semiconductor layer that are sequentially stacked, at least one first metal layer connected to the first compound semiconductor layer, a second metal layer connected to the second compound semiconductor layer, a substrate having a conductive bonding layer on a first surface of the substrate, and a bonding metal layer configured for eutectic bonding between the at least one first metal layer and the conductive bonding layer. | 2014-01-16 |
20140014991 | Light-Emitting Element with Window Layers Sandwiching Distributed Bragg Reflector - A light-emitting element includes a substrate; a light-emitting stacked layer on the substrate; a first window layer under the substrate; and a DBR under the first window layer; wherein the first window layer has a width substantially equal to that of the substrate in a cross-sectional view. | 2014-01-16 |
20140014992 | LED MOUNTING SUBSTRATE AND METHOD OF MANUFACTURING THE SAME - An LED mounting substrate includes a base substrate, a conductive pattern formed on the base substrate and including a recessed portion on an upper surface thereof, and a light reflecting film formed in an inter-pattern gap of the conductive pattern on the base substrate and in the recessed portion of the conductive pattern. | 2014-01-16 |
20140014993 | LIGHT-EMITTING DEVICE - A light-emitting device includes an LED chip, and a case including a sidewall portion that surrounds the LED chip so as to reflect a light emitted from the LED chip. The case further includes a resin that includes a glass fiber and is integrally formed by injection molding. An average length of the glass fiber is greater than a thickness of the sidewall portion. The resin has a refractive index different from the glass fiber. | 2014-01-16 |
20140014994 | OPTOELECTRONIC DEVICE AND THE MANUFACTURING METHOD THEREOF - An optoelectronic device comprising a substrate; a first window layer on the substrate, having a first sheet resistance, a first thickness, and a first impurity concentration; a second window layer having a second sheet resistance, a second thickness, and a second impurity concentration; and a semiconductor system between the first window layer and the second window layer; wherein the second window layer comprises a semiconductor material different from the semiconductor system, and the second sheet resistance is greater than the first sheet resistance. | 2014-01-16 |
20140014995 | OPTOELECTRONIC COMPONENT AND METHOD FOR PRODUCING AN OPTOELECTRONIC COMPONENT - An optoelectronic component includes a substrate, a semiconductor chip arranged on the substrate, and a light-transmissive cover, wherein the light-transmissive cover covers at least an area of the semiconductor chip facing away from the substrate, the light-transmissive cover has a hardness greater than that of silicone, and a connecting material is arranged as a potting material between the light-transmissive cover and the substrate such that those areas of the semiconductor chip not covered by the substrate are surrounded by the connecting material, and the connecting material forms a cavity seal. | 2014-01-16 |
20140014996 | ELECTROLUMINESCENCE DISPLAY DEVICE - Disclosed is an electroluminescence device having a substrate, a thin film transistor over the substrate, an insulating film over the thin film transistor, an electroluminescence element over the insulating film, a passivation film over the electroluminescence element, and a counter substrate over the passivation film. The electroluminescence element is configured to emit light through the counter substrate, and a space between the substrate and the counter substrate is filled with a filler. The electroluminescence device is featured by the tapered side surface of a gate electrode of the thin film transistor. | 2014-01-16 |
20140014997 | NITRIDE SEMICONDUCTOR LIGHT-EMITTING ELEMENT AND LIGHT SOURCE INCLUDING THE NITRIDE SEMICONDUCTOR LIGHT-EMITTING ELEMENT - A nitride semiconductor light-emitting element includes: n-side and p-side electrodes; n-type and p-type nitride semiconductor layers; and an active layer arranged between the n- and p-type nitride semiconductor layers. The p-type nitride semiconductor layer has a projection having a height of 30 nm to 50 nm. The projection is formed of a p-type nitride semiconductor including magnesium and silicon. The p-type nitride semiconductor has a silicon concentration of 1.0×10 | 2014-01-16 |
20140014998 | SEMICONDUCTOR LIGHT-EMITTING DEVICE - A semiconductor light-emitting device includes a substrate; a first cladding layer formed on the substrate; a first guide layer formed on the first cladding layer; an active layer formed on the first guide layer; a second guide layer formed on the active layer; a contact layer formed on the second guide layer; a cladding electrode formed on the contact layer, and made of conductive metal oxide; and a pad electrode electrically coupled to the cladding electrode. The semiconductor light-emitting device includes a mesa structure including the contact layer. The cladding electrode has a greater width than the mesa structure. The cladding electrode covers an upper surface and side surfaces of the mesa structure, and is electrically coupled to the contact layer. | 2014-01-16 |
20140014999 | SOLID STATE LIGHTING DEVICES WITH LOW CONTACT RESISTANCE AND METHODS OF MANUFACTURING - Solid state lighting (“SSL”) devices with improved contacts and associated methods of manufacturing are disclosed herein. In one embodiment, an SSL device includes a first semiconductor material, a second semiconductor material spaced apart from the first semiconductor material, and an active region between the first and second semiconductor materials. The SSL device also includes a contact on one of the first or second semiconductor materials. The contact includes a first conductive material and a plurality of contact elements in contact with one of the first or second conductive materials. The contact elements individually include a portion of a second conductive material that is different from the first conductive material. | 2014-01-16 |
20140015000 | RESIN COMPOSITION, RESIN SHEET, CURED RESIN SHEET, RESIN SHEET LAMINATE, CURED RESIN SHEET LAMINATE AND METHOD FOR PRODUCING SAME, SEMICONDUCTOR DEVICE AND LED DEVICE - The present invention provides a resin composition including an epoxy resin monomer, a novolac resin containing a compound having a structural unit represented by the following general Formula (I), and a filler, in which a particle size distribution of the filler, measured using laser diffractometry, has peaks in the respective ranges of from 0.01 μm to less than 1 μm, from 1 μm to less than 10 μm, and from 10 μm to 100 μm, and the filler contains boron nitride particles having particle sizes of from 10 μm to 100 μm. In the general Formula (I), R | 2014-01-16 |
20140015001 | THYRISTOR RANDOM ACCESS MEMORY DEVICE AND METHOD - Memory devices and methods of making memory devices are shown. Methods and configurations as shown provide folded and vertical memory devices for increased memory density. Methods provided reduce a need for manufacturing methods such as deep dopant implants. | 2014-01-16 |
20140015002 | MOS TRANSISTOR ON SOI PROTECTED AGAINST OVERVOLTAGES - A MOS transistor protected against overvoltages formed in an SOI-type semiconductor layer arranged on an insulating layer itself arranged on a semiconductor substrate including a lateral field-effect control thyristor formed in the substrate at least partly under the MOS transistor, a field-effect turn-on region of the thyristor extending under at least a portion of a main electrode of the MOS transistor and being separated there-from by said insulating layer, the anode and the cathode of the thyristor being respectively connected to the drain and to the source of the MOS transistor, whereby the thyristor turns on in case of a positive overvoltage between the drain and the source of the MOS transistor. | 2014-01-16 |
20140015003 | SEMICONDUCTOR DEVICE AND METHOD FOR MANUFACTURING SEMICONDUCTOR DEVICE - Disclosed herein are a semiconductor device, and a method for manufacturing the semiconductor device. The semiconductor device includes a semiconductor substrate, a base region formed on an upper region of an inside of the semiconductor substrate, at least one gate electrode that penetrates through the base region and has an inverted triangular shape, a gate insulating film formed to enclose an upper portion of the semiconductor substrate and the gate electrode, an inter-layer insulating film formed on an upper portion of the gate electrode and the gate insulating film, an emitter region formed inside the base region and on both sides of the gate electrode, an emitter metal layer formed on an upper portion of the base region and inter-layer insulating film, and a buffer region formed to enclose a lower portion of the gate electrode and to be spaced apart from the base region. | 2014-01-16 |
20140015004 | SEMICONDUCTOR DEVICE - On a main surface of a semiconductor substrate, an N | 2014-01-16 |
20140015005 | SINGLE CHIP IGNITER AND INTERNAL COMBUSTION ENGINE IGNITION DEVICE - Aspects of the invention are directed to a single chip igniter such that it is possible to realize a reduction in operating voltage, an increase in noise tolerance, a reduction in size, and a reduction in cost. By reducing the gate threshold voltage of a MOS transistor, and reducing the operating voltages of a current limiter circuit, an overheat detector circuit, a timer circuit, an overvoltage protection circuit, an input hysteresis circuit, and the like, it is possible to reduce the operating voltage of a single chip igniter. In some aspects of the invention, the effective gate voltage of the MOS transistor is 1V or more, and the channel length of the MOS transistor is 4 μm or less. Also, in some aspects of the invention, the thickness of a gate oxide film of the MOS transistor is 5 nm or more, 25 nm or less. | 2014-01-16 |
20140015006 | SEMICONDUCTOR DEVICE AND METHOD FOR MANUFACTURING SAME - An N type well (NW) is formed over a prescribed depth from a main surface of a semiconductor substrate (SUB), and a P type well (PW) and an N type drain region (ND) are formed in the N type well (NW). An N type source region (NS), an N+ type source region (NNS), and a P+ type impurity region (BCR) are formed in the P type well (PW). The N type source region (NS) is formed on a region situated directly below the N+ type source region (NNS), and not on a region situated directly below the type impurity region (BCR), and the P+ type impurity region (BCR) is in direct contact with the P type well (PW). | 2014-01-16 |
20140015007 | Semiconductor Device with Charge Carrier Lifetime Reduction Means - A semiconductor device includes a cell region having at least one device cell, wherein the at least one device cell includes a first device region of a first conductivity type. The semiconductor device further includes a drift region of a second conductivity type adjoining the first device region of the at least one device cell, a doped region of the first conductivity type adjoining the drift region, and charge carrier lifetime reduction means configured to reduce a charge carrier lifetime in the doped region of the first conductivity type. | 2014-01-16 |
20140015008 | Transient Voltage Suppressor Circuit, and Diode Device Therefor and Manufacturing Method Thereof - The present invention discloses a transient voltage suppressor (TVS) circuit, and a diode device therefor and a manufacturing method thereof. The TVS circuit is for coupling to a protected circuit to limit amplitude of a transient voltage which is inputted to the protected circuit. The TVS circuit includes a suppressor device and at least a diode device. The diode device is formed in a substrate, which includes: a well formed in the substrate; a separation region formed beneath the upper surface; a anode region and a cathode region, which are formed at two sides of the separation region beneath the upper surface respectively, wherein the anode region and the cathode region are separated by the separation region; and a buried layer, which is formed in the substrate below the well with a higher impurity density and a same conductive type as the well. | 2014-01-16 |
20140015009 | TUNNEL TRANSISTOR WITH HIGH CURRENT BY BIPOLAR AMPLIFICATION - A tunnel-effect transistor the drain region of which includes a first zone doped with a doping of a first type, and a second zone doped with a doping of a second type forming a junction with the first zone. | 2014-01-16 |
20140015010 | Drain Extended Field Effect Transistors and Methods of Formation Thereof - In an embodiment of the invention, a semiconductor device includes a first region having a first doping type, a channel region having the first doping type disposed in the first region, and a retrograde well having a second doping type. The second doping type is opposite to the first doping type. The retrograde well has a shallower layer with a first peak doping and a deeper layer with a second peak doping higher than the first peak doping. The device further includes a drain region having the second doping type over the retrograde well. An extended drain region is disposed in the retrograde well, and couples the channel region with the drain region. An isolation region is disposed between a gate overlap region of the extended drain region and the drain region. A length of the drain region is greater than a depth of the isolation region. | 2014-01-16 |
20140015011 | Novel Fabrication Technique for High Frequency, High Power Group III Nitride Electronic Devices - Fabrication methods of a high frequency (sub-micron gate length) operation of AlInGaN/InGaN/GaN MOS-DHFET, and the HFET device resulting from the fabrication methods, are generally disclosed. The method of forming the HFET device generally includes a novel double-recess etching and a pulsed deposition of an ultra-thin, high-quality silicon dioxide layer as the active gate-insulator. The methods of the present invention can be utilized to form any suitable field effect transistor (FET), and are particular suited for forming high electron mobility transistors (HEMT). | 2014-01-16 |
20140015012 | SOLID STATE IMAGING DEVICE, DRIVING METHOD OF THE SOLID STATE IMAGING DEVICE AND ELECTRONIC EQUIPMENT - A solid state imaging device including multiple unit pixels including a photoelectric converter generating electrical charge in accordance with incident light quantity and accumulating the charge, a first transfer gate transferring the accumulated charge, a charge holding region holding the transferred charge, a second transfer gate transferring the held charge, and a floating diffusion region converting the transferred charge into voltage; an intermediate charge transfer unit transferring, to the charge holding region, a charge exceeding a predetermined charge amount as a first signal charge; and a pixel driving unit setting the first transfer gate to a non-conducting state, set the second transfer gate to a conducting state, transfer the first signal charge to the floating diffusion region, set the second transfer gate to a non-conducting state, set the first transfer gate to a conducting state, and transfer the accumulated charge to the charge holding region as a second signal charge. | 2014-01-16 |
20140015013 | SOLID-STATE IMAGE PICKUP DEVICE, METHOD OF MANUFACTURING SOLID-STATE IMAGE PICKUP DEVICE, AND ELECTRONIC APPARATUS - There is provided a solid-state image pickup device including a semiconductor substrate, and a plurality of pixel portions that are provided on the semiconductor substrate. Each of the pixel portions includes a photoelectric converting unit that generates a charge on the basis of incident light, a memory unit that accumulates the charge generated by the photoelectric converting unit, a light shielding portion that shields at least the memory unit from light, a digging portion that digs into the semiconductor substrate between the photoelectric converting unit and the memory unit and is formed of a light shielding material, and a transmitting unit that transmits the charge from the photoelectric converting unit to the memory unit, by forming a channel for transmission in the digging portion. | 2014-01-16 |
20140015014 | FIELD EFFECT TRANSISTORS WITH VARYING THRESHOLD VOLTAGES - A method including providing a semiconductor substrate including a first semiconductor device and a second semiconductor device, the first and second semiconductor devices including dummy spacers, dummy gates, and extension regions; protecting the second semiconductor device with a mask; removing the dummy spacers from the first semiconductor device; and depositing in-situ doped epitaxial regions on top of the extension regions of the first semiconductor device. | 2014-01-16 |
20140015015 | FINFET DEVICE WITH A GRAPHENE GATE ELECTRODE AND METHODS OF FORMING SAME - One illustrative device disclosed herein includes at least one fin comprised of a semiconducting material, a layer of gate insulation material positioned adjacent an outer surface of the fin, a gate electrode comprised of graphene positioned on the layer of gate insulation material around at least a portion of the fin, and an insulating material formed on the gate electrode. | 2014-01-16 |
20140015016 | SEMICONDUCTOR STRUCTURE AND METHOD FOR FORMING THE SAME - A semiconductor structure and a method for forming the same are provided. The semiconductor structure includes a bulk, a gate, a source, a drain and a bulk contact region. The gate is on the bulk. The source and the drain are in the bulk on opposing sides of the gate respectively. The bulk contact region is only in a region of the bulk adjacent to the source. The bulk contact region is electrically connected to the bulk. | 2014-01-16 |
20140015017 | HIGH VOLTAGE SEMICONDUCTOR DEVICE AND THE ASSOCIATED METHOD OF MANUFACTURING - The present disclosure discloses a high voltage semiconductor device and the associated methods of manufacturing. In one embodiment, the high voltage semiconductor device comprises: an epitaxial layer, a first low voltage well formed in the epitaxial layer; a second low voltage well formed in the epitaxial layer; a high voltage well formed in the epitaxial layer, wherein the second low voltage well is surrounded by the high voltage well; a first highly doping region formed in the first low voltage well; a second highly doping region and a third highly doping region formed in the second low voltage well, wherein the third highly doping region is adjacent to the second highly doping region; a field oxide formed in the epitaxial layer as a shallow-trench isolation structure; and a gate region formed on the epitaxial layer. | 2014-01-16 |
20140015018 | SEMICONDUCTOR DEVICE AND METHOD OF FABRICATING THE SAME - A semiconductor device having a dummy active region for metal ion gathering, which is capable of preventing device failure due to metal ion contamination, and a method of fabricating the same are provided. The semiconductor device includes active regions defined by an isolation layer in a semiconductor substrate and ion-implanted with an impurity, and a dummy active region ion-implanted with an impurity having a concentration higher than that of the impurity in the active region and configured to gather metal ions. | 2014-01-16 |
20140015019 | SEMICONDUCTOR DEVICE - The reliability of a field effect transistor made of a nitride semiconductor material is improved. An ohmic electrode includes a plurality of unit electrodes isolated to be separated from each other. With this configuration, an on-state current can be prevented from flowing in the unit electrodes in a y-axial direction (negative direction). Further, in the respective unit electrodes, a current density of the on-state current flowing in the y-axial direction (negative direction) can be prevented from increasing. As a result, an electromigration resistance of the ohmic electrode can be improved. | 2014-01-16 |
20140015020 | METHOD FOR FORMING N-SHAPED BOTTOM STRESS LINER - Semiconductor devices with n-shaped bottom stress liners are formed. Embodiments include forming a protuberance on a substrate, conformally forming a sacrificial material layer over the protuberance, forming a gate stack above the sacrificial material layer on a silicon layer, removing the sacrificial material layer to form a tunnel, and forming a stress liner in the tunnel conforming to the shape of the protuberance. Embodiments further include forming a silicon layer over the sacrificial material layer and lining the tunnel with a passivation layer prior to forming the stress liner. | 2014-01-16 |
20140015021 | FLOATING BODY MEMORY CELL HAVING GATES FAVORING DIFFERENT CONDUCTIVITY TYPE REGIONS - A method for fabricating floating body memory cells (FBCs), and the resultant FBCs where gates favoring different conductivity type regions are used is described. In one embodiment, a p type back gate with a thicker insulation is used with a thinner insulated n type front gate. Processing, which compensates for misalignment, which allows the different oxide and gate materials to be fabricated is described. | 2014-01-16 |
20140015022 | SEMICONDUCTOR DEVICE HAVING RING-SHAPED GATE ELECTRODE, DESIGN APPARATUS, AND PROGRAM - A semiconductor device includes: a substrate; a transistor that has a ring-shaped gate electrode formed on the substrate; a plurality of external dummy electrodes that are arranged outside the gate electrode and are formed in the same layer as the gate electrode; and at least one internal dummy electrode that is arranged inside the gate electrode and is formed in the same layer as the gate electrode. | 2014-01-16 |
20140015023 | SUBSTRATE HAVING A CHARGED ZONE IN AN INSULATING BURIED LAYER - Embodiments of the invention relate to substrates comprising a base wafer, an insulating layer and a top semiconductor layer, wherein the insulating layer comprises at least a zone wherein a density of charges is in absolute value higher than 10 | 2014-01-16 |
20140015024 | SOLID-STATE IMAGE PICKUP DEVICE - According to one embodiment, a solid-state image pickup device includes a photoelectric converter, transfer, reset and amplifier transistors and a floating diffusion layer formed on a semiconductor substrate. The photoelectric converter coverts incident light to a signal charge. The transfer transistor transfers the signal charge converted by the photoelectric converter. The floating diffusion layer stores the signal charge transferred by the transfer transistor. The reset transistor resets the signal charge stored in the floating diffusion layer. The amplifier transistor amplifies the signal charge stored in the floating diffusion layer. Source and drain regions of the reset transistor, and its channel region are formed in an L-shape on the semiconductor substrate. | 2014-01-16 |
20140015025 | IMAGE SENSORS INCLUDING CHANNEL STOP REGIONS SURROUNDING PHOTODIODES AND METHODS OF FABRICATING THE SAME - Image sensors are provided. In the image sensor, an area of a device isolation layer may be reduced and elements may be isolated from each other by a channel stop region extending between the photoelectric conversion region and the device isolation layer, such that a dark current property of the image sensor may be improved. | 2014-01-16 |
20140015026 | IMAGE SENSORS INCLUDING WELL REGIONS OF DIFFERENT CONCENTRATIONS - An image sensor includes a high concentration well region in contact with a device isolation layer extending along a periphery of a photoelectric converting part, which can improve dark current properties of the image sensor. The image sensor also includes a low concentration well region in contact with a sidewall of the device isolation layer overlapped with a transfer gate, which can improve image lag properties of the image sensor. Related fabrication methods are also discussed. | 2014-01-16 |
20140015027 | SEMICONDUCTOR DEVICE HAVING GATE ELECTRODE EMBEDDED IN GATE TRENCH - Disclosed herein is a device that includes: a substrate having a gate trench; a gate electrode embedded in the gate trench with an intervention of a gate insulation film; and an embedded insulation film embedded in the gate trench. The substrate includes a first impurity diffusion region in contact with the embedded insulation film and a second impurity diffusion region in contact with the gate insulation film. The gate trench including a first trench portion extending in a first direction and second and third trench portions branching from the first trench portion and extending in a second direction that crosses the first direction. The gate electrode including first, second and third electrode portions embedded in the first, second and third trench portions of the gate trench, respectively. The first impurity diffusion region being sandwiched between the second and third electrode portions. | 2014-01-16 |
20140015028 | MICROELECTRONIC MEMORY DEVICES HAVING FLAT STOPPER LAYERS - Memory devices comprise a lower layer that extends across a cell array region and across a peripheral region and that includes a flat outer surface from the cell array region to the peripheral region. A signal transfer conductor layer extends in the cell array region beneath the flat outer surface of the lower layer and extends in the peripheral region above the flat outer surface of the lower layer. An insulating layer is provided on the lower layer, including a flat outer surface from the cell array region to the peripheral region. A flat stopper layer is provided on the flat outer surface of the insulating layer and extending across the cell array region and the peripheral region. Related methods are also provided. | 2014-01-16 |
20140015029 | SEMICONDUCTOR DEVICE AND METHOD OF FABRICATING THE SAME - A semiconductor device includes two floating gates, a control gate and a first dielectric layer. The floating gates are disposed on a semiconductor substrate. The control gate partially overlaps each of the floating gates, and a part of the control gate is disposed between the two floating gates. Furthermore, the first dielectric layer disposed between the two floating gates and the control gate has a fixed thickness. | 2014-01-16 |
20140015030 | SEMICONDUCTOR DEVICES AND METHODS OF FABRICATING THE SAME - A semiconductor device includes a lower insulating pattern on a semiconductor substrate, a lower gate pattern on the lower insulating pattern and formed of a doped polysilicon layer, a residual insulating pattern with an opening exposing a portion of a top surface of the lower gate pattern, an upper gate pattern on the residual insulating pattern, the upper gate pattern filling the opening, and a diffusion barrier pattern in contact with the portion of the top surface of the lower gate pattern and extending between the residual insulating pattern and the upper gate pattern. | 2014-01-16 |
20140015031 | Apparatus and Method for Memory Device - An apparatus comprises a gate stack formed over a substrate, wherein the gate stack comprises a first gate structure, wherein a first dielectric layer is formed between the first gate structure and the substrate and a second gate structure stacked on the first gate structure, wherein a second dielectric layer is formed between the first gate structure and the second gate structure. The apparatus further comprises a first drain/source region and a first recess formed between a top surface of the first drain/source region and the second dielectric layer. | 2014-01-16 |
20140015032 | INTEGRATED CIRCUIT MEMORY DEVICES HAVING VERTICAL TRANSISTOR ARRAYS THEREIN AND METHODS OF FORMING SAME - An integrated circuit device includes a transistor array having a vertical stack of independently controllable gate electrodes therein. A first semiconductor channel region is provided, which extends on a first sidewall of the vertical stack of independently controllable gate electrodes. A first electrically insulating layer is also provided, which extends between the first semiconductor channel region and the first sidewall of the vertical stack of independently controllable gate electrodes. Source and drain regions are provided, which are electrically coupled to first and second ends of the first semiconductor channel region, respectively. | 2014-01-16 |
20140015033 | NONVOLATILE SEMICONDUCTOR STORAGE DEVICE AND METHOD OF MANUFACTURE THEREOF - A nonvolatile semiconductor storage device including a number of memory cells formed on a semiconductor substrate, each of the memory cells has a tunnel insulating film, a charge storage layer, a block insulating film, and a gate electrode which are formed in sequence on the substrate. The gate electrode is structured such that at least first and second gate electrode layers are stacked. The dimension in the direction of gate length of the second gate electrode layer, which is formed on the first gate electrode layer, is smaller than the dimension in the direction of gate length of the first gate electrode layer. | 2014-01-16 |
20140015034 | VERTICAL SEMICONDUCTOR DEVICE, MODULE AND SYSTEM EACH INCLUDING THE SAME, AND METHOD FOR MANUFACTURING THE VERTICAL SEMICONDUCTOR DEVICE - A vertical semiconductor device having a vertical channel region is disclosed. The vertical semiconductor device includes a pillar having a vertical channel region, a bit line buried in a semiconductor substrate located at a lower part of the pillar, and a body connection unit configured to couple at least one sidewall of the pillar to the semiconductor substrate. As a result, the floating body effect of the vertical semiconductor device can be more effectively removed. | 2014-01-16 |
20140015035 | SEMICONDUCTOR DEVICE HAVING VERTICAL TRANSISTOR - Disclosed herein is a semiconductor device that includes: a semiconductor pillar projecting from a main surface of the semiconductor substrate, the semiconductor pillar having a first side surface extending in a first direction that is parallel to the main surface of the semiconductor substrate and a second side surface extending in a second direction crossing to the first direction and parallel to the main surface of the semiconductor substrate; a first impurity diffusion layer formed in an upper portion of the semiconductor pillar; a second impurity diffusion layer formed in the semiconductor substrate near a lower portion of the semiconductor pillar; an insulating pillar covering the first side surface; and a gate electrode covering the second side surface with an intervention of a gate insulating film. A width in the first direction of the semiconductor pillar is narrowed at the first side surface. | 2014-01-16 |
20140015036 | TRENCHED AND IMPLANTED ACCUMULATION MODE METAL-OXIDE-SEMICONDUCTOR FIELD-EFFECT TRANSISTOR - The present invention provides AccuFETs with single or dual accumulation channels and methods for manufacturing the same. The present invention also provides for products produced by the methods of the present invention and for apparatuses used to perform the methods of the present invention. | 2014-01-16 |
20140015037 | Novel Metal/Polysilicon Gate Trench Power Mosfet - The present disclosure relates to a power MOSFET device having a relatively low resistance hybrid gate electrode that enables good switching performance. In some embodiments, the power MOSFET device has a semiconductor body. An epitaxial layer is disposed on the semiconductor body. A hybrid gate electrode, which controls the flow of electrons between a source electrode and a drain electrode, is located within a trench extending into the epitaxial layer. The hybrid gate electrode has an inner region having a low resistance metal, an outer region having a polysilicon material, and a barrier region disposed between the inner region and the outer region. The low resistance of the inner region provides for a low resistance to the hybrid gate electrode that enables good switching performance for the power MOSFET device. | 2014-01-16 |
20140015038 | Apparatus and Method for Power MOS Transistor - A MOS transistor comprises a substrate, a first region formed over the substrate, a second region grown from the first region, a third region of formed in the second region, a first drain/source region formed in the third region, a first gate electrode formed in a first trench, a second drain/source region formed in the second region and on an opposite side of the first trench from the first drain/source region and a second trench coupled between the second drain/source region and the second region, wherein the second trench is of a same depth as the first trench. | 2014-01-16 |
20140015039 | METHOD OF MAKING AN INSULATED GATE SEMICONDUCTOR DEVICE HAVING A SHIELD ELECTRODE STRUCTURE AND STRUCTURE THEREFOR - In one embodiment, a semiconductor device includes a multi-portion shield electrode structure formed in a drift region. The shield electrode includes a wide portion formed in proximity to a channel side of the drift region, and a narrow portion formed deeper in the drift region. The narrow portion is separated from the drift region by a thicker dielectric region, and the wide portion is separated from the drift region by a thinner dielectric region. That portion of the drift region in proximity to the wide portion can have a higher dopant concentration than other portions of the drift region. | 2014-01-16 |
20140015040 | POWER SEMICONDUCTOR DEVICE AND FABRICATION METHOD THEREOF - A power semiconductor device includes a substrate, a semiconductor layer grown on the substrate, a plurality of alternately arranged first conductivity type doping trenches and second conductivity type doping trenches in the semiconductor substrate, a first diffusion region of the first conductivity type around each of the first conductivity type doping trenches, and a second diffusion region of the second conductivity type around each of the second conductivity type doping trenches, wherein distance between an edge of the first conductivity type doping trench and PN junction between the first and second diffusion regions substantially equals to a distance between an edge of the second conductivity type doping trench and the PN junction. | 2014-01-16 |
20140015041 | TRENCH GATE MOSFET - A trench gate MOSFET is provided. An epitaxial layer is disposed on a substrate. A body layer is disposed in the epitaxial layer. The epitaxial layer has a first trench therein, the body layer has a second trench therein, and the first trench is disposed below the second trench. A first conductive layer is disposed in the first trench. A first insulating layer is disposed between the first conductive layer and the epitaxial layer. A second conductive layer is disposed on a sidewall of the second trench. A second insulating layer is disposed between the second conductive layer and the body layer, and between the second conductive layer and the first conductive layer. A dielectric layer is disposed on the epitaxial layer and fills up the second trench. Two doped regions are disposed in the body layer respectively beside the second trench. | 2014-01-16 |
20140015042 | SEMICONDUCTOR DEVICE AND THE METHOD OF MANUFACTURING THE SAME - A semiconductor device includes a p-type well region | 2014-01-16 |
20140015043 | SEMICONDUCTOR DEVICE AND METHOD OF FABRICATING THE SAME - A semiconductor device includes active regions defined by a device isolation layer, gates disposed in the active regions of cell channel regions, word lines disposed on the gates and extending along a first direction, and gate contacts configured to connect the gates to the word lines. The gates have a box shape which extends over two active regions. | 2014-01-16 |
20140015044 | SEMICONDUCTOR DEVICE AND METHOD FOR MANUFACTURING SAME - According to an embodiment, a semiconductor device includes a second semiconductor layer provided on a first semiconductor layer and including first pillars and second pillars. A first control electrode is provided in a trench of the second semiconductor layer and a second control electrode is provided on the second semiconductor layer and connected to the first control electrode. A first semiconductor region is provided on a surface of the second semiconductor layer except for a portion under the second control electrode. A second semiconductor region is provided on a surface of the first semiconductor region, the second semiconductor region being apart from the portion under the second control electrode and a third semiconductor region is provided on the first semiconductor region. A first major electrode is connected electrically to the first semiconductor layer and a second major electrode is connected electrically to the second and the third semiconductor region. | 2014-01-16 |
20140015045 | Apparatus and Method for Power MOS Transistor - A power MOS transistor comprises a drain contact plug formed over a first side of a substrate, a source contact plug formed over a second side of the substrate and a trench formed between the first drain/source region and the second drain/source region. The trench comprises a first gate electrode, a second gate electrode, wherein top surfaces of the first gate electrode and the second gate electrode are aligned with a bottom surface of drain region. The trench further comprises a field plate formed between the first gate electrode and the second gate electrode, wherein the field plate is electrically coupled to the source region. | 2014-01-16 |
20140015046 | Current Sense Transistor with Embedding of Sense Transistor Cells - A semiconductor device a field of transistor cells integrated in a semiconductor body. A number of the transistor cells forming a power transistor and at least one of the transistor cells forming a sense transistor. A first source electrode is arranged on the semiconductor body electrically connected to the transistor cell(s) of the sense transistor but electrically isolated from the transistor cells of the power transistor. A second source electrode is arranged on the semiconductor body and covers the transistor cells of both the power transistor and the sense transistor, and at least partially covering the first source electrode in such a manner that the second source electrode is electrically connected only to the transistor cells of the power transistor but electrically isolated from the transistor cells of the sense transistor. | 2014-01-16 |
20140015047 | Integrated Circuit Having a Vertical Power MOS Transistor - An integrated circuit comprises a plurality of lateral devices and quasi vertical devices formed in a same semiconductor die. The quasi vertical devices include two trenches. A first trench is formed between a first drain/source region and a second drain/source region. The first trench comprises a dielectric layer formed in a bottom portion of the first trench and a gate region formed in an upper portion of the first trench. A second trench is formed on an opposite side of the second drain/source region from the first trench. The second trench is coupled between the second drain/source region and a buried layer, wherein the second trench is of a same depth as the first trench. | 2014-01-16 |
20140015048 | FinFET with Trench Field Plate - An integrated circuit device includes a pad layer having a body portion with a first doping type laterally adjacent to a drift region portion with a second doping type, a trench formed in the pad layer, the trench extending through an interface of the body portion and the drift region portion, a gate formed in the trench and over a top surface of the pad layer along the interface of the body portion and the drift region portion, an oxide formed in the trench on opposing sides of the gate, and a field plate embedded in the oxide on each of the opposing sides of the gate. | 2014-01-16 |
20140015049 | SEMICONDUCTOR DEVICE - An LDMOSFET includes a semiconductor substrate having a first semiconductor region formed of a feeding region of a first conduction type at a position where a field oxide film is not present on a surface layer of a semiconductor region in which the field oxide film is selectively formed, and a second semiconductor region formed of a well region of a second conduction type which is an opposite conduction type, and feeding regions of the first and second conduction types formed on an upper layer of the well region, and a gate electrode that faces the well region through a gate oxide film. The feeding region is formed at a distance from the field oxide film in an end portion in a longitudinal direction, and desirably the feeding region is intermittently formed at given intervals in the longitudinal direction, and the feeding region is applied to the first semiconductor region. | 2014-01-16 |
20140015050 | SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD THEREOF - In a semiconductor device, a logic MOSFET and a switch MOSFET are formed in a high-resistance substrate. The logic MOSFET includes an epitaxial layer formed on the high-resistance substrate and a well layer formed on the epitaxial layer. The switch MOSFET includes a LOCOS oxide film formed on the high-resistance substrate, the LOCOS oxide film being sandwiched between trenches and thus having a mesa-shape in its upper part. The switch MOSFET further includes a buried oxide film and a SOI layer formed on the mesa-shape of the LOCOS oxide film. The upper surface of the mesa-shape of the LOCOS oxide film is positioned at the same height as the upper surface of the epitaxial layer. | 2014-01-16 |
20140015051 | METHOD OF REPLACING SILICON WITH METAL IN INTEGRATED CIRCUIT CHIP FABRICATION - A method of replacing semiconductor material with metal, Replacement Metal Gate Field Effect Transistors (RMG FETs) and Contacts (RMCs), and Integrated Circuit (IC) chips including the FETs and/or RMCs. A patterned semiconductor layer, e.g., silicon, is formed on a dielectric layer, e.g., a layered gate dielectric. A field dielectric layer fills between shapes in the patterned semiconductor layer. Metal is deposited on the shapes. The wafer is annealed to replace semiconductor in each shape with metal to form metal FET gates or contacts. | 2014-01-16 |
20140015052 | ON-SOI integrated circuit comprising a thyristor (SCR) for protection against electrostatic discharges - An integrated circuit includes an UTBOX insulating layer under and plumb with first and second electronic components, and corresponding ground planes and oppositely-doped wells made plumb with them. The wells contact with corresponding ground planes. A pair of oppositely doped bias electrodes, suitable for connecting corresponding bias voltages, contacts respective wells and ground planes. A third electrode contacts the first well. A first trench isolates one bias electrode from the third electrode and extends through the layer and into the first well. A second trench isolates the first bias electrode from one component. This trench has an extent that falls short of reaching an interface between the first ground plane and the first well. | 2014-01-16 |
20140015053 | SELF-PROTECTED METAL-OXIDE-SEMICONDUCTOR FIELD-EFFECT TRANSISTOR - Device structures, design structures, and fabrication methods for a metal-oxide-semiconductor field-effect transistor. A gate structure is formed on a top surface of a substrate. First and second trenches are formed in the substrate adjacent to a sidewall of the gate structure. The second trench is formed laterally between the first trench and the first sidewall. First and second epitaxial layers are respectively formed in the first and second trenches. A contact is formed to the first epitaxial layer, which serves as a drain. The second epitaxial layer in the second trench is not contacted so that the second epitaxial layer serves as a ballasting resistor. | 2014-01-16 |
20140015054 | FIELD EFFECT TRANSISTOR DEVICES HAVING THICK GATE DIELECTRIC LAYERS AND THIN GATE DIELECTRIC LAYERS - A semiconductor device includes a substrate, a fin arranged on the substrate, a first field effect transistor (FET) comprising a first gate stack disposed over the a portion of the fin, the first gate stack including a polysilicon layer and a silicide material disposed on the polysilicon layer, and an epitaxial material disposed over portions of the fin, the epitaxial material defining source and drain regions of the first FET, and a second effect transistor (FET) comprising a second gate stack disposed over the a portion of the fin, the second gate stack including a metal gate material layer, and an epitaxial material disposed over portions of the fin, the epitaxial material defining source and drain regions of the second FET. | 2014-01-16 |
20140015055 | FINFET STRUCTURES AND METHODS FOR FABRICATING THE SAME - A method is disclosed for fabricating an integrated circuit in a replacement-gate process flow utilizing a dummy-gate structure overlying a plurality of fin structures. The method includes removing the dummy-gate structure to form a first void space, depositing a shaper material to fill the first void space, removing a portion of the plurality of fin structures to form a second void space, epitaxially growing a high carrier mobility material to fill the second void space, removing the shaper material to form a third void space, and depositing a replacement metal gate material to fill the third void space. | 2014-01-16 |
20140015056 | MULTI-GATE MOSFET AND PROCESS THEREOF - A multi-gate MOSFET includes a substrate, a dielectric layer and at least a fin-shaped structure. The substrate has a first area and a second area. The dielectric layer is only located in the substrate of the first area. At least a fin-shaped structure is located on the dielectric layer. Moreover, the present invention also provides a multi-gate MOSFET process forming said multi-gate MOSFET. | 2014-01-16 |
20140015057 | SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING THE SAME - A semiconductor device includes a cell structure; n first pad structures formed on one side of the cell structure and each configured to have a step form in which 2n layers form one stage; and n second pad structures formed on the other side of the cell structure each configured to have a step form in which 2n layers form one stage, wherein n is a natural number of 1 or higher, and the first pad structures and the second pad structures have asymmetrical step forms having different heights. | 2014-01-16 |
20140015058 | WORK FUNCTION ADJUSTMENT IN A HIGH-K GATE ELECTRODE STRUCTURE AFTER TRANSISTOR FABRICATION BY USING LANTHANUM - The work function of a high-k gate electrode structure may be adjusted in a late manufacturing stage on the basis of a lanthanum species in an N-channel transistor, thereby obtaining the desired high work function in combination with a typical conductive barrier material, such as titanium nitride. For this purpose, in some illustrative embodiments, the lanthanum species may be formed directly on the previously provided metal-containing electrode material, while an efficient barrier material may be provided in the P-channel transistor, thereby avoiding undue interaction of the lanthanum species in the P-channel transistor. | 2014-01-16 |
20140015059 | SEMICONDUCTOR DEVICE INCLUDING PILLAR TRANSISTORS - A first pillar transistor and a second pillar transistor are arranged with no other pillar transistor therebetween, a distance between a first silicon pillar in the first pillar transistor and a second silicon pillar in the second pillar transistor is smaller than a distance between a third silicon pillar in a third pillar transistor and the first silicon pillar. | 2014-01-16 |
20140015060 | STRESS ENHANCED CMOS CIRCUITS AND METHODS FOR THEIR MANUFACTURE - A method for fabricating a stress enhanced CMOS circuit includes forming a first plurality of MOS transistors at a first pitch and forming a second plurality of MOS transistors at a second pitch. The second pitch is larger than the first pitch. The method further includes depositing a single stress liner overlying the first and second plurality of MOS transistors. The single stress liner is the only stress liner deposited in the fabrication of the stress enhanced CMOS circuit. A stress enhanced CMOS circuit includes a first plurality of MOS transistors formed at a first pitch and a second plurality of MOS transistors formed at a second pitch. The second pitch is larger than the first pitch. The circuit further includes a single stress liner overlying the first and second plurality of MOS transistors. The single stress liner is the only stress liner formed on the stress enhanced CMOS circuit. | 2014-01-16 |
20140015061 | METHODS AND STRUCTURES FOR MULTIPORT MEMORY DEVICES - A memory device includes a storage unit formed using a substrate, a true bit line BL | 2014-01-16 |
20140015062 | Method for Forming Gate Structure, Method for Forming Semiconductor Device, and Semiconductor Device - An embodiment of the present disclosure provides a method for forming a gate structure, comprising: providing a substrate, where the substrate includes a nMOSFET area and a pMOSFET area, each of the nMOSFET area and the pMOSFET area has a gate trench, and each of the gate trenches is provided at a bottom portion with a gate dielectric layer; forming a gate dielectric capping layer on a surface of the substrate; forming an oxygen scavenging element layer on the gate dielectric capping layer; forming an etching stop layer on the oxygen scavenging element layer; forming a work function adjustment layer on the etching stop layer; performing metal layer deposition and annealing process to fill the gate trenches with a metal layer; and removing the metal layer outside the gate trenches. | 2014-01-16 |
20140015063 | Method for Forming Gate Structure, Method for Forming Semiconductor Device, and Semiconductor Device - A method for forming a gate structure, comprising: providing a substrate, where the substrate includes a nMOSFET area and a pMOSFET area, each of the nMOSFET area and the pMOSFET area has a gate trench, and each of the gate trenches is provided at a bottom portion with a gate dielectric layer; forming a gate dielectric capping layer on the substrate; forming an etching stop layer on the gate dielectric capping layer; forming an oxygen scavenging element layer on the etching stop layer; forming a first work function adjustment layer on the oxygen scavenging element layer; etching the first work function adjustment layer above the nMOSFET area; forming a second work function adjustment layer on the surface of the substrate; metal layer depositing and annealing to fill the gate trenches with a metal layer; and removing the metal layer outside the gate trenches. | 2014-01-16 |
20140015064 | CMOS DEVICES AND FABRICATION METHOD - A method is provided for fabricating a CMOS device. The method includes providing a semiconductor substrate having a first active region and a second active region. The method also includes forming a first trench on the first active region using a first barrier layer and a second substitute gate electrode layer to protect a gate region on the second active region, followed by forming a first work function layer and a first metal gate in the first trench. Further, the method includes forming a second trench on the second active region using a second barrier layer to protect the first metal gate structure, followed by forming a second work function layer and a second metal gate in the second trench. | 2014-01-16 |
20140015065 | CMOS DEVICE AND FABRICATION METHOD - Various embodiments provide complementary metal-oxide-semiconductor (CMOS) devices and their fabrication methods. A semiconductor substrate is provided to include a first region to form a PMOS transistor and a second region to form an NMOS transistor. One of the first and second regions can include a metal gate structure having a metal top layer. The other of the first and second regions can include an interfacial oxide layer formed on a high-k dielectric layer. A surface of the metal top layer can be oxidized to form a metal oxide top layer covering the metal top layer. The metal oxide top layer and the interfacial oxide layer can be removed by wet etching. A metal gate can be formed on the high-k dielectric layer. | 2014-01-16 |
20140015066 | SEMICONDUCTOR ELECTRONIC COMPONENTS WITH INTEGRATED CURRENT LIMITERS - An electronic component includes a high-voltage depletion-mode transistor and a low-voltage enhancement-mode transistor. A source electrode of the high-voltage depletion-mode transistor is electrically connected to a drain electrode of the low-voltage enhancement-mode transistor, and a gate electrode of the high-voltage depletion-mode transistor is electrically coupled to the source electrode of the low-voltage enhancement-mode transistor. The on-resistance of the enhancement-mode transistor is less than the on-resistance of the depletion-mode transistor, and the maximum current level of the enhancement-mode transistor is smaller than the maximum current level of the depletion-mode transistor. | 2014-01-16 |
20140015067 | SOURCE/DRAIN EXTENSION CONTROL FOR ADVANCED TRANSISTORS - A planar transistor with improved performance has a source and a drain on a semiconductor substrate that includes a substantially undoped channel extending between the source and the drain. A gate is positioned over the substantially undoped channel on the substrate. Implanted source/drain extensions contact the source and the drain, with the implanted source/drain extensions having a dopant concentration of less than about 1×10 | 2014-01-16 |
20140015068 | Gate Structure, Semiconductor Device and Methods for Forming the Same - The disclosure relates to a gate structure, a semiconductor device and methods for forming the same. An embodiment of the disclosure provides a method for forming a gate structure, including: providing a substrate; forming an interface layer on the substrate; forming a gate dielectric layer on the interface layer; forming a gate dielectric capping layer on the gate dielectric layer; forming an etching stop layer on the gate dielectric capping layer; forming an oxygen scavenging element layer on the etching stop layer; forming an oxygen scavenging element capping layer on the oxygen scavenging element layer; performing Post-Metallization Annealing; performing etching until the etching stop layer is exposed; forming a work function adjustment layer on the etching stop layer; and forming a gate layer on the work function adjustment layer. | 2014-01-16 |
20140015069 | MEMS Devices, Packaged MEMS Devices, and Methods of Manufacture Thereof - MEMS devices, packaged MEMS devices, and methods of manufacture thereof are disclosed. In one embodiment, a microelectromechanical system (MEMS) device includes a first MEMS functional structure and a second MEMS functional structure. An interior region of the second MEMS functional structure has a pressure that is different than a pressure of an interior region of the first MEMS functional structure. | 2014-01-16 |
20140015070 | COMPONENT HAVING A MICROMECHANICAL MICROPHONE PATTERN - A microphone component has a micromechanical microphone pattern which is implemented in a layer construction on a semiconductor substrate and includes (i) an acoustically active diaphragm which at least partially spans a sound opening on the backside of the substrate, (ii) at least one movable electrode of a microphone capacitor system, and (iii) a stationary acoustically penetrable counterelement having through holes, which counterelement is situated in the layer construction over the diaphragm and functions as the carrier for at least one immovable electrode of the microphone capacitor system. The diaphragm is tied in to the semiconductor substrate in a middle area, and the diaphragm has a corrugated sheet metal type of corrugation, at least in regions. | 2014-01-16 |
20140015071 | ENCAPSULATED MICRO-ELECTRO-MECHANICAL DEVICE, IN PARTICULAR A MEMS ACOUSTIC TRANSDUCER - An encapsulated micro-electro-mechanical device, wherein a MEMS chip is encapsulated by a package formed by a first, a second, and a third substrates that are bonded together. The first substrate has a main surface bearing the MEMS chip, the second substrate is bonded to the first substrate and defines a chamber surrounding the MEMS chip, and the third substrate is bonded to the second substrate and upwardly closes the chamber. A grid or mesh structure of electrically conductive material is formed in or on the third substrate and overlies the MEMS chip; the second substrate has a conductive connection structure coating the walls of the chamber, and the first substrate incorporates an electrically conductive region, which forms, together with the conductive layer and the grid or mesh structure, a Faraday cage. | 2014-01-16 |
20140015072 | ELECTRONIC DEVICE PACKAGES AND METHODS OF MANUFACTURING THE SAME - The electronic device package includes a package substrate including a frame portion and a cantilever portion surrounded by the frame portion, at least one semiconductor chip mounted on the cantilever portion, and a molding member disposed on the package substrate to cover the at least one semiconductor chip. The cantilever portion has a first edge connected to the frame portion and declines from the first edge toward a second edge located opposite to the first edge. Related methods are also provided. | 2014-01-16 |
20140015073 | THERMALLY STABLE MAGNETIC TUNNEL JUNCTION CELL AND MEMORY DEVICE INCLUDING THE SAME - A thermally stable Magnetic Tunnel Junction (MTJ) cell, and a memory device including the same, include a pinned layer having a pinned magnetization direction, a separation layer on the pinned layer, and a free layer on the separation layer and having a variable magnetization direction. The pinned layer and the free layer include a magnetic material having Perpendicular Magnetic Anisotropy (PMA). The free layer may include a central part and a marginal part on a periphery of the central part. The free layer is shaped in the form of a protrusion in which the central part is thicker than the marginal part. | 2014-01-16 |
20140015074 | PRECESSIONAL REVERSAL IN ORTHOGONAL SPIN TRANSFER MAGNETIC RAM DEVICES - Orthogonal spin-torque bit cells whose spin torques from a perpendicular polarizer and an in-plane magnetized reference layer are constructively or destructively combined. An orthogonal spin-torque bit cell includes a perpendicular magnetized polarizing layer configured to provide a first spin-torque; an in-plane magnetized free layer and a reference layer configured to provide a second spin-torque. The first spin-torque and the second spin-torque combine and the combined first spin-torque and second spin-torque influences the magnetic state of the in-plane magnetized free layer. The in-plane magnetized free layer and the reference layer form a magnetic tunnel junction. The first spin-torque and second spin-torque can combine constructively to lower a switching current, increase a switching speed, and/or torque decrease an operating energy of the orthogonal spin-torque bit cell. | 2014-01-16 |
20140015075 | MAGNETIC MEMORY WITH SEPARATE READ AND WRITE PATHS - Magnetic memory having separate read and write paths is disclosed. The magnetic memory unit includes a ferromagnetic strip having a first end portion with a first magnetization orientation, an opposing second end portion with a second magnetization orientation, and a middle portion between the first end portion and the second end portion, the middle portion having a free magnetization orientation. The first magnetization orientation opposes the second magnetization orientation. A tunneling barrier separates a magnetic reference layer from the middle portion forming a magnetic tunnel junction. A bit line is electrically coupled to the second end portion. A source line is electrically coupled to the first end portion and a read line is electrically coupled to the magnetic tunnel junction. | 2014-01-16 |
20140015076 | PERPENDICULAR STTMRAM DEVICE WITH BALANCED REFERENCE LAYER - A spin toque transfer magnetic random access memory (STTMRAM) element comprises a reference layer, which can be a single layer structure or a synthetic multi-layer structure, formed on a substrate, with a fixed perpendicular magnetic component. A junction layer is formed on top of the reference layer and a free layer is formed on top of the junction layer with a perpendicular magnetic orientation, at substantially its center of the free layer and switchable. A tuning layer is formed on top of the free layer and a fixed layer is formed on top of the tuning layer, the fixed layer has a fixed perpendicular magnetic component opposite to that of the reference layer. The magnetic orientation of the free layer switches relative to that of the fixed layer. The perpendicular magnetic components of the fixed layer and the reference layer substantially cancel each other and the free layer has an in-plane edge magnetization field. | 2014-01-16 |
20140015077 | REDUCING SOURCE LOADING EFFECT IN SPIN TORQUE TRANSFER MAGNETORESISTIVE RANDOM ACCESS MEMORY (STT-MRAM) - A memory cell comprises a magnetic tunnel junction (MTJ) structure that includes a free layer coupled to a bit line and a pinned layer. A magnetic moment of the free layer is substantially parallel to a magnetic moment of the pinned layer in a first state and substantially antiparallel to the magnetic moment of the pinned layer in a second state. The pinned layer has a physical dimension to produce an offset magnetic field corresponding to a first switching current of the MTJ structure to enable switching between the first state and the second state when a first voltage is applied from the bit line to a source line coupled to an access transistor and a second switching current to enable switching between the second state and the first state when the first voltage is applied from the source line to the bit line. | 2014-01-16 |
20140015078 | SPIN TRANSFER TORQUE MAGNETIC RANDOM ACCESS MEMORY (STTMRAM) HAVING GRADED SYNTHETIC FREE LAYER - A spin transfer torque memory random access memory (STTMRAM) element is capable of switching states when electrical current is applied thereto for storing data and includes the following layers. An anti-ferromagnetic layer, a fixed layer formed on top of the anti-ferromagnetic layer, a barrier layer formed on top of the second magnetic layer of the fixed layer, and a free layer including a first magnetic layer formed on top of the barrier layer, a second magnetic layer formed on top of the first magnetic layer, a nonmagnetic insulating layer formed on top of the second magnetic layer and a third magnetic layer formed on top of the non-magnetic insulating layer. A capping layer is formed on top of the non-magnetic insulating layer. | 2014-01-16 |