03rd week of 2015 patent applcation highlights part 32 |
Patent application number | Title | Published |
20150016141 | LIGHT EMITTING PANEL ASSEMBLIES AND LIGHT GUIDES THEREFOR - A light emitting panel assembly is provided. The assembly includes: a light source; a transition area including a first major side and a second major side, wherein at least one of the first major side and the second major side includes a plurality of vertically extending flutes, wherein the flutes extend at least a portion of the height of the transition area; and an emission area in optical communication with the transition area, the emission area including light extraction elements. | 2015-01-15 |
20150016142 | LIGHTING MODULE AND OPTICAL FIBER LIGHTING DEVICE USING THE SAME - A lighting module comprises a first light source, a second light source and a phosphor element is provided. The first light source emits a first exciting light. The second light source emits a second exciting light. The phosphor element converts the first exciting light and the second exciting light to an emission light. The first exciting light and the second exciting light are input to the phosphor element in different directions of incidence. | 2015-01-15 |
20150016143 | LIGHTING ASSEMBLY - A lighting assembly includes a light guide having opposed major surfaces between which light propagates by total internal reflection and a light input edge. The light assembly also includes a light engine. The light engine has a heat conductive armature having a receptacle for a portion of the light guide that includes the light input edge and a light source retained by and thermally coupled to the armature. The armature functions as a heat sink for dissipating heat generated by the light source. The light guide is mechanically retained in the receptacle, and the light guide and the armature cooperate to align the light input edge with the light source for inputting light from the light source into the light guide through the light input edge. | 2015-01-15 |
20150016144 | Functional Support with Button Functions - A process for producing a multifunctional functional support in which operating elements or display elements are arranged. The process includes flexible transparent plastic film supplied from a roll; the flat plastic film is placed into an injection mold, and is backmolded to form a rigid support structure-on a first side, wherein in the region of the operating elements or display elements it remains exposed in the form of at least two clearances; on the second side the plastic film is flooded in the same injection mold with a transparent curing casting compound in an RIM process to form a transparent surface layer, membrane regions that are flexible at least in places being formed in the region of the clearances; operating elements or display elements are placed into the clearances and joined to the plastic support. | 2015-01-15 |
20150016145 | Display Device - A backlight unit includes a light source having an emission region, a wiring board having the light source mounted thereon, a light guide plate having a side surface into which light from the light source enters, and a front surface from which the light exits, a light shielding adhesive tape adhering to the wiring board, and an optical sheet which overlaps with the front surface of the light guide plate. The front surface of the light guide plate includes an effective region serving as a planar light source and a light entering region ranging from the side surface to the effective region. The wiring board and the light-shielding adhesive tape each have a part positioned in the light entering region, and the optical sheet is arranged from the effective region to the light entering region. An end portion of the optical sheet overlaps with the light-shielding tape. | 2015-01-15 |
20150016146 | ILLUMINATING DEVICE AND LIQUID CRYSTAL DISPLAY APPARATUS - An illuminating device includes light emitting elements extending in a lengthwise direction and a light guide plate having a first principal surface for emitting light from the light emitting elements and a second principal surface facing the first principal surface. The light guide plate has light guide regions corresponding to the light emitting elements. The light emitting elements overlap the light guide plate on a side of the second principal surface of the light guide plate in plan view. The side of the second principal surface of the light guide plate has first sectional surfaces, on which light originated from each of the light emitting elements is incident. The side of the second principal surface of the light guide plate has second sectional surfaces, each having a reflection surface for reflecting the light originated from each light emitting element toward the first sectional surface, corresponding to the light emitting elements. | 2015-01-15 |
20150016147 | LED TUBE WITH LIGHT REFLECTIVE FACE - An LED tube includes a light guide, an LED and a reflector. The light guide includes a light incident face at an end thereof and a light emerging face adjacent to the light incident face. The reflector is mounted on an opposite end of the light guide. The reflector forms a light reflective face facing the light guide to reflect light backward into the light guide. | 2015-01-15 |
20150016148 | LIGHT GUIDING PLATE AND LIGHT GUIDING DEVICE INCLUDING THE SAME - A light guiding plate and a light guiding device are provided, and the light guiding plate is implemented in the light guiding device. The light guiding device includes a side light source emitting light to the light guiding plate. The light guiding plate includes a first surface, a second surface and a third surface. The second surface is opposite to the first surface, and the third surface is adjacent to the first surface and the second surface. The second surface includes plural light guiding units, and each of the light guiding units includes a total reflection concavity and a light emitting convexity. The light emitting convexity surrounds the total reflection concavity. | 2015-01-15 |
20150016149 | Lighting Device - The invention relates to a lighting device comprising a light source, a light source support, and a cover that extends longitudinally along a longitudinal axis between a first end and a second end. Each of the first and second ends includes an opening and the light source support is adapted to be moved in part or in full through a said opening. The lighting device also has a closure member for closing at least one of the openings at the first and second ends, the closure member being movable between a closed position and an open position, and a connector ( | 2015-01-15 |
20150016150 | MULTI-PHASE CONVERTER - Disclosed is a multi-phase converter comprising a plurality of electric phases, each of which can be triggered by a switching means. At least one coupling means ( | 2015-01-15 |
20150016151 | BJT DRIVE SCHEME - The invention generally relates to switch mode power converters (SMPCs). and methods for providing supplementary base drive to a bipolar transistor of an SMPC, and more particularly to a switching control circuit for a SMPC, a said SMPC having an inductive component coupled to receive power from an input to the SMPC, a bipolar transistor coupled to control current flow in the inductive component, an auxiliary power rail, a charge store for supplying power via the auxiliary rail to a switching control circuit for driving the bipolar transistor, and a bootstrap circuit for bleeding current from the input to the bipolar transistor to thereby provide an amplified current to the charge store, the switching control circuit comprising: a base current line for coupling to a base terminal of a said bipolar transistor, an emitter current line for coupling to an emitter terminal of a said bipolar transistor, an auxiliary line for coupling to a said auxiliary power rail, and at least one reference line for coupling to a reference voltage; a base current switch configured to controllably couple a base current source to the base current line; an emitter current switch configured to controllably couple the emitter current line to a said reference line; a bootstrap element for bleeding current from the emitter current line to the auxiliary line, the bootstrap element further operable to block a said current according to a current or voltage bias; a base discharge switch configured to controllably bleed current from the base current line to a said reference line; and a supplementary base drive line for coupling to a series circuit comprising a supplementary base drive resistor and current control element coupled in series, a said series circuit for bleeding current from a said input to a said base terminal, a said current control element for blocking current flow from a said bootstrap circuit to a said supplementary base drive resistor. | 2015-01-15 |
20150016152 | POWER SUPPLY APPARATUS AND IMAGE FORMING APPARATUS - The power supply apparatus includes a transformer; a switching unit that causes two switching elements connected in series to drive the primary winding of the transformer; a detection unit that detects current flowing on the primary side of the transformer; a correction unit that corrects a detection result of the detection unit according to an input voltage input into the transformer; and a nonlinear correction unit that corrects the detection result such that correction by the correction unit is nonlinear to the input voltage. | 2015-01-15 |
20150016153 | PULSE MODE ACTIVE CLAMPING - An active clamp circuit includes a clamp capacitance and a clamp switch coupled in a circuit path, and a diode coupled across the clamp switch. | 2015-01-15 |
20150016154 | PEAK SAMPLE CIRCUIT FOR AC VOLTAGE AND METHOD THEREOF - A peak sample circuit for AC voltage, including: a rectifier coupled to receive an AC voltage and to rectify the AC voltage to generate a rectified signal; a delay circuit coupled to receive the rectified signal and to delay the rectified signal to generate a delayed rectified signal; a comparison circuit coupled to receive the delayed rectified signal and to generate a square signal based on the comparison of the rectified signal and the delayed rectified signal; and a sample output circuit coupled to receive the rectified signal, wherein the sample output circuit samples the rectified signal under the control of the square signal and provides a peak sample signal representative of the peak value of the AC voltage. | 2015-01-15 |
20150016155 | POWER SUPPLY APPARATUS - A power conversion circuit connected to a three phase alternating current line is controlled in a PWM system. To control an arm corresponding to each phase, first to third carrier wave signals are generated. The first to third carrier wave signals include two signals having phases, respectively, offset by 180 degrees from each other. This allows a zero phase component to less frequently reach a peak value and be accordingly reduced as time averaged. This can reduce a zero phase harmonic component generated from a power supply apparatus. | 2015-01-15 |
20150016156 | COMPOSITE AC-TO-DC POWER CONVERTER WITH BOOSTING CAPABILITIES - A boosting AC-to-DC converter may include a main rectifier, first and second auxiliary rectifiers, and an autotransformer. The autotransformer may include a plurality of winding assemblies each having a primary terminal connected to an AC power source, a main secondary terminal connected to the main rectifier, a first auxiliary secondary terminal connected to the first auxiliary rectifier, and a second auxiliary secondary terminal connected to the second auxiliary rectifier. Impedance between the primary terminal of each of the winding assemblies and the main rectifier is less than impedance between the primary terminal of each of the winding assemblies and either the first auxiliary rectifier or the second auxiliary rectifier. Impedance between the primary terminal of each of the first winding assemblies and the first auxiliary rectifier is different from impedance between the primary terminal of each of the winding assemblies and the second auxiliary rectifier. | 2015-01-15 |
20150016157 | Constant switching frequency discontinuous current mode average output current control scheme - The constant switching frequency discontinuous current mode average output current control scheme is composed of a reference block, reference calculation block, state detecting block, error detector block, zero state detector, power driver block and internal clock. The reference block generates preset reference; The reference calculation block, based on the power current converter's power topology, the correspondent algorithm is calculated to convert the input reference from the reference block into correspondent output; It is the output of reference calculation block that makes state detecting block, error detector block, zero state detector, power driver block and internal clock operate together and control the power current converter's output following with the output of reference block | 2015-01-15 |
20150016158 | METHOD FOR PROVIDING LOW VOLTAGE DC POWER FROM AC MAINS POWER - According to one aspect, embodiments of the invention provide a power supply system comprising an input line configured to receive input AC power, a first capacitor coupled to the input line, a second capacitor, a controller, a rectifier having an input coupled to the first capacitor and an output coupled to the second capacitor, the second capacitor further coupled to the controller, and a switch selectively coupled across the first capacitor, and configured to selectively bypass the first capacitor, wherein the controller is configured to detect a voltage across the second capacitor, operate the switch to charge the second capacitor at a first rate if the voltage is above a predetermined threshold, and operate the switch to charge the second capacitor at a second rate if the voltage is below a predetermined threshold. | 2015-01-15 |
20150016159 | Multiphase Power Converter Circuit and Method - A multiphase power converter circuit includes at least two single phase power converter circuits. Each single phase power converter circuit includes at least one converter series circuit with a number of converter units. The converter series circuit is configured to output a series circuit output current. A synchronization circuit is configured to generate at least one synchronization signal. At least one of the converter units is configured to generate an output current such that at least one of a frequency and a phase of the output current is dependent on the synchronization signal. | 2015-01-15 |
20150016160 | POWER CONVERTER - A power converter includes inverters, AC sides of the inverters being connected in parallel, and a controller configured to control total output power of the inverters by controlling output power of at least one of the inverters in a control cycle shorter than a shortest communication cycle which allows communication with each of the inverters. | 2015-01-15 |
20150016161 | POWER CONVERTER - A power converter includes inverters, AC sides of the inverters being connected in parallel, a power command value determiner configured to determine a first power command value and a second power command value, the first power command value being lower than a proportional division power value obtained by proportionally dividing a required power value required as total output power of the inverters based on respective rated outputs of the inverters, the second power command value being higher than the proportional division power value, and a controller configured to control output powers of the inverters at the first power command value and the second power command value determined by the power command value determiner. | 2015-01-15 |
20150016162 | PHOTOVOLTAIC INVERTER WITH SWINGING LINE FILTER INDUCTORS - The invention is a high efficiency single-phase or poly-phase DC-to-AC power converter apparatus and power conversion method which includes a line filter inductor or line filter inductors to integrate or filter pulse modulated waveforms into substantially sinusoidal waveforms wherein (i) the line filter inductor or inductors have inductance values that swing substantially from zero current to peak rated current and (ii) a pulse width modulation technique is used that varies both pulse width modulation duty cycles and periods as a function of the predicted instantaneous line filter inductance and the predicted di/dt across the line filter inductor or inductors in order to minimize power converter switching losses while maintaining AC power quality. With the invention, substantial CEC power conversion efficiency enhancements should be achievable and with an overall reduction in power converter parts cost. | 2015-01-15 |
20150016163 | DETECTOR AND A VOLTAGE CONVERTER - A detector for detecting an occurrence of a current strength of interest of a current of a signal to be sensed includes a magnetoresistive structure and a detection unit. The magnetoresistive structure varies a resistance depending on a magnetic field caused by the current of the signal to be sensed. Further, the detection unit generates and provides a current detection signal indicating an occurrence of the current strength of interest based on a detected magnitude of the varying resistance of the magnetoresistive structure. | 2015-01-15 |
20150016164 | HIGH-VOLTAGE POWER SUPPLY APPARATUS AND IMAGE FORMING APPARATUS - The high-voltage power supply apparatus includes an inductor to be applied with a voltage when a driving unit is driven by a drive signal at a predetermined frequency, a rectification unit connected to both ends of the inductor, the rectification unit including multiple capacitors and multiple diodes, a current detection unit configured to detect a current flowing through the rectification unit, and a control unit configured to control a duty of the drive signal based on a result of detection by the current detection unit. | 2015-01-15 |
20150016165 | GATED THYRISTOR POWER DEVICE - An improved gated thyristor that utilizes less silicon area than IGBT, BIPOLARs or MOSFETs sized for the same application is provided. Embodiments of the inventive thyristor have a lower gate charge, and a lower forward drop for a given current density. Embodiments of the thyristor once triggered have a latch structure that does not have the same Cgd or Ccb capacitor that must be charged from the gate, and therefore the gated thyristor is cheaper to produce, and requires a smaller gate driver, and takes up less space than standard solutions. Embodiments of the inventive thyristor provide a faster turn off speed than the typical >600 ns using a modified MCT structure which results in the improved tail current turn off profile (<250 ns). Additionally, series resistance of the device is reduced without comprising voltage blocking ability is achieved. Finally, a positive only gate drive means is taught as is a method to module the saturation current using the gate terminal. | 2015-01-15 |
20150016166 | Line Current Reference Generator - The invention generally relates to the field of power factor correction and specifically to generation of a reference waveform which is proportional to line voltage and is controllable in amplitude. | 2015-01-15 |
20150016167 | Multilevel Converter - A multilevel converter for performing a DC to AC or an AC to DC voltage conversion as provided. The multilevel converter has a first DC terminal and a second DC terminal, a first converter arm and a second converter arm, wherein each converter arm comprises at least one converter cell, at least one AC terminal and an electric component. The first converter arm, the electric component and the second converter arm are connected in series between the first DC terminal and the second DC terminal. The electric component is connected between the first converter arm and the second converter arm. | 2015-01-15 |
20150016168 | HIGHLY STABLE MAXIMUM POWER POINT TRACKING FOR BIPOLAR PHOTOVOLTAIC INVERTERS - The invention is a method of tracking the overall maximum power point of a grounded bipolar photovoltaic array by tracking and regulating the voltage of the weaker of the two monopolar subarrays at any instant in time. The transfer between subarrays being tracked for the maximum power point is seamless when the voltage of one subarray becomes lower than the other. This tracking method insures stable operation and maximum power transfer under all balanced and unbalanced PV array conditions. This tracking algorithm would typically be part of a larger digital power converter control system. | 2015-01-15 |
20150016169 | MULTILEVEL INVERTERS AND THEIR COMPONENTS - A multilevel inverter includes a first half bridge in series with a second half bridge, each comprising a switch having a channel. The switch is configured to block a substantial voltage in a first direction during a first mode of operation, to conduct substantial current through the channel in the first direction during a second mode of operation, and to conduct substantial current through the channel in a second direction during a third mode of operation. During the third mode of operation, a gate of the switch is biased relative to a source of the switch at a voltage that is less than a threshold voltage of the switch. The inverter may also include a third half bridge. The inverter can be configured such that in operation, switches of the third half bridge are switched at a substantially lower frequency than the switches of the first and second half bridges. | 2015-01-15 |
20150016170 | METHOD FOR CONTROLLING A MULTIPHASE CONVERTER - A method for controlling a polyphase inverter that includes a number of half bridges connected into an intermediate voltage circuit and center taps between switching elements. By cyclically switching the switching elements, the respective center taps of the half bridges are connected to an upper intermediate circuit rail or to a lower intermediate circuit rail of the intermediate voltage circuit according to the principle of pulse width modulation. The switching elements of at least one half bridge are driven in a modified manner, at least in some time intervals, in that the switching pulses of at least two consecutive periods of the pulse width modulation are concatenated directly in time as one switching pulse. In this way, the switching frequencies of the correspondingly driven switching elements and thus the switching losses of the latter can be further reduced. | 2015-01-15 |
20150016171 | TRACTION CONVERTER AND RAILWAY VEHICLE - The present invention equalizes the temperatures of semiconductor elements and efficiently cools the semiconductor elements in a lightweight device configuration, by optimally combining the configurations of heat radiation fins in accordance with the configuration of the semiconductor elements. A traction converter includes plural semiconductor elements included in a traction converting circuit and a cooler to radiate heat from the plural semiconductor elements to outside air, the cooler including a heat receiving block, plural heat pipes and plural heat radiation fins, the plural semiconductor elements being arrayed on one surface of the heat receiving block, heat receiving parts of the plural heat pipes being buried in the opposite surface of the heat receiving block, heat radiation parts of the plural heat pipes being erectly provided so as to protrude from the heat receiving block, the plural heat radiation fins being joined to the heat radiation parts. In the cooler, three semiconductor elements are provided in a cooling wind flow direction, and, when a region at which the plural heat radiation fins are provided is divided in the cooling wind flow direction into three of an up-wind region, a mid-wind region and a down-wind region, a heat radiation fin surface area at the up-wind region is in a range of 0.33 to 0.42 times of a heat radiation fin surface area at the down-wind region, and a heat radiation fin surface area at the mid-wind region is in a range of 0.42 to 0.63 times of the heat radiation fin surface area at the down-wind region. | 2015-01-15 |
20150016172 | QUERY OPERATIONS FOR STACKED-DIE MEMORY DEVICE - An integrated circuit (IC) package includes a stacked-die memory device. The stacked-die memory device includes a set of one or more stacked memory dies implementing memory cell circuitry. The stacked-die memory device further includes a set of one or more logic dies electrically coupled to the memory cell circuitry. The set of one or more logic dies includes a query controller and a memory controller. The memory controller is coupleable to at least one device external to the stacked-die memory device. The query controller is to perform a query operation on data stored in the memory cell circuitry responsive to a query command received from the external device. | 2015-01-15 |
20150016173 | ROM Chip Manufacturing Structures - An integrated circuit (IC) chip embodiment includes first and second ROM cells arranged in a same row of a ROM array. The first and second ROM cells include first portions of first and second gate structures, respectively. The IC chip further includes a strap cell disposed between the first and second ROM cells. The strap cell includes second portions of the first and second gate structures. The first gate structure is physically separated from the second gate structure. | 2015-01-15 |
20150016174 | INTEGRATED CIRCUITS WITH PROGRAMMABLE ELECTRICAL CONNECTIONS AND METHODS FOR FABRICATING THE SAME - Methods and apparatus are provided for an integrated circuit with a programmable electrical connection. The apparatus includes an inactive area with a memory line passing over the inactive area. The memory line includes a programmable layer. An interlayer dielectric is positioned over the memory line and the inactive area, and an extending member extends through the interlayer dielectric. The extending member is electrically connected to the programmable layer of the memory line at a point above the inactive area. | 2015-01-15 |
20150016175 | CMOS Analog Memories Utilizing Ferroelectric Capacitors - A memory cell and memories constructed from that memory cell are disclosed. A memory according to the present invention includes a ferroelectric capacitor, a charge source and a read circuit. The charge source receives a data value to be stored in the ferroelectric capacitor. The charge source converts the data value to a remanent charge to be stored in the ferroelectric capacitor and causes that remanent charge to be stored in the ferroelectric capacitor. The read circuit determines a charge stored in the ferroelectric capacitor. The data value has more than three distinct possible states, and the determined charge has more than three determined values. The memory also includes a reset circuit that causes the ferroelectric capacitor to enter a predetermined known reference state of polarization. | 2015-01-15 |
20150016176 | MEMORY STORAGE CIRCUIT AND METHOD OF DRIVING MEMORY STORAGE CIRCUIT - A memory storage circuit includes a volatile memory portion, a control portion, and a non-volatile memory portion. The volatile memory portion includes a first node and a second node to store a pair of complementary logic data. The control portion includes a first transistor and a second transistor. Gate electrodes of the first and second transistors are coupled to receive a store signal, and first electrodes of the first and second transistors are coupled to receive a control signal. The non-volatile memory portion includes a first resistive memory element and a second resistive memory element to store the pair of complementary logic data. The first resistive memory element is coupled between a second electrode of the first transistor and the first node, and the second resistive memory element is coupled between a second electrode of the second transistor and the second node. | 2015-01-15 |
20150016177 | NONVOLATILE SEMICONDUCTOR MEMORY DEVICE - A nonvolatile semiconductor memory device according to an embodiment comprises: a memory cell array including a plurality of memory cells provided one at each of intersections of a plurality of first lines and a plurality of second lines and each storing data by a data storing state of a filament; and a control circuit configured to execute a write sequence that writes data to the memory cell, the write sequence including: a setting operation that applies a setting pulse having a first polarity to the memory cell; and a removing operation that applies a removing pulse having a second polarity opposite to the first polarity to the memory cell; and the control circuit, during execution of the write sequence, is configured to repeatedly execute the setting operation until the memory cell attains a desired data storing state, and then to execute the removing operation. | 2015-01-15 |
20150016178 | All around electrode for novel 3D RRAM applications - A resistive switching memory device can include three or more electrodes interfacing a switching layer, including a top electrode, a bottom electrode, and a side electrode. The top and bottom electrodes can be used for forming conductive filaments and for reading the memory device. The side electrode can be used to control the resistance state of the switching layer. | 2015-01-15 |
20150016179 | MEMORY CIRCUIT - While the supply of power is stopped, a data signal that has been held in a volatile memory section can be held in a nonvolatile memory section. In the nonvolatile memory section, a transistor having an extremely low off-state current allows a data signal to be held in the capacitor for a long period of time. Thus, the nonvolatile memory section can hold the logic state even while the supply of power is stopped. When the supply of power is started again, the data signal that has been held in the capacitor while the supply of power has been stopped is set at such a potential that malfunction does not occur by turning on the reset circuit. | 2015-01-15 |
20150016180 | MEMORY ARCHITECTURES HAVING DENSE LAYOUTS - Some embodiments relate to a memory cell to store one or more bits of data. The memory cell includes a capacitor including first and second capacitor plates which are separated from one another by a dielectric. The first capacitor plate corresponds to a doped region disposed in a semiconductor substrate, and the second capacitor plate is a polysilicon or metal layer arranged over the doped region. The memory cell also includes a transistor laterally spaced apart from the capacitor and including a gate electrode arranged between first and second source/drain regions. An interconnect structure is disposed over the semiconductor substrate and couples the gate electrode of the transistor to the second capacitor plate. | 2015-01-15 |
20150016181 | MEMORY DEVICE AND DRIVING METHOD OF THE MEMORY DEVICE - A memory device which can reduce power consumption and a driving method thereof are disclosed. In a memory element including an inverter and the like, a capacitor for holding data and a capacitor switching element for controlling store and release of charge in the capacitor are provided. The capacitor switching element is designed so that the off-state current is sufficiently low. Therefore, even when power supply of the inverter is stopped after charge corresponding to data is stored in the capacitor, data can be held for a long period of time. In order to return data, potentials of output and input terminals of the inverter are set to a precharge potential, then charge in the capacitor is released, and power is supplied to the inverter. A switching element for supplying the precharge potential may be provided. | 2015-01-15 |
20150016182 | SRAM MEMORY CARD AND VOLTAGE MONITORING CIRCUIT - An SRAM memory card includes a monitoring unit that monitors, via a contact, a power supply voltage generated by a battery, set an ON value in an alarm signal when electric potential at the contact is lower than a threshold and set an OFF value in the alarm signal when the electric potential at the contact is equal to or higher than the threshold, and output the alarm signal to an apparatus via an interface unit; a detecting unit that detects an ON/OFF state of the power supply of the apparatus via the interface unit; and a discharge circuit that discharges, according to the ON/OFF state of the power supply of the apparatus detected by the detecting unit, charges accumulated in a first electrode of a capacitive element. | 2015-01-15 |
20150016183 | SENSE AMPLIFIER WITH TRANSISTOR THRESHOLD COMPENSATION - One embodiment provides, in a sense amplifier for an electronic memory array in which a selected memory cell drives a developing voltage differential according to a logic state of the memory cell, a method to store the logic state. The method includes poising source voltages of first and second transistors at levels offset, respectively, by threshold voltages of the first and second transistors. The method also includes applying the voltage differential between a gate of the first transistor and a gate of the second transistor, the first and second transistors configured to oppose each other in a cross-coupled inverter stage of the sense amplifier. | 2015-01-15 |
20150016184 | MAGNETIC FIELD SENSING USING MAGNETORESISTIVE RANDOM ACCESS MEMORY (MRAM) CELLS - A magnetic field sensing system includes one or more magnetoresistive random access memory (MRAM) cells, and may be configured to determine one or more of a presence, a magnitude, and a polarity of an external magnetic field incident upon an MRAM cell. In some examples, a control module of the system controls a write current source. Of another device, to provide a write current through a write line associated with the MRAM cell to induce a magnetic field proximate to the MRAM cell. The magnetic field may be less than a magnetic switching threshold of the MRAM cell. After initiating the provision of the write current through the write line, the control module may determine a magnetic state of the MRAM cell, and determine a presence of an external magnetic field incident upon the MRAM cell based at least in part on the magnetic state of the MRAM cell. | 2015-01-15 |
20150016185 | Electro-Mechanical Diode Non-Volatile Memory Cell For Cross-Point Memory Arrays - A non-volatile electro-mechanical diode memory cell is described for implementation of compact (4F | 2015-01-15 |
20150016186 | METHODS AND APPARATUSES FOR DETERMINING THRESHOLD VOLTAGE SHIFT - Apparatuses and methods for determining threshold voltage shift are described. A number of methods for determining threshold voltage shift in memory cells include determining changes in threshold voltage for memory cells at each data state of a first number of data states by searching threshold voltage data of memory cells programmed to the first number of data states and determining changes in threshold voltage for memory cells at each data state of a second number of data states by searching threshold voltage data of memory cells programmed to the second number of data states within a range of threshold voltages, wherein the range is shifted from a previous range based on the changes in threshold voltage for memory cells programmed to the first number of data states. | 2015-01-15 |
20150016187 | ASYMMETRIC LOG-LIKELIHOOD RATIO FOR FLASH CHANNEL - Disclosed is a system and method for reading a flash memory cell with an adjusted read level. A current read level is set to a new read level associated with increasing a first error rate to decrease a second error rate. The first error rate is associated with determining that the most significant bit of the flash memory cell is a binary 1 and the second error rate is associated with determining that the most significant bit is a binary 0. On reading the memory cell, a probability value is generated for the most significant bit, the probability being higher if the bit is equivalent to a binary 0 than if the bit is equivalent to a binary 1. | 2015-01-15 |
20150016188 | Method for Managing the Operation of a Memory Device Having a SRAM Memory Plane and a Non Volatile Memory Plane, and Corresponding Memory Device - A method can be used for managing the operation of a memory cell that includes an SRAM elementary memory cell and a non-volatile elementary memory cell coupled to one another. A data bit is transferred between the SRAM elementary memory cell and the non-volatile elementary memory cell. A control datum is stored in a control memory cell that is functionally analogous to and associated with the memory cell. The data bit is read from the SRAM elementary memory cell and a corresponding read of the control datum is performed. The data bit read from the SRAM elementary memory cell is inverted if the control datum has a first value but the data bit read from the SRAM elementary memory cell is not inverted if the control datum has a second value. | 2015-01-15 |
20150016189 | SEMICONDUCTOR MEMORY DEVICE AND METHOD OF OPERATING THE SAME - Disclosed are a semiconductor memory device and an operating method thereof. The semiconductor memory device includes a memory cell block including a plurality of memory cells, a voltage providing unit suitable for providing a pass voltage or a read voltage to word lines coupled with the memory cells and a control circuit suitable for controlling the voltage providing unit to adjust a pass voltage applied to the memory cells disposed at one side of a selected memory cell and a pass voltage applied to the memory cells disposed at the other side of the selected memory cell based on an address of a word line of the selected memory cell among the memory cells during a read operation or a verification operation. | 2015-01-15 |
20150016190 | NONVOLATILE SEMICONDUCTOR MEMORY DEVICE - A nonvolatile semiconductor memory device comprises multiple memory strings each including a plurality of first and second groups of serially connected memory cells, and a back gate transistor serially connected between the first and second groups of memory cells, a plurality of word lines, each word line being connected to a control gate of a different memory cell in each of the memory strings, a voltage generating circuit configured to generate control voltages of different voltage levels, and a control circuit configured to control application of control voltages to the word lines and the back gate line. A control voltage applied to the back gate line may be varied depending on how far a selected word line is from the back gate line, and a control voltage applied to unselected word lines may be varied depending on how far the unselected word line is from the selected word line. | 2015-01-15 |
20150016191 | DATA STORAGE DEVICE AND FLASH MEMORY CONTROL METHOD - An overclocking process for a data storage device using a flash memory. A controller for the flash memory tests the flash memory using test clocks with various frequencies to determine at least one clock signal suitable to the flash memory. The clock candidates suitable to the flash memory are selected from the test clocks. The flash memory is operated in a variable-frequency manner by which the flash memory is switched between the clock candidates, such that electromagnetic interference is spread over different bands. | 2015-01-15 |
20150016192 | METHOD OF USING NON-VOLATILE MEMORIES FOR ON-DIMM MEMORY ADDRESS LIST STORAGE - An integrated circuit device. The device includes an address input(s) configured to receive address information from an address stream from an address command bus coupled to a host controller and an address output(s) configured to drive address information, and is coupled to a plurality of memory (DRAM) devices provided on a DIMM. The device has an address match table comprising a non-volatile memory device configured to store at least a revised address corresponding to a spare memory location and a bad address of at least one of the plurality of memory (DRAM) devices. The device has a control module configured to process and determine whether each address matches with a stored address in the address match table to identify the bad address and configured to replace the bad address with the revised address of the spare memory location. | 2015-01-15 |
20150016193 | CIRCUIT CONFIGURATION AND OPERATING METHOD FOR SAME - A circuit configuration is described including a first input for inputting a first set of digital input data, an output for outputting digital output data, and a control input for receiving a control signal. At least two register units are provided and the circuit configuration is designed to write, as a function of the control signal, into a first register unit optionally at least a part of the first set of input data or of the second set of digital input data and to write into a second register unit optionally at least a part of the first set of input data or of the second set of input data. | 2015-01-15 |
20150016194 | SEMICONDUCTOR MEMORY DEVICE AND MEMORY SYSTEM INCLUDING THE SAME - A semiconductor memory device and a memory system including the same are provided. The semiconductor memory device includes a first memory unit and a plurality of second memory unit, each including a plurality of memory cells and page buffers corresponding to the memory cells, and a redundancy memory unit including a plurality of redundancy memory cells and a plurality of redundancy page buffers corresponding to the redundancy memory cells. First input/output (I/O) data lines coupled to the first memory unit and second I/O data lines coupled to the second memory unit are coupled to the redundancy memory unit. | 2015-01-15 |
20150016195 | COMPENSATION CIRCUIT FOR USE WITH INPUT BUFFER AND METHOD OF OPERATING THE SAME - A compensation circuit for use with an input buffer includes an input buffer configured to amplify an input signal and output a compensated signal. A process detector includes a replica of the input buffer. The process detector is configured to output at least one comparison signal indicating a variation in the input buffer. The input buffer controls an output signal based on the at least one comparison signal. | 2015-01-15 |
20150016196 | DATA INPUT CIRCUIT - A data input circuit includes a clock sampling unit, a final clock generation unit, and a write latch signal generation unit. The sampling unit is configured to generate a shifting signal including a pulse generated after a write latency is elapsed, and generate a sampling clock by sampling an internal clock during a burst period from substantially a time when the pulse of the shifting signal is generated. The final clock generation unit is configured to generate a level signal by latching the shifting signal in synchronization with the sampling clock and generate a final clock from the level signal in response to a burst signal. The write latch signal generation unit is configured to generate an enable signal by latching the final clock and generate a write latch signal for latching and outputting aligned data in response to the enable signal. | 2015-01-15 |
20150016197 | SEMICONDUCTOR MEMORY DEVICE THAT DOES NOT REQUIRE A SENSE AMPLIFIER - A semiconductor memory device that does not require a sense amplifier includes a memory cell group having at least one memory cell, a buffer unit, and a bias voltage unit. The buffer unit includes a tri-state buffer that has an input terminal coupled to the memory cell group, and an output terminal coupled to a data line unit. The tri-state buffer is operable to switch between a conducting state and a non-conducting state. The bias voltage unit controls supply of a preset bias voltage to the input terminal of the tri-state buffer. By using the tri-state buffer, the parasitic capacitance attributed to the memory cell can be reduced, such that no sense amplifier is required to ensure proper operation, thereby reducing power consumption. | 2015-01-15 |
20150016198 | Multiple Power Domain Circuit and Related Method - A method comprises providing a trigger signal, generating an input pulse according to the trigger signal, inverting the input pulse to generate an inverted input pulse and pulling down an output voltage using the inverted input pulse, wherein the inverted pulse is applied to a transistor of a high threshold voltage circuit. | 2015-01-15 |
20150016199 | BIT LINE EQUALIZING CIRCUIT - There is provided a bit line equalizing circuit including: an active region; a first bit line disposed on the active region in a first direction; a second bit line disposed on the active region in the first direction; a gate pattern including a first pattern disposed on the active region in a second direction crossing the first direction, and a second pattern extended from one side of the first pattern to be disposed in the first direction, and formed in a stair shape; a first contact disposed at one side of the first pattern and one side of the second pattern, and configured to connect the active region and the first bit line; a second contact disposed at one side of the first pattern and the other side of the second pattern, and configured to connect the active region and the second bit line; and a third contact disposed at the other side of the first pattern, and configured to provide a predetermined voltage to the active region. | 2015-01-15 |
20150016200 | MEMORY DEVICE FOR MASKING READ DATA AND A METHOD OF TESTING THE SAME - A memory device includes a memory array, a plurality of input/output pins, a mask signal generator, an input/output block. The memory array is configured to output read data including a plurality of data bits. The mask signal generator is configured to generate at least one data mask signal. The input/output block is configured to mask bits having a logic level among the plurality of data bits in the read data to output the masked read data to the plurality of input/output pins. | 2015-01-15 |
20150016201 | SEMICONDUCTOR DEVICE - A semiconductor device includes first and second bank groups coupled to first and second data lines which are electrically isolated from each other. The semiconductor device includes a register unit suitable for providing predetermined data to the second data line in a specific mode, a data transfer and output unit suitable for externally outputting the predetermined data loaded onto the second data line and simultaneously transferring the predetermined data to the first data line in the specific mode, and a data output unit suitable for externally outputting the predetermined data loaded onto the first data line in the specific mode. | 2015-01-15 |
20150016202 | MEMORY DEVICES, SYSTEMS AND METHODS EMPLOYING COMMAND/ADDRESS CALIBRATION - During a command/address calibration mode, a memory controller may transmit multiple cycles of test patterns as signals to a memory device. Each cycle of test pattern signals may be transmitted at an adjusted relative phase with respect to a clock also transmitted to the memory device. The memory device may input the test pattern signals at a timing determined by the clock, such as rising and/or falling edges of the clock. The test pattern as input by the memory device may be sent to the memory controller to determine if the test pattern was successfully transmitted to the memory device during the cycle. Multiple cycles of test pattern transmissions are evaluated to determine a relative phase of command/address signals with respect to the clock for transmission during operation of the system. | 2015-01-15 |
20150016203 | DRAM SUB-ARRAY LEVEL AUTONOMIC REFRESH MEMORY CONTROLLER OPTIMIZATION - A method of refreshing a dynamic random access memory (DRAM) includes detecting an open page of the DRAM at a row of a DRAM bank within an open sub-array of the DRAM bank. The method also includes delaying issuance of a refresh command to a target refresh row of the DRAM bank when the target refresh row of the DRAM bank is within the open sub-array of the DRAM bank. | 2015-01-15 |
20150016204 | INSERTION-OVERRIDE COUNTER TO SUPPORT MULTIPLE MEMORY REFRESH RATES - A memory refresh method includes determining positions at which to insert refresh operations of weak rows of a memory block among regularly scheduled refresh operations of normal rows of the memory block. The refresh operations occur at a substantially constant refresh rate. The positions at which to insert are based on an actual weak page address. The method also includes performing inserted refresh operations at the determined positions to coordinate distribution of the inserted refresh operations among the regularly scheduled refresh operations. | 2015-01-15 |
20150016205 | SEMICONDUCTOR CIRCUIT - A semiconductor circuit includes a first input section into which a first input signal is inputted, a second input section into which a second input signal is inputted, an output generation circuit which is connected to the first and second input sections and generates an output signal based on the input signals, an output section which outputs the output signal, and a current source which is connected to connection nodes between the input sections and the output generation circuit. | 2015-01-15 |
20150016206 | APPARATUS AND METHOD TO MEASURE ENERGY CAPACITY OF A BACKUP POWER SUPPLY WITHOUT COMPROMISING POWER DELIVERY - A device includes a backup power supply configured to provide power to an external system upon loss of primary system power. The backup power provided by at least one capacitor. While the capacitor is available as a backup power supply to the external system, a transient elevation of the capacitor's stored potential is created above an upper predetermined operating potential of the capacitor. Measurements of a capacitor's output voltage are obtained during the transient elevation of the capacitor's stored potential. A capacitance of the capacitor is determined from the measurements. | 2015-01-15 |
20150016207 | Systems and Methods for Reducing Standby Power in Floating Body Memory Devices - Methods, devices, arrays and systems for reducing standby power for a floating body memory array. One method includes counting bits of data before data enters the array, wherein the counting includes counting at least one of: a total number of bits at state 1 and a total number of all bits; a total number of bits at state 0 and the total number of all bits; or the total number of bits at state 1 and the total number of bits at state 0. This method further includes detecting whether the total number of bits at state 1 is greater than the total number of bits at state 0; setting an inversion bit when the total number of bits at state 1 is greater than the total number of bits at state 0; and inverting contents of all the bits of data before writing the bits of data to the memory array when the inversion bit has been set. | 2015-01-15 |
20150016208 | MULTI-CHAMBER CONTAINER FOR STORING AND MIXING LIQUIDS - The present disclosure is drawn to a multi-chamber container and related methods for storing and mixing liquids and associated methods of use. The multi-chamber container includes a first chamber configured to contain a first liquid composition. The multi-chamber container also includes a second chamber configured to contain a second liquid composition. The multi-chamber container further includes a barrier operable to separate the first chamber and the second chamber. Additionally, the multi-chamber container includes a compliant mechanism movable between a first position and a second position and a plunger movable with the compliant mechanism to alter or remove the barrier. In the first position, the barrier is operable to maintain the first liquid composition and the second liquid composition separate from one another. In the second position, the plunger is operable to alter or remove the barrier to facilitate contact of the first liquid composition and the second liquid composition. | 2015-01-15 |
20150016209 | MOBILE BLENDING APPARATUS - A blending system includes one or more tank platforms. The tank platforms are transportable via road, rail, or vessel. One or more bulk containers are located on the tank platforms. The bulk containers are capable of storing and handling concentrated fluids. A blending platform may be coupled to the tank platforms. The blending platform is transportable via road, rail, or vessel. A blending unit is located on the blending platform. The blending unit blends the concentrated fluids with one or more of the additive fluids and water to continuously produce fracking fluids as needed (e.g,. fluids are continuously produced on an on-demand basis). The fracking fluids may have a selected concentration of concentrated fluid, additive fluid, and/or water. | 2015-01-15 |
20150016210 | STEAM/WATER STATIC MIXER INJECTOR FOR EXTRUSION EQUIPMENT - Apparatus ( | 2015-01-15 |
20150016211 | STEAM/WATER STATIC MIXER INJECTOR FOR EXTRUSION EQUIPMENT - Apparatus ( | 2015-01-15 |
20150016212 | RETRACTABLE MIXING DEVICE AND METHOD - A system for mixing a fluid in a tank includes a mixer assembly, a housing, and an actuator. The mixer assembly has a motor, a shaft, and an impeller. The housing is disposed in a side wall of the tank. The housing has sufficient volume to contain the impeller. The actuator is configured to retract the mixer assembly and draw the impeller into the housing. The mixer assembly has a first conformation and a second conformation. In the first conformation the impeller is disposed in a main portion of the tank and configured to mix the fluid in response to rotation of the impeller via the motor and shaft. In the second conformation the impeller is disposed in the housing and out of the main portion of the tank. | 2015-01-15 |
20150016213 | RETRACTABLE MIXING DEVICE AND METHOD - A system for mixing a fluid in a tank includes a mixer assembly, a housing, and an actuator. The mixer assembly has a motor, a shaft, and an impeller. The housing is disposed in a side wall of the tank. The housing has sufficient volume to contain the impeller. The actuator is configured to retract the mixer assembly and draw the impeller into the housing. The mixer assembly has a first conformation and a second conformation. In the first conformation the impeller is disposed in a main portion of the tank and configured to mix the fluid in response to rotation of the impeller via the motor and shaft. In the second conformation the impeller is disposed in the housing and out of the main portion of the tank. | 2015-01-15 |
20150016214 | MIXER DEVICE - The present invention relates to a mixer device for distributing and evaporating a liquid introduced into a gas flow, in particular into an exhaust-gas flow, wherein the mixer device comprises at least one mixer vane ( | 2015-01-15 |
20150016215 | IMAGE PROCESSING MODULE, ULTRASOUND IMAGING APPARATUS, IMAGE PROCESSING METHOD, AND CONTROL METHOD OF ULTRASOUND IMAGING APPARATUS - An image processing module includes an input unit, a weight operator, and a synthesizer. The input unit is configured to receive a plurality of input signals of a plurality of channels. The weight operator is configured to calculate at least one weight to be applied to each channel based on at least one converted signal. The at least one converted signal is acquired by converting at least one input signal among the plurality of input signals of each channel, or by converting a synthesized input signal of the plurality of input signals of each channel. The synthesizer is configured to synthesize the plurality of input signals of the plurality of channels using the weight. | 2015-01-15 |
20150016216 | In Situ Accelerometer Calibration - Disclosed are methods and systems for calibration of an accelerometer used in a geophysical sensor while deployed in the water. An embodiment may include towing a streamer behind a survey vessel in a body of water, wherein the streamer comprises an accelerometer; causing at least a portion of the streamer to twist; receiving data from the accelerometer at a selected plurality of times during the twist; and based at least in part on the data, determining at least one calibration parameter of the accelerometer. | 2015-01-15 |
20150016217 | Methods and Systems for Streamer Anti-Twist - Disclosed are methods and systems for enabling anti-twist functionality in marine geophysical streamers. An embodiment discloses a method comprising: towing a streamer behind a survey vessel in a body of water, wherein the streamer comprises rotation sensors and streamer rotation devices; receiving data from at least one rotation sensor indicative of streamer twist; and rotating a portion of the streamer with at least one streamer rotation device to reduce the streamer twist based, at least in part on the data. | 2015-01-15 |
20150016218 | MARINE SEISMIC SURVEY METHOD AND SYSTEM - An inventive method provides for control of a seismic survey spread while conducting a seismic survey, the spread having a vessel, a plurality of spread control elements, a plurality of navigation nodes, and a plurality of sources and receivers. The method includes the step of collecting input data, including navigation data for the navigation nodes, operating states from sensors associated with the spread control elements, environmental data for the survey, and survey design data. The positions of the sources and receivers are estimated using the navigation data, the operating states, and the environmental data. Optimum tracks for the sources and receivers are determined using the position estimates and a portion of the input data that includes at least the survey design data. Drive commands are calculated for at least two of the spread control elements using the determined optimum tracks. The inventive method is complemented by an inventive system. | 2015-01-15 |
20150016219 | DEVICE FOR PRODUCING AN ACOUSTIC SIGNAL IN A LIQUID MEDIUM, EQUIPPED WITH HYDRAULIC MEANS FOR CONTROLLING OUTPUT ACOUSTIC SIGNAL - A device is provided for producing an acoustic signal in a liquid medium. The device includes a pneumatic chamber to contain a compressed gas volume, at least one pneumatic exhaust port allowing the compressed gas volume to be released out of the pneumatic chamber, and a shuttle movable along a translational axis during an opening phase, between two positions: a closed position in which the compressed gas volume is enclosed within the pneumatic chamber, and an open position in which the compressed gas volume is released out of the pneumatic chamber through the pneumatic exhaust port, to produce the acoustic signal in the liquid medium. A hydraulic brake is used to brake the shuttle during the opening phase. The hydraulic brake includes a hydraulic chamber and having a hydraulic exhaust area of a hydraulic volume out of the hydraulic chamber, and includes a control for controlling the acoustic signal. | 2015-01-15 |
20150016220 | SONIC/ACOUSTIC MONITORING USING OPTICAL DISTRIBUTED ACOUSTIC SENSING - Methods and apparatus for performing sonic well logging within a wellbore based on optical Distributed Acoustic Sensing (DAS) are provided. A sonic well logging system based on DAS may be capable of producing the functional equivalent of tens, hundreds, or even thousands of acoustic sensors. In this manner, the emplacement of the sonic well logging system based on DAS may not be nearly as complex or expensive as emplacing a sonic well logging system based on traditional methods. Furthermore, multiplexing may be simpler, downhole electronics need not be used, and the sonic well logging system may be used in extreme, high temperature environments. | 2015-01-15 |
20150016221 | TRANSDUCER AND SUBJECT INFORMATION ACQUISITION APPARATUS - A transducer includes a plurality of elements each including at least one cell structured in such a way that a diaphragm including one of a first electrode and a second electrode disposed facing each other via a space is vibratably supported, bias wiring for supplying a bias voltage to the first electrode to provide a potential difference between the first and the second electrodes, and for electrically connecting the first electrodes of the elements to each other, and signal wiring lines each connected to a different one of the elements. The bias wiring includes a plurality of branch wiring lines to each of which the first electrodes of a part of the elements are connected, a plurality of first common wiring lines for connecting the branch wiring lines to each other, and a second common wiring line for connecting the first common wiring lines to each other. | 2015-01-15 |
20150016222 | ELECTROSTATIC CAPACITANCE TRANSDUCER, PROBE, AND SUBJECT INFORMATION ACQUIRING DEVICE - An electrostatic capacitance transducer includes: multiple elements each having a cell including a first electrode, and a vibrating film including a second electrode, formed across a gap from the first electrode; a first flexible printed circuit having multiple first lines; and a second flexible printed circuit having multiple second lines. Part of the multiple elements are grouped into a first element group, each one thereof being electrically connected to a different one of the first lines. Part of the multiple elements other than the first element group are grouped into a second element group, each one thereof being electrically connected to a different one of the second lines. The intervals between adjacent lines in at least part of the plurality of first and second lines are wider at an opposite side from a connection side where the lines have been connected to the multiple elements, than at the connection side. | 2015-01-15 |
20150016223 | SENSOR ARRAY WITH RECEIVER BIAS ELECTRODE - A method of operation of an ultrasonic sensor array includes receiving a receiver bias voltage at a receiver bias electrode of the ultrasonic sensor array to bias piezoelectric sensor elements of the ultrasonic sensor array. The method further includes receiving a transmitter control signal at the ultrasonic sensor array to cause an ultrasonic transmitter of the ultrasonic sensor array to generate an ultrasonic wave. The method further includes generating data samples based on a reflection of the ultrasonic wave. The receiver bias voltage and the transmitter control signal are received from an integrated circuit that is coupled to the ultrasonic sensor array. | 2015-01-15 |
20150016224 | SIGNAL PROCESSING APPARATUS, OBJECT DETECTING APPARATUS, APPARATUS PROVIDED WITH OBJECT DETECTING FUNCTION, AND OBJECT DETECTING METHOD - Provided is a technology which is able to detect an object with high accuracy. A signal processing apparatus | 2015-01-15 |
20150016225 | System and Method for Target Detection - A sonar based sensor for localization of a target in air is described. The sensor comprises a wide or ultra-wide band emitter for emitting a wide or ultra-wide band signal, and a set of spatially randomly or irregularly positioned receivers for receiving the wide or ultra-wide band signal after reflection at the target. A corresponding processor and method for localizing also is disclosed. | 2015-01-15 |
20150016226 | BEAMFORMER, BEAMFORMING METHOD, ULTRASONIC IMAGING APPARATUS, AND CONTROL METHOD OF ULTRASONIC IMAGING APPARATUS - Disclosed herein is a beamformer that performs beamforming, including a weight computation processor configured to compute a covariance of a conversion signal which is obtainable by converting an input signal using at least one conversion function, approximate the computed covariance to a Toeplitz matrix form, and compute a conversion signal weight that is a weight for the conversion signal based on the approximation result, and a synthesizer configured to generate an output signal using the conversion signal weight computed by the weight computation processor. | 2015-01-15 |
20150016227 | CAPACITIVE MICRO-MACHINED ULTRASOUND TRANSDUCER DEVICE WITH CHARGING VOLTAGE SOURCE - The present invention relates to a capacitive micro-machined ultrasound transducer (CMUT) device ( | 2015-01-15 |
20150016228 | REMOTE CONTROL SIGNALING USING AUDIO WATERMARKS - A system for using a watermark embedded in an audio signal to remotely control a device. Various devices such as toys, computers, and appliances, equipped with an appropriate detector, detect the hidden signals, which can trigger an action, or change a state of the device. The watermarks can be used with a “time gate” device, where detection of the watermark opens a time interval within which a user is allowed to perform an action, such as pressing a button, typing in an answer, turning a key in a lock, etc. | 2015-01-15 |
20150016229 | ELECTRONIC TIMEPIECE WITH BUILT-IN ANTENNA - An electronic timepiece includes a tubular exterior case, a cover glass plate that blocks one of two openings of the exterior case, a ring-shaped antenna body provided along an inner circumference of the exterior case, a circuit substrate which is provided in a position below the antenna body when viewed from the cover glass plate and on which a shield pattern G is formed, and a GPS receiver that is so provided on the circuit substrate that the GPS receiver faces away from the antenna body with the shield pattern G being a boundary and amplifies and processes a signal received by the antenna body. | 2015-01-15 |
20150016230 | TIMEPIECE MECHANISM, TIMEPIECE MOVEMENT AND TIMEPIECE - A mechanism ( | 2015-01-15 |
20150016231 | MICROMETRIC ADJUSTMENT OF THE ENDSHAKE OF A TIMEPIECE WHEEL SET - Device for the micrometric endshake adjustment of a timepiece wheel set in an axial direction in relation to a structure, including a pivot bearing for this wheel set defining an axial stop member for this wheel set in this axial direction. | 2015-01-15 |
20150016232 | TIMEPIECE MECHANISM, TIMEPIECE MOVEMENT AND TIMEPIECE - A mechanism ( | 2015-01-15 |
20150016233 | METHODS AND DEVICES FOR OPERATING MOBILE TERMINAL ALARM CLOCK UNDER SHUTDOWN STATE - A mobile terminal may comprise an executing unit being configured to activate an alarm clock when the mobile terminal is off. The mobile terminal may be configured to receive a target alarm clock activation time; determine a time difference between a current time and the target alarm clock activation time; and compare the time difference with a first reference time period. Upon determining that time difference is less than the first reference time period, the mobile terminal may start up. Upon determining that the time that the mobile terminal completes the startup is less than a second reference time period, the mobile terminal may activate the alarm clock. | 2015-01-15 |
20150016234 | PLASMONIC FUNNEL FOR FOCUSED OPTICAL DELIVERY TO A METALLIC MEDIUM - An apparatus includes a transducer including a plasmonic funnel having first and second ends with the first end having a smaller cross-sectional area than the second end, and a first section positioned adjacent to the first end of the plasmonic funnel, and a first waveguide having a core, positioned to cause light in the core to excite surface plasmons on the transducer. | 2015-01-15 |
20150016235 | DISK DRIVE SUSPENSION ASSEMBLY HAVING A PARTIALLY FLANGELESS LOAD POINT DIMPLE - Various embodiments concern a suspension assembly of a disk drive. The suspension assembly includes a load beam comprising a major planar area formed from a substrate. The load beam further comprises a window in the substrate, a dimple formed from the substrate, and a flange. The flange is a region of the major planar area that extends partially around the dimple but does not extend along an edge of the dimple. The edge of the dimple is adjacent to the window. The dimple is in contact with the flexure. A HAMR block or other element can extend through the window. The lack of a full flange can minimize the necessary clearance between the dimple and the HAMR block or other element and thereby allow the window to be enlarged to accommodate the HAMR block or other element. | 2015-01-15 |
20150016236 | MAGNETIC RECORDING MEDIUM, MAGNETIC RECORDING AND REPRODUCING APPARATUS, MAGNETIC RECORDING METHOD AND MAGNETIC REPRODUCING METHOD - Provided is a magnetic recording medium including a structure in which at least a soft magnetic underlayer, a non-magnetic intermediate layer, and a magnetic recording layer are sequentially laminated on a non-magnetic substrate, wherein the magnetic recording layer includes a first magnetic layer, a non-magnetic layer, and a second magnetic layer in order from the non-magnetic substrate side, has a structure in which the first magnetic layer and the second magnetic layer are magnetically separated from each other with the non-magnetic layer interposed therebetween, and consists of a plurality of patterns which are magnetically separated from each other, and the coercive force Hc of the second magnetic layer is larger than that of the first magnetic layer, and the coercive force Hc of the second magnetic layer is smaller than that of the first magnetic layer temporarily when the second magnetic layer is heated. | 2015-01-15 |
20150016237 | METHOD FOR FABRICATING A PATTERNED COMPOSITE STRUCTURE - The embodiments disclose a patterned composite magnetic layer structure configured to use magnetic materials having differing temperature and magnetization characteristics in a recording device, wherein the patterned composite magnetic layer structure includes magnetic layers, at least one first magnetic material configured to be used in a particular order to reduce a recording temperature and configured to control and regulate coupling and decoupling of the magnetic layers and at least one second magnetic material with differing temperature characteristics is configured to control recording and erasing of data. | 2015-01-15 |
20150016238 | PLASMONIC WAVEGUIDE WITH AN ANGLED, ELONGATED PORTION - An apparatus includes an input region having a high-refractive-index material and an input surface configured to receive light emitted from a laser. An output surface of the apparatus is configured to deliver energy to a recording medium. The apparatus includes a plasmonic waveguide having a first elongated portion at an angle to the input surface and configured to receive the light through the input region. In response to receiving the light, surface plasmons are excited and guided to an end of the first elongated portion. The plasmonic waveguide includes a second elongated portion coupled to the end of the first elongated portion and configured to guide the surface plasmons to the output surface. | 2015-01-15 |
20150016239 | METHOD AND APPARATUS FOR SETTING REFERENCE SIGNAL - Disclosed are a method and an apparatus for setting a reference signal. A wireless apparatus receives a primary synchronization signal (PSS) transmitted by a first orthogonal frequency division multiplexing (OFDM) symbol and a secondary synchronization signal (SSS) from a second OFDM symbol, and can search information for setting a reference signal on the basis of symbol numbers of the first OFDM symbol and the second OFDM symbol. Inter-cell interference can be reduced by means of a variety of methods for setting a reference signal. | 2015-01-15 |
20150016240 | APPARATUS AND METHOD FOR REMOTE BEAM FORMING FOR DBS SATELLITES - A satellite broadcasting system is achieved where remote beam forming processors combined with wavefront multiplexers located among distributed ground stations are used to control downlink beam footprints and pointing directions. Digital beam forming (DBF) techniques allow a single satellite download broadcast antenna array to generate multiple independently pointed simultaneous downlinks, which may contain distinct information content. Allocation of some uplink back-channel elements as diagnostic signals allows for continuous calibration of uplink channels, improving downlink broadcast array and user broadcast performance. Wavefront multiplexing/demultiplexing allows all array element signals to be radiated by the broadcasting antenna array, with simultaneous propagation from ground stations to the broadcasting satellites through available parallel propagation channels in the uplinks of feeder links, with equalized amplitude and phase differentials. Further, additional wavefront multiplexing/demultiplexing pairs are further used to coherently broadcast signals from a remote beam forming facility on ground to cover areas through multiple broadcasting satellites. | 2015-01-15 |